Re: [PATCH 4/4] drm/i915/psr: Apply SDP on prior scanline workaround for NVL

["Hogander, Jouni" <jouni.hogander@intel.com>]

On Wed, 2026-05-06 at 07:29 +0000, Kandpal, Suraj wrote:
> > Subject: [PATCH 4/4] drm/i915/psr: Apply SDP on prior scanline
> > workaround
> > for NVL
> > 
> > In NVL there is an HW optimization done. When there is an SU
> > triggered in
> > Capture state, Link will be kept ON post Capture CRC SDP. Before
> > valid SU
> > pixels Intel source will transmit dummy pixels. Some TCONS are
> > improperly
> > considering these dummy pixels as a valid pixel data. Prior NVL
> > link was was
> > turned of even if there was SU triggered in Capture state and no
> > dummy pixels
> 
> *off
> *capture
> 
> > were transmitted. These dummy pixels are problem only if SDP on
> > prior
> > scanline is used and Early Transport is not in use. The workaround
> > is to start
> > SU area always at scanline 0.
> > 
> > Bspec: 74741, 79482
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 341186622ed4..28668fed8347 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -2910,6 +2910,11 @@ intel_psr_apply_su_area_workarounds(struct
> > intel_crtc_state *crtc_state)
> >  	    crtc_state->splitter.enable)
> >  		crtc_state->psr2_su_area.y1 = 0;
> > 
> > +	/* Wa_16029024088 */
> > +	if (DISPLAY_VER(display) >= 35 && crtc_state-
> > > req_psr2_sdp_prior_scanline &&
> > +	    !crtc_state->enable_psr2_su_region_et)
> > +		crtc_state->psr2_su_area.y1 = 0;
> 
> I am a little confused as to what the WA is asking from us
> According to Bspec
> "Selective Update Considerations
> When exiting the Capture frame, if there is an SU available, the PSR2
> function will keep the main link awake until the SU has been sent to
> the Panel.  Some Panels may have a problem with this behavior which
> will require the Driver to do one of the following (in order of
> priority):
> 
> Set 0x3F0 DPCD to 0x2 which means the TCON has no restriction of
> 100nsec between VSC SDP to SU start.
> If above cannot be supported plus the TCON vendor can support early
> transport, then enable early transport.
> If neither of #1 and #2 can be done from TCON, it will be a custom WA
> in driver to always start SU at scanline 0 (this will come as a power
> penalty).
> "
> 
> Here it says its driver's responsibility to set 0x3F0 DPCD (I don't
> see that happeining anywhere)  but then all we do is just read this
> DPCD and decide if crtc_state-
> > req_psr2_sdp_prior_scanline's value .Is that some sort of typo or
> > am I missing something here ?

Generally this INTEL_WA_REGISTER caps is a capabilities register and
supposed to be read only for driver. To my understanding we are not
supposed to write anything there. Anyways I will ask for clarification
in Bspec just to be sure and to get Bspec corrected on this.

BR,
Jouni Högander

> 
> Regards,
> Suraj Kandpal
> 
> > +
> >  	/* Wa 14019834836 */
> >  	if (DISPLAY_VER(display) == 30)
> >  		intel_psr_apply_pr_link_on_su_wa(crtc_state);
> > --
> > 2.43.0
>