From: Jani Nikula <jani.nikula@intel.com>
To: Uma Shankar <uma.shankar@intel.com>,
intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, Uma Shankar <uma.shankar@intel.com>
Subject: Re: [PATCH 02/19] drm/{i915, xe}: Extract South chicken registers
Date: Wed, 17 Dec 2025 15:58:35 +0200 [thread overview]
Message-ID: <bf82d4c00e17f964220054ea49dbd4df7f83987e@intel.com> (raw)
In-Reply-To: <20251217062209.852324-3-uma.shankar@intel.com>
On Wed, 17 Dec 2025, Uma Shankar <uma.shankar@intel.com> wrote:
> Extract South Chicken registers to common header.
> This allows intel_pch_refclk.c not to include i915_reg.h
Why not intel_display_regs.h?
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> .../gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 27 -------------------
> include/drm/intel/intel_gmd_common_regs.h | 27 +++++++++++++++++++
> 3 files changed, 28 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> index 9a89bb6dcf65..55abb97c6562 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> @@ -4,8 +4,8 @@
> */
>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_common_regs.h>
>
> -#include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_display_regs.h"
> #include "intel_display_types.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f60259c41c56..c1f33c11ac1b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1023,33 +1023,6 @@
> #define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
> #define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
>
> -#define SOUTH_CHICKEN1 _MMIO(0xc2000)
> -#define FDIA_PHASE_SYNC_SHIFT_OVR 19
> -#define FDIA_PHASE_SYNC_SHIFT_EN 18
> -#define INVERT_DDIE_HPD REG_BIT(28)
> -#define INVERT_DDID_HPD_MTP REG_BIT(27)
> -#define INVERT_TC4_HPD REG_BIT(26)
> -#define INVERT_TC3_HPD REG_BIT(25)
> -#define INVERT_TC2_HPD REG_BIT(24)
> -#define INVERT_TC1_HPD REG_BIT(23)
> -#define INVERT_DDID_HPD (1 << 18)
> -#define INVERT_DDIC_HPD (1 << 17)
> -#define INVERT_DDIB_HPD (1 << 16)
> -#define INVERT_DDIA_HPD (1 << 15)
> -#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
> -#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
> -#define FDI_BC_BIFURCATION_SELECT (1 << 12)
> -#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
> -#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
> -#define SBCLK_RUN_REFCLK_DIS (1 << 7)
> -#define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
> -#define SPT_PWM_GRANULARITY (1 << 0)
> -#define SOUTH_CHICKEN2 _MMIO(0xc2004)
> -#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
> -#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
> -#define LPT_PWM_GRANULARITY (1 << 5)
> -#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
> -
> #define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
> #define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
> #define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
> diff --git a/include/drm/intel/intel_gmd_common_regs.h b/include/drm/intel/intel_gmd_common_regs.h
> index 4d91bc2dbb27..b4cfd186d5c0 100644
> --- a/include/drm/intel/intel_gmd_common_regs.h
> +++ b/include/drm/intel/intel_gmd_common_regs.h
> @@ -4,6 +4,33 @@
> #ifndef _INTEL_GMD_COMMON_REG_H_
> #define _INTEL_GMD_COMMON_REG_H_
>
> +#define SOUTH_CHICKEN1 _MMIO(0xc2000)
> +#define FDIA_PHASE_SYNC_SHIFT_OVR 19
> +#define FDIA_PHASE_SYNC_SHIFT_EN 18
> +#define INVERT_DDIE_HPD REG_BIT(28)
> +#define INVERT_DDID_HPD_MTP REG_BIT(27)
> +#define INVERT_TC4_HPD REG_BIT(26)
> +#define INVERT_TC3_HPD REG_BIT(25)
> +#define INVERT_TC2_HPD REG_BIT(24)
> +#define INVERT_TC1_HPD REG_BIT(23)
> +#define INVERT_DDID_HPD (1 << 18)
> +#define INVERT_DDIC_HPD (1 << 17)
> +#define INVERT_DDIB_HPD (1 << 16)
> +#define INVERT_DDIA_HPD (1 << 15)
> +#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
> +#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
> +#define FDI_BC_BIFURCATION_SELECT (1 << 12)
> +#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
> +#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
> +#define SBCLK_RUN_REFCLK_DIS (1 << 7)
> +#define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
> +#define SPT_PWM_GRANULARITY (1 << 0)
> +#define SOUTH_CHICKEN2 _MMIO(0xc2004)
> +#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
> +#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
> +#define LPT_PWM_GRANULARITY (1 << 5)
> +#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
> +
> #define _TRANSA_CHICKEN2 0xf0064
> #define _TRANSB_CHICKEN2 0xf1064
> #define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
--
Jani Nikula, Intel
next prev parent reply other threads:[~2025-12-17 13:58 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-17 6:21 [PATCH 00/19] Make Display free from i915_reg.h Uma Shankar
2025-12-17 6:21 ` [PATCH 01/19] drm/{i915, xe}: Extract common registers into a separate file Uma Shankar
2025-12-17 13:57 ` Jani Nikula
2025-12-18 9:06 ` Shankar, Uma
2025-12-17 6:21 ` [PATCH 02/19] drm/{i915, xe}: Extract South chicken registers Uma Shankar
2025-12-17 13:58 ` Jani Nikula [this message]
2025-12-17 6:21 ` [PATCH 03/19] drm/{i915, xe}: Extract display interrupt definitions Uma Shankar
2025-12-17 6:21 ` [PATCH 04/19] drm/{i915, xe}: Extract DSPCLK_GATE_D Uma Shankar
2025-12-17 14:01 ` Jani Nikula
2025-12-17 6:21 ` [PATCH 05/19] drm/{i915, xe}: Extract pcode definitions Uma Shankar
2025-12-17 6:21 ` [PATCH 06/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_device.c Uma Shankar
2025-12-17 6:21 ` [PATCH 07/19] drm/{i915, xe}: Remove i915_reg.h from intel_dram.c Uma Shankar
2025-12-17 14:03 ` Jani Nikula
2025-12-17 6:21 ` [PATCH 08/19] drm/{i915, xe}: Removed i915_reg.h from intel_display.c Uma Shankar
2025-12-17 14:04 ` Jani Nikula
2025-12-17 6:21 ` [PATCH 09/19] drm/{i915, xe}: Remove i915_reg.h from intel_overlay.c Uma Shankar
2025-12-17 6:22 ` [PATCH 10/19] drm/{i915, xe}: Remove i915_reg.h from g4x_dp.c Uma Shankar
2025-12-17 6:22 ` [PATCH 11/19] drm/{i915, xe}: Remove i915_reg.h from i9xx_wm.c Uma Shankar
2025-12-17 6:22 ` [PATCH 12/19] drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c Uma Shankar
2025-12-17 6:22 ` [PATCH 13/19] drm/{i915, xe}: Remove i915_reg.h from intel_rom.c Uma Shankar
2025-12-17 6:22 ` [PATCH 14/19] drm/{i915, xe}: Remove i915_reg.h from intel_psr.c Uma Shankar
2025-12-17 6:22 ` [PATCH 15/19] drm/{i915, xe}: Remove i915_reg.h from intel_fifo_underrun.c Uma Shankar
2025-12-17 6:22 ` [PATCH 16/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_irq.c Uma Shankar
2025-12-17 6:22 ` [PATCH 17/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_power_well.c Uma Shankar
2025-12-17 6:22 ` [PATCH 18/19] drm/{i915, xe}: Remove i915_reg.h from intel_modeset_setup.c Uma Shankar
2025-12-17 6:22 ` [PATCH 19/19] drm/{i915, xe}: Removed i915_reg.h from display Uma Shankar
2025-12-17 7:56 ` ✓ i915.CI.BAT: success for Make Display free from i915_reg.h Patchwork
2025-12-17 9:04 ` ✗ i915.CI.Full: failure " Patchwork
2025-12-17 14:06 ` [PATCH 00/19] " Jani Nikula
2025-12-18 9:08 ` Shankar, Uma
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