From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
To: Radhakrishna Sripada <radhakrishna.sripada@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: nanley.g.chery@intel.com,
Kalyan Kondapally <kalyan.kondapally@intel.com>,
ville.syrjala@intel.com
Subject: Re: [PATCH v2 10/11] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color
Date: Fri, 04 Oct 2019 17:07:44 -0700 [thread overview]
Message-ID: <bfbedcb02668ba8c2bfaaf0c2f10ccb79311b4db.camel@intel.com> (raw)
In-Reply-To: <20190924000328.29571-11-radhakrishna.sripada@intel.com>
On Mon, 2019-09-23 at 17:03 -0700, Radhakrishna Sripada wrote:
> Gen12 display can decompress surfaces compressed by render engine with Clear Color, add
> a new modifier as the driver needs to know the surface was compressed by render engine.
>
> V2: Description changes as suggested by Rafael.
>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Kalyan Kondapally <kalyan.kondapally@intel.com>
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Cc: Nanley Chery <nanley.g.chery@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
> include/uapi/drm/drm_fourcc.h | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index c4a4e0fdbee5..99c61ee9b61f 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -434,6 +434,17 @@ extern "C" {
> */
> #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
>
> +/*
> + * Intel color control surfaces Clear Color(CCS_CC) for Gen-12 render compression.
> + *
> + * The main surface is Y-tiled and is at plane index 0 whereas CCS_CC is linear
> + * and at index 1.
Clear color data is fixed size - 64b, that should be in the documentation here.
> The clear color is stored at index 2, and the pitch should
> + * be ignored. A CCS_CC cache line corresponds to an area of 4x1 tiles in the
That's a CCS cache line, not a CCS_CC cache line, right?
> + * main surface. The main surface pitch is required to be a multiple of 4 tile
> + * widths.
> + */
> +#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
> +
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> *
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-10-05 0:07 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-24 0:03 [PATCH v2 00/11] Clear Color Support for TGL Render Decompression Radhakrishna Sripada
2019-09-24 0:03 ` [PATCH v2 01/11] drm/framebuffer: Format modifier for Intel Gen-12 render compression Radhakrishna Sripada
2019-09-24 0:03 ` [PATCH v2 02/11] drm/i915: Use intel_tile_height() instead of re-implementing Radhakrishna Sripada
2019-09-24 0:03 ` [PATCH v2 03/11] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment Radhakrishna Sripada
2019-09-24 0:03 ` [PATCH v2 04/11] drm/i915/tgl: Gen-12 render decompression Radhakrishna Sripada
2019-09-24 0:03 ` [PATCH v2 05/11] drm/i915: Extract framebufer CCS offset checks into a function Radhakrishna Sripada
2019-09-24 0:03 ` [PATCH v2 06/11] drm/framebuffer: Format modifier for Intel Gen-12 media compression Radhakrishna Sripada
2019-09-24 0:03 ` [PATCH v2 07/11] drm/i915: Skip rotated offset adjustment for unsupported modifiers Radhakrishna Sripada
2019-09-24 0:03 ` [PATCH v2 08/11] drm/fb: Extend format_info member arrays to handle four planes Radhakrishna Sripada
2019-09-24 0:03 ` [PATCH v2 09/11] Gen-12 display can decompress surfaces compressed by the media engine Radhakrishna Sripada
2019-09-24 0:03 ` [PATCH v2 10/11] drm/framebuffer/tgl: Format modifier for Intel Gen 12 render compression with Clear Color Radhakrishna Sripada
2019-10-05 0:07 ` Dhinakaran Pandiyan [this message]
2019-10-08 23:19 ` Sripada, Radhakrishna
2019-09-24 0:03 ` [PATCH v2 11/11] drm/i915/tgl: Add Clear Color supoort for TGL Render Decompression Radhakrishna Sripada
2019-09-27 22:28 ` [PATCH v3 " Radhakrishna Sripada
2019-10-04 23:52 ` Matt Roper
2019-10-05 0:17 ` Dhinakaran Pandiyan
2019-10-05 0:20 ` Matt Roper
2019-10-08 23:18 ` Sripada, Radhakrishna
2019-09-24 0:29 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev2) Patchwork
2019-09-24 1:06 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-09-28 0:05 ` ✗ Fi.CI.CHECKPATCH: warning for Clear Color Support for TGL Render Decompression (rev3) Patchwork
2019-09-28 0:44 ` ✗ Fi.CI.BAT: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=bfbedcb02668ba8c2bfaaf0c2f10ccb79311b4db.camel@intel.com \
--to=dhinakaran.pandiyan@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=kalyan.kondapally@intel.com \
--cc=nanley.g.chery@intel.com \
--cc=radhakrishna.sripada@intel.com \
--cc=ville.syrjala@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox