From: "Govindapillai, Vinod" <vinod.govindapillai@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/reg: fix QGV points register access offsets
Date: Thu, 23 Mar 2023 11:48:50 +0000 [thread overview]
Message-ID: <c4f80d41e305914f2bdf89882872ac8c1d2ad1bb.camel@intel.com> (raw)
In-Reply-To: <ZBsSbERoJlz0KE9z@intel.com>
On Wed, 2023-03-22 at 16:36 +0200, Ville Syrjälä wrote:
> On Wed, Mar 22, 2023 at 04:20:50PM +0200, Vinod Govindapillai wrote:
> > Wrong offsets are calculated to read QGV point registers. Fix it
> > to read from the correct registers.
> >
> > v2: Avoid magic number and better handling the second bitgroup
> >
> > Bspec: 64602
> >
> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index d22ffd7a32dc..74468ed9dc9d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7724,12 +7724,13 @@ enum skl_power_gate {
> > #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
> > #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
> >
> > -#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(0x45710 + (point) * 2)
> > +#define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710
> > +#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point)
> > * 2 * 0x4)
> > #define MTL_TRCD_MASK REG_GENMASK(31, 24)
> > #define MTL_TRP_MASK REG_GENMASK(23, 16)
> > #define MTL_DCLK_MASK REG_GENMASK(15, 0)
> >
> > -#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(0x45714 + (point) * 2)
> > +#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + 4 +
> > (point) * 2 * 0x4)
>
> The normal style is to just do '(point) * 8' and '(point) * 8 + 4'
Thanks Ville. Update and v3 sent
BR
vinod
>
> > #define MTL_TRAS_MASK REG_GENMASK(16, 8)
> > #define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
> >
> > --
> > 2.34.1
>
next prev parent reply other threads:[~2023-03-23 11:48 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-22 14:20 [Intel-gfx] [PATCH v2 0/2] Correction to QGV related register addresses Vinod Govindapillai
2023-03-22 14:20 ` [Intel-gfx] [PATCH v2 1/2] drm/i915/reg: fix QGV points register access offsets Vinod Govindapillai
2023-03-22 14:36 ` Ville Syrjälä
2023-03-23 11:48 ` Govindapillai, Vinod [this message]
2023-03-22 14:20 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/reg: use the correct register to access SAGV block time Vinod Govindapillai
2023-03-22 15:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Correction to QGV related register addresses (rev2) Patchwork
2023-03-22 15:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-22 20:18 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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