Re: Speed boost disabling RCC clock gating ECO

[Chris Wilson <chris@chris-wilson.co.uk>]

On Sat, 30 Oct 2010 03:34:37 +0100, Peter Clifton <pcjc2@cam.ac.uk> wrote:
> Hi guys,
> 
> Just a note on a data-point I found here:
> 
> sudo intel_reg_read 0x21D0
> [sudo] password for pcjc2: 
> 0x21D0 : 0x307
> 
> sudo intel_reg_write 0x21D0 0x1000207
> Value before: 0x307
> Value after: 0x207
> 
> 
> This boosted FPS of my displaylist frame benchmark from 35fps to 37fps.
> 
> This was clearing bit 8 of ECOSKPD, which is controlling the following
> ECO:
> 
> Clock gating for the RCC (Disable one clock gate cell)

Bizarre, here that's documented as only being defined for Crestline. Maybe
they meant mobile parts? The impact would be to disable some powersaving
and maybe risk exceeding its thermal envelope.

> Any chance someone knows why the ECO is in place, or whether it is
> dangerous to disable?

They look fairly benign. A couple change the behaviour significantly that
could result in undefined behaviour if the driver exceeded the new limits.

> I also noticed that the specs for bit 12 and 9 (working around a CLIP
> bug) are set in an invalid state according to the G45 PRM.
> 
> I have bit 12=0, bit9=1

Well the good news is that those are intended to workaround silicon bugs
in Broadwater (965G) and Crestline (965GM).

> This does match the expected default setting though.. is there a typo in
> the PRM (Vol1a, P.322.) mixing bits 9 and 12 around in the table?

The bad news is that those were copied verbatim from the original. And
(1,0) is indeed supposed to be invalid. Aren't unexplained magic bits
exciting?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre