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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Vinod Govindapillai <vinod.govindapillai@intel.com>,
	intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: vinod.govindapillai@intel.com, ville.syrjala@intel.com,
	matthew.d.roper@intel.com, shawn.c.lee@intel.com
Subject: Re: [PATCH] drm/i915/display: update BW buddy initialization for LPDDR4 and LPDDR5
Date: Fri, 29 May 2026 16:39:13 +0300	[thread overview]
Message-ID: <d661dae5343e317fdf286194af4c5e707cbeea97@intel.com> (raw)
In-Reply-To: <20260528182601.205595-1-vinod.govindapillai@intel.com>

On Thu, 28 May 2026, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote:
> Pcode reports the number of subchannels for LPDDR4 and LPDDR5.
> But the page mask selection table is based on the channels. So
> adjust the number of channels for LPDDR4 and LPDDR5 so that the
> correct page mask can be picked. There are two subchannels per
> channel.

IMO the parsing of the information belongs in intel_dram.c. If you get
subchannels from pcode or where ever, intel_dram.c should figure it out,
and store the number of channels in ->num_channels.

If we need the subchannel info separately, we'll need to add the
subchannel info in struct dram_info.

BR,
Jani.



>
> Bspec: 68871
> Suggested-by: Ville Syrjala <ville.syrjala@intel.com>
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 2e51dfcd5dce..758ce1287cac 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1614,12 +1614,18 @@ static void tgl_bw_buddy_init(struct intel_display *display)
>  	const struct dram_info *dram_info = intel_dram_info(display);
>  	const struct buddy_page_mask *table;
>  	unsigned long abox_mask = DISPLAY_INFO(display)->abox_mask;
> +	u8 channels = dram_info->num_channels;
>  	int config, i;
>  
>  	/* BW_BUDDY registers are not used on dgpu's beyond DG1 */
>  	if (display->platform.dgfx && !display->platform.dg1)
>  		return;
>  
> +	/* For LPDDR4 / LPDDR5, pcode reports subchannels. */
> +	if (dram_info->type == INTEL_DRAM_LPDDR4 ||
> +	    dram_info->type == INTEL_DRAM_LPDDR5)
> +		channels /= 2;
> +
>  	if (intel_display_wa(display, INTEL_DISPLAY_WA_1409767108))
>  		/* Wa_1409767108 */
>  		table = wa_1409767108_buddy_page_masks;
> @@ -1627,7 +1633,7 @@ static void tgl_bw_buddy_init(struct intel_display *display)
>  		table = tgl_buddy_page_masks;
>  
>  	for (config = 0; table[config].page_mask != 0; config++)
> -		if (table[config].num_channels == dram_info->num_channels &&
> +		if (table[config].num_channels == channels &&
>  		    table[config].type == dram_info->type)
>  			break;

-- 
Jani Nikula, Intel

  parent reply	other threads:[~2026-05-29 13:39 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-28 18:26 [PATCH] drm/i915/display: update BW buddy initialization for LPDDR4 and LPDDR5 Vinod Govindapillai
2026-05-28 19:52 ` ✗ i915.CI.BAT: failure for " Patchwork
2026-05-29 13:26 ` ✓ i915.CI.BAT: success " Patchwork
2026-05-29 13:39 ` Jani Nikula [this message]
2026-05-29 15:20   ` [PATCH] " Ville Syrjälä
2026-05-29 15:46     ` Govindapillai, Vinod
2026-06-01 20:00       ` Govindapillai, Vinod
2026-05-30  0:48 ` ✓ i915.CI.Full: success for " Patchwork

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