From: "Souza, Jose" <jose.souza@intel.com>
To: "Gupta, Anshuman" <anshuman.gupta@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH v7 4/4] drm/i915: Add transcoder restriction to PSR2
Date: Mon, 12 Aug 2019 17:39:41 +0000 [thread overview]
Message-ID: <d8dd615dcacce3e039a31e86a6f04b946ec8d6ff.camel@intel.com> (raw)
In-Reply-To: <0d587aab-b706-fe1f-095a-002e51dab820@intel.com>
On Mon, 2019-08-12 at 19:20 +0530, Gupta, Anshuman wrote:
>
> On 7/31/2019 4:17 AM, José Roberto de Souza wrote:
> > According to PSR2_CTL definition on BSpec there is only one
> > instance
> > of PSR2_CTL also ICL display overview state that PSR2 is only
> > supported in EDP transcoder, so now that is possible to have PSR in
> > any transcoder lets add this hardware restriction.
> >
> > BSpec: 7713
> > BSpec: 20584
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index f06b4a0b9e26..526990767c52 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -545,6 +545,11 @@ static bool intel_psr2_config_valid(struct
> > intel_dp *intel_dp,
> > if (!dev_priv->psr.sink_psr2_support)
> > return false;
> >
> > + if (crtc_state->cpu_transcoder != TRANSCODER_EDP) {
> > + DRM_DEBUG_KMS("PSR2 is only supported in EDP
> > transcoder\n");
> > + return false;
> > + }
> > +
> TGL supports PSR2 on TRANSCODER_A, am i missing anything here?
That is right TGL support PSR2 on TRANSCODER_A, this series was being
sent before TGL was made public that is why this why only edp in here,
I will fix that in the next version but anyways there a few more PSR
patches to enable PSR on TGL.
> > /*
> > * DSC and PSR2 cannot be enabled simultaneously. If a
> > requested
> > * resolution requires DSC to be enabled, priority is given to
> > DSC
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2019-08-12 17:48 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-30 22:47 [PATCH v7 1/4] drm/i915/bdw+: Move misc display IRQ handling to it own function José Roberto de Souza
2019-07-30 22:47 ` [PATCH v7 2/4] drm/i915: Add _TRANS2() José Roberto de Souza
2019-08-06 23:31 ` Lucas De Marchi
2019-08-13 23:03 ` Souza, Jose
2019-07-30 22:47 ` [PATCH v7 3/4] drm/i915/psr: Make PSR registers relative to transcoders José Roberto de Souza
2019-07-30 22:47 ` [PATCH v7 4/4] drm/i915: Add transcoder restriction to PSR2 José Roberto de Souza
2019-08-12 13:50 ` Gupta, Anshuman
2019-08-12 17:39 ` Souza, Jose [this message]
2019-07-30 23:31 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v7,1/4] drm/i915/bdw+: Move misc display IRQ handling to it own function Patchwork
2019-07-30 23:51 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-01 14:15 ` ✓ Fi.CI.IGT: " Patchwork
2019-08-06 23:23 ` [PATCH v7 1/4] " Lucas De Marchi
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