From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
To: <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v3] drm/i915/dg2: Add performance workaround 18019455067
Date: Wed, 20 Jul 2022 11:19:18 +0300 [thread overview]
Message-ID: <ef543323-4341-77d8-d0b1-059331cf3ca4@intel.com> (raw)
In-Reply-To: <6bbebede-8e13-6e5c-75df-0e19c0bd51f0@intel.com>
Ping?
On 11/07/2022 14:30, Lionel Landwerlin wrote:
> Ping?
>
> On 30/06/2022 11:35, Lionel Landwerlin wrote:
>> The recommended number of stackIDs for Ray Tracing subsystem is 512
>> rather than 2048 (default HW programming).
>>
>> v2: Move the programming to dg2_ctx_gt_tuning_init() (Lucas)
>>
>> v3: Move programming to general_render_compute_wa_init() (Matt)
>>
>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++++
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 9 +++++++++
>> 2 files changed, 13 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> index 07ef111947b8c..12fc87b957425 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
>> @@ -1112,6 +1112,10 @@
>> #define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
>> #define RT_CTRL _MMIO(0xe530)
>> +#define RT_CTRL_NUMBER_OF_STACKIDS_MASK REG_GENMASK(6, 5)
>> +#define NUMBER_OF_STACKIDS_512 2
>> +#define NUMBER_OF_STACKIDS_1024 1
>> +#define NUMBER_OF_STACKIDS_2048 0
>> #define DIS_NULL_QUERY REG_BIT(10)
>> #define EU_PERF_CNTL1 _MMIO(0xe558)
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 3213c593a55f4..ea674e456cd76 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -2737,6 +2737,15 @@ general_render_compute_wa_init(struct
>> intel_engine_cs *engine, struct i915_wa_li
>> wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
>> wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
>> }
>> +
>> + if (IS_DG2(i915)) {
>> + /* Performance tuning for Ray-tracing */
>> + wa_write_clr_set(wal,
>> + RT_CTRL,
>> + RT_CTRL_NUMBER_OF_STACKIDS_MASK,
>> + REG_FIELD_PREP(RT_CTRL_NUMBER_OF_STACKIDS_MASK,
>> + NUMBER_OF_STACKIDS_512));
>> + }
>> }
>> static void
>
>
next prev parent reply other threads:[~2022-07-20 8:19 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-30 8:35 [Intel-gfx] [PATCH v3] drm/i915/dg2: Add performance workaround 18019455067 Lionel Landwerlin
2022-06-30 9:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Add performance workaround 18019455067 (rev3) Patchwork
2022-06-30 15:05 ` [Intel-gfx] [PATCH v3] drm/i915/dg2: Add performance workaround 18019455067 Lucas De Marchi
2022-06-30 20:41 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg2: Add performance workaround 18019455067 (rev3) Patchwork
2022-07-11 11:30 ` [Intel-gfx] [PATCH v3] drm/i915/dg2: Add performance workaround 18019455067 Lionel Landwerlin
2022-07-20 8:19 ` Lionel Landwerlin [this message]
2022-07-25 23:23 ` Matt Roper
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