* [Intel-wired-lan] [PATCH] igb: index regs_buff array via index variable
@ 2019-12-12 10:58 Vasyl Gomonovych
2019-12-12 18:49 ` David Miller
2019-12-13 0:48 ` Alexander Duyck
0 siblings, 2 replies; 4+ messages in thread
From: Vasyl Gomonovych @ 2019-12-12 10:58 UTC (permalink / raw)
To: intel-wired-lan
This patch is just a preparation for additional register dump in regs_buff.
To make new register insertion in the middle of regs_buff array easier
change array indexing to use local counter reg_ix.
---
Basically this path is just a subject to ask
How to add a new register to dump from dataseet
Because it is logically better to add an additional register
in the middle of an array but that will break ABI.
To not have the ABI problem we should just add it at the
end of the array and increase the array size.
---
Signed-off-by: Vasyl Gomonovych <gomonovych@gmail.com>
---
drivers/net/ethernet/intel/igb/igb_ethtool.c | 110 ++++++++++---------
1 file changed, 57 insertions(+), 53 deletions(-)
diff --git a/drivers/net/ethernet/intel/igb/igb_ethtool.c b/drivers/net/ethernet/intel/igb/igb_ethtool.c
index 3182b059bf55..4531f7ea9d99 100644
--- a/drivers/net/ethernet/intel/igb/igb_ethtool.c
+++ b/drivers/net/ethernet/intel/igb/igb_ethtool.c
@@ -459,6 +459,7 @@ static void igb_get_regs(struct net_device *netdev,
struct e1000_hw *hw = &adapter->hw;
u32 *regs_buff = p;
u8 i;
+ int reg_ix = 0;
memset(p, 0, IGB_REGS_LEN * sizeof(u32));
@@ -603,116 +604,119 @@ static void igb_get_regs(struct net_device *netdev,
regs_buff[119] = adapter->stats.scvpc;
regs_buff[120] = adapter->stats.hrmpc;
+ reg_ix = 121;
for (i = 0; i < 4; i++)
- regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
+ regs_buff[reg_ix++] = rd32(E1000_SRRCTL(i));
for (i = 0; i < 4; i++)
- regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
+ regs_buff[reg_ix++] = rd32(E1000_PSRTYPE(i));
for (i = 0; i < 4; i++)
- regs_buff[129 + i] = rd32(E1000_RDBAL(i));
+ regs_buff[reg_ix++] = rd32(E1000_RDBAL(i));
for (i = 0; i < 4; i++)
- regs_buff[133 + i] = rd32(E1000_RDBAH(i));
+ regs_buff[reg_ix++] = rd32(E1000_RDBAH(i));
for (i = 0; i < 4; i++)
- regs_buff[137 + i] = rd32(E1000_RDLEN(i));
+ regs_buff[reg_ix++] = rd32(E1000_RDLEN(i));
for (i = 0; i < 4; i++)
- regs_buff[141 + i] = rd32(E1000_RDH(i));
+ regs_buff[reg_ix++] = rd32(E1000_RDH(i));
for (i = 0; i < 4; i++)
- regs_buff[145 + i] = rd32(E1000_RDT(i));
+ regs_buff[reg_ix++] = rd32(E1000_RDT(i));
for (i = 0; i < 4; i++)
- regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
+ regs_buff[reg_ix++] = rd32(E1000_RXDCTL(i));
for (i = 0; i < 10; i++)
- regs_buff[153 + i] = rd32(E1000_EITR(i));
+ regs_buff[reg_ix++] = rd32(E1000_EITR(i));
for (i = 0; i < 8; i++)
- regs_buff[163 + i] = rd32(E1000_IMIR(i));
+ regs_buff[reg_ix++] = rd32(E1000_IMIR(i));
for (i = 0; i < 8; i++)
- regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
+ regs_buff[reg_ix++] = rd32(E1000_IMIREXT(i));
for (i = 0; i < 16; i++)
- regs_buff[179 + i] = rd32(E1000_RAL(i));
+ regs_buff[reg_ix++] = rd32(E1000_RAL(i));
for (i = 0; i < 16; i++)
- regs_buff[195 + i] = rd32(E1000_RAH(i));
+ regs_buff[reg_ix++] = rd32(E1000_RAH(i));
for (i = 0; i < 4; i++)
- regs_buff[211 + i] = rd32(E1000_TDBAL(i));
+ regs_buff[reg_ix++] = rd32(E1000_TDBAL(i));
for (i = 0; i < 4; i++)
- regs_buff[215 + i] = rd32(E1000_TDBAH(i));
+ regs_buff[reg_ix++] = rd32(E1000_TDBAH(i));
for (i = 0; i < 4; i++)
- regs_buff[219 + i] = rd32(E1000_TDLEN(i));
+ regs_buff[reg_ix++] = rd32(E1000_TDLEN(i));
for (i = 0; i < 4; i++)
- regs_buff[223 + i] = rd32(E1000_TDH(i));
+ regs_buff[reg_ix++] = rd32(E1000_TDH(i));
for (i = 0; i < 4; i++)
- regs_buff[227 + i] = rd32(E1000_TDT(i));
+ regs_buff[reg_ix++] = rd32(E1000_TDT(i));
for (i = 0; i < 4; i++)
- regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
+ regs_buff[reg_ix++] = rd32(E1000_TXDCTL(i));
for (i = 0; i < 4; i++)
- regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
+ regs_buff[reg_ix++] = rd32(E1000_TDWBAL(i));
for (i = 0; i < 4; i++)
- regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
+ regs_buff[reg_ix++] = rd32(E1000_TDWBAH(i));
for (i = 0; i < 4; i++)
- regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
+ regs_buff[reg_ix++] = rd32(E1000_DCA_TXCTRL(i));
for (i = 0; i < 4; i++)
- regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
+ regs_buff[reg_ix++] = rd32(E1000_IP4AT_REG(i));
for (i = 0; i < 4; i++)
- regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
+ regs_buff[reg_ix++] = rd32(E1000_IP6AT_REG(i));
for (i = 0; i < 32; i++)
- regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
+ regs_buff[reg_ix++] = rd32(E1000_WUPM_REG(i));
for (i = 0; i < 128; i++)
- regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
+ regs_buff[reg_ix++] = rd32(E1000_FFMT_REG(i));
for (i = 0; i < 128; i++)
- regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
+ regs_buff[reg_ix++] = rd32(E1000_FFVT_REG(i));
for (i = 0; i < 4; i++)
- regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
+ regs_buff[reg_ix++] = rd32(E1000_FFLT_REG(i));
- regs_buff[547] = rd32(E1000_TDFH);
- regs_buff[548] = rd32(E1000_TDFT);
- regs_buff[549] = rd32(E1000_TDFHS);
- regs_buff[550] = rd32(E1000_TDFPC);
+ regs_buff[reg_ix++] = rd32(E1000_TDFH);
+ regs_buff[reg_ix++] = rd32(E1000_TDFT);
+ regs_buff[reg_ix++] = rd32(E1000_TDFHS);
+ regs_buff[reg_ix++] = rd32(E1000_TDFPC);
if (hw->mac.type > e1000_82580) {
- regs_buff[551] = adapter->stats.o2bgptc;
- regs_buff[552] = adapter->stats.b2ospc;
- regs_buff[553] = adapter->stats.o2bspc;
- regs_buff[554] = adapter->stats.b2ogprc;
+ regs_buff[reg_ix++] = adapter->stats.o2bgptc;
+ regs_buff[reg_ix++] = adapter->stats.b2ospc;
+ regs_buff[reg_ix++] = adapter->stats.o2bspc;
+ regs_buff[reg_ix++] = adapter->stats.b2ogprc;
}
+ reg_ix = 555;
if (hw->mac.type == e1000_82576) {
for (i = 0; i < 12; i++)
- regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
+ regs_buff[reg_ix++] = rd32(E1000_SRRCTL(i + 4));
for (i = 0; i < 4; i++)
- regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
+ regs_buff[reg_ix++] = rd32(E1000_PSRTYPE(i + 4));
for (i = 0; i < 12; i++)
- regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
+ regs_buff[reg_ix++] = rd32(E1000_RDBAL(i + 4));
for (i = 0; i < 12; i++)
- regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
+ regs_buff[reg_ix++] = rd32(E1000_RDBAH(i + 4));
for (i = 0; i < 12; i++)
- regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
+ regs_buff[reg_ix++] = rd32(E1000_RDLEN(i + 4));
for (i = 0; i < 12; i++)
- regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
+ regs_buff[reg_ix++] = rd32(E1000_RDH(i + 4));
for (i = 0; i < 12; i++)
- regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
+ regs_buff[reg_ix++] = rd32(E1000_RDT(i + 4));
for (i = 0; i < 12; i++)
- regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
+ regs_buff[reg_ix++] = rd32(E1000_RXDCTL(i + 4));
for (i = 0; i < 12; i++)
- regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
+ regs_buff[reg_ix++] = rd32(E1000_TDBAL(i + 4));
for (i = 0; i < 12; i++)
- regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
+ regs_buff[reg_ix++] = rd32(E1000_TDBAH(i + 4));
for (i = 0; i < 12; i++)
- regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
+ regs_buff[reg_ix++] = rd32(E1000_TDLEN(i + 4));
for (i = 0; i < 12; i++)
- regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
+ regs_buff[reg_ix++] = rd32(E1000_TDH(i + 4));
for (i = 0; i < 12; i++)
- regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
+ regs_buff[reg_ix++] = rd32(E1000_TDT(i + 4));
for (i = 0; i < 12; i++)
- regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
+ regs_buff[reg_ix++] = rd32(E1000_TXDCTL(i + 4));
for (i = 0; i < 12; i++)
- regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
+ regs_buff[reg_ix++] = rd32(E1000_TDWBAL(i + 4));
for (i = 0; i < 12; i++)
- regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
+ regs_buff[reg_ix++] = rd32(E1000_TDWBAH(i + 4));
}
+ reg_ix = 739;
if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211)
- regs_buff[739] = rd32(E1000_I210_RR2DCDELAY);
+ regs_buff[reg_ix] = rd32(E1000_I210_RR2DCDELAY);
}
static int igb_get_eeprom_len(struct net_device *netdev)
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [Intel-wired-lan] [PATCH] igb: index regs_buff array via index variable
2019-12-12 10:58 [Intel-wired-lan] [PATCH] igb: index regs_buff array via index variable Vasyl Gomonovych
@ 2019-12-12 18:49 ` David Miller
2019-12-13 0:48 ` Alexander Duyck
1 sibling, 0 replies; 4+ messages in thread
From: David Miller @ 2019-12-12 18:49 UTC (permalink / raw)
To: intel-wired-lan
From: Vasyl Gomonovych <gomonovych@gmail.com>
Date: Thu, 12 Dec 2019 11:58:47 +0100
> This patch is just a preparation for additional register dump in regs_buff.
> To make new register insertion in the middle of regs_buff array easier
> change array indexing to use local counter reg_ix.
>
> ---
>
> Basically this path is just a subject to ask
> How to add a new register to dump from dataseet
> Because it is logically better to add an additional register
> in the middle of an array but that will break ABI.
> To not have the ABI problem we should just add it at the
> end of the array and increase the array size.
>
> ---
>
> Signed-off-by: Vasyl Gomonovych <gomonovych@gmail.com>
Anything you put after "---" will be removed by git if someone actually
applies this patch, which means your signoff will disappear.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Intel-wired-lan] [PATCH] igb: index regs_buff array via index variable
2019-12-12 10:58 [Intel-wired-lan] [PATCH] igb: index regs_buff array via index variable Vasyl Gomonovych
2019-12-12 18:49 ` David Miller
@ 2019-12-13 0:48 ` Alexander Duyck
2019-12-13 11:25 ` Gomonovych, Vasyl
1 sibling, 1 reply; 4+ messages in thread
From: Alexander Duyck @ 2019-12-13 0:48 UTC (permalink / raw)
To: intel-wired-lan
On Thu, Dec 12, 2019 at 2:58 AM Vasyl Gomonovych <gomonovych@gmail.com> wrote:
>
> This patch is just a preparation for additional register dump in regs_buff.
> To make new register insertion in the middle of regs_buff array easier
> change array indexing to use local counter reg_ix.
>
> ---
>
> Basically this path is just a subject to ask
> How to add a new register to dump from dataseet
> Because it is logically better to add an additional register
> in the middle of an array but that will break ABI.
> To not have the ABI problem we should just add it at the
> end of the array and increase the array size.
So I am pretty sure the patch probably breaks ABI. The reasons for the
fixed offsets is because this driver supports multiple parts that have
different register sets so we cannot have them overlapping.
We cannot change the register locations because it will break the
interface with ethtool. If you need to add additional registers you
will need to add them to the end of the array.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Intel-wired-lan] [PATCH] igb: index regs_buff array via index variable
2019-12-13 0:48 ` Alexander Duyck
@ 2019-12-13 11:25 ` Gomonovych, Vasyl
0 siblings, 0 replies; 4+ messages in thread
From: Gomonovych, Vasyl @ 2019-12-13 11:25 UTC (permalink / raw)
To: intel-wired-lan
Ok, thanks for the clarification.
On Fri, 13 Dec 2019, 02:49 Alexander Duyck, <alexander.duyck@gmail.com>
wrote:
> On Thu, Dec 12, 2019 at 2:58 AM Vasyl Gomonovych <gomonovych@gmail.com>
> wrote:
> >
> > This patch is just a preparation for additional register dump in
> regs_buff.
> > To make new register insertion in the middle of regs_buff array easier
> > change array indexing to use local counter reg_ix.
> >
> > ---
> >
> > Basically this path is just a subject to ask
> > How to add a new register to dump from dataseet
> > Because it is logically better to add an additional register
> > in the middle of an array but that will break ABI.
> > To not have the ABI problem we should just add it at the
> > end of the array and increase the array size.
>
> So I am pretty sure the patch probably breaks ABI. The reasons for the
> fixed offsets is because this driver supports multiple parts that have
> different register sets so we cannot have them overlapping.
>
> We cannot change the register locations because it will break the
> interface with ethtool. If you need to add additional registers you
> will need to add them to the end of the array.
>
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2019-12-12 10:58 [Intel-wired-lan] [PATCH] igb: index regs_buff array via index variable Vasyl Gomonovych
2019-12-12 18:49 ` David Miller
2019-12-13 0:48 ` Alexander Duyck
2019-12-13 11:25 ` Gomonovych, Vasyl
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