From: Maciej Machnikowski <maciej.machnikowski@intel.com>
To: intel-wired-lan@osuosl.org
Subject: [Intel-wired-lan] [PATCH intel-next 1/4] ice: Refactor ice_aqc_link_topo_addr
Date: Mon, 16 Aug 2021 12:27:26 +0200 [thread overview]
Message-ID: <20210816102729.1266522-2-maciej.machnikowski@intel.com> (raw)
In-Reply-To: <20210816102729.1266522-1-maciej.machnikowski@intel.com>
Separate link topo parameters and move to the ice_aqc_link_topo_params
in the ice_aqc_link_topo_addr.
Signed-off-by: Maciej Machnikowski <maciej.machnikowski@intel.com>
---
drivers/net/ethernet/intel/ice/ice_adminq_cmd.h | 6 +++++-
drivers/net/ethernet/intel/ice/ice_common.c | 8 +++++---
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
index 6c727745bb29..941342f4be85 100644
--- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
+++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h
@@ -1283,7 +1283,7 @@ struct ice_aqc_set_mac_lb {
u8 reserved[15];
};
-struct ice_aqc_link_topo_addr {
+struct ice_aqc_link_topo_params {
u8 lport_num;
u8 lport_num_valid;
#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
@@ -1309,6 +1309,10 @@ struct ice_aqc_link_topo_addr {
#define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
#define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
u8 index;
+};
+
+struct ice_aqc_link_topo_addr {
+ struct ice_aqc_link_topo_params topo_params;
__le16 handle;
#define ICE_AQC_LINK_TOPO_HANDLE_S 0
#define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c
index 1a3c6b60fdca..5822589aebdc 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.c
+++ b/drivers/net/ethernet/intel/ice/ice_common.c
@@ -240,11 +240,13 @@ ice_aq_get_link_topo_handle(struct ice_port_info *pi, u8 node_type,
ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
- cmd->addr.node_type_ctx = (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
- ICE_AQC_LINK_TOPO_NODE_CTX_S);
+ cmd->addr.topo_params.node_type_ctx =
+ (ICE_AQC_LINK_TOPO_NODE_CTX_PORT <<
+ ICE_AQC_LINK_TOPO_NODE_CTX_S);
/* set node type */
- cmd->addr.node_type_ctx |= (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
+ cmd->addr.topo_params.node_type_ctx |=
+ (ICE_AQC_LINK_TOPO_NODE_TYPE_M & node_type);
return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
}
--
2.26.3
next prev parent reply other threads:[~2021-08-16 10:27 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-16 10:27 [Intel-wired-lan] [PATCH intel-next 0/4] Add support for E810-T PTP pins Maciej Machnikowski
2021-08-16 10:27 ` Maciej Machnikowski [this message]
2021-08-26 6:23 ` [Intel-wired-lan] [PATCH intel-next 1/4] ice: Refactor ice_aqc_link_topo_addr Mekala, SunithaX D
2021-08-26 6:31 ` Paul Menzel
2021-08-16 10:27 ` [Intel-wired-lan] [PATCH intel-next 2/4] ice: Implement functions for reading and setting GPIO pins Maciej Machnikowski
2021-08-16 23:49 ` Nguyen, Anthony L
2021-08-16 10:27 ` [Intel-wired-lan] [PATCH intel-next 3/4] ice: Add support for SMA control multiplexer Maciej Machnikowski
2021-08-16 23:59 ` Nguyen, Anthony L
2021-08-16 10:27 ` [Intel-wired-lan] [PATCH intel-next 4/4] ice: Implement support for SMA and U.FL on E810-T Maciej Machnikowski
2021-08-17 0:13 ` Nguyen, Anthony L
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