Re: [Intel-wired-lan] [PATCH 2/5] igc: remove I226 Qbv BaseTime restriction

[Tony Nguyen <anthony.l.nguyen@intel.com>]

On 10/29/2022 9:53 PM, Muhammad Husaini Zulkifli wrote:
> Remove the Qbv BaseTime restriction for I226 so that the BaseTime can be
> scheduled to the future time. A new register bit of Tx Qav Control
> (Bit-7: FutScdDis) was introduced to allow I226 scheduling future time as
> Qbv BaseTime and not having the Tx hang timeout issue.
> 
> Besides, according to datasheet section 7.5.2.9.3.3, FutScdDis bit has to
> be configured first before the cycle time and base time.
> 
> Indeed the FutScdDis bit is only active on re-configuration, thus we have
> to set the BASET_L to zero and then only set it to the desired value.
> 
> Please also note that the Qbv configuration flow is moved around based on
> the Qbv programming guideline that is documented in the latest datasheet.
> 
> Co-Developed-by : Tan Tee Min <tee.min.tan@linux.intel.com>

Nit: no space after the -by i.e. 'Co-Developed-by:'
However, if this doesn't need a revision outside of this, I'll fix it up 
myself.

> Signed-off-by: Tan Tee Min <tee.min.tan@linux.intel.com>
> Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com>
> ---

<snip>

> @@ -240,21 +232,43 @@ static int igc_tsn_enable_offload(struct igc_adapter *adapter)
>   		wr32(IGC_TXQCTL(i), txqctl);
>   	}
>   
> +	tqavctrl = rd32(IGC_TQAVCTRL);
> +	tqavctrl |= IGC_TQAVCTRL_TRANSMIT_MODE_TSN | IGC_TQAVCTRL_ENHANCED_QAV;
> +
> +	cycle = adapter->cycle_time;
> +	base_time = adapter->base_time;
> +
>   	nsec = rd32(IGC_SYSTIML);
>   	sec = rd32(IGC_SYSTIMH);
>   
>   	systim = ktime_set(sec, nsec);
> -
>   	if (ktime_compare(systim, base_time) > 0) {
> -		s64 n;
> +		s64 n = div64_s64(ktime_sub_ns(systim, base_time), cycle);
>   
> -		n = div64_s64(ktime_sub_ns(systim, base_time), cycle);
>   		base_time = ktime_add_ns(base_time, (n + 1) * cycle);
> +	} else {
> +		/* According to datasheet section 7.5.2.9.3.3, FutScdDis bit
> +		 * has to be configured before the cycle time and base time.
> +		 */
> +		if (igc_is_device_id_i226(hw))
> +			tqavctrl |= IGC_TQAVCTRL_FUTSCDDIS;
>   	}
>   
> -	baset_h = div_s64_rem(base_time, NSEC_PER_SEC, &baset_l);
> +	wr32(IGC_TQAVCTRL, tqavctrl);
> +
> +	wr32(IGC_QBVCYCLET_S, cycle);
> +	wr32(IGC_QBVCYCLET, cycle);
>   
> +	baset_h = div_s64_rem(base_time, NSEC_PER_SEC, &baset_l);
>   	wr32(IGC_BASET_H, baset_h);
> +
> +	/* In i226, Future base time is only supported when FutScdDis bit
> +	 * is enabled and only active for re-configuration.
> +	 * In this case, initialize the base time with zero to create
> +	 * "re-configuration" scenario then only set the desired base time.
> +	 */
> +	if (tqavctrl & IGC_TQAVCTRL_FUTSCDDIS)
> +		wr32(IGC_BASET_L, 0);
>   	wr32(IGC_BASET_L, baset_l);

Do you need to flush the registers?

>   	return 0;
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