[Intel-xe] [PATCH v9 00/11] Supporting RAS on XE

[Intel-xe] [PATCH v9 00/11] Supporting RAS on XE

[Himal Prasad Ghimiray]

Our platforms support Reliability, Availability and Serviceability(RAS).
In case of hardware errors, our hardwares provides the causes via
sending interrupt or pcie errors. The fatal errors are propogated 
as pci errors and non fatal errors as MSI. This series focuses on 
loging and updating counters for these errors, which will be  helpful to avoid, 
detect and repair hardware faults.

This [1] series proposes mechanism to expose this counters to userspace.
[1]: https://patchwork.freedesktop.org/series/118435/

The error counters  exposed by KMD will be used by L0/sysman 
They will be categorized to specific category of error in sysman:
https://spec.oneapi.io/level-zero/latest/sysman/api.html#ras

We have very limited capabilities for error injection to validate the
code flow.
Output of L3 fabric fatal injection from PVC is:
xe 0000:8c:00.0: [drm] *ERROR* [Hardware Error]: TILE0 detected GT FATAL error bit[0] is set
xe 0000:8c:00.0: [drm] *ERROR* [Hardware Error]: GT0 detected L3 FABRIC FATAL error. ERR_VECT_GT_FATAL[7]:0x00000087

v2
- Use different headers for error registers. (Nikula)
- Correctable errors shouldn't be considered as dmesg errors (Matt)
- Limit series to HW errors.(Aravind)

v3
- Rebase

v4
- Use xe_regs.h only for registers, move enums out of it.
- Make sure global data/structures are immutable.
- Avoid adding custom error logging macro's.
- Redesign the registers error name and counter index
structures for maintainability. (Nikula)

v5
- move struct hw_err_regs out of CONFIG_DRM_XE_DISPLAY.

v6
- Addressing Review comments from Aravind.

v7
- CI fixes.

v8
- Conditional check fixes.

v9
- Fix patch no.

Himal Prasad Ghimiray (4):
  drm/xe: Handle errors from various components.
  drm/xe: Add new helpers to log hardware errrors.
  drm/xe: Log and count the GT hardware errors.
  drm/xe: Support GT hardware error reporting for PVC.
  drm/xe: Support GSC hardware error reporting for PVC.
  drm/xe: Notify userspace about GSC HW errors.
  drm/xe: Support SOC FATAL error handling for PVC.
  drm/xe: Support SOC NONFATAL error handling for PVC.
  drm/xe: Handle MDFI error severity.
  drm/xe: Clear SOC CORRECTABLE error registers.
  drm/xe: Clear all SoC errors post warm reset.

 drivers/gpu/drm/xe/Makefile                  |   1 +
 drivers/gpu/drm/xe/regs/xe_gt_error_regs.h   |  29 +
 drivers/gpu/drm/xe/regs/xe_regs.h            |   4 +
 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  65 ++
 drivers/gpu/drm/xe/xe_device.c               |  13 +
 drivers/gpu/drm/xe/xe_device_types.h         |  23 +-
 drivers/gpu/drm/xe/xe_gt_printk.h            |   7 +
 drivers/gpu/drm/xe/xe_gt_types.h             |   6 +
 drivers/gpu/drm/xe/xe_hw_error.c             | 909 +++++++++++++++++++
 drivers/gpu/drm/xe/xe_hw_error.h             | 204 +++++
 drivers/gpu/drm/xe/xe_irq.c                  |   9 +
 drivers/gpu/drm/xe/xe_tile.c                 |   3 +
 include/uapi/drm/xe_drm.h                    |   9 +
 13 files changed, 1281 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
 create mode 100644 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
 create mode 100644 drivers/gpu/drm/xe/xe_hw_error.c
 create mode 100644 drivers/gpu/drm/xe/xe_hw_error.h

-- 
2.25.1

[Intel-xe] [PATCH v9 01/11] drm/xe: Handle errors from various components.

[Himal Prasad Ghimiray]

The GFX device reports two classes of errors: uncorrectable and
correctable. Depending on the severity uncorrectable errors are
further classified as non fatal and fatal. Driver will only handle
logging of errors and updating counters from various components within
the graphics device. Anything more will be handled at system level.

Correctable and NonFatal errors are reported as interrupts, bits in
the Master Interrupt Register will be used to convey the class of error.
Determine source of error (IP block) by reading the Device Error Source
Register (RW1C) that corresponds to the class of error being serviced

Fatal errors are reported as PCIe errors. When a PCIe error is asserted,
the OS will perform a device warm reset which causes the driver to
reload. The error registers are sticky and the values are maintained
through a warm reset. We read these registers during the boot flow of the
driver and increment the respective error counters.

Bspec: 50875, 53073, 53074, 53075, 53076

v6
- Limit the implementation to DG2 and PVC.
- Limit the tile level logging to only PVC.
- Use xarray instead of array for error counters.
- Squash the fatal error reporting patch with this patch.
- use drm_dbg instead of drm_info to dump register values.
- use XE_HW_ERR_UNSPEC for error which are reported by leaf registers.
- use source_typeoferror_errorname convention for enum and error loging.
- Clean unused enums and there are no display supported ras error,
categorize them as unknown.
- Dont make xe_assign_hw_err_regs static.
- Use err_name_index_pair instead of err_msg_cntr_pair.(Aravind)

v7
- Ci fix

v8
- Avoid unnecessary write if reg is empty incase of DG2.

v9
- For reg being blank print error for DG2 too.
- Maintain order of headers.
- Make XE_HW_ERR_UNSPEC 0. (Aravind)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/Makefile                  |   1 +
 drivers/gpu/drm/xe/regs/xe_regs.h            |   4 +
 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  13 +
 drivers/gpu/drm/xe/xe_device.c               |  10 +
 drivers/gpu/drm/xe/xe_device_types.h         |  13 +-
 drivers/gpu/drm/xe/xe_hw_error.c             | 256 +++++++++++++++++++
 drivers/gpu/drm/xe/xe_hw_error.h             |  52 ++++
 drivers/gpu/drm/xe/xe_irq.c                  |   4 +
 drivers/gpu/drm/xe/xe_tile.c                 |   2 +
 9 files changed, 354 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
 create mode 100644 drivers/gpu/drm/xe/xe_hw_error.c
 create mode 100644 drivers/gpu/drm/xe/xe_hw_error.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index cee57681732d..ed772f440689 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -77,6 +77,7 @@ xe-y += xe_bb.o \
 	xe_heci_gsc.o \
 	xe_hw_engine.o \
 	xe_hw_engine_class_sysfs.o \
+	xe_hw_error.o \
 	xe_hw_fence.o \
 	xe_huc.o \
 	xe_huc_debugfs.o \
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index 2240cd157603..a9611ec9cf96 100644
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -57,6 +57,9 @@
 
 #define SOFTWARE_FLAGS_SPR33			XE_REG(0x4f084)
 
+#define DEV_PCIEERR_STATUS			XE_REG(0x100180)
+#define   DEV_PCIEERR_IS_FATAL(x)		REG_BIT(x * 4 + 2)
+
 #define GU_CNTL					XE_REG(0x101010)
 #define   LMEM_INIT				REG_BIT(7)
 
@@ -95,6 +98,7 @@
 #define   GU_MISC_IRQ				REG_BIT(29)
 #define   DISPLAY_IRQ				REG_BIT(16)
 #define   GT_DW_IRQ(x)				REG_BIT(x)
+#define   XE_ERROR_IRQ(x)			REG_BIT(26 + (x))
 
 #define PVC_RP_STATE_CAP			XE_REG(0x281014)
 
diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
new file mode 100644
index 000000000000..ba5480fb2789
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+#ifndef XE_TILE_ERROR_REGS_H_
+#define XE_TILE_ERROR_REGS_H_
+
+#define _DEV_ERR_STAT_NONFATAL                         0x100178
+#define _DEV_ERR_STAT_CORRECTABLE                      0x10017c
+#define DEV_ERR_STAT_REG(x)                            XE_REG(_PICK_EVEN((x), \
+								_DEV_ERR_STAT_CORRECTABLE, \
+								_DEV_ERR_STAT_NONFATAL))
+#endif
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 8341acf66e5f..7b6487cfaf61 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -387,8 +387,18 @@ static void xe_device_remove_display(struct xe_device *xe)
 	xe_display_driver_remove(xe);
 }
 
+static void xe_hw_error_fini(struct xe_device *xe)
+{
+	struct xe_tile *tile;
+	int i;
+
+	for_each_tile(tile, xe, i)
+		xa_destroy(&tile->errors.hw_error);
+}
+
 void xe_device_remove(struct xe_device *xe)
 {
+	xe_hw_error_fini(xe);
 	xe_device_remove_display(xe);
 
 	xe_display_fini(xe);
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 44d622d4cc3a..d817016b4e38 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -13,8 +13,9 @@
 #include <drm/ttm/ttm_device.h>
 
 #include "xe_devcoredump_types.h"
-#include "xe_heci_gsc.h"
 #include "xe_gt_types.h"
+#include "xe_heci_gsc.h"
+#include "xe_hw_error.h"
 #include "xe_platform_types.h"
 #include "xe_pt_types.h"
 #include "xe_pmu.h"
@@ -190,6 +191,11 @@ struct xe_tile {
 
 	/** @sysfs: sysfs' kobj used by xe_tile_sysfs */
 	struct kobject *sysfs;
+
+	/** @errors: count of hardware errors reported for the tile */
+	struct tile_hw_errors {
+		struct xarray hw_error;
+	} errors;
 };
 
 /**
@@ -405,6 +411,11 @@ struct xe_device {
 	/** @heci_gsc: graphics security controller */
 	struct xe_heci_gsc heci_gsc;
 
+	/** @hw_err_regs: list of hw error regs*/
+	struct hardware_errors_regs {
+		const struct err_name_index_pair *dev_err_stat[HARDWARE_ERROR_MAX];
+	} hw_err_regs;
+
 	/* private: */
 
 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
new file mode 100644
index 000000000000..a4f2f00823ef
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include "xe_hw_error.h"
+
+#include "regs/xe_regs.h"
+#include "regs/xe_tile_error_regs.h"
+#include "xe_device.h"
+#include "xe_mmio.h"
+
+static const char *
+hardware_error_type_to_str(const enum hardware_error hw_err)
+{
+	switch (hw_err) {
+	case HARDWARE_ERROR_CORRECTABLE:
+		return "CORRECTABLE";
+	case HARDWARE_ERROR_NONFATAL:
+		return "NONFATAL";
+	case HARDWARE_ERROR_FATAL:
+		return "FATAL";
+	default:
+		return "UNKNOWN";
+	}
+}
+
+static const struct err_name_index_pair dg2_err_stat_fatal_reg[] = {
+	[0]         = {"GT",			XE_HW_ERR_TILE_UNSPEC},
+	[1 ... 3]   = {"Undefined",		XE_HW_ERR_TILE_FATAL_UNKNOWN},
+	[4 ... 7]   = {"Undefined",		XE_HW_ERR_TILE_FATAL_UNKNOWN},
+	[8]         = {"GSC",			XE_HW_ERR_TILE_UNSPEC},
+	[9 ... 11]  = {"Undefined",		XE_HW_ERR_TILE_FATAL_UNKNOWN},
+	[12]        = {"SGUNIT",		XE_HW_ERR_TILE_FATAL_SGUNIT},
+	[13 ... 15] = {"Undefined",             XE_HW_ERR_TILE_FATAL_UNKNOWN},
+	[16]        = {"SOC",			XE_HW_ERR_TILE_UNSPEC},
+	[17 ... 31] = {"Undefined",             XE_HW_ERR_TILE_FATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair dg2_err_stat_nonfatal_reg[] = {
+	[0]         = {"GT",			XE_HW_ERR_TILE_UNSPEC},
+	[1 ... 3]   = {"Undefined",		XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+	[4 ... 7]   = {"Undefined",		XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+	[8]         = {"GSC",			XE_HW_ERR_TILE_UNSPEC},
+	[9 ... 11]  = {"Undefined",		XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+	[12]        = {"SGUNIT",		XE_HW_ERR_TILE_NONFATAL_SGUNIT},
+	[13 ... 15] = {"Undefined",             XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+	[16]        = {"SOC",			XE_HW_ERR_TILE_UNSPEC},
+	[17 ... 19] = {"Undefined",             XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+	[20]        = {"MERT",			XE_HW_ERR_TILE_NONFATAL_MERT},
+	[21 ... 31] = {"Undefined",             XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair dg2_err_stat_correctable_reg[] = {
+	[0]         = {"GT",			XE_HW_ERR_TILE_UNSPEC},
+	[1 ... 3]   = {"Undefined",		XE_HW_ERR_TILE_CORR_UNKNOWN},
+	[4 ... 7]   = {"Undefined",		XE_HW_ERR_TILE_CORR_UNKNOWN},
+	[8]         = {"GSC",			XE_HW_ERR_TILE_UNSPEC},
+	[9 ... 11]  = {"Undefined",		XE_HW_ERR_TILE_CORR_UNKNOWN},
+	[12]        = {"SGUNIT",		XE_HW_ERR_TILE_CORR_SGUNIT},
+	[13 ... 15] = {"Undefined",             XE_HW_ERR_TILE_CORR_UNKNOWN},
+	[16]        = {"SOC",			XE_HW_ERR_TILE_UNSPEC},
+	[17 ... 31] = {"Undefined",             XE_HW_ERR_TILE_CORR_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_err_stat_fatal_reg[] = {
+	[0]         =  {"GT",			XE_HW_ERR_TILE_UNSPEC},
+	[1]         =  {"SGGI Cmd Parity",	XE_HW_ERR_TILE_FATAL_SGGI},
+	[2 ... 7]   =  {"Undefined",		XE_HW_ERR_TILE_FATAL_UNKNOWN},
+	[8]         =  {"GSC",			XE_HW_ERR_TILE_UNSPEC},
+	[9]         =  {"SGLI Cmd Parity",	XE_HW_ERR_TILE_FATAL_SGLI},
+	[10 ... 12] =  {"Undefined",		XE_HW_ERR_TILE_FATAL_UNKNOWN},
+	[13]        =  {"SGCI Cmd Parity",	XE_HW_ERR_TILE_FATAL_SGCI},
+	[14 ... 15] =  {"Undefined",		XE_HW_ERR_TILE_FATAL_UNKNOWN},
+	[16]        =  {"SOC ERROR",		XE_HW_ERR_TILE_UNSPEC},
+	[17 ... 19] =  {"Undefined",		XE_HW_ERR_TILE_FATAL_UNKNOWN},
+	[20]        =  {"MERT Cmd Parity",	XE_HW_ERR_TILE_FATAL_MERT},
+	[21 ... 31] =  {"Undefined",		XE_HW_ERR_TILE_FATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_err_stat_nonfatal_reg[] = {
+	[0]         =  {"GT",			XE_HW_ERR_TILE_UNSPEC},
+	[1]         =  {"SGGI Data Parity",	XE_HW_ERR_TILE_NONFATAL_SGGI},
+	[2 ... 7]   =  {"Undefined",		XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+	[8]         =  {"GSC",			XE_HW_ERR_TILE_UNSPEC},
+	[9]         =  {"SGLI Data Parity",	XE_HW_ERR_TILE_NONFATAL_SGLI},
+	[10 ... 12] =  {"Undefined",		XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+	[13]        =  {"SGCI Data Parity",	XE_HW_ERR_TILE_NONFATAL_SGCI},
+	[14 ... 15] =  {"Undefined",		XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+	[16]        =  {"SOC",			XE_HW_ERR_TILE_UNSPEC},
+	[17 ... 19] =  {"Undefined",		XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+	[20]        =  {"MERT Data Parity",	XE_HW_ERR_TILE_NONFATAL_MERT},
+	[21 ... 31] =  {"Undefined",            XE_HW_ERR_TILE_NONFATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_err_stat_correctable_reg[] = {
+	[0]         =  {"GT",			XE_HW_ERR_TILE_UNSPEC},
+	[1 ... 7]   =  {"Undefined",		XE_HW_ERR_TILE_CORR_UNKNOWN},
+	[8]         =  {"GSC",			XE_HW_ERR_TILE_UNSPEC},
+	[9 ... 31]  =  {"Undefined",		XE_HW_ERR_TILE_CORR_UNKNOWN},
+};
+
+void xe_assign_hw_err_regs(struct xe_device *xe)
+{
+	const struct err_name_index_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
+
+	/* Error reporting is supported only for DG2 and PVC currently. */
+	if (xe->info.platform == XE_DG2) {
+		dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = dg2_err_stat_correctable_reg;
+		dev_err_stat[HARDWARE_ERROR_NONFATAL] = dg2_err_stat_nonfatal_reg;
+		dev_err_stat[HARDWARE_ERROR_FATAL] = dg2_err_stat_fatal_reg;
+	}
+
+	if (xe->info.platform == XE_PVC) {
+		dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = pvc_err_stat_correctable_reg;
+		dev_err_stat[HARDWARE_ERROR_NONFATAL] = pvc_err_stat_nonfatal_reg;
+		dev_err_stat[HARDWARE_ERROR_FATAL] = pvc_err_stat_fatal_reg;
+	}
+}
+
+static bool xe_platform_has_ras(struct xe_device *xe)
+{
+	if (xe->info.platform == XE_PVC || xe->info.platform == XE_DG2)
+		return true;
+
+	return false;
+}
+
+static void
+xe_update_hw_error_cnt(struct drm_device *drm, struct xarray *hw_error, unsigned long index)
+{
+	unsigned long flags;
+	void *entry;
+
+	entry = xa_load(hw_error, index);
+	entry = xa_mk_value(xa_to_value(entry) + 1);
+
+	xa_lock_irqsave(hw_error, flags);
+	if (xa_is_err(__xa_store(hw_error, index, entry, GFP_ATOMIC)))
+		drm_err_ratelimited(drm,
+				    HW_ERR "Error reported by index %ld is lost\n", index);
+	xa_unlock_irqrestore(hw_error, flags);
+}
+
+static void
+xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
+{
+	const char *hw_err_str = hardware_error_type_to_str(hw_err);
+	const struct hardware_errors_regs *err_regs;
+	const struct err_name_index_pair *errstat;
+	unsigned long errsrc;
+	unsigned long flags;
+	const char *name;
+	struct xe_gt *gt;
+	u32 indx;
+	u32 errbit;
+
+	if (!xe_platform_has_ras(tile_to_xe(tile)))
+		return;
+
+	spin_lock_irqsave(&tile_to_xe(tile)->irq.lock, flags);
+	err_regs = &tile_to_xe(tile)->hw_err_regs;
+	errstat = err_regs->dev_err_stat[hw_err];
+	gt = tile->primary_gt;
+	errsrc = xe_mmio_read32(gt, DEV_ERR_STAT_REG(hw_err));
+	if (!errsrc) {
+		drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
+				    "TILE%d reported DEV_ERR_STAT_REG_%s blank!\n",
+				    tile->id, hw_err_str);
+		goto unlock;
+	}
+
+	if (tile_to_xe(tile)->info.platform != XE_DG2)
+		drm_dbg(&tile_to_xe(tile)->drm, HW_ERR
+			"TILE%d reported DEV_ERR_STAT_REG_%s=0x%08lx\n",
+			tile->id, hw_err_str, errsrc);
+
+	for_each_set_bit(errbit, &errsrc, XE_RAS_REG_SIZE) {
+		name = errstat[errbit].name;
+		indx = errstat[errbit].index;
+
+		if (hw_err == HARDWARE_ERROR_CORRECTABLE &&
+		    tile_to_xe(tile)->info.platform != XE_DG2)
+			drm_warn(&tile_to_xe(tile)->drm,
+				 HW_ERR "TILE%d reported %s %s error, bit[%d] is set\n",
+				 tile->id, name, hw_err_str, errbit);
+
+		else if (tile_to_xe(tile)->info.platform != XE_DG2)
+			drm_err_ratelimited(&tile_to_xe(tile)->drm,
+					    HW_ERR "TILE%d reported %s %s error, bit[%d] is set\n",
+					    tile->id, name, hw_err_str, errbit);
+
+		if (indx != XE_HW_ERR_TILE_UNSPEC)
+			xe_update_hw_error_cnt(&tile_to_xe(tile)->drm,
+					       &tile->errors.hw_error, indx);
+	}
+
+	xe_mmio_write32(gt, DEV_ERR_STAT_REG(hw_err), errsrc);
+unlock:
+	spin_unlock_irqrestore(&tile_to_xe(tile)->irq.lock, flags);
+}
+
+/*
+ * XE Platforms adds three Error bits to the Master Interrupt
+ * Register to support error handling. These three bits are
+ * used to convey the class of error:
+ * FATAL, NONFATAL, or CORRECTABLE.
+ *
+ * To process an interrupt:
+ *       Determine source of error (IP block) by reading
+ *	 the Device Error Source Register (RW1C) that
+ *	 corresponds to the class of error being serviced
+ *	 and log the error.
+ */
+void
+xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl)
+{
+	enum hardware_error hw_err;
+
+	for (hw_err = 0; hw_err < HARDWARE_ERROR_MAX; hw_err++) {
+		if (master_ctl & XE_ERROR_IRQ(hw_err))
+			xe_hw_error_source_handler(tile, hw_err);
+	}
+}
+
+/*
+ * xe_process_hw_errors - checks for the occurrence of HW errors
+ *
+ * Fatal will result in a card warm reset and driver will be reloaded.
+ * This checks for the HW Errors that might have occurred in the
+ * previous boot of the driver.
+ */
+void xe_process_hw_errors(struct xe_device *xe)
+{
+	struct xe_tile *root_tile = xe_device_get_root_tile(xe);
+	struct xe_gt *root_gt = root_tile->primary_gt;
+
+	u32 dev_pcieerr_status, master_ctl;
+	struct xe_tile *tile;
+	int i;
+
+	dev_pcieerr_status = xe_mmio_read32(root_gt, DEV_PCIEERR_STATUS);
+
+	for_each_tile(tile, xe, i) {
+		struct xe_gt *gt = tile->primary_gt;
+
+		if (dev_pcieerr_status & DEV_PCIEERR_IS_FATAL(i))
+			xe_hw_error_source_handler(tile, HARDWARE_ERROR_FATAL);
+
+		master_ctl = xe_mmio_read32(gt, GFX_MSTR_IRQ);
+		xe_hw_error_irq_handler(tile, master_ctl);
+		xe_mmio_write32(gt, GFX_MSTR_IRQ, master_ctl);
+	}
+	if (dev_pcieerr_status)
+		xe_mmio_write32(root_gt, DEV_PCIEERR_STATUS, dev_pcieerr_status);
+}
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
new file mode 100644
index 000000000000..1932f64e26da
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+#ifndef XE_HW_ERRORS_H_
+#define XE_HW_ERRORS_H_
+
+#include <linux/stddef.h>
+#include <linux/types.h>
+
+#define XE_RAS_REG_SIZE 32
+
+/* Error categories reported by hardware */
+enum hardware_error {
+	HARDWARE_ERROR_CORRECTABLE = 0,
+	HARDWARE_ERROR_NONFATAL = 1,
+	HARDWARE_ERROR_FATAL = 2,
+	HARDWARE_ERROR_MAX,
+};
+
+/* Count of Correctable and Uncorrectable errors reported on tile */
+enum xe_tile_hw_errors {
+	XE_HW_ERR_TILE_UNSPEC = 0,
+	XE_HW_ERR_TILE_FATAL_SGGI,
+	XE_HW_ERR_TILE_FATAL_SGLI,
+	XE_HW_ERR_TILE_FATAL_SGUNIT,
+	XE_HW_ERR_TILE_FATAL_SGCI,
+	XE_HW_ERR_TILE_FATAL_MERT,
+	XE_HW_ERR_TILE_FATAL_UNKNOWN,
+	XE_HW_ERR_TILE_NONFATAL_SGGI,
+	XE_HW_ERR_TILE_NONFATAL_SGLI,
+	XE_HW_ERR_TILE_NONFATAL_SGUNIT,
+	XE_HW_ERR_TILE_NONFATAL_SGCI,
+	XE_HW_ERR_TILE_NONFATAL_MERT,
+	XE_HW_ERR_TILE_NONFATAL_UNKNOWN,
+	XE_HW_ERR_TILE_CORR_SGUNIT,
+	XE_HW_ERR_TILE_CORR_UNKNOWN,
+};
+
+struct err_name_index_pair {
+	const char *name;
+	const u32 index;
+};
+
+struct xe_device;
+struct xe_tile;
+
+void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);
+void xe_assign_hw_err_regs(struct xe_device *xe);
+void xe_process_hw_errors(struct xe_device *xe);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 61350ed32c61..8365a4cb0c45 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -444,6 +444,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
 		xe_mmio_write32(mmio, GFX_MSTR_IRQ, master_ctl);
 
 		gt_irq_handler(tile, master_ctl, intr_dw, identity);
+		xe_hw_error_irq_handler(tile, master_ctl);
 
 		/*
 		 * Display interrupts (including display backlight operations
@@ -619,6 +620,9 @@ int xe_irq_install(struct xe_device *xe)
 		return -EINVAL;
 	}
 
+	xe_assign_hw_err_regs(xe);
+	xe_process_hw_errors(xe);
+
 	xe_irq_reset(xe);
 
 	err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_MSIX);
diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
index 131752a57f65..bc79145eadc0 100644
--- a/drivers/gpu/drm/xe/xe_tile.c
+++ b/drivers/gpu/drm/xe/xe_tile.c
@@ -84,6 +84,8 @@ int xe_tile_alloc(struct xe_tile *tile)
 {
 	struct drm_device *drm = &tile_to_xe(tile)->drm;
 
+	xa_init(&tile->errors.hw_error);
+
 	tile->mem.ggtt = drmm_kzalloc(drm, sizeof(*tile->mem.ggtt),
 				      GFP_KERNEL);
 	if (!tile->mem.ggtt)
-- 
2.25.1

[Intel-xe] [PATCH v1 02/11] drm/xe: Add new helpers to log hardware errrors.

[Himal Prasad Ghimiray]

Introducing xe_gt_log_hw_err and xe_gt_log_hw_err helper to
report gt specific hardware errors.

Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/xe_gt_printk.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h
index 5991bcadd47e..10e5c4a23c34 100644
--- a/drivers/gpu/drm/xe/xe_gt_printk.h
+++ b/drivers/gpu/drm/xe/xe_gt_printk.h
@@ -43,4 +43,11 @@
 #define xe_gt_WARN_ON_ONCE(_gt, _condition) \
 	xe_gt_WARN_ONCE((_gt), _condition, "%s(%s)", "gt_WARN_ON_ONCE", __stringify(_condition))
 
+#define xe_gt_log_hw_err(gt, fmt, ...) \
+	drm_err_ratelimited(&gt_to_xe(gt)->drm, HW_ERR "GT%d reported " fmt, \
+			    gt->info.id, ##__VA_ARGS__)
+
+#define xe_gt_log_hw_warn(gt, fmt, ...) \
+	drm_warn(&gt_to_xe(gt)->drm, HW_ERR "GT%d detected " fmt, gt->info.id, ##__VA_ARGS__)
+
 #endif
-- 
2.25.1

[Intel-xe] [PATCH v8 03/11] drm/xe: Log and count the GT hardware errors.

[Himal Prasad Ghimiray]

For the errors reported by GT unit, read the GT error register.
Log and count these errors and clear the error register.

Bspec: 53088, 53089, 53090

v6
- define the BIT and use it.
- Limit the GT error reporting to DG2 and PVC only.
- Rename function to xe_gt_hw_error_log_status_reg from
  xe_gt_hw_error_status_reg_handler. (Aravind)

v7
- ci fixes

v8
- Initialize xarray only for primary gt.
- maintain header orders.
- Use new defined helper for gt error loging. (Aravind)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_error_regs.h   | 13 +++
 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  1 +
 drivers/gpu/drm/xe/xe_device.c               |  5 +-
 drivers/gpu/drm/xe/xe_device_types.h         |  1 +
 drivers/gpu/drm/xe/xe_gt_types.h             |  6 ++
 drivers/gpu/drm/xe/xe_hw_error.c             | 94 +++++++++++++++++++-
 drivers/gpu/drm/xe/xe_hw_error.h             | 24 +++++
 drivers/gpu/drm/xe/xe_tile.c                 |  1 +
 8 files changed, 143 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_gt_error_regs.h

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
new file mode 100644
index 000000000000..6180704a6149
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+#ifndef XE_GT_ERROR_REGS_H_
+#define XE_GT_ERROR_REGS_H_
+
+#define _ERR_STAT_GT_COR                0x100160
+#define _ERR_STAT_GT_NONFATAL           0x100164
+#define ERR_STAT_GT_REG(x)              XE_REG(_PICK_EVEN((x), \
+						_ERR_STAT_GT_COR, \
+						_ERR_STAT_GT_NONFATAL))
+#endif
diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
index ba5480fb2789..45bd6b85e115 100644
--- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
@@ -10,4 +10,5 @@
 #define DEV_ERR_STAT_REG(x)                            XE_REG(_PICK_EVEN((x), \
 								_DEV_ERR_STAT_CORRECTABLE, \
 								_DEV_ERR_STAT_NONFATAL))
+#define   XE_GT_ERROR				       0
 #endif
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 7b6487cfaf61..628cb46a2509 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -392,8 +392,11 @@ static void xe_hw_error_fini(struct xe_device *xe)
 	struct xe_tile *tile;
 	int i;
 
-	for_each_tile(tile, xe, i)
+	for_each_tile(tile, xe, i) {
 		xa_destroy(&tile->errors.hw_error);
+		xa_destroy(&tile->primary_gt->errors.hw_error);
+	}
+
 }
 
 void xe_device_remove(struct xe_device *xe)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index d817016b4e38..675cf0c00be2 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -414,6 +414,7 @@ struct xe_device {
 	/** @hw_err_regs: list of hw error regs*/
 	struct hardware_errors_regs {
 		const struct err_name_index_pair *dev_err_stat[HARDWARE_ERROR_MAX];
+		const struct err_name_index_pair *err_stat_gt[HARDWARE_ERROR_MAX];
 	} hw_err_regs;
 
 	/* private: */
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index d3f2793684e2..f6ef1e381d55 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -9,6 +9,7 @@
 #include "xe_force_wake_types.h"
 #include "xe_gt_idle_sysfs_types.h"
 #include "xe_hw_engine_types.h"
+#include "xe_hw_error.h"
 #include "xe_hw_fence_types.h"
 #include "xe_reg_sr_types.h"
 #include "xe_sa_types.h"
@@ -347,6 +348,11 @@ struct xe_gt {
 		/** @oob: bitmap with active OOB workaroudns */
 		unsigned long *oob;
 	} wa_active;
+
+	/** @errors: count of hardware errors reported for the gt */
+	struct gt_hw_errors {
+		struct xarray hw_error;
+	} errors;
 };
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index a4f2f00823ef..c4bc24a35231 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -6,6 +6,7 @@
 #include "xe_hw_error.h"
 
 #include "regs/xe_regs.h"
+#include "regs/xe_gt_error_regs.h"
 #include "regs/xe_tile_error_regs.h"
 #include "xe_device.h"
 #include "xe_mmio.h"
@@ -100,15 +101,48 @@ static const struct err_name_index_pair pvc_err_stat_correctable_reg[] = {
 	[9 ... 31]  =  {"Undefined",		XE_HW_ERR_TILE_CORR_UNKNOWN},
 };
 
+static const struct err_name_index_pair dg2_stat_gt_fatal_reg[] = {
+	[0]         =  {"Undefined",		XE_HW_ERR_GT_FATAL_UNKNOWN},
+	[1]         =  {"Array BIST",		XE_HW_ERR_GT_FATAL_ARR_BIST},
+	[2]         =  {"Undefined",		XE_HW_ERR_GT_FATAL_UNKNOWN},
+	[3]         =  {"FPU",			XE_HW_ERR_GT_FATAL_FPU},
+	[4]         =  {"L3 Double",		XE_HW_ERR_GT_FATAL_L3_DOUB},
+	[5]         =  {"L3 ECC Checker",	XE_HW_ERR_GT_FATAL_L3_ECC_CHK},
+	[6]         =  {"GUC SRAM",		XE_HW_ERR_GT_FATAL_GUC},
+	[7]         =  {"Undefined",		XE_HW_ERR_GT_FATAL_UNKNOWN},
+	[8]         =  {"IDI PARITY",		XE_HW_ERR_GT_FATAL_IDI_PAR},
+	[9]	    =  {"SQIDI",		XE_HW_ERR_GT_FATAL_SQIDI},
+	[10 ... 11] =  {"Undefined",		XE_HW_ERR_GT_FATAL_UNKNOWN},
+	[12]        =  {"SAMPLER",		XE_HW_ERR_GT_FATAL_SAMPLER},
+	[13]        =  {"SLM",			XE_HW_ERR_GT_FATAL_SLM},
+	[14]        =  {"EU IC",		XE_HW_ERR_GT_FATAL_EU_IC},
+	[15]        =  {"EU GRF",		XE_HW_ERR_GT_FATAL_EU_GRF},
+	[16 ... 31] =  {"Undefined",            XE_HW_ERR_GT_FATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair dg2_stat_gt_correctable_reg[] = {
+	[0]         = {"L3 SINGLE",		XE_HW_ERR_GT_CORR_L3_SNG},
+	[1]         = {"SINGLE BIT GUC SRAM",	XE_HW_ERR_GT_CORR_GUC},
+	[2 ... 11]  = {"Undefined",		XE_HW_ERR_GT_CORR_UNKNOWN},
+	[12]        = {"SINGLE BIT SAMPLER",	XE_HW_ERR_GT_CORR_SAMPLER},
+	[13]        = {"SINGLE BIT SLM",	XE_HW_ERR_GT_CORR_SLM},
+	[14]        = {"SINGLE BIT EU IC",	XE_HW_ERR_GT_CORR_EU_IC},
+	[15]        = {"SINGLE BIT EU GRF",	XE_HW_ERR_GT_CORR_EU_GRF},
+	[16 ... 31] = {"Undefined",             XE_HW_ERR_GT_CORR_UNKNOWN},
+};
+
 void xe_assign_hw_err_regs(struct xe_device *xe)
 {
 	const struct err_name_index_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
+	const struct err_name_index_pair **err_stat_gt = xe->hw_err_regs.err_stat_gt;
 
 	/* Error reporting is supported only for DG2 and PVC currently. */
 	if (xe->info.platform == XE_DG2) {
 		dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = dg2_err_stat_correctable_reg;
 		dev_err_stat[HARDWARE_ERROR_NONFATAL] = dg2_err_stat_nonfatal_reg;
 		dev_err_stat[HARDWARE_ERROR_FATAL] = dg2_err_stat_fatal_reg;
+		err_stat_gt[HARDWARE_ERROR_CORRECTABLE] = dg2_stat_gt_correctable_reg;
+		err_stat_gt[HARDWARE_ERROR_FATAL] = dg2_stat_gt_fatal_reg;
 	}
 
 	if (xe->info.platform == XE_PVC) {
@@ -116,6 +150,7 @@ void xe_assign_hw_err_regs(struct xe_device *xe)
 		dev_err_stat[HARDWARE_ERROR_NONFATAL] = pvc_err_stat_nonfatal_reg;
 		dev_err_stat[HARDWARE_ERROR_FATAL] = pvc_err_stat_fatal_reg;
 	}
+
 }
 
 static bool xe_platform_has_ras(struct xe_device *xe)
@@ -142,6 +177,62 @@ xe_update_hw_error_cnt(struct drm_device *drm, struct xarray *hw_error, unsigned
 	xa_unlock_irqrestore(hw_error, flags);
 }
 
+static void
+xe_gt_hw_error_log_status_reg(struct xe_gt *gt, const enum hardware_error hw_err)
+{
+	const char *hw_err_str = hardware_error_type_to_str(hw_err);
+	const struct err_name_index_pair *errstat;
+	struct hardware_errors_regs *err_regs;
+	unsigned long errsrc;
+	const char *name;
+	u32 indx;
+	u32 errbit;
+
+	err_regs = &gt_to_xe(gt)->hw_err_regs;
+	errsrc = xe_mmio_read32(gt, ERR_STAT_GT_REG(hw_err));
+	if (!errsrc) {
+		xe_gt_log_hw_err(gt, "ERR_STAT_GT_REG_%s blank!\n", hw_err_str);
+		return;
+	}
+
+	drm_dbg(&gt_to_xe(gt)->drm, HW_ERR "GT%d ERR_STAT_GT_REG_%s=0x%08lx\n",
+		gt->info.id, hw_err_str, errsrc);
+
+	if (hw_err == HARDWARE_ERROR_NONFATAL) {
+		/*  The GT Non Fatal Error Status Register has only reserved bits
+		 *  Nothing to service.
+		 */
+		xe_gt_log_hw_err(gt, "%s error\n", hw_err_str);
+		goto clear_reg;
+	}
+
+	errstat = err_regs->err_stat_gt[hw_err];
+	for_each_set_bit(errbit, &errsrc, XE_RAS_REG_SIZE) {
+		name = errstat[errbit].name;
+		indx = errstat[errbit].index;
+
+		if (hw_err == HARDWARE_ERROR_FATAL)
+			xe_gt_log_hw_err(gt, "%s %s error, bit[%d] is set\n",
+					 name, hw_err_str, errbit);
+		else
+			xe_gt_log_hw_err(gt, "%s %s error, bit[%d] is set\n",
+					 name, hw_err_str, errbit);
+
+		xe_update_hw_error_cnt(&gt_to_xe(gt)->drm, &gt->errors.hw_error, indx);
+	}
+clear_reg:
+	xe_mmio_write32(gt, ERR_STAT_GT_REG(hw_err), errsrc);
+}
+
+static void
+xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
+{
+	lockdep_assert_held(&gt_to_xe(gt)->irq.lock);
+
+	if (gt_to_xe(gt)->info.platform == XE_DG2)
+		xe_gt_hw_error_log_status_reg(gt, hw_err);
+}
+
 static void
 xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 {
@@ -193,8 +284,9 @@ xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_er
 		if (indx != XE_HW_ERR_TILE_UNSPEC)
 			xe_update_hw_error_cnt(&tile_to_xe(tile)->drm,
 					       &tile->errors.hw_error, indx);
+		if (errbit == XE_GT_ERROR)
+			xe_gt_hw_error_handler(tile->primary_gt, hw_err);
 	}
-
 	xe_mmio_write32(gt, DEV_ERR_STAT_REG(hw_err), errsrc);
 unlock:
 	spin_unlock_irqrestore(&tile_to_xe(tile)->irq.lock, flags);
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index 1932f64e26da..40869e2b97d3 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -37,6 +37,30 @@ enum xe_tile_hw_errors {
 	XE_HW_ERR_TILE_CORR_UNKNOWN,
 };
 
+/* Count of GT Correctable and FATAL HW ERRORS */
+enum xe_gt_hw_errors {
+	XE_HW_ERR_GT_CORR_L3_SNG,
+	XE_HW_ERR_GT_CORR_GUC,
+	XE_HW_ERR_GT_CORR_SAMPLER,
+	XE_HW_ERR_GT_CORR_SLM,
+	XE_HW_ERR_GT_CORR_EU_IC,
+	XE_HW_ERR_GT_CORR_EU_GRF,
+	XE_HW_ERR_GT_CORR_UNKNOWN,
+	XE_HW_ERR_GT_FATAL_ARR_BIST,
+	XE_HW_ERR_GT_FATAL_FPU,
+	XE_HW_ERR_GT_FATAL_L3_DOUB,
+	XE_HW_ERR_GT_FATAL_L3_ECC_CHK,
+	XE_HW_ERR_GT_FATAL_GUC,
+	XE_HW_ERR_GT_FATAL_IDI_PAR,
+	XE_HW_ERR_GT_FATAL_SQIDI,
+	XE_HW_ERR_GT_FATAL_SAMPLER,
+	XE_HW_ERR_GT_FATAL_SLM,
+	XE_HW_ERR_GT_FATAL_EU_IC,
+	XE_HW_ERR_GT_FATAL_EU_GRF,
+	XE_HW_ERR_GT_FATAL_UNKNOWN,
+	XE_HW_ERR_GT_MAX,
+};
+
 struct err_name_index_pair {
 	const char *name;
 	const u32 index;
diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
index bc79145eadc0..bc80d24df572 100644
--- a/drivers/gpu/drm/xe/xe_tile.c
+++ b/drivers/gpu/drm/xe/xe_tile.c
@@ -85,6 +85,7 @@ int xe_tile_alloc(struct xe_tile *tile)
 	struct drm_device *drm = &tile_to_xe(tile)->drm;
 
 	xa_init(&tile->errors.hw_error);
+	xa_init(&tile->primary_gt->errors.hw_error);
 
 	tile->mem.ggtt = drmm_kzalloc(drm, sizeof(*tile->mem.ggtt),
 				      GFP_KERNEL);
-- 
2.25.1

[Intel-xe] [PATCH v7 04/11] drm/xe: Support GT hardware error reporting for PVC.

[Himal Prasad Ghimiray]

PVC supports GT error reporting via vector registers alongwith
error status register. Add support to report these errors and
update respective counters.
Incase of Subslice error reported by vector register, process the
error status register for applicable bits.

Bspec: 54179, 54177, 53088, 53089

v6
- Define registers ascending order of their addresses.
- use xe_gt_hw_error_log_vector_reg instead of
  xe_gt_hw_error_vectr_reg_handler.
- use xe_assign_hw_err_regs for reg initialization.
- use switch-case instead of if-else.

v7
- Use all vctr for correctable too.
- Use helper functions to log gt hardware errors. (Aravind)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_error_regs.h |  16 +++
 drivers/gpu/drm/xe/xe_device_types.h       |   1 +
 drivers/gpu/drm/xe/xe_hw_error.c           | 124 ++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_hw_error.h           |  19 ++++
 4 files changed, 158 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
index 6180704a6149..59631c2e8e12 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
@@ -10,4 +10,20 @@
 #define ERR_STAT_GT_REG(x)              XE_REG(_PICK_EVEN((x), \
 						_ERR_STAT_GT_COR, \
 						_ERR_STAT_GT_NONFATAL))
+
+#define _ERR_STAT_GT_FATAL_VCTR_0       0x100260
+#define _ERR_STAT_GT_FATAL_VCTR_1       0x100264
+#define ERR_STAT_GT_FATAL_VCTR_REG(x)   XE_REG(_PICK_EVEN((x), \
+						_ERR_STAT_GT_FATAL_VCTR_0, \
+						_ERR_STAT_GT_FATAL_VCTR_1))
+
+#define _ERR_STAT_GT_COR_VCTR_0         0x1002a0
+#define _ERR_STAT_GT_COR_VCTR_1         0x1002a4
+#define ERR_STAT_GT_COR_VCTR_REG(x)     XE_REG(_PICK_EVEN((x), \
+						_ERR_STAT_GT_COR_VCTR_0, \
+						_ERR_STAT_GT_COR_VCTR_1))
+
+#define ERR_STAT_GT_VCTR_REG(hw_err, x) (hw_err == HARDWARE_ERROR_CORRECTABLE ? \
+						ERR_STAT_GT_COR_VCTR_REG(x) : \
+						ERR_STAT_GT_FATAL_VCTR_REG(x))
 #endif
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 675cf0c00be2..4624f2f53b26 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -415,6 +415,7 @@ struct xe_device {
 	struct hardware_errors_regs {
 		const struct err_name_index_pair *dev_err_stat[HARDWARE_ERROR_MAX];
 		const struct err_name_index_pair *err_stat_gt[HARDWARE_ERROR_MAX];
+		const struct err_name_index_pair *err_vctr_gt[HARDWARE_ERROR_MAX];
 	} hw_err_regs;
 
 	/* private: */
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index c4bc24a35231..c94825b9c1fe 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -131,10 +131,47 @@ static const struct err_name_index_pair dg2_stat_gt_correctable_reg[] = {
 	[16 ... 31] = {"Undefined",             XE_HW_ERR_GT_CORR_UNKNOWN},
 };
 
+static const struct err_name_index_pair pvc_err_stat_gt_fatal_reg[] = {
+	[0 ... 2]   =  {"Undefined",		XE_HW_ERR_GT_FATAL_UNKNOWN},
+	[3]         =  {"FPU",			XE_HW_ERR_GT_FATAL_FPU},
+	[4 ... 5]   =  {"Undefined",            XE_HW_ERR_GT_FATAL_UNKNOWN},
+	[6]         =  {"GUC SRAM",		XE_HW_ERR_GT_FATAL_GUC},
+	[7 ... 12]  =  {"Undefined",		XE_HW_ERR_GT_FATAL_UNKNOWN},
+	[13]        =  {"SLM",			XE_HW_ERR_GT_FATAL_SLM},
+	[14]        =  {"Undefined",		XE_HW_ERR_GT_FATAL_UNKNOWN},
+	[15]        =  {"EU GRF",		XE_HW_ERR_GT_FATAL_EU_GRF},
+	[16 ... 31] =  {"Undefined",            XE_HW_ERR_GT_FATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_err_stat_gt_correctable_reg[] = {
+	[0]         = {"Undefined",             XE_HW_ERR_GT_CORR_UNKNOWN},
+	[1]         = {"SINGLE BIT GUC SRAM",	XE_HW_ERR_GT_CORR_GUC},
+	[2 ... 12]  = {"Undefined",		XE_HW_ERR_GT_CORR_UNKNOWN},
+	[13]        = {"SINGLE BIT SLM",	XE_HW_ERR_GT_CORR_SLM},
+	[14]        = {"SINGLE BIT EU IC",	XE_HW_ERR_GT_CORR_EU_IC},
+	[15]        = {"SINGLE BIT EU GRF",	XE_HW_ERR_GT_CORR_EU_GRF},
+	[16 ... 31] = {"Undefined",             XE_HW_ERR_GT_CORR_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_err_vectr_gt_fatal_reg[] = {
+	[0 ... 1]         = {"SUBSLICE",	XE_HW_ERR_GT_FATAL_SUBSLICE},
+	[2 ... 3]         = {"L3BANK",		XE_HW_ERR_GT_FATAL_L3BANK},
+	[4 ... 5]         = {"Undefined",	XE_HW_ERR_GT_FATAL_UNKNOWN},
+	[6]               = {"TLB",		XE_HW_ERR_GT_FATAL_TLB},
+	[7]               = {"L3 FABRIC",	XE_HW_ERR_GT_FATAL_L3_FABRIC},
+};
+
+static const struct err_name_index_pair pvc_err_vectr_gt_correctable_reg[] = {
+	[0 ... 1]         = {"SUBSLICE",	XE_HW_ERR_GT_CORR_SUBSLICE},
+	[2 ... 3]         = {"L3BANK",		XE_HW_ERR_GT_CORR_L3BANK},
+	[4 ... 7]         = {"Undefined",       XE_HW_ERR_GT_CORR_UNKNOWN},
+};
+
 void xe_assign_hw_err_regs(struct xe_device *xe)
 {
 	const struct err_name_index_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
 	const struct err_name_index_pair **err_stat_gt = xe->hw_err_regs.err_stat_gt;
+	const struct err_name_index_pair **err_vctr_gt = xe->hw_err_regs.err_vctr_gt;
 
 	/* Error reporting is supported only for DG2 and PVC currently. */
 	if (xe->info.platform == XE_DG2) {
@@ -149,6 +186,10 @@ void xe_assign_hw_err_regs(struct xe_device *xe)
 		dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = pvc_err_stat_correctable_reg;
 		dev_err_stat[HARDWARE_ERROR_NONFATAL] = pvc_err_stat_nonfatal_reg;
 		dev_err_stat[HARDWARE_ERROR_FATAL] = pvc_err_stat_fatal_reg;
+		err_stat_gt[HARDWARE_ERROR_CORRECTABLE] = pvc_err_stat_gt_correctable_reg;
+		err_stat_gt[HARDWARE_ERROR_FATAL] = pvc_err_stat_gt_fatal_reg;
+		err_vctr_gt[HARDWARE_ERROR_CORRECTABLE] = pvc_err_vectr_gt_correctable_reg;
+		err_vctr_gt[HARDWARE_ERROR_FATAL] = pvc_err_vectr_gt_fatal_reg;
 	}
 
 }
@@ -162,13 +203,14 @@ static bool xe_platform_has_ras(struct xe_device *xe)
 }
 
 static void
-xe_update_hw_error_cnt(struct drm_device *drm, struct xarray *hw_error, unsigned long index)
+xe_update_hw_error_cnt_with_value(struct drm_device *drm, struct xarray *hw_error,
+				  unsigned long index, unsigned long val)
 {
 	unsigned long flags;
 	void *entry;
 
 	entry = xa_load(hw_error, index);
-	entry = xa_mk_value(xa_to_value(entry) + 1);
+	entry = xa_mk_value(xa_to_value(entry) + val);
 
 	xa_lock_irqsave(hw_error, flags);
 	if (xa_is_err(__xa_store(hw_error, index, entry, GFP_ATOMIC)))
@@ -177,6 +219,12 @@ xe_update_hw_error_cnt(struct drm_device *drm, struct xarray *hw_error, unsigned
 	xa_unlock_irqrestore(hw_error, flags);
 }
 
+static void
+xe_update_hw_error_cnt(struct drm_device *drm, struct xarray *hw_error, unsigned long index)
+{
+	xe_update_hw_error_cnt_with_value(drm, hw_error, index, 1);
+}
+
 static void
 xe_gt_hw_error_log_status_reg(struct xe_gt *gt, const enum hardware_error hw_err)
 {
@@ -188,6 +236,7 @@ xe_gt_hw_error_log_status_reg(struct xe_gt *gt, const enum hardware_error hw_err
 	u32 indx;
 	u32 errbit;
 
+	lockdep_assert_held(&gt_to_xe(gt)->irq.lock);
 	err_regs = &gt_to_xe(gt)->hw_err_regs;
 	errsrc = xe_mmio_read32(gt, ERR_STAT_GT_REG(hw_err));
 	if (!errsrc) {
@@ -224,6 +273,74 @@ xe_gt_hw_error_log_status_reg(struct xe_gt *gt, const enum hardware_error hw_err
 	xe_mmio_write32(gt, ERR_STAT_GT_REG(hw_err), errsrc);
 }
 
+static void
+xe_gt_hw_error_log_vector_reg(struct xe_gt *gt, const enum hardware_error hw_err)
+{
+	const char *hw_err_str = hardware_error_type_to_str(hw_err);
+	const struct err_name_index_pair *errvctr;
+	struct hardware_errors_regs *err_regs;
+	const char *name;
+	bool errstat_read;
+	unsigned long val;
+	u32 num_vctr_reg;
+	u32 indx;
+	u32 vctr;
+	u32 i;
+
+	if (hw_err == HARDWARE_ERROR_NONFATAL) {
+		/*  The GT Non Fatal Error Status Register has only reserved bits
+		 *  Nothing to service.
+		 */
+		xe_gt_log_hw_err(gt, "%s error\n", hw_err_str);
+		return;
+	}
+
+	errstat_read = false;
+	num_vctr_reg = ERR_STAT_GT_VCTR_LEN;
+	err_regs = &gt_to_xe(gt)->hw_err_regs;
+	errvctr = err_regs->err_vctr_gt[hw_err];
+	for (i = 0 ; i < num_vctr_reg; i++) {
+		vctr = xe_mmio_read32(gt, ERR_STAT_GT_VCTR_REG(hw_err, i));
+		if (!vctr)
+			continue;
+
+		name = errvctr[i].name;
+		indx = errvctr[i].index;
+
+		if (hw_err == HARDWARE_ERROR_FATAL)
+			xe_gt_log_hw_err(gt, "%s %s error. ERR_VECT_GT_%s[%d]:0x%08x\n",
+					 name, hw_err_str, hw_err_str, i, vctr);
+		else
+			xe_gt_log_hw_warn(gt, "%s %s error. ERR_VECT_GT_%s[%d]:0x%08x\n",
+					  name, hw_err_str, hw_err_str, i, vctr);
+
+		switch (i) {
+		case ERR_STAT_GT_VCTR0:
+		case ERR_STAT_GT_VCTR1:
+		case ERR_STAT_GT_VCTR2:
+		case ERR_STAT_GT_VCTR3:
+			val = hweight32(vctr);
+			if (i < ERR_STAT_GT_VCTR2 && !errstat_read) {
+				xe_gt_hw_error_log_status_reg(gt, hw_err);
+				errstat_read = true;
+			}
+			xe_update_hw_error_cnt_with_value(&gt_to_xe(gt)->drm,
+							  &gt->errors.hw_error, indx, val);
+			break;
+		case ERR_STAT_GT_VCTR6:
+		case ERR_STAT_GT_VCTR7:
+			val = (i == ERR_STAT_GT_VCTR6) ? hweight16(vctr) : hweight8(vctr);
+			xe_update_hw_error_cnt_with_value(&gt_to_xe(gt)->drm,
+							  &gt->errors.hw_error, indx, val);
+			break;
+		default:
+			break;
+		}
+
+		xe_mmio_write32(gt, ERR_STAT_GT_VCTR_REG(hw_err, i), vctr);
+	}
+}
+
 static void
 xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
 {
@@ -231,6 +348,9 @@ xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
 
 	if (gt_to_xe(gt)->info.platform == XE_DG2)
 		xe_gt_hw_error_log_status_reg(gt, hw_err);
+
+	if (gt_to_xe(gt)->info.platform == XE_PVC)
+		xe_gt_hw_error_log_vector_reg(gt, hw_err);
 }
 
 static void
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index 40869e2b97d3..440e03c7649d 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -10,6 +10,8 @@
 
 #define XE_RAS_REG_SIZE 32
 
+#define ERR_STAT_GT_VCTR_LEN (8)
+
 /* Error categories reported by hardware */
 enum hardware_error {
 	HARDWARE_ERROR_CORRECTABLE = 0,
@@ -37,8 +39,21 @@ enum xe_tile_hw_errors {
 	XE_HW_ERR_TILE_CORR_UNKNOWN,
 };
 
+enum gt_vctr_registers {
+	ERR_STAT_GT_VCTR0 = 0,
+	ERR_STAT_GT_VCTR1,
+	ERR_STAT_GT_VCTR2,
+	ERR_STAT_GT_VCTR3,
+	ERR_STAT_GT_VCTR4,
+	ERR_STAT_GT_VCTR5,
+	ERR_STAT_GT_VCTR6,
+	ERR_STAT_GT_VCTR7,
+};
+
 /* Count of GT Correctable and FATAL HW ERRORS */
 enum xe_gt_hw_errors {
+	XE_HW_ERR_GT_CORR_SUBSLICE,
+	XE_HW_ERR_GT_CORR_L3BANK,
 	XE_HW_ERR_GT_CORR_L3_SNG,
 	XE_HW_ERR_GT_CORR_GUC,
 	XE_HW_ERR_GT_CORR_SAMPLER,
@@ -46,6 +61,10 @@ enum xe_gt_hw_errors {
 	XE_HW_ERR_GT_CORR_EU_IC,
 	XE_HW_ERR_GT_CORR_EU_GRF,
 	XE_HW_ERR_GT_CORR_UNKNOWN,
+	XE_HW_ERR_GT_FATAL_SUBSLICE,
+	XE_HW_ERR_GT_FATAL_L3BANK,
+	XE_HW_ERR_GT_FATAL_TLB,
+	XE_HW_ERR_GT_FATAL_L3_FABRIC,
 	XE_HW_ERR_GT_FATAL_ARR_BIST,
 	XE_HW_ERR_GT_FATAL_FPU,
 	XE_HW_ERR_GT_FATAL_L3_DOUB,
-- 
2.25.1

[Intel-xe] [PATCH v3 05/11] drm/xe: Support GSC hardware error reporting for PVC.

[Himal Prasad Ghimiray]

Add support to report GSC hw errors and counter update in case
of correctable errors.

v2
- skip FW_ERR reporting via counters.
- maintain uniform naming for enums.
- Use same convention for error reporting.(Aravind)

v3
- Move gsc error in same enum as tile.
- Leave blankline before comments.

Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h | 11 +++
 drivers/gpu/drm/xe/xe_device_types.h         |  1 +
 drivers/gpu/drm/xe/xe_hw_error.c             | 97 ++++++++++++++++++++
 drivers/gpu/drm/xe/xe_hw_error.h             | 15 +++
 4 files changed, 124 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
index 45bd6b85e115..3ab28b321622 100644
--- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
@@ -5,10 +5,21 @@
 #ifndef XE_TILE_ERROR_REGS_H_
 #define XE_TILE_ERROR_REGS_H_
 
+
+#define _GSC_HEC_UNCOR_ERR_STATUS                      0x118
+#define _GSC_HEC_CORR_ERR_STATUS                       0x128
+#define GSC_HEC_ERR_STAT_REG(base, x)                  XE_REG(_PICK_EVEN((x), \
+								(base) + _GSC_HEC_CORR_ERR_STATUS, \
+								(base) + _GSC_HEC_UNCOR_ERR_STATUS))
+
 #define _DEV_ERR_STAT_NONFATAL                         0x100178
 #define _DEV_ERR_STAT_CORRECTABLE                      0x10017c
 #define DEV_ERR_STAT_REG(x)                            XE_REG(_PICK_EVEN((x), \
 								_DEV_ERR_STAT_CORRECTABLE, \
 								_DEV_ERR_STAT_NONFATAL))
 #define   XE_GT_ERROR				       0
+#define   XE_GSC_ERROR				       8
+
+#define PVC_GSC_HECI1_BASE                             0x284000
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 4624f2f53b26..3b371e0f6168 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -416,6 +416,7 @@ struct xe_device {
 		const struct err_name_index_pair *dev_err_stat[HARDWARE_ERROR_MAX];
 		const struct err_name_index_pair *err_stat_gt[HARDWARE_ERROR_MAX];
 		const struct err_name_index_pair *err_vctr_gt[HARDWARE_ERROR_MAX];
+		const struct err_name_index_pair *gsc_error[HARDWARE_ERROR_MAX];
 	} hw_err_regs;
 
 	/* private: */
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index c94825b9c1fe..84533ef6a51e 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -167,11 +167,34 @@ static const struct err_name_index_pair pvc_err_vectr_gt_correctable_reg[] = {
 	[4 ... 7]         = {"Undefined",       XE_HW_ERR_GT_CORR_UNKNOWN},
 };
 
+static const struct err_name_index_pair pvc_gsc_nonfatal_err_reg[] = {
+	[0]  = {"MinuteIA Unexpected Shutdown",		 XE_HW_ERR_GSC_NONFATAL_MIA_SHUTDOWN},
+	[1]  = {"MinuteIA Internal Error",		 XE_HW_ERR_GSC_NONFATAL_MIA_INTERNAL},
+	[2]  = {"Double bit error on SRAM",		 XE_HW_ERR_GSC_NONFATAL_SRAM},
+	[3]  = {"WDT 2nd Timeout",			 XE_HW_ERR_GSC_NONFATAL_WDG},
+	[4]  = {"ROM has a parity error",		 XE_HW_ERR_GSC_NONFATAL_ROM_PARITY},
+	[5]  = {"Ucode has a parity error",		 XE_HW_ERR_GSC_NONFATAL_UCODE_PARITY},
+	[6]  = {"Errors Reported to and Detected by FW", XE_HW_ERR_TILE_UNSPEC},
+	[7]  = {"Glitch is detected on voltage rail",	 XE_HW_ERR_GSC_NONFATAL_VLT_GLITCH},
+	[8]  = {"Fuse Pull Error",			 XE_HW_ERR_GSC_NONFATAL_FUSE_PULL},
+	[9]  = {"Fuse CRC Check Failed on Fuse Pull",	 XE_HW_ERR_GSC_NONFATAL_FUSE_CRC},
+	[10] = {"Self Mbist Failed",			 XE_HW_ERR_GSC_NONFATAL_SELF_MBIST},
+	[11] = {"AON RF has parity error",		 XE_HW_ERR_GSC_NONFATAL_AON_RF_PARITY},
+	[12 ... 31] = {"Undefined",			 XE_HW_ERR_GSC_NONFATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_gsc_correctable_err_reg[] = {
+	[0]  = {"Single bit error on SRAM",			XE_HW_ERR_GSC_CORR_SRAM},
+	[1]  = {"Errors Reported to FW and Detected by FW",	XE_HW_ERR_TILE_UNSPEC},
+	[2 ... 31] = {"Undefined",				XE_HW_ERR_GSC_CORR_UNKNOWN},
+};
+
 void xe_assign_hw_err_regs(struct xe_device *xe)
 {
 	const struct err_name_index_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
 	const struct err_name_index_pair **err_stat_gt = xe->hw_err_regs.err_stat_gt;
 	const struct err_name_index_pair **err_vctr_gt = xe->hw_err_regs.err_vctr_gt;
+	const struct err_name_index_pair **gsc_error = xe->hw_err_regs.gsc_error;
 
 	/* Error reporting is supported only for DG2 and PVC currently. */
 	if (xe->info.platform == XE_DG2) {
@@ -190,6 +213,8 @@ void xe_assign_hw_err_regs(struct xe_device *xe)
 		err_stat_gt[HARDWARE_ERROR_FATAL] = pvc_err_stat_gt_fatal_reg;
 		err_vctr_gt[HARDWARE_ERROR_CORRECTABLE] = pvc_err_vectr_gt_correctable_reg;
 		err_vctr_gt[HARDWARE_ERROR_FATAL] = pvc_err_vectr_gt_fatal_reg;
+		gsc_error[HARDWARE_ERROR_CORRECTABLE] = pvc_gsc_correctable_err_reg;
+		gsc_error[HARDWARE_ERROR_NONFATAL] = pvc_gsc_nonfatal_err_reg;
 	}
 
 }
@@ -353,6 +378,73 @@ xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
 		xe_gt_hw_error_log_vector_reg(gt, hw_err);
 }
 
+static void
+xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
+{
+	const char *hw_err_str = hardware_error_type_to_str(hw_err);
+	const struct err_name_index_pair *errstat;
+	struct hardware_errors_regs *err_regs;
+	struct xe_gt *gt;
+	unsigned long errsrc;
+	const char *name;
+	u32 indx;
+	u32 errbit;
+	u32 base;
+
+	if ((tile_to_xe(tile)->info.platform != XE_PVC))
+		return;
+
+	/*
+	 * GSC errors are valid only on root tile and for NONFATAL and
+	 * CORRECTABLE type.For non root tiles or FATAL type it should
+	 * be categorized as undefined GSC HARDWARE ERROR
+	 */
+	base = PVC_GSC_HECI1_BASE;
+
+	if (tile->id || hw_err == HARDWARE_ERROR_FATAL) {
+		drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
+				    "Tile%d reported GSC %s Undefined error.\n",
+				    tile->id, hw_err_str);
+		return;
+	}
+
+	lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
+	err_regs = &tile_to_xe(tile)->hw_err_regs;
+	errstat = err_regs->gsc_error[hw_err];
+	gt = tile->primary_gt;
+	errsrc = xe_mmio_read32(gt, GSC_HEC_ERR_STAT_REG(base, hw_err));
+	if (!errsrc) {
+		drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
+				    "Tile0 reported GSC_HEC_ERR_STAT_REG_%s blank!\n", hw_err_str);
+		goto clear_reg;
+	}
+
+	drm_dbg(&tile_to_xe(tile)->drm, HW_ERR
+		 "Tile0 reported GSC_HEC_ERR_STAT_REG_%s=0x%08lx\n", hw_err_str, errsrc);
+
+	for_each_set_bit(errbit, &errsrc, XE_RAS_REG_SIZE) {
+		name = errstat[errbit].name;
+		indx = errstat[errbit].index;
+
+		if (hw_err == HARDWARE_ERROR_CORRECTABLE) {
+			drm_warn(&tile_to_xe(tile)->drm,
+				 HW_ERR "Tile0 reported GSC %s %s error, bit[%d] is set\n",
+				 name, hw_err_str, errbit);
+
+		} else {
+			drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
+					    "Tile0 reported GSC %s %s error, bit[%d] is set\n",
+					    name, hw_err_str, errbit);
+		}
+		if (indx != XE_HW_ERR_TILE_UNSPEC)
+			xe_update_hw_error_cnt(&tile_to_xe(tile)->drm,
+					       &tile->errors.hw_error, indx);
+	}
+
+clear_reg:
+	xe_mmio_write32(gt, GSC_HEC_ERR_STAT_REG(base, hw_err), errsrc);
+}
+
 static void
 xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 {
@@ -404,9 +496,14 @@ xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_er
 		if (indx != XE_HW_ERR_TILE_UNSPEC)
 			xe_update_hw_error_cnt(&tile_to_xe(tile)->drm,
 					       &tile->errors.hw_error, indx);
+
 		if (errbit == XE_GT_ERROR)
 			xe_gt_hw_error_handler(tile->primary_gt, hw_err);
+
+		if (errbit == XE_GSC_ERROR)
+			xe_gsc_hw_error_handler(tile, hw_err);
 	}
+
 	xe_mmio_write32(gt, DEV_ERR_STAT_REG(hw_err), errsrc);
 unlock:
 	spin_unlock_irqrestore(&tile_to_xe(tile)->irq.lock, flags);
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index 440e03c7649d..997747b6b603 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -37,6 +37,21 @@ enum xe_tile_hw_errors {
 	XE_HW_ERR_TILE_NONFATAL_UNKNOWN,
 	XE_HW_ERR_TILE_CORR_SGUNIT,
 	XE_HW_ERR_TILE_CORR_UNKNOWN,
+	XE_HW_ERR_GSC_CORR_SRAM,
+	XE_HW_ERR_GSC_CORR_UNKNOWN,
+	XE_HW_ERR_GSC_NONFATAL_MIA_SHUTDOWN,
+	XE_HW_ERR_GSC_NONFATAL_MIA_INTERNAL,
+	XE_HW_ERR_GSC_NONFATAL_SRAM,
+	XE_HW_ERR_GSC_NONFATAL_WDG,
+	XE_HW_ERR_GSC_NONFATAL_ROM_PARITY,
+	XE_HW_ERR_GSC_NONFATAL_UCODE_PARITY,
+	XE_HW_ERR_GSC_NONFATAL_VLT_GLITCH,
+	XE_HW_ERR_GSC_NONFATAL_FUSE_PULL,
+	XE_HW_ERR_GSC_NONFATAL_FUSE_CRC,
+	XE_HW_ERR_GSC_NONFATAL_SELF_MBIST,
+	XE_HW_ERR_GSC_NONFATAL_AON_RF_PARITY,
+	XE_HW_ERR_GSC_NONFATAL_UNKNOWN,
+	XE_HW_ERROR_TILE_MAX
 };
 
 enum gt_vctr_registers {
-- 
2.25.1

[Intel-xe] [PATCH v3 06/11] drm/xe: Notify userspace about GSC HW errors.

[Himal Prasad Ghimiray]

Send uevent incase of nonfatal errors reported by gsc.

TODO: Since XE_RESET_FAILED_UEVENT and XE_GSC_HW_HEALTH_UEVENT
both pass DEVICE_STATUS=NEEDS_RESET. Use same Uevent to determine
the RESET_REQUIRED and pass reasons for reset required as additional
info.

v2
- No need to provide tile info in uevent because error is
accepted only in tile0. (Aravind)

v3
- Use pci node to send uevent.
- Pass RESET_REASON for uevent.

Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/xe_device_types.h |  3 +++
 drivers/gpu/drm/xe/xe_hw_error.c     | 17 +++++++++++++++++
 drivers/gpu/drm/xe/xe_hw_error.h     |  3 ++-
 drivers/gpu/drm/xe/xe_irq.c          |  4 ++++
 include/uapi/drm/xe_drm.h            |  9 +++++++++
 5 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 3b371e0f6168..bc7b545ce37b 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -196,6 +196,9 @@ struct xe_tile {
 	struct tile_hw_errors {
 		struct xarray hw_error;
 	} errors;
+
+	/** @gsc_hw_err_work: worker for uevent to report GSC HW errors */
+	struct work_struct gsc_hw_err_work;
 };
 
 /**
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 84533ef6a51e..644e63d4d717 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -3,6 +3,8 @@
  * Copyright © 2023 Intel Corporation
  */
 
+#include <drm/xe_drm.h>
+
 #include "xe_hw_error.h"
 
 #include "regs/xe_regs.h"
@@ -378,6 +380,20 @@ xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
 		xe_gt_hw_error_log_vector_reg(gt, hw_err);
 }
 
+void xe_gsc_hw_error_work(struct work_struct *work)
+{
+	struct xe_tile *tile = container_of(work, typeof(*tile), gsc_hw_err_work);
+	struct pci_dev *pdev = to_pci_dev(tile_to_xe(tile)->drm.dev);
+	char *csc_hw_error_event[3];
+
+	csc_hw_error_event[0] = XE_GSC_HW_HEALTH_UEVENT "=1";
+	csc_hw_error_event[1] = "RESET_REASON=CSC_HW_ERROR";
+	csc_hw_error_event[2] = NULL;
+
+	kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE,
+			   csc_hw_error_event);
+}
+
 static void
 xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 {
@@ -435,6 +451,7 @@ xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 			drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
 					    "Tile0 reported GSC %s %s error, bit[%d] is set\n",
 					    name, hw_err_str, errbit);
+			schedule_work(&tile->gsc_hw_err_work);
 		}
 		if (indx != XE_HW_ERR_TILE_UNSPEC)
 			xe_update_hw_error_cnt(&tile_to_xe(tile)->drm,
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index 997747b6b603..3c02fbd3b256 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -7,6 +7,7 @@
 
 #include <linux/stddef.h>
 #include <linux/types.h>
+#include <linux/workqueue.h>
 
 #define XE_RAS_REG_SIZE 32
 
@@ -106,5 +107,5 @@ struct xe_tile;
 void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);
 void xe_assign_hw_err_regs(struct xe_device *xe);
 void xe_process_hw_errors(struct xe_device *xe);
-
+void xe_gsc_hw_error_work(struct work_struct *work);
 #endif
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 8365a4cb0c45..bc0f01a2abc1 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -614,6 +614,10 @@ int xe_irq_install(struct xe_device *xe)
 	irq_handler_t irq_handler;
 	int err, irq;
 
+	struct xe_tile *tile = xe_device_get_root_tile(xe);
+
+	INIT_WORK(&tile->gsc_hw_err_work, xe_gsc_hw_error_work);
+
 	irq_handler = xe_irq_handler(xe);
 	if (!irq_handler) {
 		drm_err(&xe->drm, "No supported interrupt handler");
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 24bf8f0f52e8..4e5e57bc9f69 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -16,6 +16,15 @@ extern "C" {
  * subject to backwards-compatibility constraints.
  */
 
+/**
+ * DOC: uevent generated by xe on it's pci node.
+ *
+ * XE_GSC_HW_HEALTH_UEVENT - Event is generated when GSC reports HW
+ * errors. The value supplied with the event is always "NEEDS_RESET"
+ * Additional information supplied is "RESET_REASON=CSC_HW_ERROR".
+ */
+#define XE_GSC_HW_HEALTH_UEVENT "DEVICE_STATUS"
+
 /**
  * DOC: uevent generated by xe on it's pci node.
  *
-- 
2.25.1

[Intel-xe] [PATCH v4 07/11] drm/xe: Support SOC FATAL error handling for PVC.

[Himal Prasad Ghimiray]

Report the SOC fatal hardware error and update the counters which will
increment incase of error.

v2
- Use xe_assign_hw_err_regs to initilaize registers.
- Use separate enums for SOC errors.
- Use xarray.
- No need to prepend register offsets with 0's.
- Dont use the counters if error is being reported by second level
  registers.
- Fix Num of IEH to 2.
- define the bits along with respective register and use.
- Follow the convention source_typeoferror_errorname for enum and error
reporting.(Aravind)

v3
- Fix the condition check.

v4
- Make soc errors as part of tile_hw_errors.

Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  31 +++
 drivers/gpu/drm/xe/xe_device_types.h         |   4 +
 drivers/gpu/drm/xe/xe_hw_error.c             | 188 +++++++++++++++++++
 drivers/gpu/drm/xe/xe_hw_error.h             |  55 +++++-
 4 files changed, 277 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
index 3ab28b321622..1b35fe5ee785 100644
--- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
@@ -11,6 +11,33 @@
 #define GSC_HEC_ERR_STAT_REG(base, x)                  XE_REG(_PICK_EVEN((x), \
 								(base) + _GSC_HEC_CORR_ERR_STATUS, \
 								(base) + _GSC_HEC_UNCOR_ERR_STATUS))
+#define _SOC_GCOERRSTS		                       0x200
+#define _SOC_GNFERRSTS		                       0x210
+#define _SOC_GFAERRSTS		                       0x220
+#define SOC_GLOBAL_ERR_STAT_SLAVE_REG(base, x)		XE_REG(_PICK_EVEN((x), \
+								(base) + _SOC_GCOERRSTS, \
+								(base) + _SOC_GNFERRSTS))
+#define SOC_IEH1_LOCAL_ERR_STATUS                      0
+
+#define SOC_GLOBAL_ERR_STAT_MASTER_REG(base, x)		XE_REG(_PICK_EVEN((x), \
+								(base) + _SOC_GCOERRSTS, \
+								(base) + _SOC_GNFERRSTS))
+#define SOC_IEH0_LOCAL_ERR_STATUS                      0
+
+#define _SOC_GSYSEVTCTL		                       0x264
+#define SOC_GSYSEVTCTL_REG(base, slave_base, x)		XE_REG(_PICK_EVEN((x), \
+								(base) + _SOC_GSYSEVTCTL, \
+								slave_base + _SOC_GSYSEVTCTL))
+
+#define _SOC_LERRCORSTS		                       0x294
+#define _SOC_LERRUNCSTS		                       0x280
+#define SOC_LOCAL_ERR_STAT_SLAVE_REG(base, x)		XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
+								(base) + _SOC_LERRUNCSTS : \
+								(base) + _SOC_LERRCORSTS)
+#define SOC_LOCAL_ERR_STAT_MASTER_REG(base, x)		XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
+								(base) + _SOC_LERRUNCSTS : \
+								(base) + _SOC_LERRCORSTS)
+
 
 #define _DEV_ERR_STAT_NONFATAL                         0x100178
 #define _DEV_ERR_STAT_CORRECTABLE                      0x10017c
@@ -19,6 +46,10 @@
 								_DEV_ERR_STAT_NONFATAL))
 #define   XE_GT_ERROR				       0
 #define   XE_GSC_ERROR				       8
+#define   XE_SOC_ERROR                                 16
+
+#define SOC_PVC_BASE	                               0x282000
+#define SOC_PVC_SLAVE_BASE                             0x283000
 
 #define PVC_GSC_HECI1_BASE                             0x284000
 
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index bc7b545ce37b..a1bacf820d37 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -420,6 +420,10 @@ struct xe_device {
 		const struct err_name_index_pair *err_stat_gt[HARDWARE_ERROR_MAX];
 		const struct err_name_index_pair *err_vctr_gt[HARDWARE_ERROR_MAX];
 		const struct err_name_index_pair *gsc_error[HARDWARE_ERROR_MAX];
+		const struct err_name_index_pair *soc_mstr_glbl[HARDWARE_ERROR_MAX];
+		const struct err_name_index_pair *soc_mstr_lcl[HARDWARE_ERROR_MAX];
+		const struct err_name_index_pair *soc_slave_glbl[HARDWARE_ERROR_MAX];
+		const struct err_name_index_pair *soc_slave_lcl[HARDWARE_ERROR_MAX];
 	} hw_err_regs;
 
 	/* private: */
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 644e63d4d717..084be7ddb551 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -191,12 +191,85 @@ static const struct err_name_index_pair pvc_gsc_correctable_err_reg[] = {
 	[2 ... 31] = {"Undefined",				XE_HW_ERR_GSC_CORR_UNKNOWN},
 };
 
+static const struct err_name_index_pair pvc_soc_mstr_glbl_err_reg_fatal[] = {
+	[0]         = {"MASTER LOCAL Reported",			XE_HW_ERR_TILE_UNSPEC},
+	[1]         = {"SLAVE GLOBAL Reported",			XE_HW_ERR_TILE_UNSPEC},
+	[2]         = {"HBM SS0: Channel0",			XE_HW_ERR_SOC_FATAL_HBM0_CHNL0},
+	[3]         = {"HBM SS0: Channel1",			XE_HW_ERR_SOC_FATAL_HBM0_CHNL1},
+	[4]         = {"HBM SS0: Channel2",			XE_HW_ERR_SOC_FATAL_HBM0_CHNL2},
+	[5]         = {"HBM SS0: Channel3",			XE_HW_ERR_SOC_FATAL_HBM0_CHNL3},
+	[6]         = {"HBM SS0: Channel4",			XE_HW_ERR_SOC_FATAL_HBM0_CHNL4},
+	[7]         = {"HBM SS0: Channel5",			XE_HW_ERR_SOC_FATAL_HBM0_CHNL5},
+	[8]         = {"HBM SS0: Channel6",                     XE_HW_ERR_SOC_FATAL_HBM0_CHNL6},
+	[9]         = {"HBM SS0: Channel7",                     XE_HW_ERR_SOC_FATAL_HBM0_CHNL7},
+	[10]        = {"HBM SS1: Channel0",                     XE_HW_ERR_SOC_FATAL_HBM1_CHNL0},
+	[11]        = {"HBM SS1: Channel1",                     XE_HW_ERR_SOC_FATAL_HBM1_CHNL1},
+	[12]        = {"HBM SS1: Channel2",                     XE_HW_ERR_SOC_FATAL_HBM1_CHNL2},
+	[13]        = {"HBM SS1: Channel3",                     XE_HW_ERR_SOC_FATAL_HBM1_CHNL3},
+	[14]        = {"HBM SS1: Channel4",                     XE_HW_ERR_SOC_FATAL_HBM1_CHNL4},
+	[15]        = {"HBM SS1: Channel5",                     XE_HW_ERR_SOC_FATAL_HBM1_CHNL5},
+	[16]        = {"HBM SS1: Channel6",                     XE_HW_ERR_SOC_FATAL_HBM1_CHNL6},
+	[17]        = {"HBM SS1: Channel7",                     XE_HW_ERR_SOC_FATAL_HBM1_CHNL7},
+	[18]	    = {"PUNIT",					XE_HW_ERR_SOC_FATAL_PUNIT},
+	[19 ... 31] = {"Undefined",				XE_HW_ERR_SOC_FATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_soc_slave_glbl_err_reg_fatal[] = {
+	[0]         = {"SLAVE LOCAL Reported",			XE_HW_ERR_TILE_UNSPEC},
+	[1]         = {"HBM SS2: Channel0",			XE_HW_ERR_SOC_FATAL_HBM2_CHNL0},
+	[2]         = {"HBM SS2: Channel1",			XE_HW_ERR_SOC_FATAL_HBM2_CHNL1},
+	[3]         = {"HBM SS2: Channel2",			XE_HW_ERR_SOC_FATAL_HBM2_CHNL2},
+	[4]         = {"HBM SS2: Channel3",			XE_HW_ERR_SOC_FATAL_HBM2_CHNL3},
+	[5]         = {"HBM SS2: Channel4",			XE_HW_ERR_SOC_FATAL_HBM2_CHNL4},
+	[6]         = {"HBM SS2: Channel5",			XE_HW_ERR_SOC_FATAL_HBM2_CHNL5},
+	[7]         = {"HBM SS2: Channel6",                     XE_HW_ERR_SOC_FATAL_HBM2_CHNL6},
+	[8]         = {"HBM SS2: Channel7",                     XE_HW_ERR_SOC_FATAL_HBM2_CHNL7},
+	[9]         = {"HBM SS3: Channel0",                     XE_HW_ERR_SOC_FATAL_HBM3_CHNL0},
+	[10]        = {"HBM SS3: Channel1",                     XE_HW_ERR_SOC_FATAL_HBM3_CHNL1},
+	[11]        = {"HBM SS3: Channel2",                     XE_HW_ERR_SOC_FATAL_HBM3_CHNL2},
+	[12]        = {"HBM SS3: Channel3",                     XE_HW_ERR_SOC_FATAL_HBM3_CHNL3},
+	[13]        = {"HBM SS3: Channel4",                     XE_HW_ERR_SOC_FATAL_HBM3_CHNL4},
+	[14]        = {"HBM SS3: Channel5",                     XE_HW_ERR_SOC_FATAL_HBM3_CHNL5},
+	[15]        = {"HBM SS3: Channel6",                     XE_HW_ERR_SOC_FATAL_HBM3_CHNL6},
+	[16]        = {"HBM SS3: Channel7",                     XE_HW_ERR_SOC_FATAL_HBM3_CHNL7},
+	[18]	    = {"ANR MDFI",				XE_HW_ERR_SOC_FATAL_ANR_MDFI},
+	[17]        = {"Undefined",                             XE_HW_ERR_SOC_FATAL_UNKNOWN},
+	[19 ... 31] = {"Undefined",				XE_HW_ERR_SOC_FATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_soc_slave_lcl_err_reg_fatal[] = {
+	[0]         = {"Local IEH Internal: Malformed PCIe AER",     XE_HW_ERR_SOC_FATAL_PCIE_AER},
+	[1]         = {"Local IEH Internal: Malformed PCIe ERR",     XE_HW_ERR_SOC_FATAL_PCIE_ERR},
+	[2]         = {"Local IEH Internal: UR CONDITIONS IN IEH",   XE_HW_ERR_SOC_FATAL_UR_COND},
+	[3]         = {"Local IEH Internal: FROM SERR SOURCES",      XE_HW_ERR_SOC_FATAL_SERR_SRCS},
+	[4 ... 31]  = {"Undefined",				     XE_HW_ERR_SOC_FATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_soc_mstr_lcl_err_reg_fatal[] = {
+	[0 ... 3]   = {"Undefined",				XE_HW_ERR_SOC_FATAL_UNKNOWN},
+	[4]         = {"Base Die MDFI T2T",			XE_HW_ERR_SOC_FATAL_MDFI_T2T},
+	[5]         = {"Undefined",				XE_HW_ERR_SOC_FATAL_UNKNOWN},
+	[6]         = {"Base Die MDFI T2C",			XE_HW_ERR_SOC_FATAL_MDFI_T2C},
+	[7]         = {"Undefined",				XE_HW_ERR_SOC_FATAL_UNKNOWN},
+	[8]         = {"Invalid CSC PSF Command Parity",	XE_HW_ERR_SOC_FATAL_CSC_PSF_CMD},
+	[9]         = {"Invalid CSC PSF Unexpected Completion",	XE_HW_ERR_SOC_FATAL_CSC_PSF_CMP},
+	[10]        = {"Invalid CSC PSF Unsupported Request",	XE_HW_ERR_SOC_FATAL_CSC_PSF_REQ},
+	[11]        = {"Invalid PCIe PSF Command Parity",	XE_HW_ERR_SOC_FATAL_PCIE_PSF_CMD},
+	[12]        = {"PCIe PSF Unexpected Completion",	XE_HW_ERR_SOC_FATAL_PCIE_PSF_CMP},
+	[13]        = {"PCIe PSF Unsupported Request",		XE_HW_ERR_SOC_FATAL_PCIE_PSF_REQ},
+	[14 ... 31] = {"Undefined",				XE_HW_ERR_SOC_FATAL_UNKNOWN},
+};
+
 void xe_assign_hw_err_regs(struct xe_device *xe)
 {
 	const struct err_name_index_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
 	const struct err_name_index_pair **err_stat_gt = xe->hw_err_regs.err_stat_gt;
 	const struct err_name_index_pair **err_vctr_gt = xe->hw_err_regs.err_vctr_gt;
 	const struct err_name_index_pair **gsc_error = xe->hw_err_regs.gsc_error;
+	const struct err_name_index_pair **soc_mstr_glbl = xe->hw_err_regs.soc_mstr_glbl;
+	const struct err_name_index_pair **soc_mstr_lcl = xe->hw_err_regs.soc_mstr_lcl;
+	const struct err_name_index_pair **soc_slave_glbl = xe->hw_err_regs.soc_slave_glbl;
+	const struct err_name_index_pair **soc_slave_lcl = xe->hw_err_regs.soc_slave_lcl;
 
 	/* Error reporting is supported only for DG2 and PVC currently. */
 	if (xe->info.platform == XE_DG2) {
@@ -217,6 +290,10 @@ void xe_assign_hw_err_regs(struct xe_device *xe)
 		err_vctr_gt[HARDWARE_ERROR_FATAL] = pvc_err_vectr_gt_fatal_reg;
 		gsc_error[HARDWARE_ERROR_CORRECTABLE] = pvc_gsc_correctable_err_reg;
 		gsc_error[HARDWARE_ERROR_NONFATAL] = pvc_gsc_nonfatal_err_reg;
+		soc_mstr_glbl[HARDWARE_ERROR_FATAL] = pvc_soc_mstr_glbl_err_reg_fatal;
+		soc_mstr_lcl[HARDWARE_ERROR_FATAL] = pvc_soc_mstr_lcl_err_reg_fatal;
+		soc_slave_glbl[HARDWARE_ERROR_FATAL] = pvc_soc_slave_glbl_err_reg_fatal;
+		soc_slave_lcl[HARDWARE_ERROR_FATAL] = pvc_soc_slave_lcl_err_reg_fatal;
 	}
 
 }
@@ -462,6 +539,114 @@ xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 	xe_mmio_write32(gt, GSC_HEC_ERR_STAT_REG(base, hw_err), errsrc);
 }
 
+static void
+xe_soc_log_err_update_cntr(struct xe_tile *tile, const enum hardware_error hw_err,
+			   u32 errbit, const struct err_name_index_pair *reg_info)
+{
+	const char *name;
+	u32 indx;
+
+	const char *hwerr_to_str = hardware_error_type_to_str(hw_err);
+
+	name = reg_info[errbit].name;
+	indx = reg_info[errbit].index;
+
+	drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
+			    "Tile%d reported SOC %s %s error, bit[%d] is set\n",
+			    tile->id, name, hwerr_to_str, errbit);
+
+	if (indx != XE_HW_ERR_TILE_UNSPEC)
+		xe_update_hw_error_cnt(&tile_to_xe(tile)->drm, &tile->errors.hw_error, indx);
+}
+
+static void
+xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
+{
+	unsigned long mst_glb_errstat, slv_glb_errstat, lcl_errstat;
+	struct hardware_errors_regs *err_regs;
+	u32 errbit, base, slave_base;
+	int i;
+
+	struct xe_gt *gt = tile->primary_gt;
+
+	lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
+
+	if ((tile_to_xe(tile)->info.platform != XE_PVC) ||  hw_err != HARDWARE_ERROR_FATAL)
+		return;
+
+	base = SOC_PVC_BASE;
+	slave_base = SOC_PVC_SLAVE_BASE;
+	err_regs = &tile_to_xe(tile)->hw_err_regs;
+
+	/*
+	 * Mask error type in GSYSEVTCTL so that no new errors of the type
+	 * will be reported. Read the master global IEH error register if
+	 * BIT 1 is set then process the slave IEH first. If BIT 0 in
+	 * global error register is set then process the corresponding
+	 * Local error registers
+	 */
+	for (i = 0; i < XE_SOC_NUM_IEH; i++)
+		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i), ~REG_BIT(hw_err));
+
+	mst_glb_errstat = xe_mmio_read32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err));
+	drm_dbg(&tile_to_xe(tile)->drm, HW_ERR
+		 "Tile%d reported SOC_GLOBAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
+		 tile->id, mst_glb_errstat);
+
+	if (mst_glb_errstat & REG_BIT(XE_SOC_SLAVE_IEH)) {
+		slv_glb_errstat = xe_mmio_read32(gt,
+						 SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err));
+		 drm_dbg(&tile_to_xe(tile)->drm, HW_ERR
+			  "Tile%d reported SOC_GLOBAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
+			  tile->id, slv_glb_errstat);
+
+		if (slv_glb_errstat & REG_BIT(SOC_IEH1_LOCAL_ERR_STATUS)) {
+			lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base,
+										      hw_err));
+			 drm_dbg(&tile_to_xe(tile)->drm, HW_ERR
+				  "Tile%d reported SOC_LOCAL_ERR_STAT_SLAVE_REG_FATAL:0x%08lx\n",
+				  tile->id, lcl_errstat);
+
+			for_each_set_bit(errbit, &lcl_errstat, XE_RAS_REG_SIZE)
+				xe_soc_log_err_update_cntr(tile, hw_err, errbit,
+							   err_regs->soc_slave_lcl[hw_err]);
+
+			xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+					lcl_errstat);
+		}
+
+		for_each_set_bit(errbit, &slv_glb_errstat, XE_RAS_REG_SIZE)
+			xe_soc_log_err_update_cntr(tile, hw_err, errbit,
+						   err_regs->soc_slave_glbl[hw_err]);
+
+		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+				slv_glb_errstat);
+	}
+
+	if (mst_glb_errstat & REG_BIT(SOC_IEH0_LOCAL_ERR_STATUS)) {
+		lcl_errstat = xe_mmio_read32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err));
+		drm_dbg(&tile_to_xe(tile)->drm, HW_ERR
+			"Tile%d reported SOC_LOCAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
+			tile->id, lcl_errstat);
+
+		for_each_set_bit(errbit, &lcl_errstat, XE_RAS_REG_SIZE)
+			xe_soc_log_err_update_cntr(tile, hw_err, errbit,
+						   err_regs->soc_mstr_lcl[hw_err]);
+
+		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err), lcl_errstat);
+	}
+
+	for_each_set_bit(errbit, &mst_glb_errstat, XE_RAS_REG_SIZE)
+		xe_soc_log_err_update_cntr(tile, hw_err, errbit, err_regs->soc_mstr_glbl[hw_err]);
+
+	xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
+			mst_glb_errstat);
+
+	for (i = 0; i < XE_SOC_NUM_IEH; i++)
+		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
+				(HARDWARE_ERROR_MAX << 1) + 1);
+}
+
 static void
 xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 {
@@ -519,6 +704,9 @@ xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_er
 
 		if (errbit == XE_GSC_ERROR)
 			xe_gsc_hw_error_handler(tile, hw_err);
+
+		if (errbit == XE_SOC_ERROR)
+			xe_soc_hw_error_handler(tile, hw_err);
 	}
 
 	xe_mmio_write32(gt, DEV_ERR_STAT_REG(hw_err), errsrc);
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index 3c02fbd3b256..bd380b7a7130 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -21,6 +21,12 @@ enum hardware_error {
 	HARDWARE_ERROR_MAX,
 };
 
+enum soc_num_ieh {
+	XE_SOC_MASTER_IEH = 0,
+	XE_SOC_SLAVE_IEH,
+	XE_SOC_NUM_IEH,
+};
+
 /* Count of Correctable and Uncorrectable errors reported on tile */
 enum xe_tile_hw_errors {
 	XE_HW_ERR_TILE_UNSPEC = 0,
@@ -52,7 +58,54 @@ enum xe_tile_hw_errors {
 	XE_HW_ERR_GSC_NONFATAL_SELF_MBIST,
 	XE_HW_ERR_GSC_NONFATAL_AON_RF_PARITY,
 	XE_HW_ERR_GSC_NONFATAL_UNKNOWN,
-	XE_HW_ERROR_TILE_MAX
+	XE_HW_ERR_SOC_FATAL_HBM0_CHNL0,
+	XE_HW_ERR_SOC_FATAL_HBM0_CHNL1,
+	XE_HW_ERR_SOC_FATAL_HBM0_CHNL2,
+	XE_HW_ERR_SOC_FATAL_HBM0_CHNL3,
+	XE_HW_ERR_SOC_FATAL_HBM0_CHNL4,
+	XE_HW_ERR_SOC_FATAL_HBM0_CHNL5,
+	XE_HW_ERR_SOC_FATAL_HBM0_CHNL6,
+	XE_HW_ERR_SOC_FATAL_HBM0_CHNL7,
+	XE_HW_ERR_SOC_FATAL_HBM1_CHNL0,
+	XE_HW_ERR_SOC_FATAL_HBM1_CHNL1,
+	XE_HW_ERR_SOC_FATAL_HBM1_CHNL2,
+	XE_HW_ERR_SOC_FATAL_HBM1_CHNL3,
+	XE_HW_ERR_SOC_FATAL_HBM1_CHNL4,
+	XE_HW_ERR_SOC_FATAL_HBM1_CHNL5,
+	XE_HW_ERR_SOC_FATAL_HBM1_CHNL6,
+	XE_HW_ERR_SOC_FATAL_HBM1_CHNL7,
+	XE_HW_ERR_SOC_FATAL_PUNIT,
+	XE_HW_ERR_SOC_FATAL_UNKNOWN,
+	XE_HW_ERR_SOC_FATAL_HBM2_CHNL0,
+	XE_HW_ERR_SOC_FATAL_HBM2_CHNL1,
+	XE_HW_ERR_SOC_FATAL_HBM2_CHNL2,
+	XE_HW_ERR_SOC_FATAL_HBM2_CHNL3,
+	XE_HW_ERR_SOC_FATAL_HBM2_CHNL4,
+	XE_HW_ERR_SOC_FATAL_HBM2_CHNL5,
+	XE_HW_ERR_SOC_FATAL_HBM2_CHNL6,
+	XE_HW_ERR_SOC_FATAL_HBM2_CHNL7,
+	XE_HW_ERR_SOC_FATAL_HBM3_CHNL0,
+	XE_HW_ERR_SOC_FATAL_HBM3_CHNL1,
+	XE_HW_ERR_SOC_FATAL_HBM3_CHNL2,
+	XE_HW_ERR_SOC_FATAL_HBM3_CHNL3,
+	XE_HW_ERR_SOC_FATAL_HBM3_CHNL4,
+	XE_HW_ERR_SOC_FATAL_HBM3_CHNL5,
+	XE_HW_ERR_SOC_FATAL_HBM3_CHNL6,
+	XE_HW_ERR_SOC_FATAL_HBM3_CHNL7,
+	XE_HW_ERR_SOC_FATAL_ANR_MDFI,
+	XE_HW_ERR_SOC_FATAL_PCIE_AER,
+	XE_HW_ERR_SOC_FATAL_PCIE_ERR,
+	XE_HW_ERR_SOC_FATAL_UR_COND,
+	XE_HW_ERR_SOC_FATAL_SERR_SRCS,
+	XE_HW_ERR_SOC_FATAL_MDFI_T2T,
+	XE_HW_ERR_SOC_FATAL_MDFI_T2C,
+	XE_HW_ERR_SOC_FATAL_CSC_PSF_CMD,
+	XE_HW_ERR_SOC_FATAL_CSC_PSF_CMP,
+	XE_HW_ERR_SOC_FATAL_CSC_PSF_REQ,
+	XE_HW_ERR_SOC_FATAL_PCIE_PSF_CMD,
+	XE_HW_ERR_SOC_FATAL_PCIE_PSF_CMP,
+	XE_HW_ERR_SOC_FATAL_PCIE_PSF_REQ,
+	XE_TILE_HW_ERROR_MAX,
 };
 
 enum gt_vctr_registers {
-- 
2.25.1

[Intel-xe] [PATCH v2 08/11] drm/xe: Support SOC NONFATAL error handling for PVC.

[Himal Prasad Ghimiray]

Report the SOC nonfatal hardware error and update the counters which
will increment incase of error.

v2
- Use xe_assign_hw_err_regs to initilaize registers.
- Dont use the counters if error is being reported by second level
  registers.
- Fix Num of IEH to 2.
- Follow the convention source_typeoferror_errorname for enum and error
reporting.(Aravind)

Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_error.c | 70 +++++++++++++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_hw_error.h | 39 ++++++++++++++++++
 2 files changed, 108 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 084be7ddb551..7c41e51fbb11 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -260,6 +260,67 @@ static const struct err_name_index_pair pvc_soc_mstr_lcl_err_reg_fatal[] = {
 	[14 ... 31] = {"Undefined",				XE_HW_ERR_SOC_FATAL_UNKNOWN},
 };
 
+static const struct err_name_index_pair pvc_soc_mstr_glbl_err_reg_nonfatal[] = {
+	[0]         = {"MASTER LOCAL Reported",			XE_HW_ERR_TILE_UNSPEC},
+	[1]         = {"SLAVE GLOBAL Reported",			XE_HW_ERR_TILE_UNSPEC},
+	[2]         = {"HBM SS0: Channel0",			XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL0},
+	[3]         = {"HBM SS0: Channel1",			XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL1},
+	[4]         = {"HBM SS0: Channel2",			XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL2},
+	[5]         = {"HBM SS0: Channel3",			XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL3},
+	[6]         = {"HBM SS0: Channel4",			XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL4},
+	[7]         = {"HBM SS0: Channel5",			XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL5},
+	[8]         = {"HBM SS0: Channel6",                     XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL6},
+	[9]         = {"HBM SS0: Channel7",                     XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL7},
+	[10]        = {"HBM SS1: Channel0",                     XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL0},
+	[11]        = {"HBM SS1: Channel1",                     XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL1},
+	[12]        = {"HBM SS1: Channel2",                     XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL2},
+	[13]        = {"HBM SS1: Channel3",                     XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL3},
+	[14]        = {"HBM SS1: Channel4",                     XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL4},
+	[15]        = {"HBM SS1: Channel5",                     XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL5},
+	[16]        = {"HBM SS1: Channel6",                     XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL6},
+	[17]        = {"HBM SS1: Channel7",                     XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL7},
+	[18 ... 31] = {"Undefined",				XE_HW_ERR_SOC_NONFATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_soc_slave_glbl_err_reg_nonfatal[] = {
+	[0]         = {"SLAVE LOCAL Reported",			XE_HW_ERR_TILE_UNSPEC},
+	[1]         = {"HBM SS2: Channel0",			XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL0},
+	[2]         = {"HBM SS2: Channel1",			XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL1},
+	[3]         = {"HBM SS2: Channel2",			XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL2},
+	[4]         = {"HBM SS2: Channel3",			XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL3},
+	[5]         = {"HBM SS2: Channel4",			XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL4},
+	[6]         = {"HBM SS2: Channel5",			XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL5},
+	[7]         = {"HBM SS2: Channel6",                     XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL6},
+	[8]         = {"HBM SS2: Channel7",                     XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL7},
+	[9]         = {"HBM SS3: Channel0",                     XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL0},
+	[10]        = {"HBM SS3: Channel1",                     XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL1},
+	[11]        = {"HBM SS3: Channel2",                     XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL2},
+	[12]        = {"HBM SS3: Channel3",                     XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL3},
+	[13]        = {"HBM SS3: Channel4",                     XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL4},
+	[14]        = {"HBM SS3: Channel5",                     XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL5},
+	[15]        = {"HBM SS3: Channel6",                     XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL6},
+	[16]        = {"HBM SS3: Channel7",                     XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL7},
+	[18]	    = {"ANR MDFI",				XE_HW_ERR_SOC_NONFATAL_ANR_MDFI},
+	[17]        = {"Undefined",                             XE_HW_ERR_SOC_NONFATAL_UNKNOWN},
+	[19 ... 31] = {"Undefined",				XE_HW_ERR_SOC_NONFATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_soc_slave_lcl_err_reg_nonfatal[] = {
+	[0 ... 31]  = {"Undefined",			XE_HW_ERR_SOC_NONFATAL_UNKNOWN},
+};
+
+static const struct err_name_index_pair pvc_soc_mstr_lcl_err_reg_nonfatal[] = {
+	[0 ... 3]   = {"Undefined",				XE_HW_ERR_SOC_NONFATAL_UNKNOWN},
+	[4]         = {"Base Die MDFI T2T",			XE_HW_ERR_SOC_NONFATAL_MDFI_T2T},
+	[5]         = {"Undefined",				XE_HW_ERR_SOC_NONFATAL_UNKNOWN},
+	[6]         = {"Base Die MDFI T2C",			XE_HW_ERR_SOC_NONFATAL_MDFI_T2C},
+	[7]         = {"Undefined",				XE_HW_ERR_SOC_NONFATAL_UNKNOWN},
+	[8]         = {"Invalid CSC PSF Command Parity",	XE_HW_ERR_SOC_NONFATAL_CSC_PSF_CMD},
+	[9]         = {"Invalid CSC PSF Unexpected Completion",	XE_HW_ERR_SOC_NONFATAL_CSC_PSF_CMP},
+	[10]        = {"Invalid CSC PSF Unsupported Request",	XE_HW_ERR_SOC_NONFATAL_CSC_PSF_REQ},
+	[11 ... 31] = {"Undefined",				XE_HW_ERR_SOC_NONFATAL_UNKNOWN},
+};
+
 void xe_assign_hw_err_regs(struct xe_device *xe)
 {
 	const struct err_name_index_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
@@ -294,6 +355,10 @@ void xe_assign_hw_err_regs(struct xe_device *xe)
 		soc_mstr_lcl[HARDWARE_ERROR_FATAL] = pvc_soc_mstr_lcl_err_reg_fatal;
 		soc_slave_glbl[HARDWARE_ERROR_FATAL] = pvc_soc_slave_glbl_err_reg_fatal;
 		soc_slave_lcl[HARDWARE_ERROR_FATAL] = pvc_soc_slave_lcl_err_reg_fatal;
+		soc_mstr_glbl[HARDWARE_ERROR_NONFATAL] = pvc_soc_mstr_glbl_err_reg_nonfatal;
+		soc_mstr_lcl[HARDWARE_ERROR_NONFATAL] = pvc_soc_mstr_lcl_err_reg_nonfatal;
+		soc_slave_glbl[HARDWARE_ERROR_NONFATAL] = pvc_soc_slave_glbl_err_reg_nonfatal;
+		soc_slave_lcl[HARDWARE_ERROR_NONFATAL] = pvc_soc_slave_lcl_err_reg_nonfatal;
 	}
 
 }
@@ -571,7 +636,10 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 
 	lockdep_assert_held(&tile_to_xe(tile)->irq.lock);
 
-	if ((tile_to_xe(tile)->info.platform != XE_PVC) ||  hw_err != HARDWARE_ERROR_FATAL)
+	if (tile_to_xe(tile)->info.platform != XE_PVC)
+		return;
+
+	if (hw_err == HARDWARE_ERROR_CORRECTABLE)
 		return;
 
 	base = SOC_PVC_BASE;
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index bd380b7a7130..e53a3f0c8b67 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -105,6 +105,45 @@ enum xe_tile_hw_errors {
 	XE_HW_ERR_SOC_FATAL_PCIE_PSF_CMD,
 	XE_HW_ERR_SOC_FATAL_PCIE_PSF_CMP,
 	XE_HW_ERR_SOC_FATAL_PCIE_PSF_REQ,
+	XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL0,
+	XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL1,
+	XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL2,
+	XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL3,
+	XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL4,
+	XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL5,
+	XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL6,
+	XE_HW_ERR_SOC_NONFATAL_HBM0_CHNL7,
+	XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL0,
+	XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL1,
+	XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL2,
+	XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL3,
+	XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL4,
+	XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL5,
+	XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL6,
+	XE_HW_ERR_SOC_NONFATAL_HBM1_CHNL7,
+	XE_HW_ERR_SOC_NONFATAL_UNKNOWN,
+	XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL0,
+	XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL1,
+	XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL2,
+	XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL3,
+	XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL4,
+	XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL5,
+	XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL6,
+	XE_HW_ERR_SOC_NONFATAL_HBM2_CHNL7,
+	XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL0,
+	XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL1,
+	XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL2,
+	XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL3,
+	XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL4,
+	XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL5,
+	XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL6,
+	XE_HW_ERR_SOC_NONFATAL_HBM3_CHNL7,
+	XE_HW_ERR_SOC_NONFATAL_ANR_MDFI,
+	XE_HW_ERR_SOC_NONFATAL_MDFI_T2T,
+	XE_HW_ERR_SOC_NONFATAL_MDFI_T2C,
+	XE_HW_ERR_SOC_NONFATAL_CSC_PSF_CMD,
+	XE_HW_ERR_SOC_NONFATAL_CSC_PSF_CMP,
+	XE_HW_ERR_SOC_NONFATAL_CSC_PSF_REQ,
 	XE_TILE_HW_ERROR_MAX,
 };
 
-- 
2.25.1

[Intel-xe] [PATCH v2 09/11] drm/xe: Handle MDFI error severity.

[Himal Prasad Ghimiray]

NONFATAL and FATAL MDFI(T2T/T2C) errors are reported by same IEH
register and bits (Bit 4 and Bit 6 of 0x282280). To determine the
severity read local first error header log register (0x2822b0).
Value 0x00330000 ensures severity is fatal and 0x00310000 is for NONFATAL
errors. This register doesn't need explicit clearing, clearing MDFI
bit in IEH reg will clear this register too. Incase of nonfatal value
being reported by status register in fatal flow don't clean the MDFI IEH
bit and continue. Same needs to be addressed if value read by status
register is fatal in nonfatal flow.

v2
- Add commit message.

Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  9 +++++++++
 drivers/gpu/drm/xe/xe_hw_error.c             | 16 ++++++++++++++--
 2 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
index 1b35fe5ee785..235dc93ce274 100644
--- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
@@ -37,6 +37,8 @@
 #define SOC_LOCAL_ERR_STAT_MASTER_REG(base, x)		XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
 								(base) + _SOC_LERRUNCSTS : \
 								(base) + _SOC_LERRCORSTS)
+#define   MDFI_T2T                                     4
+#define   MDFI_T2C                                     6
 
 
 #define _DEV_ERR_STAT_NONFATAL                         0x100178
@@ -49,6 +51,13 @@
 #define   XE_SOC_ERROR                                 16
 
 #define SOC_PVC_BASE	                               0x282000
+
+#define LOCAL_FIRST_IEH_HEADER_LOG_REG		       XE_REG(0x2822b0)
+#define MDFI_SEVERITY_FATAL		               0x00330000
+#define MDFI_SEVERITY_NONFATAL		               0x00310000
+#define MDFI_SEVERITY(x)			       ((x) == HARDWARE_ERROR_FATAL ? \
+							       MDFI_SEVERITY_FATAL : \
+							       MDFI_SEVERITY_NONFATAL)
 #define SOC_PVC_SLAVE_BASE                             0x283000
 
 #define PVC_GSC_HECI1_BASE                             0x284000
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 7c41e51fbb11..9b960292470f 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -629,7 +629,7 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 {
 	unsigned long mst_glb_errstat, slv_glb_errstat, lcl_errstat;
 	struct hardware_errors_regs *err_regs;
-	u32 errbit, base, slave_base;
+	u32 errbit, base, slave_base, ieh_header;
 	int i;
 
 	struct xe_gt *gt = tile->primary_gt;
@@ -697,9 +697,21 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 			"Tile%d reported SOC_LOCAL_ERR_STAT_MASTER_REG_FATAL:0x%08lx\n",
 			tile->id, lcl_errstat);
 
-		for_each_set_bit(errbit, &lcl_errstat, XE_RAS_REG_SIZE)
+		for_each_set_bit(errbit, &lcl_errstat, XE_RAS_REG_SIZE) {
+			if (errbit == MDFI_T2T || errbit == MDFI_T2C) {
+				ieh_header = xe_mmio_read32(gt, LOCAL_FIRST_IEH_HEADER_LOG_REG);
+				drm_info(&tile_to_xe(tile)->drm, HW_ERR "Tile%d LOCAL_FIRST_IEH_HEADER_LOG_REG:0x%08x\n",
+					 tile->id, ieh_header);
+
+				if (ieh_header != MDFI_SEVERITY(hw_err)) {
+					lcl_errstat &= ~REG_BIT(errbit);
+					continue;
+				}
+			}
+
 			xe_soc_log_err_update_cntr(tile, hw_err, errbit,
 						   err_regs->soc_mstr_lcl[hw_err]);
+		}
 
 		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err), lcl_errstat);
 	}
-- 
2.25.1

[Intel-xe] [PATCH v2 10/11] drm/xe: Clear SOC CORRECTABLE error registers.

[Himal Prasad Ghimiray]

PVC doesn't support correctable SOC error reporting, classify them as
Undefined and clear the registers.

v2
- Fix commit message.
- Although the errors are correctable but they are spurious interrupt.
Hence use drm_err instead of drm_warn.(Aravind)

Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_error.c | 23 +++++++++++++++++++++--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 9b960292470f..f6501c1a95f3 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -639,8 +639,26 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 	if (tile_to_xe(tile)->info.platform != XE_PVC)
 		return;
 
-	if (hw_err == HARDWARE_ERROR_CORRECTABLE)
-		return;
+	if (hw_err == HARDWARE_ERROR_CORRECTABLE) {
+		for (i = 0; i < XE_SOC_NUM_IEH; i++)
+			xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
+					~REG_BIT(hw_err));
+
+		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
+				REG_GENMASK(31, 0));
+		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err),
+				REG_GENMASK(31, 0));
+		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+				REG_GENMASK(31, 0));
+		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+				REG_GENMASK(31, 0));
+
+		drm_err(&tile_to_xe(tile)->drm, HW_ERR
+			"Tile%d reported Undefine SOC CORRECTABLE error.",
+			tile->id);
+
+		goto unmask_gsysevtctl;
+	}
 
 	base = SOC_PVC_BASE;
 	slave_base = SOC_PVC_SLAVE_BASE;
@@ -722,6 +740,7 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
 	xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
 			mst_glb_errstat);
 
+unmask_gsysevtctl:
 	for (i = 0; i < XE_SOC_NUM_IEH; i++)
 		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
 				(HARDWARE_ERROR_MAX << 1) + 1);
-- 
2.25.1

[Intel-xe] [PATCH v4 11/11] drm/xe: Clear all SoC errors post warm reset.

[Himal Prasad Ghimiray]

There are scenarios where there are errors being reported from the SoC
uncore to IEH and not propagated to SG unit. Since these errors are not
propagated to SG unit, driver won't be able to clean them as part of
xe_process_hw_error. Hence clear all SoC register post xe_process_hw_error
during the driver load.

v2
- Fix commit message.

v3
- Limit check to PVC.

v4
- Fix check

Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_error.c | 40 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_hw_error.h |  1 +
 drivers/gpu/drm/xe/xe_irq.c      |  1 +
 3 files changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index f6501c1a95f3..fefbdf5ef0fa 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -510,6 +510,46 @@ xe_gt_hw_error_log_vector_reg(struct xe_gt *gt, const enum hardware_error hw_err
 	}
 }
 
+void xe_clear_all_soc_errors(struct xe_device *xe)
+{
+	enum hardware_error hw_err;
+	u32 base, slave_base;
+	struct xe_tile *tile;
+	struct xe_gt *gt;
+	unsigned int i;
+
+	if (xe->info.platform != XE_PVC)
+		return;
+
+	base = SOC_PVC_BASE;
+	slave_base = SOC_PVC_SLAVE_BASE;
+
+	hw_err = HARDWARE_ERROR_CORRECTABLE;
+
+	for_each_tile(tile, xe, i) {
+		gt = tile->primary_gt;
+
+		while (hw_err < HARDWARE_ERROR_MAX) {
+			for (i = 0; i < XE_SOC_NUM_IEH; i++)
+				xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
+						~REG_BIT(hw_err));
+
+			xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
+					REG_GENMASK(31, 0));
+			xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err),
+					REG_GENMASK(31, 0));
+			xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+					REG_GENMASK(31, 0));
+			xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
+					REG_GENMASK(31, 0));
+			hw_err++;
+		}
+		for (i = 0; i < XE_SOC_NUM_IEH; i++)
+			xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
+					(HARDWARE_ERROR_MAX << 1) + 1);
+	}
+}
+
 static void
 xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
 {
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index e53a3f0c8b67..342b03e203c3 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -200,4 +200,5 @@ void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);
 void xe_assign_hw_err_regs(struct xe_device *xe);
 void xe_process_hw_errors(struct xe_device *xe);
 void xe_gsc_hw_error_work(struct work_struct *work);
+void xe_clear_all_soc_errors(struct xe_device *xe);
 #endif
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index bc0f01a2abc1..93cb948de516 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -626,6 +626,7 @@ int xe_irq_install(struct xe_device *xe)
 
 	xe_assign_hw_err_regs(xe);
 	xe_process_hw_errors(xe);
+	xe_clear_all_soc_errors(xe);
 
 	xe_irq_reset(xe);
 
-- 
2.25.1

Re: [Intel-xe] [PATCH v1 02/11] drm/xe: Add new helpers to log hardware errrors.

[Aravind Iddamsetty]

On 19/10/23 18:55, Himal Prasad Ghimiray wrote:
> Introducing xe_gt_log_hw_err and xe_gt_log_hw_err helper to
> report gt specific hardware errors.
>
> Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_gt_printk.h | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h
> index 5991bcadd47e..10e5c4a23c34 100644
> --- a/drivers/gpu/drm/xe/xe_gt_printk.h
> +++ b/drivers/gpu/drm/xe/xe_gt_printk.h
> @@ -43,4 +43,11 @@
>  #define xe_gt_WARN_ON_ONCE(_gt, _condition) \
>  	xe_gt_WARN_ONCE((_gt), _condition, "%s(%s)", "gt_WARN_ON_ONCE", __stringify(_condition))
>  
> +#define xe_gt_log_hw_err(gt, fmt, ...) \
use _gt, _fmt like how the other defines are there and (gt)->
> +	drm_err_ratelimited(&gt_to_xe(gt)->drm, HW_ERR "GT%d reported " fmt, \
> +			    gt->info.id, ##__VA_ARGS__)
> +
> +#define xe_gt_log_hw_warn(gt, fmt, ...) \
> +	drm_warn(&gt_to_xe(gt)->drm, HW_ERR "GT%d detected " fmt, gt->info.id, ##__VA_ARGS__)

why the messages need to be different, both can be reported.

with the above addressed:

Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>

Thanks,
Aravind.
> +
>  #endif

Re: [Intel-xe] [PATCH v3 06/11] drm/xe: Notify userspace about GSC HW errors.

[Welty, Brian]

On 10/19/2023 6:25 AM, Himal Prasad Ghimiray wrote:
> Send uevent incase of nonfatal errors reported by gsc.
> 
> TODO: Since XE_RESET_FAILED_UEVENT and XE_GSC_HW_HEALTH_UEVENT
> both pass DEVICE_STATUS=NEEDS_RESET. Use same Uevent to determine
> the RESET_REQUIRED and pass reasons for reset required as additional
> info.
> 
> v2
> - No need to provide tile info in uevent because error is
> accepted only in tile0. (Aravind)
> 
> v3
> - Use pci node to send uevent.
> - Pass RESET_REASON for uevent.

Can we go a step farther as Aravind was saying and just have one single 
uevent?  Or maybe you have one uevent now, but can still consolidate a 
bit more.
So replace XE_GSC_HW_HEALTH_UEVENT and XE_RESET_FAILED_UEVENT with one 
uevent, defined in uapi header with:

#define XE_RESET_REQUIRED_UEVENT		"RESET_REQUIRED"
#define XE_RESET_REQUIRED_UEVENT_REASON_CSC	"REASON=CSC_HW_ERROR"
#define XE_RESET_REQUIRED_UEVENT_REASON_GT	"REASON=GT_RESET_FAILED"

Would above work?
-Brian


> 
> Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
> Cc: Brian Welty <brian.welty@intel.com>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_device_types.h |  3 +++
>   drivers/gpu/drm/xe/xe_hw_error.c     | 17 +++++++++++++++++
>   drivers/gpu/drm/xe/xe_hw_error.h     |  3 ++-
>   drivers/gpu/drm/xe/xe_irq.c          |  4 ++++
>   include/uapi/drm/xe_drm.h            |  9 +++++++++
>   5 files changed, 35 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 3b371e0f6168..bc7b545ce37b 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -196,6 +196,9 @@ struct xe_tile {
>   	struct tile_hw_errors {
>   		struct xarray hw_error;
>   	} errors;
> +
> +	/** @gsc_hw_err_work: worker for uevent to report GSC HW errors */
> +	struct work_struct gsc_hw_err_work;
>   };
>   
>   /**
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index 84533ef6a51e..644e63d4d717 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -3,6 +3,8 @@
>    * Copyright © 2023 Intel Corporation
>    */
>   
> +#include <drm/xe_drm.h>
> +
>   #include "xe_hw_error.h"
>   
>   #include "regs/xe_regs.h"
> @@ -378,6 +380,20 @@ xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
>   		xe_gt_hw_error_log_vector_reg(gt, hw_err);
>   }
>   
> +void xe_gsc_hw_error_work(struct work_struct *work)
> +{
> +	struct xe_tile *tile = container_of(work, typeof(*tile), gsc_hw_err_work);
> +	struct pci_dev *pdev = to_pci_dev(tile_to_xe(tile)->drm.dev);
> +	char *csc_hw_error_event[3];
> +
> +	csc_hw_error_event[0] = XE_GSC_HW_HEALTH_UEVENT "=1";
> +	csc_hw_error_event[1] = "RESET_REASON=CSC_HW_ERROR";
> +	csc_hw_error_event[2] = NULL;
> +
> +	kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE,
> +			   csc_hw_error_event);
> +}
> +
>   static void
>   xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>   {
> @@ -435,6 +451,7 @@ xe_gsc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>   			drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
>   					    "Tile0 reported GSC %s %s error, bit[%d] is set\n",
>   					    name, hw_err_str, errbit);
> +			schedule_work(&tile->gsc_hw_err_work);
>   		}
>   		if (indx != XE_HW_ERR_TILE_UNSPEC)
>   			xe_update_hw_error_cnt(&tile_to_xe(tile)->drm,
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
> index 997747b6b603..3c02fbd3b256 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.h
> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
> @@ -7,6 +7,7 @@
>   
>   #include <linux/stddef.h>
>   #include <linux/types.h>
> +#include <linux/workqueue.h>
>   
>   #define XE_RAS_REG_SIZE 32
>   
> @@ -106,5 +107,5 @@ struct xe_tile;
>   void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);
>   void xe_assign_hw_err_regs(struct xe_device *xe);
>   void xe_process_hw_errors(struct xe_device *xe);
> -
> +void xe_gsc_hw_error_work(struct work_struct *work);
>   #endif
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 8365a4cb0c45..bc0f01a2abc1 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -614,6 +614,10 @@ int xe_irq_install(struct xe_device *xe)
>   	irq_handler_t irq_handler;
>   	int err, irq;
>   
> +	struct xe_tile *tile = xe_device_get_root_tile(xe);
> +
> +	INIT_WORK(&tile->gsc_hw_err_work, xe_gsc_hw_error_work);
> +
>   	irq_handler = xe_irq_handler(xe);
>   	if (!irq_handler) {
>   		drm_err(&xe->drm, "No supported interrupt handler");
> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
> index 24bf8f0f52e8..4e5e57bc9f69 100644
> --- a/include/uapi/drm/xe_drm.h
> +++ b/include/uapi/drm/xe_drm.h
> @@ -16,6 +16,15 @@ extern "C" {
>    * subject to backwards-compatibility constraints.
>    */
>   
> +/**
> + * DOC: uevent generated by xe on it's pci node.
> + *
> + * XE_GSC_HW_HEALTH_UEVENT - Event is generated when GSC reports HW
> + * errors. The value supplied with the event is always "NEEDS_RESET"
> + * Additional information supplied is "RESET_REASON=CSC_HW_ERROR".
> + */
> +#define XE_GSC_HW_HEALTH_UEVENT "DEVICE_STATUS"
> +
>   /**
>    * DOC: uevent generated by xe on it's pci node.
>    *

Re: [Intel-xe] [PATCH v3 06/11] drm/xe: Notify userspace about GSC HW errors.

[Ghimiray, Himal Prasad]

[-- Attachment #1: Type: text/plain, Size: 6484 bytes --]


On 19-10-2023 22:34, Welty, Brian wrote:
>
>
> On 10/19/2023 6:25 AM, Himal Prasad Ghimiray wrote:
>> Send uevent incase of nonfatal errors reported by gsc.
>>
>> TODO: Since XE_RESET_FAILED_UEVENT and XE_GSC_HW_HEALTH_UEVENT
>> both pass DEVICE_STATUS=NEEDS_RESET. Use same Uevent to determine
>> the RESET_REQUIRED and pass reasons for reset required as additional
>> info.
>>
>> v2
>> - No need to provide tile info in uevent because error is
>> accepted only in tile0. (Aravind)
>>
>> v3
>> - Use pci node to send uevent.
>> - Pass RESET_REASON for uevent.
>
> Can we go a step farther as Aravind was saying and just have one 
> single uevent?  Or maybe you have one uevent now, but can still 
> consolidate a bit more.
> So replace XE_GSC_HW_HEALTH_UEVENT and XE_RESET_FAILED_UEVENT with one 
> uevent, defined in uapi header with:
>
> #define XE_RESET_REQUIRED_UEVENT        "RESET_REQUIRED"
> #define XE_RESET_REQUIRED_UEVENT_REASON_CSC "REASON=CSC_HW_ERROR"
> #define XE_RESET_REQUIRED_UEVENT_REASON_GT "REASON=GT_RESET_FAILED"

Hi Brian,

While implementing XE_RESET_FAILED_UEVENT, the recommendation was to use

"DEVICE_STATUS=NEEDS_RESET" instead of "RESET_REQUIRED.

Will be proceeding with:

#define XE_RESET_REQUIRED_UEVENT        "DEVICE_STATUS=NEEDS_RESET"
#define XE_RESET_REQUIRED_UEVENT_REASON_CSC "REASON=CSC_HW_ERROR"
#define XE_RESET_REQUIRED_UEVENT_REASON_GT "REASON=GT_RESET_FAILED"

Thanks for the review comments, will be updating it in next patch.

BR
Himal

>
> Would above work?
> -Brian
>
>
>>
>> Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
>> Cc: Brian Welty <brian.welty@intel.com>
>> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_device_types.h |  3 +++
>>   drivers/gpu/drm/xe/xe_hw_error.c     | 17 +++++++++++++++++
>>   drivers/gpu/drm/xe/xe_hw_error.h     |  3 ++-
>>   drivers/gpu/drm/xe/xe_irq.c          |  4 ++++
>>   include/uapi/drm/xe_drm.h            |  9 +++++++++
>>   5 files changed, 35 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h 
>> b/drivers/gpu/drm/xe/xe_device_types.h
>> index 3b371e0f6168..bc7b545ce37b 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -196,6 +196,9 @@ struct xe_tile {
>>       struct tile_hw_errors {
>>           struct xarray hw_error;
>>       } errors;
>> +
>> +    /** @gsc_hw_err_work: worker for uevent to report GSC HW errors */
>> +    struct work_struct gsc_hw_err_work;
>>   };
>>     /**
>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c 
>> b/drivers/gpu/drm/xe/xe_hw_error.c
>> index 84533ef6a51e..644e63d4d717 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>> @@ -3,6 +3,8 @@
>>    * Copyright © 2023 Intel Corporation
>>    */
>>   +#include <drm/xe_drm.h>
>> +
>>   #include "xe_hw_error.h"
>>     #include "regs/xe_regs.h"
>> @@ -378,6 +380,20 @@ xe_gt_hw_error_handler(struct xe_gt *gt, const 
>> enum hardware_error hw_err)
>>           xe_gt_hw_error_log_vector_reg(gt, hw_err);
>>   }
>>   +void xe_gsc_hw_error_work(struct work_struct *work)
>> +{
>> +    struct xe_tile *tile = container_of(work, typeof(*tile), 
>> gsc_hw_err_work);
>> +    struct pci_dev *pdev = to_pci_dev(tile_to_xe(tile)->drm.dev);
>> +    char *csc_hw_error_event[3];
>> +
>> +    csc_hw_error_event[0] = XE_GSC_HW_HEALTH_UEVENT "=1";
>> +    csc_hw_error_event[1] = "RESET_REASON=CSC_HW_ERROR";
>> +    csc_hw_error_event[2] = NULL;
>> +
>> +    kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE,
>> +               csc_hw_error_event);
>> +}
>> +
>>   static void
>>   xe_gsc_hw_error_handler(struct xe_tile *tile, const enum 
>> hardware_error hw_err)
>>   {
>> @@ -435,6 +451,7 @@ xe_gsc_hw_error_handler(struct xe_tile *tile, 
>> const enum hardware_error hw_err)
>>               drm_err_ratelimited(&tile_to_xe(tile)->drm, HW_ERR
>>                           "Tile0 reported GSC %s %s error, bit[%d] is 
>> set\n",
>>                           name, hw_err_str, errbit);
>> +            schedule_work(&tile->gsc_hw_err_work);
>>           }
>>           if (indx != XE_HW_ERR_TILE_UNSPEC)
>> xe_update_hw_error_cnt(&tile_to_xe(tile)->drm,
>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h 
>> b/drivers/gpu/drm/xe/xe_hw_error.h
>> index 997747b6b603..3c02fbd3b256 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_error.h
>> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
>> @@ -7,6 +7,7 @@
>>     #include <linux/stddef.h>
>>   #include <linux/types.h>
>> +#include <linux/workqueue.h>
>>     #define XE_RAS_REG_SIZE 32
>>   @@ -106,5 +107,5 @@ struct xe_tile;
>>   void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 
>> master_ctl);
>>   void xe_assign_hw_err_regs(struct xe_device *xe);
>>   void xe_process_hw_errors(struct xe_device *xe);
>> -
>> +void xe_gsc_hw_error_work(struct work_struct *work);
>>   #endif
>> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>> index 8365a4cb0c45..bc0f01a2abc1 100644
>> --- a/drivers/gpu/drm/xe/xe_irq.c
>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>> @@ -614,6 +614,10 @@ int xe_irq_install(struct xe_device *xe)
>>       irq_handler_t irq_handler;
>>       int err, irq;
>>   +    struct xe_tile *tile = xe_device_get_root_tile(xe);
>> +
>> +    INIT_WORK(&tile->gsc_hw_err_work, xe_gsc_hw_error_work);
>> +
>>       irq_handler = xe_irq_handler(xe);
>>       if (!irq_handler) {
>>           drm_err(&xe->drm, "No supported interrupt handler");
>> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
>> index 24bf8f0f52e8..4e5e57bc9f69 100644
>> --- a/include/uapi/drm/xe_drm.h
>> +++ b/include/uapi/drm/xe_drm.h
>> @@ -16,6 +16,15 @@ extern "C" {
>>    * subject to backwards-compatibility constraints.
>>    */
>>   +/**
>> + * DOC: uevent generated by xe on it's pci node.
>> + *
>> + * XE_GSC_HW_HEALTH_UEVENT - Event is generated when GSC reports HW
>> + * errors. The value supplied with the event is always "NEEDS_RESET"
>> + * Additional information supplied is "RESET_REASON=CSC_HW_ERROR".
>> + */
>> +#define XE_GSC_HW_HEALTH_UEVENT "DEVICE_STATUS"
>> +
>>   /**
>>    * DOC: uevent generated by xe on it's pci node.
>>    *

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Re: [Intel-xe] [PATCH v8 03/11] drm/xe: Log and count the GT hardware errors.

[Aravind Iddamsetty]

On 19/10/23 18:55, Himal Prasad Ghimiray wrote:
> For the errors reported by GT unit, read the GT error register.
> Log and count these errors and clear the error register.
>
> Bspec: 53088, 53089, 53090
>
> v6
> - define the BIT and use it.
> - Limit the GT error reporting to DG2 and PVC only.
> - Rename function to xe_gt_hw_error_log_status_reg from
>   xe_gt_hw_error_status_reg_handler. (Aravind)
>
> v7
> - ci fixes
>
> v8
> - Initialize xarray only for primary gt.
> - maintain header orders.
> - Use new defined helper for gt error loging. (Aravind)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_error_regs.h   | 13 +++
>  drivers/gpu/drm/xe/regs/xe_tile_error_regs.h |  1 +
>  drivers/gpu/drm/xe/xe_device.c               |  5 +-
>  drivers/gpu/drm/xe/xe_device_types.h         |  1 +
>  drivers/gpu/drm/xe/xe_gt_types.h             |  6 ++
>  drivers/gpu/drm/xe/xe_hw_error.c             | 94 +++++++++++++++++++-
>  drivers/gpu/drm/xe/xe_hw_error.h             | 24 +++++
>  drivers/gpu/drm/xe/xe_tile.c                 |  1 +
>  8 files changed, 143 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
> new file mode 100644
> index 000000000000..6180704a6149
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +#ifndef XE_GT_ERROR_REGS_H_
> +#define XE_GT_ERROR_REGS_H_
> +
> +#define _ERR_STAT_GT_COR                0x100160
> +#define _ERR_STAT_GT_NONFATAL           0x100164
> +#define ERR_STAT_GT_REG(x)              XE_REG(_PICK_EVEN((x), \
> +						_ERR_STAT_GT_COR, \
> +						_ERR_STAT_GT_NONFATAL))
> +#endif
> diff --git a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> index ba5480fb2789..45bd6b85e115 100644
> --- a/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_tile_error_regs.h
> @@ -10,4 +10,5 @@
>  #define DEV_ERR_STAT_REG(x)                            XE_REG(_PICK_EVEN((x), \
>  								_DEV_ERR_STAT_CORRECTABLE, \
>  								_DEV_ERR_STAT_NONFATAL))
> +#define   XE_GT_ERROR				       0
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index 7b6487cfaf61..628cb46a2509 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -392,8 +392,11 @@ static void xe_hw_error_fini(struct xe_device *xe)
>  	struct xe_tile *tile;
>  	int i;
>  
> -	for_each_tile(tile, xe, i)
> +	for_each_tile(tile, xe, i) {
>  		xa_destroy(&tile->errors.hw_error);
> +		xa_destroy(&tile->primary_gt->errors.hw_error);
> +	}
> +
>  }
>  
>  void xe_device_remove(struct xe_device *xe)
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index d817016b4e38..675cf0c00be2 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -414,6 +414,7 @@ struct xe_device {
>  	/** @hw_err_regs: list of hw error regs*/
>  	struct hardware_errors_regs {
>  		const struct err_name_index_pair *dev_err_stat[HARDWARE_ERROR_MAX];
> +		const struct err_name_index_pair *err_stat_gt[HARDWARE_ERROR_MAX];
>  	} hw_err_regs;
>  
>  	/* private: */
> diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
> index d3f2793684e2..f6ef1e381d55 100644
> --- a/drivers/gpu/drm/xe/xe_gt_types.h
> +++ b/drivers/gpu/drm/xe/xe_gt_types.h
> @@ -9,6 +9,7 @@
>  #include "xe_force_wake_types.h"
>  #include "xe_gt_idle_sysfs_types.h"
>  #include "xe_hw_engine_types.h"
> +#include "xe_hw_error.h"
>  #include "xe_hw_fence_types.h"
>  #include "xe_reg_sr_types.h"
>  #include "xe_sa_types.h"
> @@ -347,6 +348,11 @@ struct xe_gt {
>  		/** @oob: bitmap with active OOB workaroudns */
>  		unsigned long *oob;
>  	} wa_active;
> +
> +	/** @errors: count of hardware errors reported for the gt */
> +	struct gt_hw_errors {
> +		struct xarray hw_error;
> +	} errors;
>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index a4f2f00823ef..c4bc24a35231 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -6,6 +6,7 @@
>  #include "xe_hw_error.h"
>  
>  #include "regs/xe_regs.h"
> +#include "regs/xe_gt_error_regs.h"
>  #include "regs/xe_tile_error_regs.h"
>  #include "xe_device.h"
>  #include "xe_mmio.h"
> @@ -100,15 +101,48 @@ static const struct err_name_index_pair pvc_err_stat_correctable_reg[] = {
>  	[9 ... 31]  =  {"Undefined",		XE_HW_ERR_TILE_CORR_UNKNOWN},
>  };
>  
> +static const struct err_name_index_pair dg2_stat_gt_fatal_reg[] = {
> +	[0]         =  {"Undefined",		XE_HW_ERR_GT_FATAL_UNKNOWN},
> +	[1]         =  {"Array BIST",		XE_HW_ERR_GT_FATAL_ARR_BIST},
> +	[2]         =  {"Undefined",		XE_HW_ERR_GT_FATAL_UNKNOWN},
> +	[3]         =  {"FPU",			XE_HW_ERR_GT_FATAL_FPU},
> +	[4]         =  {"L3 Double",		XE_HW_ERR_GT_FATAL_L3_DOUB},
> +	[5]         =  {"L3 ECC Checker",	XE_HW_ERR_GT_FATAL_L3_ECC_CHK},
> +	[6]         =  {"GUC SRAM",		XE_HW_ERR_GT_FATAL_GUC},
> +	[7]         =  {"Undefined",		XE_HW_ERR_GT_FATAL_UNKNOWN},
> +	[8]         =  {"IDI PARITY",		XE_HW_ERR_GT_FATAL_IDI_PAR},
> +	[9]	    =  {"SQIDI",		XE_HW_ERR_GT_FATAL_SQIDI},
> +	[10 ... 11] =  {"Undefined",		XE_HW_ERR_GT_FATAL_UNKNOWN},
> +	[12]        =  {"SAMPLER",		XE_HW_ERR_GT_FATAL_SAMPLER},
> +	[13]        =  {"SLM",			XE_HW_ERR_GT_FATAL_SLM},
> +	[14]        =  {"EU IC",		XE_HW_ERR_GT_FATAL_EU_IC},
> +	[15]        =  {"EU GRF",		XE_HW_ERR_GT_FATAL_EU_GRF},
> +	[16 ... 31] =  {"Undefined",            XE_HW_ERR_GT_FATAL_UNKNOWN},
> +};
> +
> +static const struct err_name_index_pair dg2_stat_gt_correctable_reg[] = {
> +	[0]         = {"L3 SINGLE",		XE_HW_ERR_GT_CORR_L3_SNG},
> +	[1]         = {"SINGLE BIT GUC SRAM",	XE_HW_ERR_GT_CORR_GUC},
> +	[2 ... 11]  = {"Undefined",		XE_HW_ERR_GT_CORR_UNKNOWN},
> +	[12]        = {"SINGLE BIT SAMPLER",	XE_HW_ERR_GT_CORR_SAMPLER},
> +	[13]        = {"SINGLE BIT SLM",	XE_HW_ERR_GT_CORR_SLM},
> +	[14]        = {"SINGLE BIT EU IC",	XE_HW_ERR_GT_CORR_EU_IC},
> +	[15]        = {"SINGLE BIT EU GRF",	XE_HW_ERR_GT_CORR_EU_GRF},
> +	[16 ... 31] = {"Undefined",             XE_HW_ERR_GT_CORR_UNKNOWN},
> +};
> +
>  void xe_assign_hw_err_regs(struct xe_device *xe)
>  {
>  	const struct err_name_index_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
> +	const struct err_name_index_pair **err_stat_gt = xe->hw_err_regs.err_stat_gt;
>  
>  	/* Error reporting is supported only for DG2 and PVC currently. */
>  	if (xe->info.platform == XE_DG2) {
>  		dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = dg2_err_stat_correctable_reg;
>  		dev_err_stat[HARDWARE_ERROR_NONFATAL] = dg2_err_stat_nonfatal_reg;
>  		dev_err_stat[HARDWARE_ERROR_FATAL] = dg2_err_stat_fatal_reg;
> +		err_stat_gt[HARDWARE_ERROR_CORRECTABLE] = dg2_stat_gt_correctable_reg;
> +		err_stat_gt[HARDWARE_ERROR_FATAL] = dg2_stat_gt_fatal_reg;
>  	}
>  
>  	if (xe->info.platform == XE_PVC) {
> @@ -116,6 +150,7 @@ void xe_assign_hw_err_regs(struct xe_device *xe)
>  		dev_err_stat[HARDWARE_ERROR_NONFATAL] = pvc_err_stat_nonfatal_reg;
>  		dev_err_stat[HARDWARE_ERROR_FATAL] = pvc_err_stat_fatal_reg;
>  	}
> +
>  }
>  
>  static bool xe_platform_has_ras(struct xe_device *xe)
> @@ -142,6 +177,62 @@ xe_update_hw_error_cnt(struct drm_device *drm, struct xarray *hw_error, unsigned
>  	xa_unlock_irqrestore(hw_error, flags);
>  }
>  
> +static void
> +xe_gt_hw_error_log_status_reg(struct xe_gt *gt, const enum hardware_error hw_err)
> +{
> +	const char *hw_err_str = hardware_error_type_to_str(hw_err);
> +	const struct err_name_index_pair *errstat;
> +	struct hardware_errors_regs *err_regs;
> +	unsigned long errsrc;
> +	const char *name;
> +	u32 indx;
> +	u32 errbit;
> +
> +	err_regs = &gt_to_xe(gt)->hw_err_regs;
> +	errsrc = xe_mmio_read32(gt, ERR_STAT_GT_REG(hw_err));
> +	if (!errsrc) {
> +		xe_gt_log_hw_err(gt, "ERR_STAT_GT_REG_%s blank!\n", hw_err_str);
> +		return;
> +	}
> +
> +	drm_dbg(&gt_to_xe(gt)->drm, HW_ERR "GT%d ERR_STAT_GT_REG_%s=0x%08lx\n",
> +		gt->info.id, hw_err_str, errsrc);
> +
> +	if (hw_err == HARDWARE_ERROR_NONFATAL) {
> +		/*  The GT Non Fatal Error Status Register has only reserved bits
> +		 *  Nothing to service.
> +		 */
> +		xe_gt_log_hw_err(gt, "%s error\n", hw_err_str);
> +		goto clear_reg;
> +	}
> +
> +	errstat = err_regs->err_stat_gt[hw_err];
> +	for_each_set_bit(errbit, &errsrc, XE_RAS_REG_SIZE) {
> +		name = errstat[errbit].name;
> +		indx = errstat[errbit].index;
> +
> +		if (hw_err == HARDWARE_ERROR_FATAL)
> +			xe_gt_log_hw_err(gt, "%s %s error, bit[%d] is set\n",
> +					 name, hw_err_str, errbit);
> +		else
> +			xe_gt_log_hw_err(gt, "%s %s error, bit[%d] is set\n",
> +					 name, hw_err_str, errbit);
> +
> +		xe_update_hw_error_cnt(&gt_to_xe(gt)->drm, &gt->errors.hw_error, indx);
> +	}
> +clear_reg:
> +	xe_mmio_write32(gt, ERR_STAT_GT_REG(hw_err), errsrc);
> +}
> +
> +static void
> +xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
> +{
> +	lockdep_assert_held(&gt_to_xe(gt)->irq.lock);
> +
> +	if (gt_to_xe(gt)->info.platform == XE_DG2)
> +		xe_gt_hw_error_log_status_reg(gt, hw_err);
> +}
> +
>  static void
>  xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  {
> @@ -193,8 +284,9 @@ xe_hw_error_source_handler(struct xe_tile *tile, const enum hardware_error hw_er
>  		if (indx != XE_HW_ERR_TILE_UNSPEC)
>  			xe_update_hw_error_cnt(&tile_to_xe(tile)->drm,
>  					       &tile->errors.hw_error, indx);
> +		if (errbit == XE_GT_ERROR)
> +			xe_gt_hw_error_handler(tile->primary_gt, hw_err);
>  	}
> -
>  	xe_mmio_write32(gt, DEV_ERR_STAT_REG(hw_err), errsrc);
>  unlock:
>  	spin_unlock_irqrestore(&tile_to_xe(tile)->irq.lock, flags);
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
> index 1932f64e26da..40869e2b97d3 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.h
> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
> @@ -37,6 +37,30 @@ enum xe_tile_hw_errors {
>  	XE_HW_ERR_TILE_CORR_UNKNOWN,
>  };
>  
> +/* Count of GT Correctable and FATAL HW ERRORS */
> +enum xe_gt_hw_errors {
> +	XE_HW_ERR_GT_CORR_L3_SNG,
> +	XE_HW_ERR_GT_CORR_GUC,
> +	XE_HW_ERR_GT_CORR_SAMPLER,
> +	XE_HW_ERR_GT_CORR_SLM,
> +	XE_HW_ERR_GT_CORR_EU_IC,
> +	XE_HW_ERR_GT_CORR_EU_GRF,
> +	XE_HW_ERR_GT_CORR_UNKNOWN,
> +	XE_HW_ERR_GT_FATAL_ARR_BIST,
> +	XE_HW_ERR_GT_FATAL_FPU,
> +	XE_HW_ERR_GT_FATAL_L3_DOUB,
> +	XE_HW_ERR_GT_FATAL_L3_ECC_CHK,
> +	XE_HW_ERR_GT_FATAL_GUC,
> +	XE_HW_ERR_GT_FATAL_IDI_PAR,
> +	XE_HW_ERR_GT_FATAL_SQIDI,
> +	XE_HW_ERR_GT_FATAL_SAMPLER,
> +	XE_HW_ERR_GT_FATAL_SLM,
> +	XE_HW_ERR_GT_FATAL_EU_IC,
> +	XE_HW_ERR_GT_FATAL_EU_GRF,
> +	XE_HW_ERR_GT_FATAL_UNKNOWN,
> +	XE_HW_ERR_GT_MAX,
> +};
> +
>  struct err_name_index_pair {
>  	const char *name;
>  	const u32 index;
> diff --git a/drivers/gpu/drm/xe/xe_tile.c b/drivers/gpu/drm/xe/xe_tile.c
> index bc79145eadc0..bc80d24df572 100644
> --- a/drivers/gpu/drm/xe/xe_tile.c
> +++ b/drivers/gpu/drm/xe/xe_tile.c
> @@ -85,6 +85,7 @@ int xe_tile_alloc(struct xe_tile *tile)
>  	struct drm_device *drm = &tile_to_xe(tile)->drm;
>  
>  	xa_init(&tile->errors.hw_error);
> +	xa_init(&tile->primary_gt->errors.hw_error);
>  
>  	tile->mem.ggtt = drmm_kzalloc(drm, sizeof(*tile->mem.ggtt),
>  				      GFP_KERNEL);

Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>

Thanks,
Aravind.

Re: [Intel-xe] [PATCH v7 04/11] drm/xe: Support GT hardware error reporting for PVC.

[Aravind Iddamsetty]

On 19/10/23 18:55, Himal Prasad Ghimiray wrote:
> PVC supports GT error reporting via vector registers alongwith
> error status register. Add support to report these errors and
> update respective counters.
> Incase of Subslice error reported by vector register, process the
> error status register for applicable bits.
>
> Bspec: 54179, 54177, 53088, 53089
>
> v6
> - Define registers ascending order of their addresses.
> - use xe_gt_hw_error_log_vector_reg instead of
>   xe_gt_hw_error_vectr_reg_handler.
> - use xe_assign_hw_err_regs for reg initialization.
> - use switch-case instead of if-else.
>
> v7
> - Use all vctr for correctable too.
> - Use helper functions to log gt hardware errors. (Aravind)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_error_regs.h |  16 +++
>  drivers/gpu/drm/xe/xe_device_types.h       |   1 +
>  drivers/gpu/drm/xe/xe_hw_error.c           | 124 ++++++++++++++++++++-
>  drivers/gpu/drm/xe/xe_hw_error.h           |  19 ++++
>  4 files changed, 158 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
> index 6180704a6149..59631c2e8e12 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_error_regs.h
> @@ -10,4 +10,20 @@
>  #define ERR_STAT_GT_REG(x)              XE_REG(_PICK_EVEN((x), \
>  						_ERR_STAT_GT_COR, \
>  						_ERR_STAT_GT_NONFATAL))
> +
> +#define _ERR_STAT_GT_FATAL_VCTR_0       0x100260
> +#define _ERR_STAT_GT_FATAL_VCTR_1       0x100264
> +#define ERR_STAT_GT_FATAL_VCTR_REG(x)   XE_REG(_PICK_EVEN((x), \
> +						_ERR_STAT_GT_FATAL_VCTR_0, \
> +						_ERR_STAT_GT_FATAL_VCTR_1))
> +
> +#define _ERR_STAT_GT_COR_VCTR_0         0x1002a0
> +#define _ERR_STAT_GT_COR_VCTR_1         0x1002a4
> +#define ERR_STAT_GT_COR_VCTR_REG(x)     XE_REG(_PICK_EVEN((x), \
> +						_ERR_STAT_GT_COR_VCTR_0, \
> +						_ERR_STAT_GT_COR_VCTR_1))
> +
> +#define ERR_STAT_GT_VCTR_REG(hw_err, x) (hw_err == HARDWARE_ERROR_CORRECTABLE ? \
> +						ERR_STAT_GT_COR_VCTR_REG(x) : \
> +						ERR_STAT_GT_FATAL_VCTR_REG(x))
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 675cf0c00be2..4624f2f53b26 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -415,6 +415,7 @@ struct xe_device {
>  	struct hardware_errors_regs {
>  		const struct err_name_index_pair *dev_err_stat[HARDWARE_ERROR_MAX];
>  		const struct err_name_index_pair *err_stat_gt[HARDWARE_ERROR_MAX];
> +		const struct err_name_index_pair *err_vctr_gt[HARDWARE_ERROR_MAX];
>  	} hw_err_regs;
>  
>  	/* private: */
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index c4bc24a35231..c94825b9c1fe 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -131,10 +131,47 @@ static const struct err_name_index_pair dg2_stat_gt_correctable_reg[] = {
>  	[16 ... 31] = {"Undefined",             XE_HW_ERR_GT_CORR_UNKNOWN},
>  };
>  
> +static const struct err_name_index_pair pvc_err_stat_gt_fatal_reg[] = {
> +	[0 ... 2]   =  {"Undefined",		XE_HW_ERR_GT_FATAL_UNKNOWN},
> +	[3]         =  {"FPU",			XE_HW_ERR_GT_FATAL_FPU},
> +	[4 ... 5]   =  {"Undefined",            XE_HW_ERR_GT_FATAL_UNKNOWN},
> +	[6]         =  {"GUC SRAM",		XE_HW_ERR_GT_FATAL_GUC},
> +	[7 ... 12]  =  {"Undefined",		XE_HW_ERR_GT_FATAL_UNKNOWN},
> +	[13]        =  {"SLM",			XE_HW_ERR_GT_FATAL_SLM},
> +	[14]        =  {"Undefined",		XE_HW_ERR_GT_FATAL_UNKNOWN},
> +	[15]        =  {"EU GRF",		XE_HW_ERR_GT_FATAL_EU_GRF},
> +	[16 ... 31] =  {"Undefined",            XE_HW_ERR_GT_FATAL_UNKNOWN},
> +};
> +
> +static const struct err_name_index_pair pvc_err_stat_gt_correctable_reg[] = {
> +	[0]         = {"Undefined",             XE_HW_ERR_GT_CORR_UNKNOWN},
> +	[1]         = {"SINGLE BIT GUC SRAM",	XE_HW_ERR_GT_CORR_GUC},
> +	[2 ... 12]  = {"Undefined",		XE_HW_ERR_GT_CORR_UNKNOWN},
> +	[13]        = {"SINGLE BIT SLM",	XE_HW_ERR_GT_CORR_SLM},
> +	[14]        = {"SINGLE BIT EU IC",	XE_HW_ERR_GT_CORR_EU_IC},
> +	[15]        = {"SINGLE BIT EU GRF",	XE_HW_ERR_GT_CORR_EU_GRF},
> +	[16 ... 31] = {"Undefined",             XE_HW_ERR_GT_CORR_UNKNOWN},
> +};
> +
> +static const struct err_name_index_pair pvc_err_vectr_gt_fatal_reg[] = {
> +	[0 ... 1]         = {"SUBSLICE",	XE_HW_ERR_GT_FATAL_SUBSLICE},
> +	[2 ... 3]         = {"L3BANK",		XE_HW_ERR_GT_FATAL_L3BANK},
> +	[4 ... 5]         = {"Undefined",	XE_HW_ERR_GT_FATAL_UNKNOWN},
> +	[6]               = {"TLB",		XE_HW_ERR_GT_FATAL_TLB},
> +	[7]               = {"L3 FABRIC",	XE_HW_ERR_GT_FATAL_L3_FABRIC},
> +};
> +
> +static const struct err_name_index_pair pvc_err_vectr_gt_correctable_reg[] = {
> +	[0 ... 1]         = {"SUBSLICE",	XE_HW_ERR_GT_CORR_SUBSLICE},
> +	[2 ... 3]         = {"L3BANK",		XE_HW_ERR_GT_CORR_L3BANK},
> +	[4 ... 7]         = {"Undefined",       XE_HW_ERR_GT_CORR_UNKNOWN},
> +};
> +
>  void xe_assign_hw_err_regs(struct xe_device *xe)
>  {
>  	const struct err_name_index_pair **dev_err_stat = xe->hw_err_regs.dev_err_stat;
>  	const struct err_name_index_pair **err_stat_gt = xe->hw_err_regs.err_stat_gt;
> +	const struct err_name_index_pair **err_vctr_gt = xe->hw_err_regs.err_vctr_gt;
>  
>  	/* Error reporting is supported only for DG2 and PVC currently. */
>  	if (xe->info.platform == XE_DG2) {
> @@ -149,6 +186,10 @@ void xe_assign_hw_err_regs(struct xe_device *xe)
>  		dev_err_stat[HARDWARE_ERROR_CORRECTABLE] = pvc_err_stat_correctable_reg;
>  		dev_err_stat[HARDWARE_ERROR_NONFATAL] = pvc_err_stat_nonfatal_reg;
>  		dev_err_stat[HARDWARE_ERROR_FATAL] = pvc_err_stat_fatal_reg;
> +		err_stat_gt[HARDWARE_ERROR_CORRECTABLE] = pvc_err_stat_gt_correctable_reg;
> +		err_stat_gt[HARDWARE_ERROR_FATAL] = pvc_err_stat_gt_fatal_reg;
> +		err_vctr_gt[HARDWARE_ERROR_CORRECTABLE] = pvc_err_vectr_gt_correctable_reg;
> +		err_vctr_gt[HARDWARE_ERROR_FATAL] = pvc_err_vectr_gt_fatal_reg;
>  	}
>  
>  }
> @@ -162,13 +203,14 @@ static bool xe_platform_has_ras(struct xe_device *xe)
>  }
>  
>  static void
> -xe_update_hw_error_cnt(struct drm_device *drm, struct xarray *hw_error, unsigned long index)
> +xe_update_hw_error_cnt_with_value(struct drm_device *drm, struct xarray *hw_error,
> +				  unsigned long index, unsigned long val)
>  {
>  	unsigned long flags;
>  	void *entry;
>  
>  	entry = xa_load(hw_error, index);
> -	entry = xa_mk_value(xa_to_value(entry) + 1);
> +	entry = xa_mk_value(xa_to_value(entry) + val);
>  
>  	xa_lock_irqsave(hw_error, flags);
>  	if (xa_is_err(__xa_store(hw_error, index, entry, GFP_ATOMIC)))
> @@ -177,6 +219,12 @@ xe_update_hw_error_cnt(struct drm_device *drm, struct xarray *hw_error, unsigned
>  	xa_unlock_irqrestore(hw_error, flags);
>  }
>  
> +static void
> +xe_update_hw_error_cnt(struct drm_device *drm, struct xarray *hw_error, unsigned long index)
> +{
> +	xe_update_hw_error_cnt_with_value(drm, hw_error, index, 1);
> +}
> +
>  static void
>  xe_gt_hw_error_log_status_reg(struct xe_gt *gt, const enum hardware_error hw_err)
>  {
> @@ -188,6 +236,7 @@ xe_gt_hw_error_log_status_reg(struct xe_gt *gt, const enum hardware_error hw_err
>  	u32 indx;
>  	u32 errbit;
>  
> +	lockdep_assert_held(&gt_to_xe(gt)->irq.lock);
>  	err_regs = &gt_to_xe(gt)->hw_err_regs;
>  	errsrc = xe_mmio_read32(gt, ERR_STAT_GT_REG(hw_err));
>  	if (!errsrc) {
> @@ -224,6 +273,74 @@ xe_gt_hw_error_log_status_reg(struct xe_gt *gt, const enum hardware_error hw_err
>  	xe_mmio_write32(gt, ERR_STAT_GT_REG(hw_err), errsrc);
>  }
>  
> +static void
> +xe_gt_hw_error_log_vector_reg(struct xe_gt *gt, const enum hardware_error hw_err)
> +{
> +	const char *hw_err_str = hardware_error_type_to_str(hw_err);
> +	const struct err_name_index_pair *errvctr;
> +	struct hardware_errors_regs *err_regs;
> +	const char *name;
> +	bool errstat_read;
> +	unsigned long val;
> +	u32 num_vctr_reg;
> +	u32 indx;
> +	u32 vctr;
> +	u32 i;
> +
> +	if (hw_err == HARDWARE_ERROR_NONFATAL) {
> +		/*  The GT Non Fatal Error Status Register has only reserved bits
> +		 *  Nothing to service.
> +		 */
> +		xe_gt_log_hw_err(gt, "%s error\n", hw_err_str);
> +		return;
> +	}
> +
> +	errstat_read = false;
> +	num_vctr_reg = ERR_STAT_GT_VCTR_LEN;
> +	err_regs = &gt_to_xe(gt)->hw_err_regs;
> +	errvctr = err_regs->err_vctr_gt[hw_err];
> +	for (i = 0 ; i < num_vctr_reg; i++) {
> +		vctr = xe_mmio_read32(gt, ERR_STAT_GT_VCTR_REG(hw_err, i));
> +		if (!vctr)
> +			continue;
> +
> +		name = errvctr[i].name;
> +		indx = errvctr[i].index;
> +
> +		if (hw_err == HARDWARE_ERROR_FATAL)
> +			xe_gt_log_hw_err(gt, "%s %s error. ERR_VECT_GT_%s[%d]:0x%08x\n",
> +					 name, hw_err_str, hw_err_str, i, vctr);
> +		else
> +			xe_gt_log_hw_warn(gt, "%s %s error. ERR_VECT_GT_%s[%d]:0x%08x\n",
> +					  name, hw_err_str, hw_err_str, i, vctr);
> +
> +		switch (i) {
> +		case ERR_STAT_GT_VCTR0:
> +		case ERR_STAT_GT_VCTR1:
> +		case ERR_STAT_GT_VCTR2:
> +		case ERR_STAT_GT_VCTR3:
> +			val = hweight32(vctr);
> +			if (i < ERR_STAT_GT_VCTR2 && !errstat_read) {
> +				xe_gt_hw_error_log_status_reg(gt, hw_err);
> +				errstat_read = true;
> +			}
> +			xe_update_hw_error_cnt_with_value(&gt_to_xe(gt)->drm,
> +							  &gt->errors.hw_error, indx, val);
> +			break;
> +		case ERR_STAT_GT_VCTR6:
> +		case ERR_STAT_GT_VCTR7:
> +			val = (i == ERR_STAT_GT_VCTR6) ? hweight16(vctr) : hweight8(vctr);
> +			xe_update_hw_error_cnt_with_value(&gt_to_xe(gt)->drm,
> +							  &gt->errors.hw_error, indx, val);
> +			break;
> +		default:
> +			break;
> +		}
> +
> +		xe_mmio_write32(gt, ERR_STAT_GT_VCTR_REG(hw_err, i), vctr);
> +	}
> +}
> +
>  static void
>  xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
>  {
> @@ -231,6 +348,9 @@ xe_gt_hw_error_handler(struct xe_gt *gt, const enum hardware_error hw_err)
>  
>  	if (gt_to_xe(gt)->info.platform == XE_DG2)
>  		xe_gt_hw_error_log_status_reg(gt, hw_err);
> +
> +	if (gt_to_xe(gt)->info.platform == XE_PVC)
> +		xe_gt_hw_error_log_vector_reg(gt, hw_err);
>  }
>  
>  static void
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
> index 40869e2b97d3..440e03c7649d 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.h
> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
> @@ -10,6 +10,8 @@
>  
>  #define XE_RAS_REG_SIZE 32
>  
> +#define ERR_STAT_GT_VCTR_LEN (8)
> +
>  /* Error categories reported by hardware */
>  enum hardware_error {
>  	HARDWARE_ERROR_CORRECTABLE = 0,
> @@ -37,8 +39,21 @@ enum xe_tile_hw_errors {
>  	XE_HW_ERR_TILE_CORR_UNKNOWN,
>  };
>  
> +enum gt_vctr_registers {
> +	ERR_STAT_GT_VCTR0 = 0,
> +	ERR_STAT_GT_VCTR1,
> +	ERR_STAT_GT_VCTR2,
> +	ERR_STAT_GT_VCTR3,
> +	ERR_STAT_GT_VCTR4,
> +	ERR_STAT_GT_VCTR5,
> +	ERR_STAT_GT_VCTR6,
> +	ERR_STAT_GT_VCTR7,
> +};
> +
>  /* Count of GT Correctable and FATAL HW ERRORS */
>  enum xe_gt_hw_errors {
> +	XE_HW_ERR_GT_CORR_SUBSLICE,
> +	XE_HW_ERR_GT_CORR_L3BANK,
>  	XE_HW_ERR_GT_CORR_L3_SNG,
>  	XE_HW_ERR_GT_CORR_GUC,
>  	XE_HW_ERR_GT_CORR_SAMPLER,
> @@ -46,6 +61,10 @@ enum xe_gt_hw_errors {
>  	XE_HW_ERR_GT_CORR_EU_IC,
>  	XE_HW_ERR_GT_CORR_EU_GRF,
>  	XE_HW_ERR_GT_CORR_UNKNOWN,
> +	XE_HW_ERR_GT_FATAL_SUBSLICE,
> +	XE_HW_ERR_GT_FATAL_L3BANK,
> +	XE_HW_ERR_GT_FATAL_TLB,
> +	XE_HW_ERR_GT_FATAL_L3_FABRIC,
>  	XE_HW_ERR_GT_FATAL_ARR_BIST,
>  	XE_HW_ERR_GT_FATAL_FPU,
>  	XE_HW_ERR_GT_FATAL_L3_DOUB,

Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>

Thanks,
Aravind.

[Intel-xe] ✓ CI.Patch_applied: success for Supporting RAS on XE

[Patchwork]

== Series Details ==

Series: Supporting RAS on XE
URL   : https://patchwork.freedesktop.org/series/125348/
State : success

== Summary ==

=== Applying kernel patches on branch 'drm-xe-next' with base: ===
Base commit: a0a809501 drm/xe: fix pat[2] programming with 2M/1G pages
=== git am output follows ===
Applying: drm/xe: Handle errors from various components.
Applying: drm/xe: Add new helpers to log hardware errrors.
Applying: drm/xe: Log and count the GT hardware errors.
Applying: drm/xe: Support GT hardware error reporting for PVC.
Applying: drm/xe: Support GSC hardware error reporting for PVC.
Applying: drm/xe: Notify userspace about GSC HW errors.
Applying: drm/xe: Support SOC FATAL error handling for PVC.
Applying: drm/xe: Support SOC NONFATAL error handling for PVC.
Applying: drm/xe: Handle MDFI error severity.
Applying: drm/xe: Clear SOC CORRECTABLE error registers.
Applying: drm/xe: Clear all SoC errors post warm reset.

[Intel-xe] ✗ CI.checkpatch: warning for Supporting RAS on XE

[Patchwork]

== Series Details ==

Series: Supporting RAS on XE
URL   : https://patchwork.freedesktop.org/series/125348/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
63c2b6b160bca2df6efc7bc4cea6f442097d7854
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 1975f8e9a0d35d69dbc3ed77ab2b3c5fc0bbeaff
Author: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Date:   Thu Oct 19 18:55:34 2023 +0530

    drm/xe: Clear all SoC errors post warm reset.
    
    There are scenarios where there are errors being reported from the SoC
    uncore to IEH and not propagated to SG unit. Since these errors are not
    propagated to SG unit, driver won't be able to clean them as part of
    xe_process_hw_error. Hence clear all SoC register post xe_process_hw_error
    during the driver load.
    
    v2
    - Fix commit message.
    
    v3
    - Limit check to PVC.
    
    v4
    - Fix check
    
    Cc: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
    Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
    Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
+ /mt/dim checkpatch a0a80950176b39dbc76f8faa92fddf6caaa06191 drm-intel
568243394 drm/xe: Handle errors from various components.
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:79: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#79: FILE: drivers/gpu/drm/xe/regs/xe_regs.h:61:
+#define   DEV_PCIEERR_IS_FATAL(x)		REG_BIT(x * 4 + 2)

-:93: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#93: 
new file mode 100644

total: 0 errors, 1 warnings, 1 checks, 418 lines checked
652e9fde8 drm/xe: Add new helpers to log hardware errrors.
-:21: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'gt' - possible side-effects?
#21: FILE: drivers/gpu/drm/xe/xe_gt_printk.h:46:
+#define xe_gt_log_hw_err(gt, fmt, ...) \
+	drm_err_ratelimited(&gt_to_xe(gt)->drm, HW_ERR "GT%d reported " fmt, \
+			    gt->info.id, ##__VA_ARGS__)

-:25: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'gt' - possible side-effects?
#25: FILE: drivers/gpu/drm/xe/xe_gt_printk.h:50:
+#define xe_gt_log_hw_warn(gt, fmt, ...) \
+	drm_warn(&gt_to_xe(gt)->drm, HW_ERR "GT%d detected " fmt, gt->info.id, ##__VA_ARGS__)

total: 0 errors, 0 warnings, 2 checks, 11 lines checked
8d121b3ac drm/xe: Log and count the GT hardware errors.
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#35: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 226 lines checked
22a6e0ed3 drm/xe: Support GT hardware error reporting for PVC.
-:54: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'hw_err' may be better as '(hw_err)' to avoid precedence issues
#54: FILE: drivers/gpu/drm/xe/regs/xe_gt_error_regs.h:26:
+#define ERR_STAT_GT_VCTR_REG(hw_err, x) (hw_err == HARDWARE_ERROR_CORRECTABLE ? \
+						ERR_STAT_GT_COR_VCTR_REG(x) : \
+						ERR_STAT_GT_FATAL_VCTR_REG(x))

-:54: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects?
#54: FILE: drivers/gpu/drm/xe/regs/xe_gt_error_regs.h:26:
+#define ERR_STAT_GT_VCTR_REG(hw_err, x) (hw_err == HARDWARE_ERROR_CORRECTABLE ? \
+						ERR_STAT_GT_COR_VCTR_REG(x) : \
+						ERR_STAT_GT_FATAL_VCTR_REG(x))

total: 0 errors, 0 warnings, 2 checks, 241 lines checked
70578572d drm/xe: Support GSC hardware error reporting for PVC.
-:30: CHECK:LINE_SPACING: Please don't use multiple blank lines
#30: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:8:
 
+

-:33: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#33: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:11:
+#define GSC_HEC_ERR_STAT_REG(base, x)                  XE_REG(_PICK_EVEN((x), \
+								(base) + _GSC_HEC_CORR_ERR_STATUS, \
+								(base) + _GSC_HEC_UNCOR_ERR_STATUS))

total: 0 errors, 0 warnings, 2 checks, 178 lines checked
b0e4fda31 drm/xe: Notify userspace about GSC HW errors.
57745cf57 drm/xe: Support SOC FATAL error handling for PVC.
-:42: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#42: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:17:
+#define SOC_GLOBAL_ERR_STAT_SLAVE_REG(base, x)		XE_REG(_PICK_EVEN((x), \
+								(base) + _SOC_GCOERRSTS, \
+								(base) + _SOC_GNFERRSTS))

-:47: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#47: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:22:
+#define SOC_GLOBAL_ERR_STAT_MASTER_REG(base, x)		XE_REG(_PICK_EVEN((x), \
+								(base) + _SOC_GCOERRSTS, \
+								(base) + _SOC_GNFERRSTS))

-:53: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'slave_base' may be better as '(slave_base)' to avoid precedence issues
#53: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:28:
+#define SOC_GSYSEVTCTL_REG(base, slave_base, x)		XE_REG(_PICK_EVEN((x), \
+								(base) + _SOC_GSYSEVTCTL, \
+								slave_base + _SOC_GSYSEVTCTL))

-:59: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#59: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:34:
+#define SOC_LOCAL_ERR_STAT_SLAVE_REG(base, x)		XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
+								(base) + _SOC_LERRUNCSTS : \
+								(base) + _SOC_LERRCORSTS)

-:62: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'base' - possible side-effects?
#62: FILE: drivers/gpu/drm/xe/regs/xe_tile_error_regs.h:37:
+#define SOC_LOCAL_ERR_STAT_MASTER_REG(base, x)		XE_REG((x) > HARDWARE_ERROR_CORRECTABLE ? \
+								(base) + _SOC_LERRUNCSTS : \
+								(base) + _SOC_LERRCORSTS)

total: 0 errors, 0 warnings, 5 checks, 338 lines checked
68639fb6a drm/xe: Support SOC NONFATAL error handling for PVC.
f7ece8219 drm/xe: Handle MDFI error severity.
5f183c4e5 drm/xe: Clear SOC CORRECTABLE error registers.
1975f8e9a drm/xe: Clear all SoC errors post warm reset.

[Intel-xe] ✓ CI.KUnit: success for Supporting RAS on XE

[Patchwork]

== Series Details ==

Series: Supporting RAS on XE
URL   : https://patchwork.freedesktop.org/series/125348/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
stty: 'standard input': Inappropriate ioctl for device
[16:12:42] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:12:46] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[16:13:06] Starting KUnit Kernel (1/1)...
[16:13:06] ============================================================
[16:13:06] ========================== xe_bo  ==========================
[16:13:06] [SKIPPED] xe_ccs_migrate_kunit
[16:13:06] [SKIPPED] xe_bo_evict_kunit
[16:13:06] ===================== [SKIPPED] xe_bo ======================
[16:13:06] ======================= xe_dma_buf  ========================
[16:13:06] [SKIPPED] xe_dma_buf_kunit
[16:13:06] =================== [SKIPPED] xe_dma_buf ===================
[16:13:06] ======================= xe_migrate  ========================
[16:13:06] [SKIPPED] xe_migrate_sanity_kunit
[16:13:06] =================== [SKIPPED] xe_migrate ===================
[16:13:06] ========================= xe_pci  ==========================
[16:13:06] [PASSED] xe_gmdid_graphics_ip
[16:13:06] [PASSED] xe_gmdid_media_ip
[16:13:06] ===================== [PASSED] xe_pci ======================
[16:13:06] ========================= xe_rtp  ==========================
[16:13:06] ================== xe_rtp_process_tests  ===================
[16:13:06] [PASSED] coalesce-same-reg
[16:13:06] [PASSED] no-match-no-add
[16:13:06] [PASSED] no-match-no-add-multiple-rules
[16:13:06] [PASSED] two-regs-two-entries
[16:13:06] [PASSED] clr-one-set-other
[16:13:06] [PASSED] set-field
[16:13:06] [PASSED] conflict-duplicate
[16:13:06] [PASSED] conflict-not-disjoint
[16:13:06] [PASSED] conflict-reg-type
[16:13:06] ============== [PASSED] xe_rtp_process_tests ===============
[16:13:06] ===================== [PASSED] xe_rtp ======================
[16:13:06] ========================== xe_wa  ==========================
[16:13:06] ======================== xe_wa_gt  =========================
[16:13:06] [PASSED] TIGERLAKE (B0)
[16:13:06] [PASSED] DG1 (A0)
[16:13:06] [PASSED] DG1 (B0)
[16:13:06] [PASSED] ALDERLAKE_S (A0)
[16:13:06] [PASSED] ALDERLAKE_S (B0)
[16:13:06] [PASSED] ALDERLAKE_S (C0)
[16:13:06] [PASSED] ALDERLAKE_S (D0)
[16:13:06] [PASSED] ALDERLAKE_P (A0)
[16:13:06] [PASSED] ALDERLAKE_P (B0)
[16:13:06] [PASSED] ALDERLAKE_P (C0)
[16:13:06] [PASSED] ALDERLAKE_S_RPLS (D0)
[16:13:06] [PASSED] ALDERLAKE_P_RPLU (E0)
[16:13:06] [PASSED] DG2_G10 (A0)
[16:13:06] [PASSED] DG2_G10 (A1)
[16:13:06] [PASSED] DG2_G10 (B0)
[16:13:06] [PASSED] DG2_G10 (C0)
[16:13:06] [PASSED] DG2_G11 (A0)
[16:13:06] [PASSED] DG2_G11 (B0)
[16:13:06] [PASSED] DG2_G11 (B1)
[16:13:06] [PASSED] DG2_G12 (A0)
[16:13:06] [PASSED] DG2_G12 (A1)
[16:13:06] [PASSED] PVC (B0)
[16:13:06] [PASSED] PVC (B1)
[16:13:06] [PASSED] PVC (C0)
[16:13:06] ==================== [PASSED] xe_wa_gt =====================
[16:13:06] ====================== [PASSED] xe_wa ======================
[16:13:06] ============================================================
[16:13:06] Testing complete. Ran 39 tests: passed: 35, skipped: 4
[16:13:06] Elapsed time: 24.465s total, 4.205s configuring, 20.090s building, 0.145s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[16:13:06] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:13:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[16:13:27] Starting KUnit Kernel (1/1)...
[16:13:27] ============================================================
[16:13:27] ================== drm_test_pick_cmdline  ==================
[16:13:27] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[16:13:27] =============== drm_test_pick_cmdline_named  ===============
[16:13:27] [PASSED] NTSC
[16:13:27] [PASSED] NTSC-J
[16:13:27] [PASSED] PAL
[16:13:27] [PASSED] PAL-M
[16:13:27] =========== [PASSED] drm_test_pick_cmdline_named ===========
[16:13:27] ============== [PASSED] drm_test_pick_cmdline ==============
[16:13:27] ======================== drm_buddy  ========================
[16:13:27] [PASSED] drm_test_buddy_alloc_limit
[16:13:27] [PASSED] drm_test_buddy_alloc_range
[16:13:27] [PASSED] drm_test_buddy_alloc_optimistic
[16:13:27] [PASSED] drm_test_buddy_alloc_pessimistic
[16:13:27] [PASSED] drm_test_buddy_alloc_smoke
[16:13:27] [PASSED] drm_test_buddy_alloc_pathological
[16:13:27] ==================== [PASSED] drm_buddy ====================
[16:13:27] =================== drm_cmdline_parser  ====================
[16:13:27] [PASSED] drm_test_cmdline_force_d_only
[16:13:27] [PASSED] drm_test_cmdline_force_D_only_dvi
[16:13:27] [PASSED] drm_test_cmdline_force_D_only_hdmi
[16:13:27] [PASSED] drm_test_cmdline_force_D_only_not_digital
[16:13:27] [PASSED] drm_test_cmdline_force_e_only
[16:13:27] [PASSED] drm_test_cmdline_res
[16:13:27] [PASSED] drm_test_cmdline_res_vesa
[16:13:27] [PASSED] drm_test_cmdline_res_vesa_rblank
[16:13:27] [PASSED] drm_test_cmdline_res_rblank
[16:13:27] [PASSED] drm_test_cmdline_res_bpp
[16:13:27] [PASSED] drm_test_cmdline_res_refresh
[16:13:27] [PASSED] drm_test_cmdline_res_bpp_refresh
[16:13:27] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[16:13:27] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[16:13:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[16:13:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[16:13:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[16:13:27] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[16:13:27] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[16:13:27] [PASSED] drm_test_cmdline_res_margins_force_on
[16:13:27] [PASSED] drm_test_cmdline_res_vesa_margins
[16:13:27] [PASSED] drm_test_cmdline_name
[16:13:27] [PASSED] drm_test_cmdline_name_bpp
[16:13:27] [PASSED] drm_test_cmdline_name_option
[16:13:27] [PASSED] drm_test_cmdline_name_bpp_option
[16:13:27] [PASSED] drm_test_cmdline_rotate_0
[16:13:27] [PASSED] drm_test_cmdline_rotate_90
[16:13:27] [PASSED] drm_test_cmdline_rotate_180
[16:13:27] [PASSED] drm_test_cmdline_rotate_270
[16:13:27] [PASSED] drm_test_cmdline_hmirror
[16:13:27] [PASSED] drm_test_cmdline_vmirror
[16:13:27] [PASSED] drm_test_cmdline_margin_options
[16:13:27] [PASSED] drm_test_cmdline_multiple_options
[16:13:27] [PASSED] drm_test_cmdline_bpp_extra_and_option
[16:13:27] [PASSED] drm_test_cmdline_extra_and_option
[16:13:27] [PASSED] drm_test_cmdline_freestanding_options
[16:13:27] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[16:13:27] [PASSED] drm_test_cmdline_panel_orientation
[16:13:27] ================ drm_test_cmdline_invalid  =================
[16:13:27] [PASSED] margin_only
[16:13:27] [PASSED] interlace_only
[16:13:27] [PASSED] res_missing_x
[16:13:27] [PASSED] res_missing_y
[16:13:27] [PASSED] res_bad_y
[16:13:27] [PASSED] res_missing_y_bpp
[16:13:27] [PASSED] res_bad_bpp
[16:13:27] [PASSED] res_bad_refresh
[16:13:27] [PASSED] res_bpp_refresh_force_on_off
[16:13:27] [PASSED] res_invalid_mode
[16:13:27] [PASSED] res_bpp_wrong_place_mode
[16:13:27] [PASSED] name_bpp_refresh
[16:13:27] [PASSED] name_refresh
[16:13:27] [PASSED] name_refresh_wrong_mode
[16:13:27] [PASSED] name_refresh_invalid_mode
[16:13:27] [PASSED] rotate_multiple
[16:13:27] [PASSED] rotate_invalid_val
[16:13:27] [PASSED] rotate_truncated
[16:13:27] [PASSED] invalid_option
[16:13:27] [PASSED] invalid_tv_option
[16:13:27] [PASSED] truncated_tv_option
[16:13:27] ============ [PASSED] drm_test_cmdline_invalid =============
[16:13:27] =============== drm_test_cmdline_tv_options  ===============
[16:13:27] [PASSED] NTSC
[16:13:27] [PASSED] NTSC_443
[16:13:27] [PASSED] NTSC_J
[16:13:27] [PASSED] PAL
[16:13:27] [PASSED] PAL_M
[16:13:27] [PASSED] PAL_N
[16:13:27] [PASSED] SECAM
[16:13:27] =========== [PASSED] drm_test_cmdline_tv_options ===========
[16:13:27] =============== [PASSED] drm_cmdline_parser ================
[16:13:27] ================ drm_get_tv_mode_from_name  ================
[16:13:27] ========== drm_test_get_tv_mode_from_name_valid  ===========
[16:13:27] [PASSED] NTSC
[16:13:27] [PASSED] NTSC-443
[16:13:27] [PASSED] NTSC-J
[16:13:27] [PASSED] PAL
[16:13:27] [PASSED] PAL-M
[16:13:27] [PASSED] PAL-N
[16:13:27] [PASSED] SECAM
[16:13:27] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[16:13:27] [PASSED] drm_test_get_tv_mode_from_name_truncated
[16:13:27] ============ [PASSED] drm_get_tv_mode_from_name ============
[16:13:27] ==================== drm_damage_helper  ====================
[16:13:27] [PASSED] drm_test_damage_iter_no_damage
[16:13:27] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[16:13:27] [PASSED] drm_test_damage_iter_no_damage_src_moved
[16:13:27] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[16:13:27] [PASSED] drm_test_damage_iter_no_damage_not_visible
[16:13:27] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[16:13:27] [PASSED] drm_test_damage_iter_no_damage_no_fb
[16:13:27] [PASSED] drm_test_damage_iter_simple_damage
[16:13:27] [PASSED] drm_test_damage_iter_single_damage
[16:13:27] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[16:13:27] [PASSED] drm_test_damage_iter_single_damage_outside_src
[16:13:27] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[16:13:27] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[16:13:27] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[16:13:27] [PASSED] drm_test_damage_iter_single_damage_src_moved
[16:13:27] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[16:13:27] [PASSED] drm_test_damage_iter_damage
[16:13:27] [PASSED] drm_test_damage_iter_damage_one_intersect
[16:13:27] [PASSED] drm_test_damage_iter_damage_one_outside
[16:13:27] [PASSED] drm_test_damage_iter_damage_src_moved
[16:13:27] [PASSED] drm_test_damage_iter_damage_not_visible
[16:13:27] ================ [PASSED] drm_damage_helper ================
[16:13:27] ==================== drm_dp_mst_helper  ====================
[16:13:27] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[16:13:27] [PASSED] Clock 154000 BPP 30 DSC disabled
[16:13:27] [PASSED] Clock 234000 BPP 30 DSC disabled
[16:13:27] [PASSED] Clock 297000 BPP 24 DSC disabled
[16:13:27] [PASSED] Clock 332880 BPP 24 DSC enabled
[16:13:27] [PASSED] Clock 324540 BPP 24 DSC enabled
[16:13:27] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[16:13:27] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[16:13:27] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[16:13:27] [PASSED] DP_POWER_UP_PHY with port number
[16:13:27] [PASSED] DP_POWER_DOWN_PHY with port number
[16:13:27] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[16:13:27] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[16:13:27] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[16:13:27] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[16:13:27] [PASSED] DP_QUERY_PAYLOAD with port number
[16:13:27] [PASSED] DP_QUERY_PAYLOAD with VCPI
[16:13:27] [PASSED] DP_REMOTE_DPCD_READ with port number
[16:13:27] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[16:13:27] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[16:13:27] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[16:13:27] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[16:13:27] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[16:13:27] [PASSED] DP_REMOTE_I2C_READ with port number
[16:13:27] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[16:13:27] [PASSED] DP_REMOTE_I2C_READ with transactions array
[16:13:27] [PASSED] DP_REMOTE_I2C_WRITE with port number
[16:13:27] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[16:13:27] [PASSED] DP_REMOTE_I2C_WRITE with data array
[16:13:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[16:13:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[16:13:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[16:13:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[16:13:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[16:13:27] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[16:13:27] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[16:13:27] ================ [PASSED] drm_dp_mst_helper ================
[16:13:27] ================= drm_format_helper_test  ==================
[16:13:27] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[16:13:27] [PASSED] single_pixel_source_buffer
[16:13:27] [PASSED] single_pixel_clip_rectangle
[16:13:27] [PASSED] well_known_colors
[16:13:27] [PASSED] destination_pitch
[16:13:27] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[16:13:27] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[16:13:27] [PASSED] single_pixel_source_buffer
[16:13:27] [PASSED] single_pixel_clip_rectangle
[16:13:27] [PASSED] well_known_colors
[16:13:27] [PASSED] destination_pitch
[16:13:27] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[16:13:27] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[16:13:27] [PASSED] single_pixel_source_buffer
[16:13:27] [PASSED] single_pixel_clip_rectangle
[16:13:27] [PASSED] well_known_colors
[16:13:27] [PASSED] destination_pitch
[16:13:27] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[16:13:27] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[16:13:27] [PASSED] single_pixel_source_buffer
[16:13:27] [PASSED] single_pixel_clip_rectangle
[16:13:27] [PASSED] well_known_colors
[16:13:27] [PASSED] destination_pitch
[16:13:27] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[16:13:27] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[16:13:27] [PASSED] single_pixel_source_buffer
[16:13:27] [PASSED] single_pixel_clip_rectangle
[16:13:27] [PASSED] well_known_colors
[16:13:27] [PASSED] destination_pitch
[16:13:27] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[16:13:27] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[16:13:27] [PASSED] single_pixel_source_buffer
[16:13:27] [PASSED] single_pixel_clip_rectangle
[16:13:27] [PASSED] well_known_colors
[16:13:27] [PASSED] destination_pitch
[16:13:27] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[16:13:27] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[16:13:27] [PASSED] single_pixel_source_buffer
[16:13:27] [PASSED] single_pixel_clip_rectangle
[16:13:27] [PASSED] well_known_colors
[16:13:27] [PASSED] destination_pitch
[16:13:27] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[16:13:27] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[16:13:27] [PASSED] single_pixel_source_buffer
[16:13:27] [PASSED] single_pixel_clip_rectangle
[16:13:27] [PASSED] well_known_colors
[16:13:27] [PASSED] destination_pitch
[16:13:27] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[16:13:27] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[16:13:27] [PASSED] single_pixel_source_buffer
[16:13:27] [PASSED] single_pixel_clip_rectangle
[16:13:27] [PASSED] well_known_colors
[16:13:27] [PASSED] destination_pitch
[16:13:27] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[16:13:27] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[16:13:27] [PASSED] single_pixel_source_buffer
[16:13:27] [PASSED] single_pixel_clip_rectangle
[16:13:27] [PASSED] well_known_colors
[16:13:27] [PASSED] destination_pitch
[16:13:27] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[16:13:27] ============== drm_test_fb_xrgb8888_to_mono  ===============
[16:13:27] [PASSED] single_pixel_source_buffer
[16:13:27] [PASSED] single_pixel_clip_rectangle
[16:13:27] [PASSED] well_known_colors
[16:13:27] [PASSED] destination_pitch
[16:13:27] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[16:13:27] ==================== drm_test_fb_swab  =====================
[16:13:27] [PASSED] single_pixel_source_buffer
[16:13:27] [PASSED] single_pixel_clip_rectangle
[16:13:27] [PASSED] well_known_colors
[16:13:27] [PASSED] destination_pitch
[16:13:27] ================ [PASSED] drm_test_fb_swab =================
[16:13:27] ================= drm_test_fb_clip_offset  =================
[16:13:27] [PASSED] pass through
[16:13:27] [PASSED] horizontal offset
[16:13:27] [PASSED] vertical offset
[16:13:27] [PASSED] horizontal and vertical offset
[16:13:27] [PASSED] horizontal offset (custom pitch)
[16:13:27] [PASSED] vertical offset (custom pitch)
[16:13:27] [PASSED] horizontal and vertical offset (custom pitch)
[16:13:27] ============= [PASSED] drm_test_fb_clip_offset =============
[16:13:27] ============== drm_test_fb_build_fourcc_list  ==============
[16:13:27] [PASSED] no native formats
[16:13:27] [PASSED] XRGB8888 as native format
[16:13:27] [PASSED] remove duplicates
[16:13:27] [PASSED] convert alpha formats
[16:13:27] [PASSED] random formats
[16:13:27] ========== [PASSED] drm_test_fb_build_fourcc_list ==========
[16:13:27] =================== drm_test_fb_memcpy  ====================
[16:13:27] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[16:13:27] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[16:13:27] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[16:13:27] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[16:13:27] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[16:13:27] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[16:13:27] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[16:13:27] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[16:13:27] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[16:13:27] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[16:13:27] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[16:13:27] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[16:13:27] =============== [PASSED] drm_test_fb_memcpy ================
[16:13:27] ============= [PASSED] drm_format_helper_test ==============
[16:13:27] ======================= drm_format  ========================
[16:13:27] [PASSED] drm_test_format_block_width_invalid
[16:13:27] [PASSED] drm_test_format_block_width_one_plane
[16:13:27] [PASSED] drm_test_format_block_width_two_plane
[16:13:27] [PASSED] drm_test_format_block_width_three_plane
[16:13:27] [PASSED] drm_test_format_block_width_tiled
[16:13:27] [PASSED] drm_test_format_block_height_invalid
[16:13:27] [PASSED] drm_test_format_block_height_one_plane
[16:13:27] [PASSED] drm_test_format_block_height_two_plane
[16:13:27] [PASSED] drm_test_format_block_height_three_plane
[16:13:27] [PASSED] drm_test_format_block_height_tiled
[16:13:27] [PASSED] drm_test_format_min_pitch_invalid
[16:13:27] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[16:13:27] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[16:13:27] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[16:13:27] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[16:13:27] [PASSED] drm_test_format_min_pitch_two_plane
[16:13:27] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[16:13:27] [PASSED] drm_test_format_min_pitch_tiled
[16:13:27] =================== [PASSED] drm_format ====================
[16:13:27] ===================== drm_framebuffer  =====================
[16:13:27] =============== drm_test_framebuffer_create  ===============
[16:13:27] [PASSED] ABGR8888 normal sizes
[16:13:27] [PASSED] ABGR8888 max sizes
[16:13:27] [PASSED] ABGR8888 pitch greater than min required
[16:13:27] [PASSED] ABGR8888 pitch less than min required
[16:13:27] [PASSED] ABGR8888 Invalid width
[16:13:27] [PASSED] ABGR8888 Invalid buffer handle
[16:13:27] [PASSED] No pixel format
[16:13:27] [PASSED] ABGR8888 Width 0
[16:13:27] [PASSED] ABGR8888 Height 0
[16:13:27] [PASSED] ABGR8888 Out of bound height * pitch combination
[16:13:27] [PASSED] ABGR8888 Large buffer offset
[16:13:27] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[16:13:27] [PASSED] ABGR8888 Valid buffer modifier
[16:13:27] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[16:13:27] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[16:13:27] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[16:13:27] [PASSED] NV12 Normal sizes
[16:13:27] [PASSED] NV12 Max sizes
[16:13:27] [PASSED] NV12 Invalid pitch
[16:13:27] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[16:13:27] [PASSED] NV12 different  modifier per-plane
[16:13:27] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[16:13:27] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[16:13:27] [PASSED] NV12 Modifier for inexistent plane
[16:13:27] [PASSED] NV12 Handle for inexistent plane
[16:13:27] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[16:13:27] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[16:13:27] [PASSED] YVU420 Normal sizes
[16:13:27] [PASSED] YVU420 Max sizes
[16:13:27] [PASSED] YVU420 Invalid pitch
[16:13:27] [PASSED] YVU420 Different pitches
[16:13:27] [PASSED] YVU420 Different buffer offsets/pitches
[16:13:27] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[16:13:27] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[16:13:27] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[16:13:27] [PASSED] YVU420 Valid modifier
[16:13:27] [PASSED] YVU420 Different modifiers per plane
[16:13:27] [PASSED] YVU420 Modifier for inexistent plane
[16:13:27] [PASSED] X0L2 Normal sizes
[16:13:27] [PASSED] X0L2 Max sizes
[16:13:27] [PASSED] X0L2 Invalid pitch
[16:13:27] [PASSED] X0L2 Pitch greater than minimum required
[16:13:27] [PASSED] X0L2 Handle for inexistent plane
[16:13:27] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[16:13:27] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[16:13:27] [PASSED] X0L2 Valid modifier
[16:13:27] [PASSED] X0L2 Modifier for inexistent plane
[16:13:27] =========== [PASSED] drm_test_framebuffer_create ===========
[16:13:27] ================= [PASSED] drm_framebuffer =================
[16:13:27] ==================== drm-test-managed  =====================
[16:13:27] [PASSED] drm_test_managed_run_action
[16:13:27] ================ [PASSED] drm-test-managed =================
[16:13:27] ========================= drm_mm  ==========================
[16:13:27] [PASSED] drm_test_mm_init
[16:13:27] [PASSED] drm_test_mm_debug
[16:13:38] [PASSED] drm_test_mm_reserve
[16:13:48] [PASSED] drm_test_mm_insert
[16:13:49] [PASSED] drm_test_mm_replace
[16:13:49] [PASSED] drm_test_mm_insert_range
[16:13:49] [PASSED] drm_test_mm_frag
[16:13:49] [PASSED] drm_test_mm_align
[16:13:49] [PASSED] drm_test_mm_align32
[16:13:50] [PASSED] drm_test_mm_align64
[16:13:50] [PASSED] drm_test_mm_evict
[16:13:50] [PASSED] drm_test_mm_evict_range
[16:13:50] [PASSED] drm_test_mm_topdown
[16:13:50] [PASSED] drm_test_mm_bottomup
[16:13:50] [PASSED] drm_test_mm_lowest
[16:13:50] [PASSED] drm_test_mm_highest
[16:13:51] [PASSED] drm_test_mm_color
[16:13:51] [PASSED] drm_test_mm_color_evict
[16:13:51] [PASSED] drm_test_mm_color_evict_range
[16:13:51] ===================== [PASSED] drm_mm ======================
[16:13:51] =================== drm_modes_analog_tv  ===================
[16:13:51] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[16:13:51] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[16:13:51] [PASSED] drm_test_modes_analog_tv_pal_576i
[16:13:51] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[16:13:51] =============== [PASSED] drm_modes_analog_tv ===============
[16:13:51] ==================== drm_plane_helper  =====================
[16:13:51] =============== drm_test_check_plane_state  ================
[16:13:51] [PASSED] clipping_simple
[16:13:51] [PASSED] clipping_rotate_reflect
[16:13:51] [PASSED] positioning_simple
[16:13:51] [PASSED] upscaling
[16:13:51] [PASSED] downscaling
[16:13:51] [PASSED] rounding1
[16:13:51] [PASSED] rounding2
[16:13:51] [PASSED] rounding3
[16:13:51] [PASSED] rounding4
[16:13:51] =========== [PASSED] drm_test_check_plane_state ============
[16:13:51] =========== drm_test_check_invalid_plane_state  ============
[16:13:51] [PASSED] positioning_invalid
[16:13:51] [PASSED] upscaling_invalid
[16:13:51] [PASSED] downscaling_invalid
[16:13:51] ======= [PASSED] drm_test_check_invalid_plane_state ========
[16:13:51] ================ [PASSED] drm_plane_helper =================
[16:13:51] ============ drm_connector_helper_tv_get_modes  ============
[16:13:51] ====== drm_test_connector_helper_tv_get_modes_check  =======
[16:13:51] [PASSED] None
[16:13:51] [PASSED] PAL
[16:13:51] [PASSED] NTSC
[16:13:51] [PASSED] Both, NTSC Default
[16:13:51] [PASSED] Both, PAL Default
[16:13:51] [PASSED] Both, NTSC Default, with PAL on command-line
[16:13:51] [PASSED] Both, PAL Default, with NTSC on command-line
[16:13:51] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[16:13:51] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[16:13:51] ======================== drm_rect  =========================
[16:13:51] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[16:13:51] [PASSED] drm_test_rect_clip_scaled_not_clipped
[16:13:51] [PASSED] drm_test_rect_clip_scaled_clipped
[16:13:51] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[16:13:51] ================= drm_test_rect_intersect  =================
[16:13:51] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[16:13:51] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[16:13:51] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[16:13:51] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[16:13:51] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[16:13:51] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[16:13:51] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[16:13:51] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[16:13:51] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[16:13:51] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[16:13:51] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[16:13:51] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[16:13:51] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[16:13:51] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[16:13:51] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[16:13:51] ============= [PASSED] drm_test_rect_intersect =============
[16:13:51] ================ drm_test_rect_calc_hscale  ================
[16:13:51] [PASSED] normal use
[16:13:51] [PASSED] out of max range
[16:13:51] [PASSED] out of min range
[16:13:51] [PASSED] zero dst
[16:13:51] [PASSED] negative src
[16:13:51] [PASSED] negative dst
[16:13:51] ============ [PASSED] drm_test_rect_calc_hscale ============
[16:13:51] ================ drm_test_rect_calc_vscale  ================
[16:13:51] [PASSED] normal use
[16:13:51] [PASSED] out of max range
[16:13:51] [PASSED] out of min range
[16:13:51] [PASSED] zero dst
[16:13:51] [PASSED] negative src
[16:13:51] [PASSED] negative dst
[16:13:51] ============ [PASSED] drm_test_rect_calc_vscale ============
[16:13:51] ================== drm_test_rect_rotate  ===================
[16:13:51] [PASSED] reflect-x
[16:13:51] [PASSED] reflect-y
[16:13:51] [PASSED] rotate-0
[16:13:51] [PASSED] rotate-90
[16:13:51] [PASSED] rotate-180
[16:13:51] [PASSED] rotate-270
[16:13:51] ============== [PASSED] drm_test_rect_rotate ===============
[16:13:51] ================ drm_test_rect_rotate_inv  =================
[16:13:51] [PASSED] reflect-x
[16:13:51] [PASSED] reflect-y
[16:13:51] [PASSED] rotate-0
[16:13:51] [PASSED] rotate-90
[16:13:51] [PASSED] rotate-180
[16:13:51] [PASSED] rotate-270
[16:13:51] ============ [PASSED] drm_test_rect_rotate_inv =============
stty: 'standard input': Inappropriate ioctl for device
[16:13:51] ==================== [PASSED] drm_rect =====================
[16:13:51] ======================== drm_exec  =========================
[16:13:51] [PASSED] sanitycheck
[16:13:51] [PASSED] test_lock
[16:13:51] [PASSED] test_lock_unlock
[16:13:51] [PASSED] test_duplicates
[16:13:51] [PASSED] test_prepare
[16:13:51] [PASSED] test_prepare_array
[16:13:51] [PASSED] test_multiple_loops
[16:13:51] ==================== [PASSED] drm_exec =====================
[16:13:51] ============================================================
[16:13:51] Testing complete. Ran 368 tests: passed: 368
[16:13:51] Elapsed time: 45.027s total, 1.673s configuring, 19.271s building, 24.050s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel