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From: Matthew Auld <matthew.auld@intel.com>
To: Tejas Upadhyay <tejas.upadhyay@intel.com>,
	intel-xe@lists.freedesktop.org
Cc: thomas.hellstrom@linux.intel.com
Subject: Re: [PATCH V3 2/4] drm/xe/pat: define coh_mode 2way
Date: Fri, 20 Feb 2026 10:25:31 +0000	[thread overview]
Message-ID: <0863281d-9e3d-48ba-89e3-3503c98407cd@intel.com> (raw)
In-Reply-To: <20260220101638.1609775-8-tejas.upadhyay@intel.com>

On 20/02/2026 10:16, Tejas Upadhyay wrote:
> Defining 2way (two-way coherency) is critical for
> Xe3p_LPG (Nova Lake P) platforms to support L2 flush
> optimization safely.
> 
> This mode allows the driver to skip certain manual cache
> flushes (L2 flush optimization) without risking memory
> corruption because the hardware ensures the most recent
> data is visible to both entities.
> 
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>

Reviewed-by: Matthew Auld <matthew.auld@intel.com>


  reply	other threads:[~2026-02-20 10:25 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-20 10:16 [PATCH V3 0/4] drm/xe/xe3p_lpg: L2 flush optimization Tejas Upadhyay
2026-02-20 10:16 ` [PATCH V3 1/4] drm/xe/xe3p_lpg: flush shrinker bo cachelines manually Tejas Upadhyay
2026-02-20 10:16 ` [PATCH V3 2/4] drm/xe/pat: define coh_mode 2way Tejas Upadhyay
2026-02-20 10:25   ` Matthew Auld [this message]
2026-02-20 10:16 ` [PATCH V3 3/4] drm/xe/xe3p_lpg: Enable L2 flush optimization feature Tejas Upadhyay
2026-02-20 11:46   ` Matthew Auld
2026-02-20 11:50     ` Thomas Hellström
2026-02-20 12:06       ` Matthew Auld
2026-02-20 12:58         ` Thomas Hellström
2026-02-20 13:11           ` Upadhyay, Tejas
2026-02-20 15:10           ` Matthew Auld
2026-02-20 10:16 ` [PATCH V3 4/4] drm/xe/xe3p: Skip TD flush Tejas Upadhyay
2026-02-20 10:23 ` ✓ CI.KUnit: success for drm/xe/xe3p_lpg: L2 flush optimization (rev4) Patchwork
2026-02-20 11:02 ` ✓ Xe.CI.BAT: " Patchwork
2026-02-20 22:24 ` ✗ Xe.CI.FULL: failure " Patchwork

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