[PATCH V3 0/4] drm/xe/xe3p_lpg: L2 flush optimization

[PATCH V3 0/4] drm/xe/xe3p_lpg: L2 flush optimization

[Tejas Upadhyay]

The optimization involves two key changes:

Hardware-assisted Transient Display Flush:
The new hardware can automatically manage the flushing of "transient"
display data from the L2 cache. This eliminates the need for manual
(software-driven) transient display (TD) flushes by the driver,
simplifying the code and likely improving efficiency.

Transient Application (App) Cacheline Management:
The hardware gains the ability to flush transient application cache
lines more efficiently. The patch handles the necessary integration
to utilize this new functionality and manages manual flushing where
it is still required, ensuring data coherency and optimizing
performance.

Additional handling due to L2 flush optimization:
1. Need to flush cachelines manually via async tlb flush for internal/shrinker bo
2. Define coh_mode 2way for differentiating coherency modes
3. Add restrictions for userptr, svm/madvise and dmabuf to use either 2WAY or XA+1WAY
   pat settings

Tejas Upadhyay (4):
  drm/xe/xe3p_lpg: flush shrinker bo cachelines manually
  drm/xe/pat: define coh_mode 2way
  drm/xe/xe3p_lpg: Enable L2 flush optimization feature
  drm/xe/xe3p: Skip TD flush

 drivers/gpu/drm/xe/xe_bo.c         |  3 ++-
 drivers/gpu/drm/xe/xe_device.c     | 31 ++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_device.h     |  1 +
 drivers/gpu/drm/xe/xe_guc.c        |  3 +++
 drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
 drivers/gpu/drm/xe/xe_pat.c        | 14 +++++++-------
 drivers/gpu/drm/xe/xe_pat.h        |  5 +++--
 drivers/gpu/drm/xe/xe_vm.c         | 11 ++++++++++-
 drivers/gpu/drm/xe/xe_vm_madvise.c | 20 ++++++++++++++++++-
 9 files changed, 77 insertions(+), 12 deletions(-)

-- 
2.52.0

[PATCH V3 1/4] drm/xe/xe3p_lpg: flush shrinker bo cachelines manually

[Tejas Upadhyay]

XA, new pat_index introduced post xe3p_lpg, is memory shared between the
CPU and GPU is treated differently from other GPU memory when the Media
engine is power-gated.

XA is *always* flushed, like at the end-of-submssion (and maybe other
places), just that internally as an optimisation hw doesn't need to make
that a full flush (which will also include XA) when Media is
off/powergated, since it doesn't need to worry about GT caches vs Media
coherency, and only CPU vs GPU coherency, so can make that flush a
targeted XA flush, since stuff tagged with XA now means it's shared with
the CPU. The main implication is that we now need to somehow flush non-XA
before freeing system memory pages, otherwise dirty cachelines could be
flushed after the free (like if Media suddenly turns on and does a full
flush)

V3(Thomas/MattA/MattR): Restrict userptr with non-xa, then no need to
			flush manually
V2(MattA): Expand commit description

Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
 drivers/gpu/drm/xe/xe_bo.c     |  3 ++-
 drivers/gpu/drm/xe/xe_device.c | 23 +++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_device.h |  1 +
 3 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index d6c2cb959cdd..d2ee9701eae6 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -689,7 +689,8 @@ static int xe_bo_trigger_rebind(struct xe_device *xe, struct xe_bo *bo,
 
 		if (!xe_vm_in_fault_mode(vm)) {
 			drm_gpuvm_bo_evict(vm_bo, true);
-			continue;
+			if (!xe_device_is_l2_flush_optimized(xe))
+				continue;
 		}
 
 		if (!idle) {
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 4b68a2d55651..94c9f17da4b4 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -1097,6 +1097,29 @@ static void tdf_request_sync(struct xe_device *xe)
 	}
 }
 
+/**
+ * xe_device_is_l2_flush_optimized - if L2 flush is optimized by HW
+ * @xe: The device to check.
+ *
+ * Return: true if the HW device optimizing L2 flush, false otherwise.
+ */
+bool xe_device_is_l2_flush_optimized(struct xe_device *xe)
+{
+	/* XA is *always* flushed, like at the end-of-submssion (and maybe other
+	 * places), just that internally as an optimisation hw doesn't need to make
+	 * that a full flush (which will also include XA) when Media is
+	 * off/powergated, since it doesn't need to worry about GT caches vs Media
+	 * coherency, and only CPU vs GPU coherency, so can make that flush a
+	 * targeted XA flush, since stuff tagged with XA now means it's shared with
+	 * the CPU. The main implication is that we now need to somehow flush non-XA before
+	 * freeing system memory pages, otherwise dirty cachelines could be flushed after the free
+	 * (like if Media suddenly turns on and does a full flush)
+	 */
+	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe))
+		return true;
+	return false;
+}
+
 void xe_device_l2_flush(struct xe_device *xe)
 {
 	struct xe_gt *gt;
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index 39464650533b..dfbf96e12d2e 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -184,6 +184,7 @@ void xe_device_snapshot_print(struct xe_device *xe, struct drm_printer *p);
 u64 xe_device_canonicalize_addr(struct xe_device *xe, u64 address);
 u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64 address);
 
+bool xe_device_is_l2_flush_optimized(struct xe_device *xe);
 void xe_device_td_flush(struct xe_device *xe);
 void xe_device_l2_flush(struct xe_device *xe);
 
-- 
2.52.0

[PATCH V3 2/4] drm/xe/pat: define coh_mode 2way

[Tejas Upadhyay]

Defining 2way (two-way coherency) is critical for
Xe3p_LPG (Nova Lake P) platforms to support L2 flush
optimization safely.

This mode allows the driver to skip certain manual cache
flushes (L2 flush optimization) without risking memory
corruption because the hardware ensures the most recent
data is visible to both entities.

Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
 drivers/gpu/drm/xe/xe_pat.c        | 14 +++++++-------
 drivers/gpu/drm/xe/xe_pat.h        |  5 +++--
 drivers/gpu/drm/xe/xe_vm.c         |  2 +-
 drivers/gpu/drm/xe/xe_vm_madvise.c |  2 +-
 4 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index f840d9a58740..bf581afd4d60 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -92,7 +92,7 @@ struct xe_pat_ops {
 };
 
 static const struct xe_pat_table_entry xelp_pat_table[] = {
-	[0] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },
+	[0] = { XELP_PAT_WB, XE_COH_1WAY },
 	[1] = { XELP_PAT_WC, XE_COH_NONE },
 	[2] = { XELP_PAT_WT, XE_COH_NONE },
 	[3] = { XELP_PAT_UC, XE_COH_NONE },
@@ -102,19 +102,19 @@ static const struct xe_pat_table_entry xehpc_pat_table[] = {
 	[0] = { XELP_PAT_UC, XE_COH_NONE },
 	[1] = { XELP_PAT_WC, XE_COH_NONE },
 	[2] = { XELP_PAT_WT, XE_COH_NONE },
-	[3] = { XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },
+	[3] = { XELP_PAT_WB, XE_COH_1WAY },
 	[4] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WT, XE_COH_NONE },
-	[5] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },
+	[5] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WB, XE_COH_1WAY },
 	[6] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WT, XE_COH_NONE },
-	[7] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WB, XE_COH_AT_LEAST_1WAY },
+	[7] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WB, XE_COH_1WAY },
 };
 
 static const struct xe_pat_table_entry xelpg_pat_table[] = {
 	[0] = { XELPG_PAT_0_WB, XE_COH_NONE },
 	[1] = { XELPG_PAT_1_WT, XE_COH_NONE },
 	[2] = { XELPG_PAT_3_UC, XE_COH_NONE },
-	[3] = { XELPG_PAT_0_WB | XELPG_2_COH_1W, XE_COH_AT_LEAST_1WAY },
-	[4] = { XELPG_PAT_0_WB | XELPG_3_COH_2W, XE_COH_AT_LEAST_1WAY },
+	[3] = { XELPG_PAT_0_WB | XELPG_2_COH_1W, XE_COH_1WAY },
+	[4] = { XELPG_PAT_0_WB | XELPG_3_COH_2W, XE_COH_2WAY },
 };
 
 /*
@@ -147,7 +147,7 @@ static const struct xe_pat_table_entry xelpg_pat_table[] = {
 			REG_FIELD_PREP(XE2_L3_POLICY, l3_policy) | \
 			REG_FIELD_PREP(XE2_L4_POLICY, l4_policy) | \
 			REG_FIELD_PREP(XE2_COH_MODE, __coh_mode), \
-		.coh_mode = __coh_mode ? XE_COH_AT_LEAST_1WAY : XE_COH_NONE, \
+		.coh_mode = __coh_mode ? __coh_mode : XE_COH_NONE, \
 		.valid = 1 \
 	}
 
diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h
index c7e2a53d8cee..a1e287c08f57 100644
--- a/drivers/gpu/drm/xe/xe_pat.h
+++ b/drivers/gpu/drm/xe/xe_pat.h
@@ -28,8 +28,9 @@ struct xe_pat_table_entry {
 	/**
 	 * @coh_mode: The GPU coherency mode that @value maps to.
 	 */
-#define XE_COH_NONE          1
-#define XE_COH_AT_LEAST_1WAY 2
+#define XE_COH_NONE		1
+#define XE_COH_1WAY		2
+#define XE_COH_2WAY		3
 	u16 coh_mode;
 
 	/**
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index a46f11a71c37..c06fd250e037 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -3449,7 +3449,7 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
 			goto free_bind_ops;
 		}
 
-		if (XE_WARN_ON(coh_mode > XE_COH_AT_LEAST_1WAY)) {
+		if (XE_WARN_ON(coh_mode > XE_COH_2WAY)) {
 			err = -EINVAL;
 			goto free_bind_ops;
 		}
diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c
index 52147f5eaaa0..1a1ad8c07d49 100644
--- a/drivers/gpu/drm/xe/xe_vm_madvise.c
+++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
@@ -301,7 +301,7 @@ static bool madvise_args_are_sane(struct xe_device *xe, const struct drm_xe_madv
 		if (XE_IOCTL_DBG(xe, !coh_mode))
 			return false;
 
-		if (XE_WARN_ON(coh_mode > XE_COH_AT_LEAST_1WAY))
+		if (XE_WARN_ON(coh_mode > XE_COH_2WAY))
 			return false;
 
 		if (XE_IOCTL_DBG(xe, args->pat_index.pad))
-- 
2.52.0

Re: [PATCH V3 2/4] drm/xe/pat: define coh_mode 2way

[Matthew Auld]

On 20/02/2026 10:16, Tejas Upadhyay wrote:
> Defining 2way (two-way coherency) is critical for
> Xe3p_LPG (Nova Lake P) platforms to support L2 flush
> optimization safely.
> 
> This mode allows the driver to skip certain manual cache
> flushes (L2 flush optimization) without risking memory
> corruption because the hardware ensures the most recent
> data is visible to both entities.
> 
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>

Reviewed-by: Matthew Auld <matthew.auld@intel.com>

[PATCH V3 3/4] drm/xe/xe3p_lpg: Enable L2 flush optimization feature

[Tejas Upadhyay]

When set, the L2 flush optimization feature will control
whether L2 is in Persistent or Transient mode through
monitoring of media activity.

To enable L2 flush optimization include new feature flag
GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when
media type is detected.

Also, restrict userptr, svm and dmabuf mappings to be
either 2WAY or XA+1WAY

V2(MattA): validate dma-buf bos and madvise pat-index

Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
 drivers/gpu/drm/xe/xe_guc.c        |  3 +++
 drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
 drivers/gpu/drm/xe/xe_vm.c         |  9 +++++++++
 drivers/gpu/drm/xe/xe_vm_madvise.c | 18 ++++++++++++++++++
 4 files changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index cbbb4d665b8f..97c33c3dd520 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
 	if (xe_guc_using_main_gamctrl_queues(guc))
 		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
 
+	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) && xe_gt_is_media_type(guc_to_gt(guc)))
+		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
+
 	return flags;
 }
 
diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
index a33ea288b907..39ff7b3e960b 100644
--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
@@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
 #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
 #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
 #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
+#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
 
 #define GUC_CTL_DEBUG			3
 #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index c06fd250e037..e2e4c9648d05 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -3474,6 +3474,11 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
 				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
 		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
 				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
+		    XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&
+				 (op == DRM_XE_VM_BIND_OP_MAP_USERPTR ||
+				  /* svm */
+				  op == (DRM_XE_VM_BIND_OP_MAP && is_cpu_addr_mirror)) &&
+				 (pat_index != 19 || coh_mode != XE_COH_2WAY)) ||
 		    XE_IOCTL_DBG(xe, comp_en &&
 				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
 		    XE_IOCTL_DBG(xe, op == DRM_XE_VM_BIND_OP_MAP_USERPTR &&
@@ -3608,6 +3613,10 @@ static int xe_vm_bind_ioctl_validate_bo(struct xe_device *xe, struct xe_bo *bo,
 	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && comp_en))
 		return -EINVAL;
 
+	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && xe_device_is_l2_flush_optimized(xe) &&
+			 (pat_index != 19 || coh_mode != XE_COH_2WAY)))
+		return -EINVAL;
+
 	/* If a BO is protected it can only be mapped if the key is still valid */
 	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) && xe_bo_is_protected(bo) &&
 	    op != DRM_XE_VM_BIND_OP_UNMAP && op != DRM_XE_VM_BIND_OP_UNMAP_ALL)
diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c
index 1a1ad8c07d49..2a35dbeba2d8 100644
--- a/drivers/gpu/drm/xe/xe_vm_madvise.c
+++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
@@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
 	struct xe_vmas_in_madvise_range madvise_range = {.addr = args->start,
 							 .range =  args->range, };
 	struct xe_madvise_details details;
+	u16 pat_index, coh_mode;
 	struct xe_vm *vm;
 	struct drm_exec exec;
 	int err, attr_type;
@@ -447,6 +448,15 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
 	if (err || !madvise_range.num_vmas)
 		goto madv_fini;
 
+	pat_index = array_index_nospec(args->pat_index.val, xe->pat.n_entries);
+	coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
+	if (XE_IOCTL_DBG(xe, madvise_range.has_svm_userptr_vmas &&
+			 xe_device_is_l2_flush_optimized(xe) &&
+			 (pat_index != 19 || coh_mode != XE_COH_2WAY))) {
+		err = -EINVAL;
+		goto madv_fini;
+	}
+
 	if (madvise_range.has_bo_vmas) {
 		if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
 			if (!check_bo_args_are_sane(vm, madvise_range.vmas,
@@ -464,6 +474,14 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
 
 				if (!bo)
 					continue;
+
+				if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
+						 xe_device_is_l2_flush_optimized(xe) &&
+						 (pat_index != 19 || coh_mode != XE_COH_2WAY))) {
+					err = -EINVAL;
+					goto err_fini;
+				}
+
 				err = drm_exec_lock_obj(&exec, &bo->ttm.base);
 				drm_exec_retry_on_contention(&exec);
 				if (err)
-- 
2.52.0

Re: [PATCH V3 3/4] drm/xe/xe3p_lpg: Enable L2 flush optimization feature

[Matthew Auld]

On 20/02/2026 10:16, Tejas Upadhyay wrote:
> When set, the L2 flush optimization feature will control
> whether L2 is in Persistent or Transient mode through
> monitoring of media activity.
> 
> To enable L2 flush optimization include new feature flag
> GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when
> media type is detected.
> 
> Also, restrict userptr, svm and dmabuf mappings to be
> either 2WAY or XA+1WAY
> 
> V2(MattA): validate dma-buf bos and madvise pat-index
> 
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_guc.c        |  3 +++
>   drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
>   drivers/gpu/drm/xe/xe_vm.c         |  9 +++++++++
>   drivers/gpu/drm/xe/xe_vm_madvise.c | 18 ++++++++++++++++++
>   4 files changed, 31 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index cbbb4d665b8f..97c33c3dd520 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc *guc)
>   	if (xe_guc_using_main_gamctrl_queues(guc))
>   		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
>   
> +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) && xe_gt_is_media_type(guc_to_gt(guc)))
> +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
> +
>   	return flags;
>   }
>   
> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
> index a33ea288b907..39ff7b3e960b 100644
> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
>   #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
>   #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
>   #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
> +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
>   
>   #define GUC_CTL_DEBUG			3
>   #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
> index c06fd250e037..e2e4c9648d05 100644
> --- a/drivers/gpu/drm/xe/xe_vm.c
> +++ b/drivers/gpu/drm/xe/xe_vm.c
> @@ -3474,6 +3474,11 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
>   				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>   		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
>   				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> +		    XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&
> +				 (op == DRM_XE_VM_BIND_OP_MAP_USERPTR ||
> +				  /* svm */
> +				  op == (DRM_XE_VM_BIND_OP_MAP && is_cpu_addr_mirror)) &&

op == (DRM_XE_VM_BIND_OP_MAP && is_cpu_addr_mirror)

I think you meant (op == DRM_XE_VM_BIND_OP_MAP) && is_cpu ?

But maybe just drop the op check. Having the check being consistent for 
bind/unbind matches existing uapi behaviour?

> +				 (pat_index != 19 || coh_mode != XE_COH_2WAY)) ||
>   		    XE_IOCTL_DBG(xe, comp_en &&
>   				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>   		    XE_IOCTL_DBG(xe, op == DRM_XE_VM_BIND_OP_MAP_USERPTR &&
> @@ -3608,6 +3613,10 @@ static int xe_vm_bind_ioctl_validate_bo(struct xe_device *xe, struct xe_bo *bo,
>   	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && comp_en))
>   		return -EINVAL;
>   
> +	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach && xe_device_is_l2_flush_optimized(xe) &&
> +			 (pat_index != 19 || coh_mode != XE_COH_2WAY)))
> +		return -EINVAL;
> +
>   	/* If a BO is protected it can only be mapped if the key is still valid */
>   	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) && xe_bo_is_protected(bo) &&
>   	    op != DRM_XE_VM_BIND_OP_UNMAP && op != DRM_XE_VM_BIND_OP_UNMAP_ALL)
> diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c
> index 1a1ad8c07d49..2a35dbeba2d8 100644
> --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
> +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
> @@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
>   	struct xe_vmas_in_madvise_range madvise_range = {.addr = args->start,
>   							 .range =  args->range, };
>   	struct xe_madvise_details details;
> +	u16 pat_index, coh_mode;
>   	struct xe_vm *vm;
>   	struct drm_exec exec;
>   	int err, attr_type;
> @@ -447,6 +448,15 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
>   	if (err || !madvise_range.num_vmas)
>   		goto madv_fini;
>   
> +	pat_index = array_index_nospec(args->pat_index.val, xe->pat.n_entries);

This needs to be conditional on DRM_XE_MEM_RANGE_ATTR_PAT. This is a 
union underneath so pat_index.val is not actually a pat_index for the 
other madv types, but just some other random data.

> +	coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
> +	if (XE_IOCTL_DBG(xe, madvise_range.has_svm_userptr_vmas &&
> +			 xe_device_is_l2_flush_optimized(xe) &&
> +			 (pat_index != 19 || coh_mode != XE_COH_2WAY))) {
> +		err = -EINVAL;
> +		goto madv_fini;
> +	}
> +
>   	if (madvise_range.has_bo_vmas) {
>   		if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
>   			if (!check_bo_args_are_sane(vm, madvise_range.vmas,
> @@ -464,6 +474,14 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
>   
>   				if (!bo)
>   					continue;
> +
> +				if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> +						 xe_device_is_l2_flush_optimized(xe) &&
> +						 (pat_index != 19 || coh_mode != XE_COH_2WAY))) {
> +					err = -EINVAL;
> +					goto err_fini;
> +				}
> +
>   				err = drm_exec_lock_obj(&exec, &bo->ttm.base);
>   				drm_exec_retry_on_contention(&exec);
>   				if (err)

Re: [PATCH V3 3/4] drm/xe/xe3p_lpg: Enable L2 flush optimization feature

[Thomas Hellström]

On Fri, 2026-02-20 at 11:46 +0000, Matthew Auld wrote:
> On 20/02/2026 10:16, Tejas Upadhyay wrote:
> > When set, the L2 flush optimization feature will control
> > whether L2 is in Persistent or Transient mode through
> > monitoring of media activity.
> > 
> > To enable L2 flush optimization include new feature flag
> > GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when
> > media type is detected.
> > 
> > Also, restrict userptr, svm and dmabuf mappings to be
> > either 2WAY or XA+1WAY
> > 
> > V2(MattA): validate dma-buf bos and madvise pat-index

Question: Assuming that we on *faulting* VMs always perform a TLB flush
on unbind. Can we eliminate the PAT restrictions on those? That would
actually then include all SVM maps.

/Thomas
 

> > 
> > Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> > ---
> >   drivers/gpu/drm/xe/xe_guc.c        |  3 +++
> >   drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
> >   drivers/gpu/drm/xe/xe_vm.c         |  9 +++++++++
> >   drivers/gpu/drm/xe/xe_vm_madvise.c | 18 ++++++++++++++++++
> >   4 files changed, 31 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_guc.c
> > b/drivers/gpu/drm/xe/xe_guc.c
> > index cbbb4d665b8f..97c33c3dd520 100644
> > --- a/drivers/gpu/drm/xe/xe_guc.c
> > +++ b/drivers/gpu/drm/xe/xe_guc.c
> > @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc
> > *guc)
> >   	if (xe_guc_using_main_gamctrl_queues(guc))
> >   		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
> >   
> > +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) &&
> > xe_gt_is_media_type(guc_to_gt(guc)))
> > +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
> > +
> >   	return flags;
> >   }
> >   
> > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > index a33ea288b907..39ff7b3e960b 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
> >   #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
> >   #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
> >   #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
> > +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
> >   
> >   #define GUC_CTL_DEBUG			3
> >   #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
> > diff --git a/drivers/gpu/drm/xe/xe_vm.c
> > b/drivers/gpu/drm/xe/xe_vm.c
> > index c06fd250e037..e2e4c9648d05 100644
> > --- a/drivers/gpu/drm/xe/xe_vm.c
> > +++ b/drivers/gpu/drm/xe/xe_vm.c
> > @@ -3474,6 +3474,11 @@ static int vm_bind_ioctl_check_args(struct
> > xe_device *xe, struct xe_vm *vm,
> >   				 op ==
> > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> >   		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
> >   				 op ==
> > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > +		    XE_IOCTL_DBG(xe,
> > xe_device_is_l2_flush_optimized(xe) &&
> > +				 (op ==
> > DRM_XE_VM_BIND_OP_MAP_USERPTR ||
> > +				  /* svm */
> > +				  op == (DRM_XE_VM_BIND_OP_MAP &&
> > is_cpu_addr_mirror)) &&
> 
> op == (DRM_XE_VM_BIND_OP_MAP && is_cpu_addr_mirror)
> 
> I think you meant (op == DRM_XE_VM_BIND_OP_MAP) && is_cpu ?
> 
> But maybe just drop the op check. Having the check being consistent
> for 
> bind/unbind matches existing uapi behaviour?
> 
> > +				 (pat_index != 19 || coh_mode !=
> > XE_COH_2WAY)) ||
> >   		    XE_IOCTL_DBG(xe, comp_en &&
> >   				 op ==
> > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> >   		    XE_IOCTL_DBG(xe, op ==
> > DRM_XE_VM_BIND_OP_MAP_USERPTR &&
> > @@ -3608,6 +3613,10 @@ static int
> > xe_vm_bind_ioctl_validate_bo(struct xe_device *xe, struct xe_bo
> > *bo,
> >   	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> > comp_en))
> >   		return -EINVAL;
> >   
> > +	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> > xe_device_is_l2_flush_optimized(xe) &&
> > +			 (pat_index != 19 || coh_mode !=
> > XE_COH_2WAY)))
> > +		return -EINVAL;
> > +
> >   	/* If a BO is protected it can only be mapped if the key
> > is still valid */
> >   	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) &&
> > xe_bo_is_protected(bo) &&
> >   	    op != DRM_XE_VM_BIND_OP_UNMAP && op !=
> > DRM_XE_VM_BIND_OP_UNMAP_ALL)
> > diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c
> > b/drivers/gpu/drm/xe/xe_vm_madvise.c
> > index 1a1ad8c07d49..2a35dbeba2d8 100644
> > --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
> > +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
> > @@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
> > void *data, struct drm_file *fil
> >   	struct xe_vmas_in_madvise_range madvise_range = {.addr =
> > args->start,
> >   							 .range = 
> > args->range, };
> >   	struct xe_madvise_details details;
> > +	u16 pat_index, coh_mode;
> >   	struct xe_vm *vm;
> >   	struct drm_exec exec;
> >   	int err, attr_type;
> > @@ -447,6 +448,15 @@ int xe_vm_madvise_ioctl(struct drm_device
> > *dev, void *data, struct drm_file *fil
> >   	if (err || !madvise_range.num_vmas)
> >   		goto madv_fini;
> >   
> > +	pat_index = array_index_nospec(args->pat_index.val, xe-
> > >pat.n_entries);
> 
> This needs to be conditional on DRM_XE_MEM_RANGE_ATTR_PAT. This is a 
> union underneath so pat_index.val is not actually a pat_index for the
> other madv types, but just some other random data.
> 
> > +	coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
> > +	if (XE_IOCTL_DBG(xe, madvise_range.has_svm_userptr_vmas &&
> > +			 xe_device_is_l2_flush_optimized(xe) &&
> > +			 (pat_index != 19 || coh_mode !=
> > XE_COH_2WAY))) {
> > +		err = -EINVAL;
> > +		goto madv_fini;
> > +	}
> > +
> >   	if (madvise_range.has_bo_vmas) {
> >   		if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
> >   			if (!check_bo_args_are_sane(vm,
> > madvise_range.vmas,
> > @@ -464,6 +474,14 @@ int xe_vm_madvise_ioctl(struct drm_device
> > *dev, void *data, struct drm_file *fil
> >   
> >   				if (!bo)
> >   					continue;
> > +
> > +				if (XE_IOCTL_DBG(xe, bo-
> > >ttm.base.import_attach &&
> > +						
> > xe_device_is_l2_flush_optimized(xe) &&
> > +						 (pat_index != 19
> > || coh_mode != XE_COH_2WAY))) {
> > +					err = -EINVAL;
> > +					goto err_fini;
> > +				}
> > +
> >   				err = drm_exec_lock_obj(&exec,
> > &bo->ttm.base);
> >   				drm_exec_retry_on_contention(&exec
> > );
> >   				if (err)

Re: [PATCH V3 3/4] drm/xe/xe3p_lpg: Enable L2 flush optimization feature

[Matthew Auld]

On 20/02/2026 11:50, Thomas Hellström wrote:
> On Fri, 2026-02-20 at 11:46 +0000, Matthew Auld wrote:
>> On 20/02/2026 10:16, Tejas Upadhyay wrote:
>>> When set, the L2 flush optimization feature will control
>>> whether L2 is in Persistent or Transient mode through
>>> monitoring of media activity.
>>>
>>> To enable L2 flush optimization include new feature flag
>>> GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when
>>> media type is detected.
>>>
>>> Also, restrict userptr, svm and dmabuf mappings to be
>>> either 2WAY or XA+1WAY
>>>
>>> V2(MattA): validate dma-buf bos and madvise pat-index
> 
> Question: Assuming that we on *faulting* VMs always perform a TLB flush
> on unbind. Can we eliminate the PAT restrictions on those? That would
> actually then include all SVM maps.

With unbind do you mean notifier invalidation flow on svm side? Or 
actual vma unbind?

> 
> /Thomas
>   
> 
>>>
>>> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
>>> ---
>>>    drivers/gpu/drm/xe/xe_guc.c        |  3 +++
>>>    drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
>>>    drivers/gpu/drm/xe/xe_vm.c         |  9 +++++++++
>>>    drivers/gpu/drm/xe/xe_vm_madvise.c | 18 ++++++++++++++++++
>>>    4 files changed, 31 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_guc.c
>>> b/drivers/gpu/drm/xe/xe_guc.c
>>> index cbbb4d665b8f..97c33c3dd520 100644
>>> --- a/drivers/gpu/drm/xe/xe_guc.c
>>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>>> @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc
>>> *guc)
>>>    	if (xe_guc_using_main_gamctrl_queues(guc))
>>>    		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
>>>    
>>> +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) &&
>>> xe_gt_is_media_type(guc_to_gt(guc)))
>>> +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
>>> +
>>>    	return flags;
>>>    }
>>>    
>>> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h
>>> b/drivers/gpu/drm/xe/xe_guc_fwif.h
>>> index a33ea288b907..39ff7b3e960b 100644
>>> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
>>> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
>>> @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
>>>    #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
>>>    #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
>>>    #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
>>> +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
>>>    
>>>    #define GUC_CTL_DEBUG			3
>>>    #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
>>> diff --git a/drivers/gpu/drm/xe/xe_vm.c
>>> b/drivers/gpu/drm/xe/xe_vm.c
>>> index c06fd250e037..e2e4c9648d05 100644
>>> --- a/drivers/gpu/drm/xe/xe_vm.c
>>> +++ b/drivers/gpu/drm/xe/xe_vm.c
>>> @@ -3474,6 +3474,11 @@ static int vm_bind_ioctl_check_args(struct
>>> xe_device *xe, struct xe_vm *vm,
>>>    				 op ==
>>> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>>>    		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
>>>    				 op ==
>>> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>>> +		    XE_IOCTL_DBG(xe,
>>> xe_device_is_l2_flush_optimized(xe) &&
>>> +				 (op ==
>>> DRM_XE_VM_BIND_OP_MAP_USERPTR ||
>>> +				  /* svm */
>>> +				  op == (DRM_XE_VM_BIND_OP_MAP &&
>>> is_cpu_addr_mirror)) &&
>>
>> op == (DRM_XE_VM_BIND_OP_MAP && is_cpu_addr_mirror)
>>
>> I think you meant (op == DRM_XE_VM_BIND_OP_MAP) && is_cpu ?
>>
>> But maybe just drop the op check. Having the check being consistent
>> for
>> bind/unbind matches existing uapi behaviour?
>>
>>> +				 (pat_index != 19 || coh_mode !=
>>> XE_COH_2WAY)) ||
>>>    		    XE_IOCTL_DBG(xe, comp_en &&
>>>    				 op ==
>>> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>>>    		    XE_IOCTL_DBG(xe, op ==
>>> DRM_XE_VM_BIND_OP_MAP_USERPTR &&
>>> @@ -3608,6 +3613,10 @@ static int
>>> xe_vm_bind_ioctl_validate_bo(struct xe_device *xe, struct xe_bo
>>> *bo,
>>>    	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
>>> comp_en))
>>>    		return -EINVAL;
>>>    
>>> +	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
>>> xe_device_is_l2_flush_optimized(xe) &&
>>> +			 (pat_index != 19 || coh_mode !=
>>> XE_COH_2WAY)))
>>> +		return -EINVAL;
>>> +
>>>    	/* If a BO is protected it can only be mapped if the key
>>> is still valid */
>>>    	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) &&
>>> xe_bo_is_protected(bo) &&
>>>    	    op != DRM_XE_VM_BIND_OP_UNMAP && op !=
>>> DRM_XE_VM_BIND_OP_UNMAP_ALL)
>>> diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c
>>> b/drivers/gpu/drm/xe/xe_vm_madvise.c
>>> index 1a1ad8c07d49..2a35dbeba2d8 100644
>>> --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
>>> +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
>>> @@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device *dev,
>>> void *data, struct drm_file *fil
>>>    	struct xe_vmas_in_madvise_range madvise_range = {.addr =
>>> args->start,
>>>    							 .range =
>>> args->range, };
>>>    	struct xe_madvise_details details;
>>> +	u16 pat_index, coh_mode;
>>>    	struct xe_vm *vm;
>>>    	struct drm_exec exec;
>>>    	int err, attr_type;
>>> @@ -447,6 +448,15 @@ int xe_vm_madvise_ioctl(struct drm_device
>>> *dev, void *data, struct drm_file *fil
>>>    	if (err || !madvise_range.num_vmas)
>>>    		goto madv_fini;
>>>    
>>> +	pat_index = array_index_nospec(args->pat_index.val, xe-
>>>> pat.n_entries);
>>
>> This needs to be conditional on DRM_XE_MEM_RANGE_ATTR_PAT. This is a
>> union underneath so pat_index.val is not actually a pat_index for the
>> other madv types, but just some other random data.
>>
>>> +	coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
>>> +	if (XE_IOCTL_DBG(xe, madvise_range.has_svm_userptr_vmas &&
>>> +			 xe_device_is_l2_flush_optimized(xe) &&
>>> +			 (pat_index != 19 || coh_mode !=
>>> XE_COH_2WAY))) {
>>> +		err = -EINVAL;
>>> +		goto madv_fini;
>>> +	}
>>> +
>>>    	if (madvise_range.has_bo_vmas) {
>>>    		if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
>>>    			if (!check_bo_args_are_sane(vm,
>>> madvise_range.vmas,
>>> @@ -464,6 +474,14 @@ int xe_vm_madvise_ioctl(struct drm_device
>>> *dev, void *data, struct drm_file *fil
>>>    
>>>    				if (!bo)
>>>    					continue;
>>> +
>>> +				if (XE_IOCTL_DBG(xe, bo-
>>>> ttm.base.import_attach &&
>>> +						
>>> xe_device_is_l2_flush_optimized(xe) &&
>>> +						 (pat_index != 19
>>> || coh_mode != XE_COH_2WAY))) {
>>> +					err = -EINVAL;
>>> +					goto err_fini;
>>> +				}
>>> +
>>>    				err = drm_exec_lock_obj(&exec,
>>> &bo->ttm.base);
>>>    				drm_exec_retry_on_contention(&exec
>>> );
>>>    				if (err)

Re: [PATCH V3 3/4] drm/xe/xe3p_lpg: Enable L2 flush optimization feature

[Thomas Hellström]

On Fri, 2026-02-20 at 12:06 +0000, Matthew Auld wrote:
> On 20/02/2026 11:50, Thomas Hellström wrote:
> > On Fri, 2026-02-20 at 11:46 +0000, Matthew Auld wrote:
> > > On 20/02/2026 10:16, Tejas Upadhyay wrote:
> > > > When set, the L2 flush optimization feature will control
> > > > whether L2 is in Persistent or Transient mode through
> > > > monitoring of media activity.
> > > > 
> > > > To enable L2 flush optimization include new feature flag
> > > > GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when
> > > > media type is detected.
> > > > 
> > > > Also, restrict userptr, svm and dmabuf mappings to be
> > > > either 2WAY or XA+1WAY
> > > > 
> > > > V2(MattA): validate dma-buf bos and madvise pat-index
> > 
> > Question: Assuming that we on *faulting* VMs always perform a TLB
> > flush
> > on unbind. Can we eliminate the PAT restrictions on those? That
> > would
> > actually then include all SVM maps.
> 
> With unbind do you mean notifier invalidation flow on svm side? Or 
> actual vma unbind?

Both actually, or to rephrase, before we release any memory back to
system we have removed its GPU mappings and flushed TLB?

/Thomas



> 
> > 
> > /Thomas
> >   
> > 
> > > > 
> > > > Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> > > > ---
> > > >    drivers/gpu/drm/xe/xe_guc.c        |  3 +++
> > > >    drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
> > > >    drivers/gpu/drm/xe/xe_vm.c         |  9 +++++++++
> > > >    drivers/gpu/drm/xe/xe_vm_madvise.c | 18 ++++++++++++++++++
> > > >    4 files changed, 31 insertions(+)
> > > > 
> > > > diff --git a/drivers/gpu/drm/xe/xe_guc.c
> > > > b/drivers/gpu/drm/xe/xe_guc.c
> > > > index cbbb4d665b8f..97c33c3dd520 100644
> > > > --- a/drivers/gpu/drm/xe/xe_guc.c
> > > > +++ b/drivers/gpu/drm/xe/xe_guc.c
> > > > @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct
> > > > xe_guc
> > > > *guc)
> > > >    	if (xe_guc_using_main_gamctrl_queues(guc))
> > > >    		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
> > > >    
> > > > +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) &&
> > > > xe_gt_is_media_type(guc_to_gt(guc)))
> > > > +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
> > > > +
> > > >    	return flags;
> > > >    }
> > > >    
> > > > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > index a33ea288b907..39ff7b3e960b 100644
> > > > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
> > > >    #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
> > > >    #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
> > > >    #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
> > > > +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
> > > >    
> > > >    #define GUC_CTL_DEBUG			3
> > > >    #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
> > > > diff --git a/drivers/gpu/drm/xe/xe_vm.c
> > > > b/drivers/gpu/drm/xe/xe_vm.c
> > > > index c06fd250e037..e2e4c9648d05 100644
> > > > --- a/drivers/gpu/drm/xe/xe_vm.c
> > > > +++ b/drivers/gpu/drm/xe/xe_vm.c
> > > > @@ -3474,6 +3474,11 @@ static int
> > > > vm_bind_ioctl_check_args(struct
> > > > xe_device *xe, struct xe_vm *vm,
> > > >    				 op ==
> > > > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > > >    		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE
> > > > &&
> > > >    				 op ==
> > > > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > > > +		    XE_IOCTL_DBG(xe,
> > > > xe_device_is_l2_flush_optimized(xe) &&
> > > > +				 (op ==
> > > > DRM_XE_VM_BIND_OP_MAP_USERPTR ||
> > > > +				  /* svm */
> > > > +				  op == (DRM_XE_VM_BIND_OP_MAP
> > > > &&
> > > > is_cpu_addr_mirror)) &&
> > > 
> > > op == (DRM_XE_VM_BIND_OP_MAP && is_cpu_addr_mirror)
> > > 
> > > I think you meant (op == DRM_XE_VM_BIND_OP_MAP) && is_cpu ?
> > > 
> > > But maybe just drop the op check. Having the check being
> > > consistent
> > > for
> > > bind/unbind matches existing uapi behaviour?
> > > 
> > > > +				 (pat_index != 19 || coh_mode
> > > > !=
> > > > XE_COH_2WAY)) ||
> > > >    		    XE_IOCTL_DBG(xe, comp_en &&
> > > >    				 op ==
> > > > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > > >    		    XE_IOCTL_DBG(xe, op ==
> > > > DRM_XE_VM_BIND_OP_MAP_USERPTR &&
> > > > @@ -3608,6 +3613,10 @@ static int
> > > > xe_vm_bind_ioctl_validate_bo(struct xe_device *xe, struct xe_bo
> > > > *bo,
> > > >    	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> > > > comp_en))
> > > >    		return -EINVAL;
> > > >    
> > > > +	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> > > > xe_device_is_l2_flush_optimized(xe) &&
> > > > +			 (pat_index != 19 || coh_mode !=
> > > > XE_COH_2WAY)))
> > > > +		return -EINVAL;
> > > > +
> > > >    	/* If a BO is protected it can only be mapped if the
> > > > key
> > > > is still valid */
> > > >    	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) &&
> > > > xe_bo_is_protected(bo) &&
> > > >    	    op != DRM_XE_VM_BIND_OP_UNMAP && op !=
> > > > DRM_XE_VM_BIND_OP_UNMAP_ALL)
> > > > diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > > b/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > > index 1a1ad8c07d49..2a35dbeba2d8 100644
> > > > --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > > +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > > @@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device
> > > > *dev,
> > > > void *data, struct drm_file *fil
> > > >    	struct xe_vmas_in_madvise_range madvise_range = {.addr
> > > > =
> > > > args->start,
> > > >    							
> > > > .range =
> > > > args->range, };
> > > >    	struct xe_madvise_details details;
> > > > +	u16 pat_index, coh_mode;
> > > >    	struct xe_vm *vm;
> > > >    	struct drm_exec exec;
> > > >    	int err, attr_type;
> > > > @@ -447,6 +448,15 @@ int xe_vm_madvise_ioctl(struct drm_device
> > > > *dev, void *data, struct drm_file *fil
> > > >    	if (err || !madvise_range.num_vmas)
> > > >    		goto madv_fini;
> > > >    
> > > > +	pat_index = array_index_nospec(args->pat_index.val,
> > > > xe-
> > > > > pat.n_entries);
> > > 
> > > This needs to be conditional on DRM_XE_MEM_RANGE_ATTR_PAT. This
> > > is a
> > > union underneath so pat_index.val is not actually a pat_index for
> > > the
> > > other madv types, but just some other random data.
> > > 
> > > > +	coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
> > > > +	if (XE_IOCTL_DBG(xe,
> > > > madvise_range.has_svm_userptr_vmas &&
> > > > +			 xe_device_is_l2_flush_optimized(xe)
> > > > &&
> > > > +			 (pat_index != 19 || coh_mode !=
> > > > XE_COH_2WAY))) {
> > > > +		err = -EINVAL;
> > > > +		goto madv_fini;
> > > > +	}
> > > > +
> > > >    	if (madvise_range.has_bo_vmas) {
> > > >    		if (args->type ==
> > > > DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
> > > >    			if (!check_bo_args_are_sane(vm,
> > > > madvise_range.vmas,
> > > > @@ -464,6 +474,14 @@ int xe_vm_madvise_ioctl(struct drm_device
> > > > *dev, void *data, struct drm_file *fil
> > > >    
> > > >    				if (!bo)
> > > >    					continue;
> > > > +
> > > > +				if (XE_IOCTL_DBG(xe, bo-
> > > > > ttm.base.import_attach &&
> > > > +						
> > > > xe_device_is_l2_flush_optimized(xe) &&
> > > > +						 (pat_index !=
> > > > 19
> > > > > > coh_mode != XE_COH_2WAY))) {
> > > > +					err = -EINVAL;
> > > > +					goto err_fini;
> > > > +				}
> > > > +
> > > >    				err = drm_exec_lock_obj(&exec,
> > > > &bo->ttm.base);
> > > >    				drm_exec_retry_on_contention(&
> > > > exec
> > > > );
> > > >    				if (err)

RE: [PATCH V3 3/4] drm/xe/xe3p_lpg: Enable L2 flush optimization feature

[Upadhyay, Tejas]

> -----Original Message-----
> From: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Sent: 20 February 2026 18:29
> To: Auld, Matthew <matthew.auld@intel.com>; Upadhyay, Tejas
> <tejas.upadhyay@intel.com>; intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH V3 3/4] drm/xe/xe3p_lpg: Enable L2 flush optimization
> feature
> 
> On Fri, 2026-02-20 at 12:06 +0000, Matthew Auld wrote:
> > On 20/02/2026 11:50, Thomas Hellström wrote:
> > > On Fri, 2026-02-20 at 11:46 +0000, Matthew Auld wrote:
> > > > On 20/02/2026 10:16, Tejas Upadhyay wrote:
> > > > > When set, the L2 flush optimization feature will control whether
> > > > > L2 is in Persistent or Transient mode through monitoring of
> > > > > media activity.
> > > > >
> > > > > To enable L2 flush optimization include new feature flag
> > > > > GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when media
> > > > > type is detected.
> > > > >
> > > > > Also, restrict userptr, svm and dmabuf mappings to be either
> > > > > 2WAY or XA+1WAY
> > > > >
> > > > > V2(MattA): validate dma-buf bos and madvise pat-index
> > >
> > > Question: Assuming that we on *faulting* VMs always perform a TLB
> > > flush on unbind. Can we eliminate the PAT restrictions on those?
> > > That would actually then include all SVM maps.
> >
> > With unbind do you mean notifier invalidation flow on svm side? Or
> > actual vma unbind?
> 
> Both actually, or to rephrase, before we release any memory back to system
> we have removed its GPU mappings and flushed TLB?

Right for faulting VM, we do TLB invalidation on unbind/rebind. So you mean when that BO goes away ( even if its non-xa), tlb invalidation will take care of required flush and thus we can allow such cases from user.

Tejas
> 
> /Thomas
> 
> 
> 
> >
> > >
> > > /Thomas
> > >
> > >
> > > > >
> > > > > Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
> > > > > ---
> > > > >    drivers/gpu/drm/xe/xe_guc.c        |  3 +++
> > > > >    drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
> > > > >    drivers/gpu/drm/xe/xe_vm.c         |  9 +++++++++
> > > > >    drivers/gpu/drm/xe/xe_vm_madvise.c | 18 ++++++++++++++++++
> > > > >    4 files changed, 31 insertions(+)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/xe/xe_guc.c
> > > > > b/drivers/gpu/drm/xe/xe_guc.c index cbbb4d665b8f..97c33c3dd520
> > > > > 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_guc.c
> > > > > +++ b/drivers/gpu/drm/xe/xe_guc.c
> > > > > @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct xe_guc
> > > > > *guc)
> > > > >    	if (xe_guc_using_main_gamctrl_queues(guc))
> > > > >    		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
> > > > >
> > > > > +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) &&
> > > > > xe_gt_is_media_type(guc_to_gt(guc)))
> > > > > +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
> > > > > +
> > > > >    	return flags;
> > > > >    }
> > > > >
> > > > > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > > b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > > index a33ea288b907..39ff7b3e960b 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > > @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
> > > > >    #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
> > > > >    #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
> > > > >    #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
> > > > > +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
> > > > >
> > > > >    #define GUC_CTL_DEBUG			3
> > > > >    #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
> > > > > diff --git a/drivers/gpu/drm/xe/xe_vm.c
> > > > > b/drivers/gpu/drm/xe/xe_vm.c index c06fd250e037..e2e4c9648d05
> > > > > 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_vm.c
> > > > > +++ b/drivers/gpu/drm/xe/xe_vm.c
> > > > > @@ -3474,6 +3474,11 @@ static int
> > > > > vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
> > > > >    				 op ==
> > > > > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > > > >    		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE
> &&
> > > > >    				 op ==
> > > > > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > > > > +		    XE_IOCTL_DBG(xe,
> > > > > xe_device_is_l2_flush_optimized(xe) &&
> > > > > +				 (op ==
> > > > > DRM_XE_VM_BIND_OP_MAP_USERPTR ||
> > > > > +				  /* svm */
> > > > > +				  op == (DRM_XE_VM_BIND_OP_MAP
> > > > > &&
> > > > > is_cpu_addr_mirror)) &&
> > > >
> > > > op == (DRM_XE_VM_BIND_OP_MAP && is_cpu_addr_mirror)
> > > >
> > > > I think you meant (op == DRM_XE_VM_BIND_OP_MAP) && is_cpu ?
> > > >
> > > > But maybe just drop the op check. Having the check being
> > > > consistent for bind/unbind matches existing uapi behaviour?
> > > >
> > > > > +				 (pat_index != 19 || coh_mode
> > > > > !=
> > > > > XE_COH_2WAY)) ||
> > > > >    		    XE_IOCTL_DBG(xe, comp_en &&
> > > > >    				 op ==
> > > > > DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
> > > > >    		    XE_IOCTL_DBG(xe, op ==
> > > > > DRM_XE_VM_BIND_OP_MAP_USERPTR && @@ -3608,6 +3613,10
> @@ static
> > > > > int xe_vm_bind_ioctl_validate_bo(struct xe_device *xe, struct
> > > > > xe_bo *bo,
> > > > >    	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> > > > > comp_en))
> > > > >    		return -EINVAL;
> > > > >
> > > > > +	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
> > > > > xe_device_is_l2_flush_optimized(xe) &&
> > > > > +			 (pat_index != 19 || coh_mode !=
> > > > > XE_COH_2WAY)))
> > > > > +		return -EINVAL;
> > > > > +
> > > > >    	/* If a BO is protected it can only be mapped if the key is
> > > > > still valid */
> > > > >    	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) &&
> > > > > xe_bo_is_protected(bo) &&
> > > > >    	    op != DRM_XE_VM_BIND_OP_UNMAP && op !=
> > > > > DRM_XE_VM_BIND_OP_UNMAP_ALL)
> > > > > diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > > > b/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > > > index 1a1ad8c07d49..2a35dbeba2d8 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > > > +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
> > > > > @@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device
> > > > > *dev, void *data, struct drm_file *fil
> > > > >    	struct xe_vmas_in_madvise_range madvise_range = {.addr =
> > > > > args->start,
> > > > >
> > > > > .range =
> > > > > args->range, };
> > > > >    	struct xe_madvise_details details;
> > > > > +	u16 pat_index, coh_mode;
> > > > >    	struct xe_vm *vm;
> > > > >    	struct drm_exec exec;
> > > > >    	int err, attr_type;
> > > > > @@ -447,6 +448,15 @@ int xe_vm_madvise_ioctl(struct drm_device
> > > > > *dev, void *data, struct drm_file *fil
> > > > >    	if (err || !madvise_range.num_vmas)
> > > > >    		goto madv_fini;
> > > > >
> > > > > +	pat_index = array_index_nospec(args->pat_index.val,
> > > > > xe-
> > > > > > pat.n_entries);
> > > >
> > > > This needs to be conditional on DRM_XE_MEM_RANGE_ATTR_PAT. This is
> > > > a union underneath so pat_index.val is not actually a pat_index
> > > > for the other madv types, but just some other random data.
> > > >
> > > > > +	coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
> > > > > +	if (XE_IOCTL_DBG(xe,
> > > > > madvise_range.has_svm_userptr_vmas &&
> > > > > +			 xe_device_is_l2_flush_optimized(xe)
> > > > > &&
> > > > > +			 (pat_index != 19 || coh_mode !=
> > > > > XE_COH_2WAY))) {
> > > > > +		err = -EINVAL;
> > > > > +		goto madv_fini;
> > > > > +	}
> > > > > +
> > > > >    	if (madvise_range.has_bo_vmas) {
> > > > >    		if (args->type ==
> > > > > DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
> > > > >    			if (!check_bo_args_are_sane(vm,
> madvise_range.vmas, @@
> > > > > -464,6 +474,14 @@ int xe_vm_madvise_ioctl(struct drm_device
> > > > > *dev, void *data, struct drm_file *fil
> > > > >
> > > > >    				if (!bo)
> > > > >    					continue;
> > > > > +
> > > > > +				if (XE_IOCTL_DBG(xe, bo-
> > > > > > ttm.base.import_attach &&
> > > > > +
> > > > > xe_device_is_l2_flush_optimized(xe) &&
> > > > > +						 (pat_index !=
> > > > > 19
> > > > > > > coh_mode != XE_COH_2WAY))) {
> > > > > +					err = -EINVAL;
> > > > > +					goto err_fini;
> > > > > +				}
> > > > > +
> > > > >    				err = drm_exec_lock_obj(&exec, &bo-
> >ttm.base);
> > > > >    				drm_exec_retry_on_contention(&
> exec );
> > > > >    				if (err)

Re: [PATCH V3 3/4] drm/xe/xe3p_lpg: Enable L2 flush optimization feature

[Matthew Auld]

On 20/02/2026 12:58, Thomas Hellström wrote:
> On Fri, 2026-02-20 at 12:06 +0000, Matthew Auld wrote:
>> On 20/02/2026 11:50, Thomas Hellström wrote:
>>> On Fri, 2026-02-20 at 11:46 +0000, Matthew Auld wrote:
>>>> On 20/02/2026 10:16, Tejas Upadhyay wrote:
>>>>> When set, the L2 flush optimization feature will control
>>>>> whether L2 is in Persistent or Transient mode through
>>>>> monitoring of media activity.
>>>>>
>>>>> To enable L2 flush optimization include new feature flag
>>>>> GUC_CTL_ENABLE_L2FLUSH_OPT for Novalake platforms when
>>>>> media type is detected.
>>>>>
>>>>> Also, restrict userptr, svm and dmabuf mappings to be
>>>>> either 2WAY or XA+1WAY
>>>>>
>>>>> V2(MattA): validate dma-buf bos and madvise pat-index
>>>
>>> Question: Assuming that we on *faulting* VMs always perform a TLB
>>> flush
>>> on unbind. Can we eliminate the PAT restrictions on those? That
>>> would
>>> actually then include all SVM maps.
>>
>> With unbind do you mean notifier invalidation flow on svm side? Or
>> actual vma unbind?
> 
> Both actually, or to rephrase, before we release any memory back to
> system we have removed its GPU mappings and flushed TLB?

Hmm, yeah I think that must be true. We should already have the 
necessary tlb invalidations in all the right places for faulting VMs to 
be well behaved today. So if memory is going be released then the 
mapping surely must have already have been invalidated, and the 
invalidation will already take care to do a PPC flush. So from security 
angle there shouldn't be gaps when binding into a faulting VM, I think.

So with the faulting VM stuff this can go with LR right, but where we 
don't have to forcefully pre-empt it? So workload is still running but 
happy to trigger a fault, if needed. Are we assuming that zapping PTE + 
TLB flush ensures that the GPU is not still accessing the physical 
memory that the PTE was pointing at, like say it is has already fetched 
that memory and is still in the middle of some op. Or does it not work 
like this at all?

> 
> /Thomas
> 
> 
> 
>>
>>>
>>> /Thomas
>>>    
>>>
>>>>>
>>>>> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
>>>>> ---
>>>>>     drivers/gpu/drm/xe/xe_guc.c        |  3 +++
>>>>>     drivers/gpu/drm/xe/xe_guc_fwif.h   |  1 +
>>>>>     drivers/gpu/drm/xe/xe_vm.c         |  9 +++++++++
>>>>>     drivers/gpu/drm/xe/xe_vm_madvise.c | 18 ++++++++++++++++++
>>>>>     4 files changed, 31 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/xe/xe_guc.c
>>>>> b/drivers/gpu/drm/xe/xe_guc.c
>>>>> index cbbb4d665b8f..97c33c3dd520 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_guc.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>>>>> @@ -98,6 +98,9 @@ static u32 guc_ctl_feature_flags(struct
>>>>> xe_guc
>>>>> *guc)
>>>>>     	if (xe_guc_using_main_gamctrl_queues(guc))
>>>>>     		flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES;
>>>>>     
>>>>> +	if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe) &&
>>>>> xe_gt_is_media_type(guc_to_gt(guc)))
>>>>> +		flags |= GUC_CTL_ENABLE_L2FLUSH_OPT;
>>>>> +
>>>>>     	return flags;
>>>>>     }
>>>>>     
>>>>> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h
>>>>> b/drivers/gpu/drm/xe/xe_guc_fwif.h
>>>>> index a33ea288b907..39ff7b3e960b 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
>>>>> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
>>>>> @@ -67,6 +67,7 @@ struct guc_update_exec_queue_policy {
>>>>>     #define   GUC_CTL_ENABLE_PSMI_LOGGING	BIT(7)
>>>>>     #define   GUC_CTL_MAIN_GAMCTRL_QUEUES	BIT(9)
>>>>>     #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
>>>>> +#define   GUC_CTL_ENABLE_L2FLUSH_OPT	BIT(15)
>>>>>     
>>>>>     #define GUC_CTL_DEBUG			3
>>>>>     #define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
>>>>> diff --git a/drivers/gpu/drm/xe/xe_vm.c
>>>>> b/drivers/gpu/drm/xe/xe_vm.c
>>>>> index c06fd250e037..e2e4c9648d05 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_vm.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_vm.c
>>>>> @@ -3474,6 +3474,11 @@ static int
>>>>> vm_bind_ioctl_check_args(struct
>>>>> xe_device *xe, struct xe_vm *vm,
>>>>>     				 op ==
>>>>> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>>>>>     		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE
>>>>> &&
>>>>>     				 op ==
>>>>> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>>>>> +		    XE_IOCTL_DBG(xe,
>>>>> xe_device_is_l2_flush_optimized(xe) &&
>>>>> +				 (op ==
>>>>> DRM_XE_VM_BIND_OP_MAP_USERPTR ||
>>>>> +				  /* svm */
>>>>> +				  op == (DRM_XE_VM_BIND_OP_MAP
>>>>> &&
>>>>> is_cpu_addr_mirror)) &&
>>>>
>>>> op == (DRM_XE_VM_BIND_OP_MAP && is_cpu_addr_mirror)
>>>>
>>>> I think you meant (op == DRM_XE_VM_BIND_OP_MAP) && is_cpu ?
>>>>
>>>> But maybe just drop the op check. Having the check being
>>>> consistent
>>>> for
>>>> bind/unbind matches existing uapi behaviour?
>>>>
>>>>> +				 (pat_index != 19 || coh_mode
>>>>> !=
>>>>> XE_COH_2WAY)) ||
>>>>>     		    XE_IOCTL_DBG(xe, comp_en &&
>>>>>     				 op ==
>>>>> DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
>>>>>     		    XE_IOCTL_DBG(xe, op ==
>>>>> DRM_XE_VM_BIND_OP_MAP_USERPTR &&
>>>>> @@ -3608,6 +3613,10 @@ static int
>>>>> xe_vm_bind_ioctl_validate_bo(struct xe_device *xe, struct xe_bo
>>>>> *bo,
>>>>>     	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
>>>>> comp_en))
>>>>>     		return -EINVAL;
>>>>>     
>>>>> +	if (XE_IOCTL_DBG(xe, bo->ttm.base.import_attach &&
>>>>> xe_device_is_l2_flush_optimized(xe) &&
>>>>> +			 (pat_index != 19 || coh_mode !=
>>>>> XE_COH_2WAY)))
>>>>> +		return -EINVAL;
>>>>> +
>>>>>     	/* If a BO is protected it can only be mapped if the
>>>>> key
>>>>> is still valid */
>>>>>     	if ((bind_flags & DRM_XE_VM_BIND_FLAG_CHECK_PXP) &&
>>>>> xe_bo_is_protected(bo) &&
>>>>>     	    op != DRM_XE_VM_BIND_OP_UNMAP && op !=
>>>>> DRM_XE_VM_BIND_OP_UNMAP_ALL)
>>>>> diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c
>>>>> b/drivers/gpu/drm/xe/xe_vm_madvise.c
>>>>> index 1a1ad8c07d49..2a35dbeba2d8 100644
>>>>> --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
>>>>> +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
>>>>> @@ -411,6 +411,7 @@ int xe_vm_madvise_ioctl(struct drm_device
>>>>> *dev,
>>>>> void *data, struct drm_file *fil
>>>>>     	struct xe_vmas_in_madvise_range madvise_range = {.addr
>>>>> =
>>>>> args->start,
>>>>>     							
>>>>> .range =
>>>>> args->range, };
>>>>>     	struct xe_madvise_details details;
>>>>> +	u16 pat_index, coh_mode;
>>>>>     	struct xe_vm *vm;
>>>>>     	struct drm_exec exec;
>>>>>     	int err, attr_type;
>>>>> @@ -447,6 +448,15 @@ int xe_vm_madvise_ioctl(struct drm_device
>>>>> *dev, void *data, struct drm_file *fil
>>>>>     	if (err || !madvise_range.num_vmas)
>>>>>     		goto madv_fini;
>>>>>     
>>>>> +	pat_index = array_index_nospec(args->pat_index.val,
>>>>> xe-
>>>>>> pat.n_entries);
>>>>
>>>> This needs to be conditional on DRM_XE_MEM_RANGE_ATTR_PAT. This
>>>> is a
>>>> union underneath so pat_index.val is not actually a pat_index for
>>>> the
>>>> other madv types, but just some other random data.
>>>>
>>>>> +	coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
>>>>> +	if (XE_IOCTL_DBG(xe,
>>>>> madvise_range.has_svm_userptr_vmas &&
>>>>> +			 xe_device_is_l2_flush_optimized(xe)
>>>>> &&
>>>>> +			 (pat_index != 19 || coh_mode !=
>>>>> XE_COH_2WAY))) {
>>>>> +		err = -EINVAL;
>>>>> +		goto madv_fini;
>>>>> +	}
>>>>> +
>>>>>     	if (madvise_range.has_bo_vmas) {
>>>>>     		if (args->type ==
>>>>> DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
>>>>>     			if (!check_bo_args_are_sane(vm,
>>>>> madvise_range.vmas,
>>>>> @@ -464,6 +474,14 @@ int xe_vm_madvise_ioctl(struct drm_device
>>>>> *dev, void *data, struct drm_file *fil
>>>>>     
>>>>>     				if (!bo)
>>>>>     					continue;
>>>>> +
>>>>> +				if (XE_IOCTL_DBG(xe, bo-
>>>>>> ttm.base.import_attach &&
>>>>> +						
>>>>> xe_device_is_l2_flush_optimized(xe) &&
>>>>> +						 (pat_index !=
>>>>> 19
>>>>>>> coh_mode != XE_COH_2WAY))) {
>>>>> +					err = -EINVAL;
>>>>> +					goto err_fini;
>>>>> +				}
>>>>> +
>>>>>     				err = drm_exec_lock_obj(&exec,
>>>>> &bo->ttm.base);
>>>>>     				drm_exec_retry_on_contention(&
>>>>> exec
>>>>> );
>>>>>     				if (err)

[PATCH V3 4/4] drm/xe/xe3p: Skip TD flush

[Tejas Upadhyay]

Xe3p has HW ability to do transient display flush so the xe driver can
enable this HW feature by default and skip the software TD flush.

Bspec: 60002
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
 drivers/gpu/drm/xe/xe_device.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 94c9f17da4b4..0dca20133b94 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -1166,6 +1166,14 @@ void xe_device_td_flush(struct xe_device *xe)
 {
 	struct xe_gt *root_gt;
 
+	/*
+	 * From Xe3p onward the HW takes care of flush of TD entries also along
+	 * with flushing XA entries, which will be at the usual sync points,
+	 * like at the end of submission, so no manual flush is needed here.
+	 */
+	if (GRAPHICS_VER(xe) >= 35)
+		return;
+
 	if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20)
 		return;
 
-- 
2.52.0

✓ CI.KUnit: success for drm/xe/xe3p_lpg: L2 flush optimization (rev4)

[Patchwork]

== Series Details ==

Series: drm/xe/xe3p_lpg: L2 flush optimization (rev4)
URL   : https://patchwork.freedesktop.org/series/158017/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[10:22:41] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:22:45] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:23:16] Starting KUnit Kernel (1/1)...
[10:23:16] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:23:17] ================== guc_buf (11 subtests) ===================
[10:23:17] [PASSED] test_smallest
[10:23:17] [PASSED] test_largest
[10:23:17] [PASSED] test_granular
[10:23:17] [PASSED] test_unique
[10:23:17] [PASSED] test_overlap
[10:23:17] [PASSED] test_reusable
[10:23:17] [PASSED] test_too_big
[10:23:17] [PASSED] test_flush
[10:23:17] [PASSED] test_lookup
[10:23:17] [PASSED] test_data
[10:23:17] [PASSED] test_class
[10:23:17] ===================== [PASSED] guc_buf =====================
[10:23:17] =================== guc_dbm (7 subtests) ===================
[10:23:17] [PASSED] test_empty
[10:23:17] [PASSED] test_default
[10:23:17] ======================== test_size  ========================
[10:23:17] [PASSED] 4
[10:23:17] [PASSED] 8
[10:23:17] [PASSED] 32
[10:23:17] [PASSED] 256
[10:23:17] ==================== [PASSED] test_size ====================
[10:23:17] ======================= test_reuse  ========================
[10:23:17] [PASSED] 4
[10:23:17] [PASSED] 8
[10:23:17] [PASSED] 32
[10:23:17] [PASSED] 256
[10:23:17] =================== [PASSED] test_reuse ====================
[10:23:17] =================== test_range_overlap  ====================
[10:23:17] [PASSED] 4
[10:23:17] [PASSED] 8
[10:23:17] [PASSED] 32
[10:23:17] [PASSED] 256
[10:23:17] =============== [PASSED] test_range_overlap ================
[10:23:17] =================== test_range_compact  ====================
[10:23:17] [PASSED] 4
[10:23:17] [PASSED] 8
[10:23:17] [PASSED] 32
[10:23:17] [PASSED] 256
[10:23:17] =============== [PASSED] test_range_compact ================
[10:23:17] ==================== test_range_spare  =====================
[10:23:17] [PASSED] 4
[10:23:17] [PASSED] 8
[10:23:17] [PASSED] 32
[10:23:17] [PASSED] 256
[10:23:17] ================ [PASSED] test_range_spare =================
[10:23:17] ===================== [PASSED] guc_dbm =====================
[10:23:17] =================== guc_idm (6 subtests) ===================
[10:23:17] [PASSED] bad_init
[10:23:17] [PASSED] no_init
[10:23:17] [PASSED] init_fini
[10:23:17] [PASSED] check_used
[10:23:17] [PASSED] check_quota
[10:23:17] [PASSED] check_all
[10:23:17] ===================== [PASSED] guc_idm =====================
[10:23:17] ================== no_relay (3 subtests) ===================
[10:23:17] [PASSED] xe_drops_guc2pf_if_not_ready
[10:23:17] [PASSED] xe_drops_guc2vf_if_not_ready
[10:23:17] [PASSED] xe_rejects_send_if_not_ready
[10:23:17] ==================== [PASSED] no_relay =====================
[10:23:17] ================== pf_relay (14 subtests) ==================
[10:23:17] [PASSED] pf_rejects_guc2pf_too_short
[10:23:17] [PASSED] pf_rejects_guc2pf_too_long
[10:23:17] [PASSED] pf_rejects_guc2pf_no_payload
[10:23:17] [PASSED] pf_fails_no_payload
[10:23:17] [PASSED] pf_fails_bad_origin
[10:23:17] [PASSED] pf_fails_bad_type
[10:23:17] [PASSED] pf_txn_reports_error
[10:23:17] [PASSED] pf_txn_sends_pf2guc
[10:23:17] [PASSED] pf_sends_pf2guc
[10:23:17] [SKIPPED] pf_loopback_nop
[10:23:17] [SKIPPED] pf_loopback_echo
[10:23:17] [SKIPPED] pf_loopback_fail
[10:23:17] [SKIPPED] pf_loopback_busy
[10:23:17] [SKIPPED] pf_loopback_retry
[10:23:17] ==================== [PASSED] pf_relay =====================
[10:23:17] ================== vf_relay (3 subtests) ===================
[10:23:17] [PASSED] vf_rejects_guc2vf_too_short
[10:23:17] [PASSED] vf_rejects_guc2vf_too_long
[10:23:17] [PASSED] vf_rejects_guc2vf_no_payload
[10:23:17] ==================== [PASSED] vf_relay =====================
[10:23:17] ================ pf_gt_config (6 subtests) =================
[10:23:17] [PASSED] fair_contexts_1vf
[10:23:17] [PASSED] fair_doorbells_1vf
[10:23:17] [PASSED] fair_ggtt_1vf
[10:23:17] ====================== fair_contexts  ======================
[10:23:17] [PASSED] 1 VF
[10:23:17] [PASSED] 2 VFs
[10:23:17] [PASSED] 3 VFs
[10:23:17] [PASSED] 4 VFs
[10:23:17] [PASSED] 5 VFs
[10:23:17] [PASSED] 6 VFs
[10:23:17] [PASSED] 7 VFs
[10:23:17] [PASSED] 8 VFs
[10:23:17] [PASSED] 9 VFs
[10:23:17] [PASSED] 10 VFs
[10:23:17] [PASSED] 11 VFs
[10:23:17] [PASSED] 12 VFs
[10:23:17] [PASSED] 13 VFs
[10:23:17] [PASSED] 14 VFs
[10:23:17] [PASSED] 15 VFs
[10:23:17] [PASSED] 16 VFs
[10:23:17] [PASSED] 17 VFs
[10:23:17] [PASSED] 18 VFs
[10:23:17] [PASSED] 19 VFs
[10:23:17] [PASSED] 20 VFs
[10:23:17] [PASSED] 21 VFs
[10:23:17] [PASSED] 22 VFs
[10:23:17] [PASSED] 23 VFs
[10:23:17] [PASSED] 24 VFs
[10:23:17] [PASSED] 25 VFs
[10:23:17] [PASSED] 26 VFs
[10:23:17] [PASSED] 27 VFs
[10:23:17] [PASSED] 28 VFs
[10:23:17] [PASSED] 29 VFs
[10:23:17] [PASSED] 30 VFs
[10:23:17] [PASSED] 31 VFs
[10:23:17] [PASSED] 32 VFs
[10:23:17] [PASSED] 33 VFs
[10:23:17] [PASSED] 34 VFs
[10:23:17] [PASSED] 35 VFs
[10:23:17] [PASSED] 36 VFs
[10:23:17] [PASSED] 37 VFs
[10:23:17] [PASSED] 38 VFs
[10:23:17] [PASSED] 39 VFs
[10:23:17] [PASSED] 40 VFs
[10:23:17] [PASSED] 41 VFs
[10:23:17] [PASSED] 42 VFs
[10:23:17] [PASSED] 43 VFs
[10:23:17] [PASSED] 44 VFs
[10:23:17] [PASSED] 45 VFs
[10:23:17] [PASSED] 46 VFs
[10:23:17] [PASSED] 47 VFs
[10:23:17] [PASSED] 48 VFs
[10:23:17] [PASSED] 49 VFs
[10:23:17] [PASSED] 50 VFs
[10:23:17] [PASSED] 51 VFs
[10:23:17] [PASSED] 52 VFs
[10:23:17] [PASSED] 53 VFs
[10:23:17] [PASSED] 54 VFs
[10:23:17] [PASSED] 55 VFs
[10:23:17] [PASSED] 56 VFs
[10:23:17] [PASSED] 57 VFs
[10:23:17] [PASSED] 58 VFs
[10:23:17] [PASSED] 59 VFs
[10:23:17] [PASSED] 60 VFs
[10:23:17] [PASSED] 61 VFs
[10:23:17] [PASSED] 62 VFs
[10:23:17] [PASSED] 63 VFs
[10:23:17] ================== [PASSED] fair_contexts ==================
[10:23:17] ===================== fair_doorbells  ======================
[10:23:17] [PASSED] 1 VF
[10:23:17] [PASSED] 2 VFs
[10:23:17] [PASSED] 3 VFs
[10:23:17] [PASSED] 4 VFs
[10:23:17] [PASSED] 5 VFs
[10:23:17] [PASSED] 6 VFs
[10:23:17] [PASSED] 7 VFs
[10:23:17] [PASSED] 8 VFs
[10:23:17] [PASSED] 9 VFs
[10:23:17] [PASSED] 10 VFs
[10:23:17] [PASSED] 11 VFs
[10:23:17] [PASSED] 12 VFs
[10:23:17] [PASSED] 13 VFs
[10:23:17] [PASSED] 14 VFs
[10:23:17] [PASSED] 15 VFs
[10:23:17] [PASSED] 16 VFs
[10:23:17] [PASSED] 17 VFs
[10:23:17] [PASSED] 18 VFs
[10:23:17] [PASSED] 19 VFs
[10:23:17] [PASSED] 20 VFs
[10:23:17] [PASSED] 21 VFs
[10:23:17] [PASSED] 22 VFs
[10:23:17] [PASSED] 23 VFs
[10:23:17] [PASSED] 24 VFs
[10:23:17] [PASSED] 25 VFs
[10:23:17] [PASSED] 26 VFs
[10:23:17] [PASSED] 27 VFs
[10:23:17] [PASSED] 28 VFs
[10:23:17] [PASSED] 29 VFs
[10:23:17] [PASSED] 30 VFs
[10:23:17] [PASSED] 31 VFs
[10:23:17] [PASSED] 32 VFs
[10:23:17] [PASSED] 33 VFs
[10:23:17] [PASSED] 34 VFs
[10:23:17] [PASSED] 35 VFs
[10:23:17] [PASSED] 36 VFs
[10:23:17] [PASSED] 37 VFs
[10:23:17] [PASSED] 38 VFs
[10:23:17] [PASSED] 39 VFs
[10:23:17] [PASSED] 40 VFs
[10:23:17] [PASSED] 41 VFs
[10:23:17] [PASSED] 42 VFs
[10:23:17] [PASSED] 43 VFs
[10:23:17] [PASSED] 44 VFs
[10:23:17] [PASSED] 45 VFs
[10:23:17] [PASSED] 46 VFs
[10:23:17] [PASSED] 47 VFs
[10:23:17] [PASSED] 48 VFs
[10:23:17] [PASSED] 49 VFs
[10:23:17] [PASSED] 50 VFs
[10:23:17] [PASSED] 51 VFs
[10:23:17] [PASSED] 52 VFs
[10:23:17] [PASSED] 53 VFs
[10:23:17] [PASSED] 54 VFs
[10:23:17] [PASSED] 55 VFs
[10:23:17] [PASSED] 56 VFs
[10:23:17] [PASSED] 57 VFs
[10:23:17] [PASSED] 58 VFs
[10:23:17] [PASSED] 59 VFs
[10:23:17] [PASSED] 60 VFs
[10:23:17] [PASSED] 61 VFs
[10:23:17] [PASSED] 62 VFs
[10:23:17] [PASSED] 63 VFs
[10:23:17] ================= [PASSED] fair_doorbells ==================
[10:23:17] ======================== fair_ggtt  ========================
[10:23:17] [PASSED] 1 VF
[10:23:17] [PASSED] 2 VFs
[10:23:17] [PASSED] 3 VFs
[10:23:17] [PASSED] 4 VFs
[10:23:17] [PASSED] 5 VFs
[10:23:17] [PASSED] 6 VFs
[10:23:17] [PASSED] 7 VFs
[10:23:17] [PASSED] 8 VFs
[10:23:17] [PASSED] 9 VFs
[10:23:17] [PASSED] 10 VFs
[10:23:17] [PASSED] 11 VFs
[10:23:17] [PASSED] 12 VFs
[10:23:17] [PASSED] 13 VFs
[10:23:17] [PASSED] 14 VFs
[10:23:17] [PASSED] 15 VFs
[10:23:17] [PASSED] 16 VFs
[10:23:17] [PASSED] 17 VFs
[10:23:17] [PASSED] 18 VFs
[10:23:17] [PASSED] 19 VFs
[10:23:17] [PASSED] 20 VFs
[10:23:17] [PASSED] 21 VFs
[10:23:17] [PASSED] 22 VFs
[10:23:17] [PASSED] 23 VFs
[10:23:17] [PASSED] 24 VFs
[10:23:17] [PASSED] 25 VFs
[10:23:17] [PASSED] 26 VFs
[10:23:17] [PASSED] 27 VFs
[10:23:17] [PASSED] 28 VFs
[10:23:17] [PASSED] 29 VFs
[10:23:17] [PASSED] 30 VFs
[10:23:17] [PASSED] 31 VFs
[10:23:17] [PASSED] 32 VFs
[10:23:17] [PASSED] 33 VFs
[10:23:17] [PASSED] 34 VFs
[10:23:17] [PASSED] 35 VFs
[10:23:17] [PASSED] 36 VFs
[10:23:17] [PASSED] 37 VFs
[10:23:17] [PASSED] 38 VFs
[10:23:17] [PASSED] 39 VFs
[10:23:17] [PASSED] 40 VFs
[10:23:17] [PASSED] 41 VFs
[10:23:17] [PASSED] 42 VFs
[10:23:17] [PASSED] 43 VFs
[10:23:17] [PASSED] 44 VFs
[10:23:17] [PASSED] 45 VFs
[10:23:17] [PASSED] 46 VFs
[10:23:17] [PASSED] 47 VFs
[10:23:17] [PASSED] 48 VFs
[10:23:17] [PASSED] 49 VFs
[10:23:17] [PASSED] 50 VFs
[10:23:17] [PASSED] 51 VFs
[10:23:17] [PASSED] 52 VFs
[10:23:17] [PASSED] 53 VFs
[10:23:17] [PASSED] 54 VFs
[10:23:17] [PASSED] 55 VFs
[10:23:17] [PASSED] 56 VFs
[10:23:17] [PASSED] 57 VFs
[10:23:17] [PASSED] 58 VFs
[10:23:17] [PASSED] 59 VFs
[10:23:17] [PASSED] 60 VFs
[10:23:17] [PASSED] 61 VFs
[10:23:17] [PASSED] 62 VFs
[10:23:17] [PASSED] 63 VFs
[10:23:17] ==================== [PASSED] fair_ggtt ====================
[10:23:17] ================== [PASSED] pf_gt_config ===================
[10:23:17] ===================== lmtt (1 subtest) =====================
[10:23:17] ======================== test_ops  =========================
[10:23:17] [PASSED] 2-level
[10:23:17] [PASSED] multi-level
[10:23:17] ==================== [PASSED] test_ops =====================
[10:23:17] ====================== [PASSED] lmtt =======================
[10:23:17] ================= pf_service (11 subtests) =================
[10:23:17] [PASSED] pf_negotiate_any
[10:23:17] [PASSED] pf_negotiate_base_match
[10:23:17] [PASSED] pf_negotiate_base_newer
[10:23:17] [PASSED] pf_negotiate_base_next
[10:23:17] [SKIPPED] pf_negotiate_base_older
[10:23:17] [PASSED] pf_negotiate_base_prev
[10:23:17] [PASSED] pf_negotiate_latest_match
[10:23:17] [PASSED] pf_negotiate_latest_newer
[10:23:17] [PASSED] pf_negotiate_latest_next
[10:23:17] [SKIPPED] pf_negotiate_latest_older
[10:23:17] [SKIPPED] pf_negotiate_latest_prev
[10:23:17] =================== [PASSED] pf_service ====================
[10:23:17] ================= xe_guc_g2g (2 subtests) ==================
[10:23:17] ============== xe_live_guc_g2g_kunit_default  ==============
[10:23:17] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[10:23:17] ============== xe_live_guc_g2g_kunit_allmem  ===============
[10:23:17] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[10:23:17] =================== [SKIPPED] xe_guc_g2g ===================
[10:23:17] =================== xe_mocs (2 subtests) ===================
[10:23:17] ================ xe_live_mocs_kernel_kunit  ================
[10:23:17] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[10:23:17] ================ xe_live_mocs_reset_kunit  =================
[10:23:17] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[10:23:17] ==================== [SKIPPED] xe_mocs =====================
[10:23:17] ================= xe_migrate (2 subtests) ==================
[10:23:17] ================= xe_migrate_sanity_kunit  =================
[10:23:17] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[10:23:17] ================== xe_validate_ccs_kunit  ==================
[10:23:17] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[10:23:17] =================== [SKIPPED] xe_migrate ===================
[10:23:17] ================== xe_dma_buf (1 subtest) ==================
[10:23:17] ==================== xe_dma_buf_kunit  =====================
[10:23:17] ================ [SKIPPED] xe_dma_buf_kunit ================
[10:23:17] =================== [SKIPPED] xe_dma_buf ===================
[10:23:17] ================= xe_bo_shrink (1 subtest) =================
[10:23:17] =================== xe_bo_shrink_kunit  ====================
[10:23:17] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[10:23:17] ================== [SKIPPED] xe_bo_shrink ==================
[10:23:17] ==================== xe_bo (2 subtests) ====================
[10:23:17] ================== xe_ccs_migrate_kunit  ===================
[10:23:17] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[10:23:17] ==================== xe_bo_evict_kunit  ====================
[10:23:17] =============== [SKIPPED] xe_bo_evict_kunit ================
[10:23:17] ===================== [SKIPPED] xe_bo ======================
[10:23:17] ==================== args (13 subtests) ====================
[10:23:17] [PASSED] count_args_test
[10:23:17] [PASSED] call_args_example
[10:23:17] [PASSED] call_args_test
[10:23:17] [PASSED] drop_first_arg_example
[10:23:17] [PASSED] drop_first_arg_test
[10:23:17] [PASSED] first_arg_example
[10:23:17] [PASSED] first_arg_test
[10:23:17] [PASSED] last_arg_example
[10:23:17] [PASSED] last_arg_test
[10:23:17] [PASSED] pick_arg_example
[10:23:17] [PASSED] if_args_example
[10:23:17] [PASSED] if_args_test
[10:23:17] [PASSED] sep_comma_example
[10:23:17] ====================== [PASSED] args =======================
[10:23:17] =================== xe_pci (3 subtests) ====================
[10:23:17] ==================== check_graphics_ip  ====================
[10:23:17] [PASSED] 12.00 Xe_LP
[10:23:17] [PASSED] 12.10 Xe_LP+
[10:23:17] [PASSED] 12.55 Xe_HPG
[10:23:17] [PASSED] 12.60 Xe_HPC
[10:23:17] [PASSED] 12.70 Xe_LPG
[10:23:17] [PASSED] 12.71 Xe_LPG
[10:23:17] [PASSED] 12.74 Xe_LPG+
[10:23:17] [PASSED] 20.01 Xe2_HPG
[10:23:17] [PASSED] 20.02 Xe2_HPG
[10:23:17] [PASSED] 20.04 Xe2_LPG
[10:23:17] [PASSED] 30.00 Xe3_LPG
[10:23:17] [PASSED] 30.01 Xe3_LPG
[10:23:17] [PASSED] 30.03 Xe3_LPG
[10:23:17] [PASSED] 30.04 Xe3_LPG
[10:23:17] [PASSED] 30.05 Xe3_LPG
[10:23:17] [PASSED] 35.10 Xe3p_LPG
[10:23:17] [PASSED] 35.11 Xe3p_XPC
[10:23:17] ================ [PASSED] check_graphics_ip ================
[10:23:17] ===================== check_media_ip  ======================
[10:23:17] [PASSED] 12.00 Xe_M
[10:23:17] [PASSED] 12.55 Xe_HPM
[10:23:17] [PASSED] 13.00 Xe_LPM+
[10:23:17] [PASSED] 13.01 Xe2_HPM
[10:23:17] [PASSED] 20.00 Xe2_LPM
[10:23:17] [PASSED] 30.00 Xe3_LPM
[10:23:17] [PASSED] 30.02 Xe3_LPM
[10:23:17] [PASSED] 35.00 Xe3p_LPM
[10:23:17] [PASSED] 35.03 Xe3p_HPM
[10:23:17] ================= [PASSED] check_media_ip ==================
[10:23:17] =================== check_platform_desc  ===================
[10:23:17] [PASSED] 0x9A60 (TIGERLAKE)
[10:23:17] [PASSED] 0x9A68 (TIGERLAKE)
[10:23:17] [PASSED] 0x9A70 (TIGERLAKE)
[10:23:17] [PASSED] 0x9A40 (TIGERLAKE)
[10:23:17] [PASSED] 0x9A49 (TIGERLAKE)
[10:23:17] [PASSED] 0x9A59 (TIGERLAKE)
[10:23:17] [PASSED] 0x9A78 (TIGERLAKE)
[10:23:17] [PASSED] 0x9AC0 (TIGERLAKE)
[10:23:17] [PASSED] 0x9AC9 (TIGERLAKE)
[10:23:17] [PASSED] 0x9AD9 (TIGERLAKE)
[10:23:17] [PASSED] 0x9AF8 (TIGERLAKE)
[10:23:17] [PASSED] 0x4C80 (ROCKETLAKE)
[10:23:17] [PASSED] 0x4C8A (ROCKETLAKE)
[10:23:17] [PASSED] 0x4C8B (ROCKETLAKE)
[10:23:17] [PASSED] 0x4C8C (ROCKETLAKE)
[10:23:17] [PASSED] 0x4C90 (ROCKETLAKE)
[10:23:17] [PASSED] 0x4C9A (ROCKETLAKE)
[10:23:17] [PASSED] 0x4680 (ALDERLAKE_S)
[10:23:17] [PASSED] 0x4682 (ALDERLAKE_S)
[10:23:17] [PASSED] 0x4688 (ALDERLAKE_S)
[10:23:17] [PASSED] 0x468A (ALDERLAKE_S)
[10:23:17] [PASSED] 0x468B (ALDERLAKE_S)
[10:23:17] [PASSED] 0x4690 (ALDERLAKE_S)
[10:23:17] [PASSED] 0x4692 (ALDERLAKE_S)
[10:23:17] [PASSED] 0x4693 (ALDERLAKE_S)
[10:23:17] [PASSED] 0x46A0 (ALDERLAKE_P)
[10:23:17] [PASSED] 0x46A1 (ALDERLAKE_P)
[10:23:17] [PASSED] 0x46A2 (ALDERLAKE_P)
[10:23:17] [PASSED] 0x46A3 (ALDERLAKE_P)
[10:23:17] [PASSED] 0x46A6 (ALDERLAKE_P)
[10:23:17] [PASSED] 0x46A8 (ALDERLAKE_P)
[10:23:17] [PASSED] 0x46AA (ALDERLAKE_P)
[10:23:17] [PASSED] 0x462A (ALDERLAKE_P)
[10:23:17] [PASSED] 0x4626 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[10:23:17] [PASSED] 0x4628 (ALDERLAKE_P)
[10:23:17] [PASSED] 0x46B0 (ALDERLAKE_P)
[10:23:17] [PASSED] 0x46B1 (ALDERLAKE_P)
[10:23:17] [PASSED] 0x46B2 (ALDERLAKE_P)
[10:23:17] [PASSED] 0x46B3 (ALDERLAKE_P)
[10:23:17] [PASSED] 0x46C0 (ALDERLAKE_P)
[10:23:17] [PASSED] 0x46C1 (ALDERLAKE_P)
[10:23:17] [PASSED] 0x46C2 (ALDERLAKE_P)
[10:23:17] [PASSED] 0x46C3 (ALDERLAKE_P)
[10:23:17] [PASSED] 0x46D0 (ALDERLAKE_N)
[10:23:17] [PASSED] 0x46D1 (ALDERLAKE_N)
[10:23:17] [PASSED] 0x46D2 (ALDERLAKE_N)
[10:23:17] [PASSED] 0x46D3 (ALDERLAKE_N)
[10:23:17] [PASSED] 0x46D4 (ALDERLAKE_N)
[10:23:17] [PASSED] 0xA721 (ALDERLAKE_P)
[10:23:17] [PASSED] 0xA7A1 (ALDERLAKE_P)
[10:23:17] [PASSED] 0xA7A9 (ALDERLAKE_P)
[10:23:17] [PASSED] 0xA7AC (ALDERLAKE_P)
[10:23:17] [PASSED] 0xA7AD (ALDERLAKE_P)
[10:23:17] [PASSED] 0xA720 (ALDERLAKE_P)
[10:23:17] [PASSED] 0xA7A0 (ALDERLAKE_P)
[10:23:17] [PASSED] 0xA7A8 (ALDERLAKE_P)
[10:23:17] [PASSED] 0xA7AA (ALDERLAKE_P)
[10:23:17] [PASSED] 0xA7AB (ALDERLAKE_P)
[10:23:17] [PASSED] 0xA780 (ALDERLAKE_S)
[10:23:17] [PASSED] 0xA781 (ALDERLAKE_S)
[10:23:17] [PASSED] 0xA782 (ALDERLAKE_S)
[10:23:17] [PASSED] 0xA783 (ALDERLAKE_S)
[10:23:17] [PASSED] 0xA788 (ALDERLAKE_S)
[10:23:17] [PASSED] 0xA789 (ALDERLAKE_S)
[10:23:17] [PASSED] 0xA78A (ALDERLAKE_S)
[10:23:17] [PASSED] 0xA78B (ALDERLAKE_S)
[10:23:17] [PASSED] 0x4905 (DG1)
[10:23:17] [PASSED] 0x4906 (DG1)
[10:23:17] [PASSED] 0x4907 (DG1)
[10:23:17] [PASSED] 0x4908 (DG1)
[10:23:17] [PASSED] 0x4909 (DG1)
[10:23:17] [PASSED] 0x56C0 (DG2)
[10:23:17] [PASSED] 0x56C2 (DG2)
[10:23:17] [PASSED] 0x56C1 (DG2)
[10:23:17] [PASSED] 0x7D51 (METEORLAKE)
[10:23:17] [PASSED] 0x7DD1 (METEORLAKE)
[10:23:17] [PASSED] 0x7D41 (METEORLAKE)
[10:23:17] [PASSED] 0x7D67 (METEORLAKE)
[10:23:17] [PASSED] 0xB640 (METEORLAKE)
[10:23:17] [PASSED] 0x56A0 (DG2)
[10:23:17] [PASSED] 0x56A1 (DG2)
[10:23:17] [PASSED] 0x56A2 (DG2)
[10:23:17] [PASSED] 0x56BE (DG2)
[10:23:17] [PASSED] 0x56BF (DG2)
[10:23:17] [PASSED] 0x5690 (DG2)
[10:23:17] [PASSED] 0x5691 (DG2)
[10:23:17] [PASSED] 0x5692 (DG2)
[10:23:17] [PASSED] 0x56A5 (DG2)
[10:23:17] [PASSED] 0x56A6 (DG2)
[10:23:17] [PASSED] 0x56B0 (DG2)
[10:23:17] [PASSED] 0x56B1 (DG2)
[10:23:17] [PASSED] 0x56BA (DG2)
[10:23:17] [PASSED] 0x56BB (DG2)
[10:23:17] [PASSED] 0x56BC (DG2)
[10:23:17] [PASSED] 0x56BD (DG2)
[10:23:17] [PASSED] 0x5693 (DG2)
[10:23:17] [PASSED] 0x5694 (DG2)
[10:23:17] [PASSED] 0x5695 (DG2)
[10:23:17] [PASSED] 0x56A3 (DG2)
[10:23:17] [PASSED] 0x56A4 (DG2)
[10:23:17] [PASSED] 0x56B2 (DG2)
[10:23:17] [PASSED] 0x56B3 (DG2)
[10:23:17] [PASSED] 0x5696 (DG2)
[10:23:17] [PASSED] 0x5697 (DG2)
[10:23:17] [PASSED] 0xB69 (PVC)
[10:23:17] [PASSED] 0xB6E (PVC)
[10:23:17] [PASSED] 0xBD4 (PVC)
[10:23:17] [PASSED] 0xBD5 (PVC)
[10:23:17] [PASSED] 0xBD6 (PVC)
[10:23:17] [PASSED] 0xBD7 (PVC)
[10:23:17] [PASSED] 0xBD8 (PVC)
[10:23:17] [PASSED] 0xBD9 (PVC)
[10:23:17] [PASSED] 0xBDA (PVC)
[10:23:17] [PASSED] 0xBDB (PVC)
[10:23:17] [PASSED] 0xBE0 (PVC)
[10:23:17] [PASSED] 0xBE1 (PVC)
[10:23:17] [PASSED] 0xBE5 (PVC)
[10:23:17] [PASSED] 0x7D40 (METEORLAKE)
[10:23:17] [PASSED] 0x7D45 (METEORLAKE)
[10:23:17] [PASSED] 0x7D55 (METEORLAKE)
[10:23:17] [PASSED] 0x7D60 (METEORLAKE)
[10:23:17] [PASSED] 0x7DD5 (METEORLAKE)
[10:23:17] [PASSED] 0x6420 (LUNARLAKE)
[10:23:17] [PASSED] 0x64A0 (LUNARLAKE)
[10:23:17] [PASSED] 0x64B0 (LUNARLAKE)
[10:23:17] [PASSED] 0xE202 (BATTLEMAGE)
[10:23:17] [PASSED] 0xE209 (BATTLEMAGE)
[10:23:17] [PASSED] 0xE20B (BATTLEMAGE)
[10:23:17] [PASSED] 0xE20C (BATTLEMAGE)
[10:23:17] [PASSED] 0xE20D (BATTLEMAGE)
[10:23:17] [PASSED] 0xE210 (BATTLEMAGE)
[10:23:17] [PASSED] 0xE211 (BATTLEMAGE)
[10:23:17] [PASSED] 0xE212 (BATTLEMAGE)
[10:23:17] [PASSED] 0xE216 (BATTLEMAGE)
[10:23:17] [PASSED] 0xE220 (BATTLEMAGE)
[10:23:17] [PASSED] 0xE221 (BATTLEMAGE)
[10:23:17] [PASSED] 0xE222 (BATTLEMAGE)
[10:23:17] [PASSED] 0xE223 (BATTLEMAGE)
[10:23:17] [PASSED] 0xB080 (PANTHERLAKE)
[10:23:17] [PASSED] 0xB081 (PANTHERLAKE)
[10:23:17] [PASSED] 0xB082 (PANTHERLAKE)
[10:23:17] [PASSED] 0xB083 (PANTHERLAKE)
[10:23:17] [PASSED] 0xB084 (PANTHERLAKE)
[10:23:17] [PASSED] 0xB085 (PANTHERLAKE)
[10:23:17] [PASSED] 0xB086 (PANTHERLAKE)
[10:23:17] [PASSED] 0xB087 (PANTHERLAKE)
[10:23:17] [PASSED] 0xB08F (PANTHERLAKE)
[10:23:17] [PASSED] 0xB090 (PANTHERLAKE)
[10:23:17] [PASSED] 0xB0A0 (PANTHERLAKE)
[10:23:17] [PASSED] 0xB0B0 (PANTHERLAKE)
[10:23:17] [PASSED] 0xFD80 (PANTHERLAKE)
[10:23:17] [PASSED] 0xFD81 (PANTHERLAKE)
[10:23:17] [PASSED] 0xD740 (NOVALAKE_S)
[10:23:17] [PASSED] 0xD741 (NOVALAKE_S)
[10:23:17] [PASSED] 0xD742 (NOVALAKE_S)
[10:23:17] [PASSED] 0xD743 (NOVALAKE_S)
[10:23:17] [PASSED] 0xD744 (NOVALAKE_S)
[10:23:17] [PASSED] 0xD745 (NOVALAKE_S)
[10:23:17] [PASSED] 0x674C (CRESCENTISLAND)
[10:23:17] [PASSED] 0xD750 (NOVALAKE_P)
[10:23:17] [PASSED] 0xD751 (NOVALAKE_P)
[10:23:17] [PASSED] 0xD752 (NOVALAKE_P)
[10:23:17] [PASSED] 0xD753 (NOVALAKE_P)
[10:23:17] [PASSED] 0xD754 (NOVALAKE_P)
[10:23:17] [PASSED] 0xD755 (NOVALAKE_P)
[10:23:17] [PASSED] 0xD756 (NOVALAKE_P)
[10:23:17] [PASSED] 0xD757 (NOVALAKE_P)
[10:23:17] [PASSED] 0xD75F (NOVALAKE_P)
[10:23:17] =============== [PASSED] check_platform_desc ===============
[10:23:17] ===================== [PASSED] xe_pci ======================
[10:23:17] =================== xe_rtp (2 subtests) ====================
[10:23:17] =============== xe_rtp_process_to_sr_tests  ================
[10:23:17] [PASSED] coalesce-same-reg
[10:23:17] [PASSED] no-match-no-add
[10:23:17] [PASSED] match-or
[10:23:17] [PASSED] match-or-xfail
[10:23:17] [PASSED] no-match-no-add-multiple-rules
[10:23:17] [PASSED] two-regs-two-entries
[10:23:17] [PASSED] clr-one-set-other
[10:23:17] [PASSED] set-field
[10:23:17] [PASSED] conflict-duplicate
[10:23:17] [PASSED] conflict-not-disjoint
[10:23:17] [PASSED] conflict-reg-type
[10:23:17] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[10:23:17] ================== xe_rtp_process_tests  ===================
[10:23:17] [PASSED] active1
[10:23:17] [PASSED] active2
[10:23:17] [PASSED] active-inactive
[10:23:17] [PASSED] inactive-active
[10:23:17] [PASSED] inactive-1st_or_active-inactive
[10:23:17] [PASSED] inactive-2nd_or_active-inactive
[10:23:17] [PASSED] inactive-last_or_active-inactive
[10:23:17] [PASSED] inactive-no_or_active-inactive
[10:23:17] ============== [PASSED] xe_rtp_process_tests ===============
[10:23:17] ===================== [PASSED] xe_rtp ======================
[10:23:17] ==================== xe_wa (1 subtest) =====================
[10:23:17] ======================== xe_wa_gt  =========================
[10:23:17] [PASSED] TIGERLAKE B0
[10:23:17] [PASSED] DG1 A0
[10:23:17] [PASSED] DG1 B0
[10:23:17] [PASSED] ALDERLAKE_S A0
[10:23:17] [PASSED] ALDERLAKE_S B0
[10:23:17] [PASSED] ALDERLAKE_S C0
[10:23:17] [PASSED] ALDERLAKE_S D0
[10:23:17] [PASSED] ALDERLAKE_P A0
[10:23:17] [PASSED] ALDERLAKE_P B0
[10:23:17] [PASSED] ALDERLAKE_P C0
[10:23:17] [PASSED] ALDERLAKE_S RPLS D0
[10:23:17] [PASSED] ALDERLAKE_P RPLU E0
[10:23:17] [PASSED] DG2 G10 C0
[10:23:17] [PASSED] DG2 G11 B1
[10:23:17] [PASSED] DG2 G12 A1
[10:23:17] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:23:17] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:23:17] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[10:23:17] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[10:23:17] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[10:23:17] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[10:23:17] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[10:23:17] ==================== [PASSED] xe_wa_gt =====================
[10:23:17] ====================== [PASSED] xe_wa ======================
[10:23:17] ============================================================
[10:23:17] Testing complete. Ran 522 tests: passed: 504, skipped: 18
[10:23:17] Elapsed time: 36.479s total, 4.213s configuring, 31.748s building, 0.479s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:23:17] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:23:19] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:23:44] Starting KUnit Kernel (1/1)...
[10:23:44] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:23:44] ============ drm_test_pick_cmdline (2 subtests) ============
[10:23:44] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[10:23:44] =============== drm_test_pick_cmdline_named  ===============
[10:23:44] [PASSED] NTSC
[10:23:44] [PASSED] NTSC-J
[10:23:44] [PASSED] PAL
[10:23:44] [PASSED] PAL-M
[10:23:44] =========== [PASSED] drm_test_pick_cmdline_named ===========
[10:23:44] ============== [PASSED] drm_test_pick_cmdline ==============
[10:23:44] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[10:23:44] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[10:23:44] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[10:23:44] =========== drm_validate_clone_mode (2 subtests) ===========
[10:23:44] ============== drm_test_check_in_clone_mode  ===============
[10:23:44] [PASSED] in_clone_mode
[10:23:44] [PASSED] not_in_clone_mode
[10:23:44] ========== [PASSED] drm_test_check_in_clone_mode ===========
[10:23:44] =============== drm_test_check_valid_clones  ===============
[10:23:44] [PASSED] not_in_clone_mode
[10:23:44] [PASSED] valid_clone
[10:23:44] [PASSED] invalid_clone
[10:23:44] =========== [PASSED] drm_test_check_valid_clones ===========
[10:23:44] ============= [PASSED] drm_validate_clone_mode =============
[10:23:44] ============= drm_validate_modeset (1 subtest) =============
[10:23:44] [PASSED] drm_test_check_connector_changed_modeset
[10:23:44] ============== [PASSED] drm_validate_modeset ===============
[10:23:44] ====== drm_test_bridge_get_current_state (2 subtests) ======
[10:23:44] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[10:23:44] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[10:23:44] ======== [PASSED] drm_test_bridge_get_current_state ========
[10:23:44] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[10:23:44] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[10:23:44] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[10:23:44] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[10:23:44] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[10:23:44] ============== drm_bridge_alloc (2 subtests) ===============
[10:23:44] [PASSED] drm_test_drm_bridge_alloc_basic
[10:23:44] [PASSED] drm_test_drm_bridge_alloc_get_put
[10:23:44] ================ [PASSED] drm_bridge_alloc =================
[10:23:44] ============= drm_cmdline_parser (40 subtests) =============
[10:23:44] [PASSED] drm_test_cmdline_force_d_only
[10:23:44] [PASSED] drm_test_cmdline_force_D_only_dvi
[10:23:44] [PASSED] drm_test_cmdline_force_D_only_hdmi
[10:23:44] [PASSED] drm_test_cmdline_force_D_only_not_digital
[10:23:44] [PASSED] drm_test_cmdline_force_e_only
[10:23:44] [PASSED] drm_test_cmdline_res
[10:23:44] [PASSED] drm_test_cmdline_res_vesa
[10:23:44] [PASSED] drm_test_cmdline_res_vesa_rblank
[10:23:44] [PASSED] drm_test_cmdline_res_rblank
[10:23:44] [PASSED] drm_test_cmdline_res_bpp
[10:23:44] [PASSED] drm_test_cmdline_res_refresh
[10:23:44] [PASSED] drm_test_cmdline_res_bpp_refresh
[10:23:44] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[10:23:44] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[10:23:44] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[10:23:44] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[10:23:44] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[10:23:44] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[10:23:44] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[10:23:44] [PASSED] drm_test_cmdline_res_margins_force_on
[10:23:44] [PASSED] drm_test_cmdline_res_vesa_margins
[10:23:44] [PASSED] drm_test_cmdline_name
[10:23:44] [PASSED] drm_test_cmdline_name_bpp
[10:23:44] [PASSED] drm_test_cmdline_name_option
[10:23:44] [PASSED] drm_test_cmdline_name_bpp_option
[10:23:44] [PASSED] drm_test_cmdline_rotate_0
[10:23:44] [PASSED] drm_test_cmdline_rotate_90
[10:23:44] [PASSED] drm_test_cmdline_rotate_180
[10:23:44] [PASSED] drm_test_cmdline_rotate_270
[10:23:44] [PASSED] drm_test_cmdline_hmirror
[10:23:44] [PASSED] drm_test_cmdline_vmirror
[10:23:44] [PASSED] drm_test_cmdline_margin_options
[10:23:44] [PASSED] drm_test_cmdline_multiple_options
[10:23:44] [PASSED] drm_test_cmdline_bpp_extra_and_option
[10:23:44] [PASSED] drm_test_cmdline_extra_and_option
[10:23:44] [PASSED] drm_test_cmdline_freestanding_options
[10:23:44] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[10:23:44] [PASSED] drm_test_cmdline_panel_orientation
[10:23:44] ================ drm_test_cmdline_invalid  =================
[10:23:44] [PASSED] margin_only
[10:23:44] [PASSED] interlace_only
[10:23:44] [PASSED] res_missing_x
[10:23:44] [PASSED] res_missing_y
[10:23:44] [PASSED] res_bad_y
[10:23:44] [PASSED] res_missing_y_bpp
[10:23:44] [PASSED] res_bad_bpp
[10:23:44] [PASSED] res_bad_refresh
[10:23:44] [PASSED] res_bpp_refresh_force_on_off
[10:23:44] [PASSED] res_invalid_mode
[10:23:44] [PASSED] res_bpp_wrong_place_mode
[10:23:44] [PASSED] name_bpp_refresh
[10:23:44] [PASSED] name_refresh
[10:23:44] [PASSED] name_refresh_wrong_mode
[10:23:44] [PASSED] name_refresh_invalid_mode
[10:23:44] [PASSED] rotate_multiple
[10:23:44] [PASSED] rotate_invalid_val
[10:23:44] [PASSED] rotate_truncated
[10:23:44] [PASSED] invalid_option
[10:23:44] [PASSED] invalid_tv_option
[10:23:44] [PASSED] truncated_tv_option
[10:23:44] ============ [PASSED] drm_test_cmdline_invalid =============
[10:23:44] =============== drm_test_cmdline_tv_options  ===============
[10:23:44] [PASSED] NTSC
[10:23:44] [PASSED] NTSC_443
[10:23:44] [PASSED] NTSC_J
[10:23:44] [PASSED] PAL
[10:23:44] [PASSED] PAL_M
[10:23:44] [PASSED] PAL_N
[10:23:44] [PASSED] SECAM
[10:23:44] [PASSED] MONO_525
[10:23:44] [PASSED] MONO_625
[10:23:44] =========== [PASSED] drm_test_cmdline_tv_options ===========
[10:23:44] =============== [PASSED] drm_cmdline_parser ================
[10:23:44] ========== drmm_connector_hdmi_init (20 subtests) ==========
[10:23:44] [PASSED] drm_test_connector_hdmi_init_valid
[10:23:44] [PASSED] drm_test_connector_hdmi_init_bpc_8
[10:23:44] [PASSED] drm_test_connector_hdmi_init_bpc_10
[10:23:44] [PASSED] drm_test_connector_hdmi_init_bpc_12
[10:23:44] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[10:23:44] [PASSED] drm_test_connector_hdmi_init_bpc_null
[10:23:44] [PASSED] drm_test_connector_hdmi_init_formats_empty
[10:23:44] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[10:23:44] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[10:23:44] [PASSED] supported_formats=0x9 yuv420_allowed=1
[10:23:44] [PASSED] supported_formats=0x9 yuv420_allowed=0
[10:23:44] [PASSED] supported_formats=0x3 yuv420_allowed=1
[10:23:44] [PASSED] supported_formats=0x3 yuv420_allowed=0
[10:23:44] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:23:44] [PASSED] drm_test_connector_hdmi_init_null_ddc
[10:23:44] [PASSED] drm_test_connector_hdmi_init_null_product
[10:23:44] [PASSED] drm_test_connector_hdmi_init_null_vendor
[10:23:44] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[10:23:44] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[10:23:44] [PASSED] drm_test_connector_hdmi_init_product_valid
[10:23:44] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[10:23:44] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[10:23:44] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[10:23:44] ========= drm_test_connector_hdmi_init_type_valid  =========
[10:23:44] [PASSED] HDMI-A
[10:23:44] [PASSED] HDMI-B
[10:23:44] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[10:23:44] ======== drm_test_connector_hdmi_init_type_invalid  ========
[10:23:44] [PASSED] Unknown
[10:23:44] [PASSED] VGA
[10:23:44] [PASSED] DVI-I
[10:23:44] [PASSED] DVI-D
[10:23:44] [PASSED] DVI-A
[10:23:44] [PASSED] Composite
[10:23:44] [PASSED] SVIDEO
[10:23:44] [PASSED] LVDS
[10:23:44] [PASSED] Component
[10:23:44] [PASSED] DIN
[10:23:44] [PASSED] DP
[10:23:44] [PASSED] TV
[10:23:44] [PASSED] eDP
[10:23:44] [PASSED] Virtual
[10:23:44] [PASSED] DSI
[10:23:44] [PASSED] DPI
[10:23:44] [PASSED] Writeback
[10:23:44] [PASSED] SPI
[10:23:44] [PASSED] USB
[10:23:44] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[10:23:44] ============ [PASSED] drmm_connector_hdmi_init =============
[10:23:44] ============= drmm_connector_init (3 subtests) =============
[10:23:44] [PASSED] drm_test_drmm_connector_init
[10:23:44] [PASSED] drm_test_drmm_connector_init_null_ddc
[10:23:44] ========= drm_test_drmm_connector_init_type_valid  =========
[10:23:44] [PASSED] Unknown
[10:23:44] [PASSED] VGA
[10:23:44] [PASSED] DVI-I
[10:23:44] [PASSED] DVI-D
[10:23:44] [PASSED] DVI-A
[10:23:44] [PASSED] Composite
[10:23:44] [PASSED] SVIDEO
[10:23:44] [PASSED] LVDS
[10:23:44] [PASSED] Component
[10:23:44] [PASSED] DIN
[10:23:44] [PASSED] DP
[10:23:44] [PASSED] HDMI-A
[10:23:44] [PASSED] HDMI-B
[10:23:44] [PASSED] TV
[10:23:44] [PASSED] eDP
[10:23:44] [PASSED] Virtual
[10:23:44] [PASSED] DSI
[10:23:44] [PASSED] DPI
[10:23:44] [PASSED] Writeback
[10:23:44] [PASSED] SPI
[10:23:44] [PASSED] USB
[10:23:44] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[10:23:44] =============== [PASSED] drmm_connector_init ===============
[10:23:44] ========= drm_connector_dynamic_init (6 subtests) ==========
[10:23:44] [PASSED] drm_test_drm_connector_dynamic_init
[10:23:44] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[10:23:44] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[10:23:44] [PASSED] drm_test_drm_connector_dynamic_init_properties
[10:23:44] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[10:23:44] [PASSED] Unknown
[10:23:44] [PASSED] VGA
[10:23:44] [PASSED] DVI-I
[10:23:44] [PASSED] DVI-D
[10:23:44] [PASSED] DVI-A
[10:23:44] [PASSED] Composite
[10:23:44] [PASSED] SVIDEO
[10:23:44] [PASSED] LVDS
[10:23:44] [PASSED] Component
[10:23:44] [PASSED] DIN
[10:23:44] [PASSED] DP
[10:23:44] [PASSED] HDMI-A
[10:23:44] [PASSED] HDMI-B
[10:23:44] [PASSED] TV
[10:23:44] [PASSED] eDP
[10:23:44] [PASSED] Virtual
[10:23:44] [PASSED] DSI
[10:23:44] [PASSED] DPI
[10:23:44] [PASSED] Writeback
[10:23:44] [PASSED] SPI
[10:23:44] [PASSED] USB
[10:23:44] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[10:23:44] ======== drm_test_drm_connector_dynamic_init_name  =========
[10:23:44] [PASSED] Unknown
[10:23:44] [PASSED] VGA
[10:23:44] [PASSED] DVI-I
[10:23:44] [PASSED] DVI-D
[10:23:44] [PASSED] DVI-A
[10:23:44] [PASSED] Composite
[10:23:44] [PASSED] SVIDEO
[10:23:44] [PASSED] LVDS
[10:23:44] [PASSED] Component
[10:23:44] [PASSED] DIN
[10:23:44] [PASSED] DP
[10:23:44] [PASSED] HDMI-A
[10:23:44] [PASSED] HDMI-B
[10:23:44] [PASSED] TV
[10:23:44] [PASSED] eDP
[10:23:44] [PASSED] Virtual
[10:23:44] [PASSED] DSI
[10:23:44] [PASSED] DPI
[10:23:44] [PASSED] Writeback
[10:23:44] [PASSED] SPI
[10:23:44] [PASSED] USB
[10:23:44] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[10:23:44] =========== [PASSED] drm_connector_dynamic_init ============
[10:23:44] ==== drm_connector_dynamic_register_early (4 subtests) =====
[10:23:44] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[10:23:44] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[10:23:44] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[10:23:44] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[10:23:44] ====== [PASSED] drm_connector_dynamic_register_early =======
[10:23:44] ======= drm_connector_dynamic_register (7 subtests) ========
[10:23:44] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[10:23:44] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[10:23:44] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[10:23:44] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[10:23:44] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[10:23:44] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[10:23:44] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[10:23:44] ========= [PASSED] drm_connector_dynamic_register ==========
[10:23:44] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[10:23:44] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[10:23:44] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[10:23:44] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[10:23:44] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[10:23:44] ========== drm_test_get_tv_mode_from_name_valid  ===========
[10:23:44] [PASSED] NTSC
[10:23:44] [PASSED] NTSC-443
[10:23:44] [PASSED] NTSC-J
[10:23:44] [PASSED] PAL
[10:23:44] [PASSED] PAL-M
[10:23:44] [PASSED] PAL-N
[10:23:44] [PASSED] SECAM
[10:23:44] [PASSED] Mono
[10:23:44] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[10:23:44] [PASSED] drm_test_get_tv_mode_from_name_truncated
[10:23:44] ============ [PASSED] drm_get_tv_mode_from_name ============
[10:23:44] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[10:23:44] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[10:23:44] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[10:23:44] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[10:23:44] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[10:23:44] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[10:23:44] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[10:23:44] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[10:23:44] [PASSED] VIC 96
[10:23:44] [PASSED] VIC 97
[10:23:44] [PASSED] VIC 101
[10:23:44] [PASSED] VIC 102
[10:23:44] [PASSED] VIC 106
[10:23:44] [PASSED] VIC 107
[10:23:44] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[10:23:44] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[10:23:44] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[10:23:44] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[10:23:44] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[10:23:44] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[10:23:44] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[10:23:44] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[10:23:44] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[10:23:44] [PASSED] Automatic
[10:23:44] [PASSED] Full
[10:23:44] [PASSED] Limited 16:235
[10:23:44] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[10:23:44] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[10:23:44] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[10:23:44] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[10:23:44] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[10:23:44] [PASSED] RGB
[10:23:44] [PASSED] YUV 4:2:0
[10:23:44] [PASSED] YUV 4:2:2
[10:23:44] [PASSED] YUV 4:4:4
[10:23:44] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[10:23:44] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[10:23:44] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[10:23:44] ============= drm_damage_helper (21 subtests) ==============
[10:23:44] [PASSED] drm_test_damage_iter_no_damage
[10:23:44] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[10:23:44] [PASSED] drm_test_damage_iter_no_damage_src_moved
[10:23:44] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[10:23:44] [PASSED] drm_test_damage_iter_no_damage_not_visible
[10:23:44] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[10:23:44] [PASSED] drm_test_damage_iter_no_damage_no_fb
[10:23:44] [PASSED] drm_test_damage_iter_simple_damage
[10:23:44] [PASSED] drm_test_damage_iter_single_damage
[10:23:44] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[10:23:44] [PASSED] drm_test_damage_iter_single_damage_outside_src
[10:23:44] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[10:23:44] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[10:23:44] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[10:23:44] [PASSED] drm_test_damage_iter_single_damage_src_moved
[10:23:44] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[10:23:44] [PASSED] drm_test_damage_iter_damage
[10:23:44] [PASSED] drm_test_damage_iter_damage_one_intersect
[10:23:44] [PASSED] drm_test_damage_iter_damage_one_outside
[10:23:44] [PASSED] drm_test_damage_iter_damage_src_moved
[10:23:44] [PASSED] drm_test_damage_iter_damage_not_visible
[10:23:44] ================ [PASSED] drm_damage_helper ================
[10:23:44] ============== drm_dp_mst_helper (3 subtests) ==============
[10:23:44] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[10:23:44] [PASSED] Clock 154000 BPP 30 DSC disabled
[10:23:44] [PASSED] Clock 234000 BPP 30 DSC disabled
[10:23:44] [PASSED] Clock 297000 BPP 24 DSC disabled
[10:23:44] [PASSED] Clock 332880 BPP 24 DSC enabled
[10:23:44] [PASSED] Clock 324540 BPP 24 DSC enabled
[10:23:44] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[10:23:44] ============== drm_test_dp_mst_calc_pbn_div  ===============
[10:23:44] [PASSED] Link rate 2000000 lane count 4
[10:23:44] [PASSED] Link rate 2000000 lane count 2
[10:23:44] [PASSED] Link rate 2000000 lane count 1
[10:23:44] [PASSED] Link rate 1350000 lane count 4
[10:23:44] [PASSED] Link rate 1350000 lane count 2
[10:23:44] [PASSED] Link rate 1350000 lane count 1
[10:23:44] [PASSED] Link rate 1000000 lane count 4
[10:23:44] [PASSED] Link rate 1000000 lane count 2
[10:23:44] [PASSED] Link rate 1000000 lane count 1
[10:23:44] [PASSED] Link rate 810000 lane count 4
[10:23:44] [PASSED] Link rate 810000 lane count 2
[10:23:44] [PASSED] Link rate 810000 lane count 1
[10:23:44] [PASSED] Link rate 540000 lane count 4
[10:23:44] [PASSED] Link rate 540000 lane count 2
[10:23:44] [PASSED] Link rate 540000 lane count 1
[10:23:44] [PASSED] Link rate 270000 lane count 4
[10:23:44] [PASSED] Link rate 270000 lane count 2
[10:23:44] [PASSED] Link rate 270000 lane count 1
[10:23:44] [PASSED] Link rate 162000 lane count 4
[10:23:44] [PASSED] Link rate 162000 lane count 2
[10:23:44] [PASSED] Link rate 162000 lane count 1
[10:23:44] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[10:23:44] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[10:23:44] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[10:23:44] [PASSED] DP_POWER_UP_PHY with port number
[10:23:44] [PASSED] DP_POWER_DOWN_PHY with port number
[10:23:44] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[10:23:44] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[10:23:44] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[10:23:44] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[10:23:44] [PASSED] DP_QUERY_PAYLOAD with port number
[10:23:44] [PASSED] DP_QUERY_PAYLOAD with VCPI
[10:23:44] [PASSED] DP_REMOTE_DPCD_READ with port number
[10:23:44] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[10:23:44] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[10:23:44] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[10:23:44] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[10:23:44] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[10:23:44] [PASSED] DP_REMOTE_I2C_READ with port number
[10:23:44] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[10:23:44] [PASSED] DP_REMOTE_I2C_READ with transactions array
[10:23:44] [PASSED] DP_REMOTE_I2C_WRITE with port number
[10:23:44] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[10:23:44] [PASSED] DP_REMOTE_I2C_WRITE with data array
[10:23:44] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[10:23:44] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[10:23:44] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[10:23:44] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[10:23:44] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[10:23:44] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[10:23:44] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[10:23:44] ================ [PASSED] drm_dp_mst_helper ================
[10:23:44] ================== drm_exec (7 subtests) ===================
[10:23:44] [PASSED] sanitycheck
[10:23:44] [PASSED] test_lock
[10:23:44] [PASSED] test_lock_unlock
[10:23:44] [PASSED] test_duplicates
[10:23:44] [PASSED] test_prepare
[10:23:44] [PASSED] test_prepare_array
[10:23:44] [PASSED] test_multiple_loops
[10:23:44] ==================== [PASSED] drm_exec =====================
[10:23:44] =========== drm_format_helper_test (17 subtests) ===========
[10:23:44] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[10:23:44] [PASSED] single_pixel_source_buffer
[10:23:44] [PASSED] single_pixel_clip_rectangle
[10:23:44] [PASSED] well_known_colors
[10:23:44] [PASSED] destination_pitch
[10:23:44] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[10:23:44] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[10:23:44] [PASSED] single_pixel_source_buffer
[10:23:44] [PASSED] single_pixel_clip_rectangle
[10:23:44] [PASSED] well_known_colors
[10:23:44] [PASSED] destination_pitch
[10:23:44] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[10:23:44] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[10:23:44] [PASSED] single_pixel_source_buffer
[10:23:44] [PASSED] single_pixel_clip_rectangle
[10:23:44] [PASSED] well_known_colors
[10:23:44] [PASSED] destination_pitch
[10:23:44] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[10:23:44] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[10:23:44] [PASSED] single_pixel_source_buffer
[10:23:44] [PASSED] single_pixel_clip_rectangle
[10:23:44] [PASSED] well_known_colors
[10:23:44] [PASSED] destination_pitch
[10:23:44] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[10:23:44] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[10:23:44] [PASSED] single_pixel_source_buffer
[10:23:44] [PASSED] single_pixel_clip_rectangle
[10:23:44] [PASSED] well_known_colors
[10:23:44] [PASSED] destination_pitch
[10:23:44] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[10:23:44] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[10:23:44] [PASSED] single_pixel_source_buffer
[10:23:44] [PASSED] single_pixel_clip_rectangle
[10:23:44] [PASSED] well_known_colors
[10:23:44] [PASSED] destination_pitch
[10:23:44] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[10:23:44] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[10:23:44] [PASSED] single_pixel_source_buffer
[10:23:44] [PASSED] single_pixel_clip_rectangle
[10:23:44] [PASSED] well_known_colors
[10:23:44] [PASSED] destination_pitch
[10:23:44] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[10:23:44] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[10:23:44] [PASSED] single_pixel_source_buffer
[10:23:44] [PASSED] single_pixel_clip_rectangle
[10:23:44] [PASSED] well_known_colors
[10:23:44] [PASSED] destination_pitch
[10:23:44] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[10:23:44] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[10:23:44] [PASSED] single_pixel_source_buffer
[10:23:44] [PASSED] single_pixel_clip_rectangle
[10:23:44] [PASSED] well_known_colors
[10:23:44] [PASSED] destination_pitch
[10:23:44] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[10:23:44] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[10:23:44] [PASSED] single_pixel_source_buffer
[10:23:44] [PASSED] single_pixel_clip_rectangle
[10:23:44] [PASSED] well_known_colors
[10:23:44] [PASSED] destination_pitch
[10:23:44] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[10:23:44] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[10:23:44] [PASSED] single_pixel_source_buffer
[10:23:44] [PASSED] single_pixel_clip_rectangle
[10:23:44] [PASSED] well_known_colors
[10:23:44] [PASSED] destination_pitch
[10:23:44] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[10:23:44] ============== drm_test_fb_xrgb8888_to_mono  ===============
[10:23:44] [PASSED] single_pixel_source_buffer
[10:23:44] [PASSED] single_pixel_clip_rectangle
[10:23:44] [PASSED] well_known_colors
[10:23:44] [PASSED] destination_pitch
[10:23:44] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[10:23:44] ==================== drm_test_fb_swab  =====================
[10:23:44] [PASSED] single_pixel_source_buffer
[10:23:44] [PASSED] single_pixel_clip_rectangle
[10:23:44] [PASSED] well_known_colors
[10:23:44] [PASSED] destination_pitch
[10:23:44] ================ [PASSED] drm_test_fb_swab =================
[10:23:44] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[10:23:44] [PASSED] single_pixel_source_buffer
[10:23:44] [PASSED] single_pixel_clip_rectangle
[10:23:44] [PASSED] well_known_colors
[10:23:44] [PASSED] destination_pitch
[10:23:44] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[10:23:44] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[10:23:44] [PASSED] single_pixel_source_buffer
[10:23:44] [PASSED] single_pixel_clip_rectangle
[10:23:44] [PASSED] well_known_colors
[10:23:44] [PASSED] destination_pitch
[10:23:44] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[10:23:44] ================= drm_test_fb_clip_offset  =================
[10:23:44] [PASSED] pass through
[10:23:44] [PASSED] horizontal offset
[10:23:44] [PASSED] vertical offset
[10:23:44] [PASSED] horizontal and vertical offset
[10:23:44] [PASSED] horizontal offset (custom pitch)
[10:23:44] [PASSED] vertical offset (custom pitch)
[10:23:44] [PASSED] horizontal and vertical offset (custom pitch)
[10:23:44] ============= [PASSED] drm_test_fb_clip_offset =============
[10:23:44] =================== drm_test_fb_memcpy  ====================
[10:23:44] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[10:23:44] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[10:23:44] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[10:23:44] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[10:23:44] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[10:23:44] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[10:23:44] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[10:23:44] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[10:23:44] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[10:23:44] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[10:23:44] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[10:23:44] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[10:23:44] =============== [PASSED] drm_test_fb_memcpy ================
[10:23:44] ============= [PASSED] drm_format_helper_test ==============
[10:23:44] ================= drm_format (18 subtests) =================
[10:23:44] [PASSED] drm_test_format_block_width_invalid
[10:23:44] [PASSED] drm_test_format_block_width_one_plane
[10:23:44] [PASSED] drm_test_format_block_width_two_plane
[10:23:44] [PASSED] drm_test_format_block_width_three_plane
[10:23:44] [PASSED] drm_test_format_block_width_tiled
[10:23:44] [PASSED] drm_test_format_block_height_invalid
[10:23:44] [PASSED] drm_test_format_block_height_one_plane
[10:23:44] [PASSED] drm_test_format_block_height_two_plane
[10:23:44] [PASSED] drm_test_format_block_height_three_plane
[10:23:44] [PASSED] drm_test_format_block_height_tiled
[10:23:44] [PASSED] drm_test_format_min_pitch_invalid
[10:23:44] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[10:23:44] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[10:23:44] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[10:23:44] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[10:23:44] [PASSED] drm_test_format_min_pitch_two_plane
[10:23:44] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[10:23:44] [PASSED] drm_test_format_min_pitch_tiled
[10:23:44] =================== [PASSED] drm_format ====================
[10:23:44] ============== drm_framebuffer (10 subtests) ===============
[10:23:44] ========== drm_test_framebuffer_check_src_coords  ==========
[10:23:44] [PASSED] Success: source fits into fb
[10:23:44] [PASSED] Fail: overflowing fb with x-axis coordinate
[10:23:44] [PASSED] Fail: overflowing fb with y-axis coordinate
[10:23:44] [PASSED] Fail: overflowing fb with source width
[10:23:44] [PASSED] Fail: overflowing fb with source height
[10:23:44] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[10:23:44] [PASSED] drm_test_framebuffer_cleanup
[10:23:44] =============== drm_test_framebuffer_create  ===============
[10:23:44] [PASSED] ABGR8888 normal sizes
[10:23:44] [PASSED] ABGR8888 max sizes
[10:23:44] [PASSED] ABGR8888 pitch greater than min required
[10:23:44] [PASSED] ABGR8888 pitch less than min required
[10:23:44] [PASSED] ABGR8888 Invalid width
[10:23:44] [PASSED] ABGR8888 Invalid buffer handle
[10:23:44] [PASSED] No pixel format
[10:23:44] [PASSED] ABGR8888 Width 0
[10:23:44] [PASSED] ABGR8888 Height 0
[10:23:44] [PASSED] ABGR8888 Out of bound height * pitch combination
[10:23:44] [PASSED] ABGR8888 Large buffer offset
[10:23:44] [PASSED] ABGR8888 Buffer offset for inexistent plane
[10:23:44] [PASSED] ABGR8888 Invalid flag
[10:23:44] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[10:23:44] [PASSED] ABGR8888 Valid buffer modifier
[10:23:44] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[10:23:44] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[10:23:44] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[10:23:44] [PASSED] NV12 Normal sizes
[10:23:44] [PASSED] NV12 Max sizes
[10:23:44] [PASSED] NV12 Invalid pitch
[10:23:44] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[10:23:44] [PASSED] NV12 different  modifier per-plane
[10:23:44] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[10:23:44] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[10:23:44] [PASSED] NV12 Modifier for inexistent plane
[10:23:44] [PASSED] NV12 Handle for inexistent plane
[10:23:44] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[10:23:44] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[10:23:44] [PASSED] YVU420 Normal sizes
[10:23:44] [PASSED] YVU420 Max sizes
[10:23:44] [PASSED] YVU420 Invalid pitch
[10:23:44] [PASSED] YVU420 Different pitches
[10:23:44] [PASSED] YVU420 Different buffer offsets/pitches
[10:23:44] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[10:23:44] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[10:23:44] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[10:23:44] [PASSED] YVU420 Valid modifier
[10:23:44] [PASSED] YVU420 Different modifiers per plane
[10:23:44] [PASSED] YVU420 Modifier for inexistent plane
[10:23:44] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[10:23:44] [PASSED] X0L2 Normal sizes
[10:23:44] [PASSED] X0L2 Max sizes
[10:23:44] [PASSED] X0L2 Invalid pitch
[10:23:44] [PASSED] X0L2 Pitch greater than minimum required
[10:23:44] [PASSED] X0L2 Handle for inexistent plane
[10:23:44] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[10:23:44] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[10:23:44] [PASSED] X0L2 Valid modifier
[10:23:44] [PASSED] X0L2 Modifier for inexistent plane
[10:23:44] =========== [PASSED] drm_test_framebuffer_create ===========
[10:23:44] [PASSED] drm_test_framebuffer_free
[10:23:44] [PASSED] drm_test_framebuffer_init
[10:23:44] [PASSED] drm_test_framebuffer_init_bad_format
[10:23:44] [PASSED] drm_test_framebuffer_init_dev_mismatch
[10:23:44] [PASSED] drm_test_framebuffer_lookup
[10:23:44] [PASSED] drm_test_framebuffer_lookup_inexistent
[10:23:44] [PASSED] drm_test_framebuffer_modifiers_not_supported
[10:23:44] ================= [PASSED] drm_framebuffer =================
[10:23:44] ================ drm_gem_shmem (8 subtests) ================
[10:23:44] [PASSED] drm_gem_shmem_test_obj_create
[10:23:44] [PASSED] drm_gem_shmem_test_obj_create_private
[10:23:44] [PASSED] drm_gem_shmem_test_pin_pages
[10:23:44] [PASSED] drm_gem_shmem_test_vmap
[10:23:44] [PASSED] drm_gem_shmem_test_get_sg_table
[10:23:44] [PASSED] drm_gem_shmem_test_get_pages_sgt
[10:23:44] [PASSED] drm_gem_shmem_test_madvise
[10:23:44] [PASSED] drm_gem_shmem_test_purge
[10:23:44] ================== [PASSED] drm_gem_shmem ==================
[10:23:44] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[10:23:44] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[10:23:44] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[10:23:44] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[10:23:44] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[10:23:44] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[10:23:44] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[10:23:44] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[10:23:44] [PASSED] Automatic
[10:23:44] [PASSED] Full
[10:23:44] [PASSED] Limited 16:235
[10:23:44] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[10:23:44] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[10:23:44] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[10:23:44] [PASSED] drm_test_check_disable_connector
[10:23:44] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[10:23:44] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[10:23:44] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[10:23:44] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[10:23:44] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[10:23:44] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[10:23:44] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[10:23:44] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[10:23:44] [PASSED] drm_test_check_output_bpc_dvi
[10:23:44] [PASSED] drm_test_check_output_bpc_format_vic_1
[10:23:44] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[10:23:44] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[10:23:44] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[10:23:44] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[10:23:44] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[10:23:44] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[10:23:44] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[10:23:44] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[10:23:44] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[10:23:44] [PASSED] drm_test_check_broadcast_rgb_value
[10:23:44] [PASSED] drm_test_check_bpc_8_value
[10:23:44] [PASSED] drm_test_check_bpc_10_value
[10:23:44] [PASSED] drm_test_check_bpc_12_value
[10:23:44] [PASSED] drm_test_check_format_value
[10:23:44] [PASSED] drm_test_check_tmds_char_value
[10:23:44] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[10:23:44] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[10:23:44] [PASSED] drm_test_check_mode_valid
[10:23:44] [PASSED] drm_test_check_mode_valid_reject
[10:23:44] [PASSED] drm_test_check_mode_valid_reject_rate
[10:23:44] [PASSED] drm_test_check_mode_valid_reject_max_clock
[10:23:44] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[10:23:44] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[10:23:44] [PASSED] drm_test_check_infoframes
[10:23:44] [PASSED] drm_test_check_reject_avi_infoframe
[10:23:44] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[10:23:44] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[10:23:44] [PASSED] drm_test_check_reject_audio_infoframe
[10:23:44] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[10:23:44] ================= drm_managed (2 subtests) =================
[10:23:44] [PASSED] drm_test_managed_release_action
[10:23:44] [PASSED] drm_test_managed_run_action
[10:23:44] =================== [PASSED] drm_managed ===================
[10:23:44] =================== drm_mm (6 subtests) ====================
[10:23:44] [PASSED] drm_test_mm_init
[10:23:44] [PASSED] drm_test_mm_debug
[10:23:44] [PASSED] drm_test_mm_align32
[10:23:44] [PASSED] drm_test_mm_align64
[10:23:44] [PASSED] drm_test_mm_lowest
[10:23:44] [PASSED] drm_test_mm_highest
[10:23:44] ===================== [PASSED] drm_mm ======================
[10:23:44] ============= drm_modes_analog_tv (5 subtests) =============
[10:23:44] [PASSED] drm_test_modes_analog_tv_mono_576i
[10:23:44] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[10:23:44] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[10:23:44] [PASSED] drm_test_modes_analog_tv_pal_576i
[10:23:44] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[10:23:44] =============== [PASSED] drm_modes_analog_tv ===============
[10:23:44] ============== drm_plane_helper (2 subtests) ===============
[10:23:44] =============== drm_test_check_plane_state  ================
[10:23:44] [PASSED] clipping_simple
[10:23:44] [PASSED] clipping_rotate_reflect
[10:23:44] [PASSED] positioning_simple
[10:23:44] [PASSED] upscaling
[10:23:44] [PASSED] downscaling
[10:23:44] [PASSED] rounding1
[10:23:44] [PASSED] rounding2
[10:23:44] [PASSED] rounding3
[10:23:44] [PASSED] rounding4
[10:23:44] =========== [PASSED] drm_test_check_plane_state ============
[10:23:44] =========== drm_test_check_invalid_plane_state  ============
[10:23:44] [PASSED] positioning_invalid
[10:23:44] [PASSED] upscaling_invalid
[10:23:44] [PASSED] downscaling_invalid
[10:23:44] ======= [PASSED] drm_test_check_invalid_plane_state ========
[10:23:44] ================ [PASSED] drm_plane_helper =================
[10:23:44] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[10:23:44] ====== drm_test_connector_helper_tv_get_modes_check  =======
[10:23:44] [PASSED] None
[10:23:44] [PASSED] PAL
[10:23:44] [PASSED] NTSC
[10:23:44] [PASSED] Both, NTSC Default
[10:23:44] [PASSED] Both, PAL Default
[10:23:44] [PASSED] Both, NTSC Default, with PAL on command-line
[10:23:44] [PASSED] Both, PAL Default, with NTSC on command-line
[10:23:44] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[10:23:44] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[10:23:44] ================== drm_rect (9 subtests) ===================
[10:23:44] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[10:23:44] [PASSED] drm_test_rect_clip_scaled_not_clipped
[10:23:44] [PASSED] drm_test_rect_clip_scaled_clipped
[10:23:44] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[10:23:44] ================= drm_test_rect_intersect  =================
[10:23:44] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[10:23:44] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[10:23:44] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[10:23:44] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[10:23:44] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[10:23:44] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[10:23:44] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[10:23:44] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[10:23:44] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[10:23:44] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[10:23:44] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[10:23:44] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[10:23:44] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[10:23:44] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[10:23:44] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[10:23:44] ============= [PASSED] drm_test_rect_intersect =============
[10:23:44] ================ drm_test_rect_calc_hscale  ================
[10:23:44] [PASSED] normal use
[10:23:44] [PASSED] out of max range
[10:23:44] [PASSED] out of min range
[10:23:44] [PASSED] zero dst
[10:23:44] [PASSED] negative src
[10:23:44] [PASSED] negative dst
[10:23:44] ============ [PASSED] drm_test_rect_calc_hscale ============
[10:23:44] ================ drm_test_rect_calc_vscale  ================
[10:23:44] [PASSED] normal use
[10:23:44] [PASSED] out of max range
[10:23:44] [PASSED] out of min range
[10:23:44] [PASSED] zero dst
[10:23:44] [PASSED] negative src
[10:23:44] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[10:23:44] ============ [PASSED] drm_test_rect_calc_vscale ============
[10:23:44] ================== drm_test_rect_rotate  ===================
[10:23:44] [PASSED] reflect-x
[10:23:44] [PASSED] reflect-y
[10:23:44] [PASSED] rotate-0
[10:23:44] [PASSED] rotate-90
[10:23:44] [PASSED] rotate-180
[10:23:44] [PASSED] rotate-270
[10:23:44] ============== [PASSED] drm_test_rect_rotate ===============
[10:23:44] ================ drm_test_rect_rotate_inv  =================
[10:23:44] [PASSED] reflect-x
[10:23:44] [PASSED] reflect-y
[10:23:44] [PASSED] rotate-0
[10:23:44] [PASSED] rotate-90
[10:23:44] [PASSED] rotate-180
[10:23:44] [PASSED] rotate-270
[10:23:44] ============ [PASSED] drm_test_rect_rotate_inv =============
[10:23:44] ==================== [PASSED] drm_rect =====================
[10:23:44] ============ drm_sysfb_modeset_test (1 subtest) ============
[10:23:44] ============ drm_test_sysfb_build_fourcc_list  =============
[10:23:44] [PASSED] no native formats
[10:23:44] [PASSED] XRGB8888 as native format
[10:23:44] [PASSED] remove duplicates
[10:23:44] [PASSED] convert alpha formats
[10:23:44] [PASSED] random formats
[10:23:44] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[10:23:44] ============= [PASSED] drm_sysfb_modeset_test ==============
[10:23:44] ================== drm_fixp (2 subtests) ===================
[10:23:44] [PASSED] drm_test_int2fixp
[10:23:44] [PASSED] drm_test_sm2fixp
[10:23:44] ==================== [PASSED] drm_fixp =====================
[10:23:44] ============================================================
[10:23:44] Testing complete. Ran 621 tests: passed: 621
[10:23:44] Elapsed time: 27.146s total, 1.581s configuring, 25.449s building, 0.110s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[10:23:44] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:23:46] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[10:23:55] Starting KUnit Kernel (1/1)...
[10:23:55] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:23:56] ================= ttm_device (5 subtests) ==================
[10:23:56] [PASSED] ttm_device_init_basic
[10:23:56] [PASSED] ttm_device_init_multiple
[10:23:56] [PASSED] ttm_device_fini_basic
[10:23:56] [PASSED] ttm_device_init_no_vma_man
[10:23:56] ================== ttm_device_init_pools  ==================
[10:23:56] [PASSED] No DMA allocations, no DMA32 required
[10:23:56] [PASSED] DMA allocations, DMA32 required
[10:23:56] [PASSED] No DMA allocations, DMA32 required
[10:23:56] [PASSED] DMA allocations, no DMA32 required
[10:23:56] ============== [PASSED] ttm_device_init_pools ==============
[10:23:56] =================== [PASSED] ttm_device ====================
[10:23:56] ================== ttm_pool (8 subtests) ===================
[10:23:56] ================== ttm_pool_alloc_basic  ===================
[10:23:56] [PASSED] One page
[10:23:56] [PASSED] More than one page
[10:23:56] [PASSED] Above the allocation limit
[10:23:56] [PASSED] One page, with coherent DMA mappings enabled
[10:23:56] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:23:56] ============== [PASSED] ttm_pool_alloc_basic ===============
[10:23:56] ============== ttm_pool_alloc_basic_dma_addr  ==============
[10:23:56] [PASSED] One page
[10:23:56] [PASSED] More than one page
[10:23:56] [PASSED] Above the allocation limit
[10:23:56] [PASSED] One page, with coherent DMA mappings enabled
[10:23:56] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:23:56] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[10:23:56] [PASSED] ttm_pool_alloc_order_caching_match
[10:23:56] [PASSED] ttm_pool_alloc_caching_mismatch
[10:23:56] [PASSED] ttm_pool_alloc_order_mismatch
[10:23:56] [PASSED] ttm_pool_free_dma_alloc
[10:23:56] [PASSED] ttm_pool_free_no_dma_alloc
[10:23:56] [PASSED] ttm_pool_fini_basic
[10:23:56] ==================== [PASSED] ttm_pool =====================
[10:23:56] ================ ttm_resource (8 subtests) =================
[10:23:56] ================= ttm_resource_init_basic  =================
[10:23:56] [PASSED] Init resource in TTM_PL_SYSTEM
[10:23:56] [PASSED] Init resource in TTM_PL_VRAM
[10:23:56] [PASSED] Init resource in a private placement
[10:23:56] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[10:23:56] ============= [PASSED] ttm_resource_init_basic =============
[10:23:56] [PASSED] ttm_resource_init_pinned
[10:23:56] [PASSED] ttm_resource_fini_basic
[10:23:56] [PASSED] ttm_resource_manager_init_basic
[10:23:56] [PASSED] ttm_resource_manager_usage_basic
[10:23:56] [PASSED] ttm_resource_manager_set_used_basic
[10:23:56] [PASSED] ttm_sys_man_alloc_basic
[10:23:56] [PASSED] ttm_sys_man_free_basic
[10:23:56] ================== [PASSED] ttm_resource ===================
[10:23:56] =================== ttm_tt (15 subtests) ===================
[10:23:56] ==================== ttm_tt_init_basic  ====================
[10:23:56] [PASSED] Page-aligned size
[10:23:56] [PASSED] Extra pages requested
[10:23:56] ================ [PASSED] ttm_tt_init_basic ================
[10:23:56] [PASSED] ttm_tt_init_misaligned
[10:23:56] [PASSED] ttm_tt_fini_basic
[10:23:56] [PASSED] ttm_tt_fini_sg
[10:23:56] [PASSED] ttm_tt_fini_shmem
[10:23:56] [PASSED] ttm_tt_create_basic
[10:23:56] [PASSED] ttm_tt_create_invalid_bo_type
[10:23:56] [PASSED] ttm_tt_create_ttm_exists
[10:23:56] [PASSED] ttm_tt_create_failed
[10:23:56] [PASSED] ttm_tt_destroy_basic
[10:23:56] [PASSED] ttm_tt_populate_null_ttm
[10:23:56] [PASSED] ttm_tt_populate_populated_ttm
[10:23:56] [PASSED] ttm_tt_unpopulate_basic
[10:23:56] [PASSED] ttm_tt_unpopulate_empty_ttm
[10:23:56] [PASSED] ttm_tt_swapin_basic
[10:23:56] ===================== [PASSED] ttm_tt ======================
[10:23:56] =================== ttm_bo (14 subtests) ===================
[10:23:56] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[10:23:56] [PASSED] Cannot be interrupted and sleeps
[10:23:56] [PASSED] Cannot be interrupted, locks straight away
[10:23:56] [PASSED] Can be interrupted, sleeps
[10:23:56] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[10:23:56] [PASSED] ttm_bo_reserve_locked_no_sleep
[10:23:56] [PASSED] ttm_bo_reserve_no_wait_ticket
[10:23:56] [PASSED] ttm_bo_reserve_double_resv
[10:23:56] [PASSED] ttm_bo_reserve_interrupted
[10:23:56] [PASSED] ttm_bo_reserve_deadlock
[10:23:56] [PASSED] ttm_bo_unreserve_basic
[10:23:56] [PASSED] ttm_bo_unreserve_pinned
[10:23:56] [PASSED] ttm_bo_unreserve_bulk
[10:23:56] [PASSED] ttm_bo_fini_basic
[10:23:56] [PASSED] ttm_bo_fini_shared_resv
[10:23:56] [PASSED] ttm_bo_pin_basic
[10:23:56] [PASSED] ttm_bo_pin_unpin_resource
[10:23:56] [PASSED] ttm_bo_multiple_pin_one_unpin
[10:23:56] ===================== [PASSED] ttm_bo ======================
[10:23:56] ============== ttm_bo_validate (21 subtests) ===============
[10:23:56] ============== ttm_bo_init_reserved_sys_man  ===============
[10:23:56] [PASSED] Buffer object for userspace
[10:23:56] [PASSED] Kernel buffer object
[10:23:56] [PASSED] Shared buffer object
[10:23:56] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[10:23:56] ============== ttm_bo_init_reserved_mock_man  ==============
[10:23:56] [PASSED] Buffer object for userspace
[10:23:56] [PASSED] Kernel buffer object
[10:23:56] [PASSED] Shared buffer object
[10:23:56] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[10:23:56] [PASSED] ttm_bo_init_reserved_resv
[10:23:56] ================== ttm_bo_validate_basic  ==================
[10:23:56] [PASSED] Buffer object for userspace
[10:23:56] [PASSED] Kernel buffer object
[10:23:56] [PASSED] Shared buffer object
[10:23:56] ============== [PASSED] ttm_bo_validate_basic ==============
[10:23:56] [PASSED] ttm_bo_validate_invalid_placement
[10:23:56] ============= ttm_bo_validate_same_placement  ==============
[10:23:56] [PASSED] System manager
[10:23:56] [PASSED] VRAM manager
[10:23:56] ========= [PASSED] ttm_bo_validate_same_placement ==========
[10:23:56] [PASSED] ttm_bo_validate_failed_alloc
[10:23:56] [PASSED] ttm_bo_validate_pinned
[10:23:56] [PASSED] ttm_bo_validate_busy_placement
[10:23:56] ================ ttm_bo_validate_multihop  =================
[10:23:56] [PASSED] Buffer object for userspace
[10:23:56] [PASSED] Kernel buffer object
[10:23:56] [PASSED] Shared buffer object
[10:23:56] ============ [PASSED] ttm_bo_validate_multihop =============
[10:23:56] ========== ttm_bo_validate_no_placement_signaled  ==========
[10:23:56] [PASSED] Buffer object in system domain, no page vector
[10:23:56] [PASSED] Buffer object in system domain with an existing page vector
[10:23:56] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[10:23:56] ======== ttm_bo_validate_no_placement_not_signaled  ========
[10:23:56] [PASSED] Buffer object for userspace
[10:23:56] [PASSED] Kernel buffer object
[10:23:56] [PASSED] Shared buffer object
[10:23:56] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[10:23:56] [PASSED] ttm_bo_validate_move_fence_signaled
[10:23:56] ========= ttm_bo_validate_move_fence_not_signaled  =========
[10:23:56] [PASSED] Waits for GPU
[10:23:56] [PASSED] Tries to lock straight away
[10:23:56] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[10:23:56] [PASSED] ttm_bo_validate_happy_evict
[10:23:56] [PASSED] ttm_bo_validate_all_pinned_evict
[10:23:56] [PASSED] ttm_bo_validate_allowed_only_evict
[10:23:56] [PASSED] ttm_bo_validate_deleted_evict
[10:23:56] [PASSED] ttm_bo_validate_busy_domain_evict
[10:23:56] [PASSED] ttm_bo_validate_evict_gutting
[10:23:56] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[10:23:56] ================= [PASSED] ttm_bo_validate =================
[10:23:56] ============================================================
[10:23:56] Testing complete. Ran 101 tests: passed: 101
[10:23:56] Elapsed time: 11.303s total, 1.687s configuring, 9.400s building, 0.186s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/xe/xe3p_lpg: L2 flush optimization (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 915 bytes --]

== Series Details ==

Series: drm/xe/xe3p_lpg: L2 flush optimization (rev4)
URL   : https://patchwork.freedesktop.org/series/158017/
State : success

== Summary ==

CI Bug Log - changes from xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120_BAT -> xe-pw-158017v4_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * IGT: IGT_8763 -> IGT_8764
  * Linux: xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120 -> xe-pw-158017v4

  IGT_8763: 8763
  IGT_8764: 8764
  xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120: 157c1f59af33fb9acf6e0e055e7317b634711120
  xe-pw-158017v4: 158017v4

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/index.html

[-- Attachment #2: Type: text/html, Size: 1477 bytes --]

✗ Xe.CI.FULL: failure for drm/xe/xe3p_lpg: L2 flush optimization (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 44363 bytes --]

== Series Details ==

Series: drm/xe/xe3p_lpg: L2 flush optimization (rev4)
URL   : https://patchwork.freedesktop.org/series/158017/
State : failure

== Summary ==

CI Bug Log - changes from xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120_FULL -> xe-pw-158017v4_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-158017v4_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-158017v4_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-158017v4_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_color@ctm-signed:
    - shard-bmg:          [PASS][1] -> [DMESG-WARN][2] +1 other test dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-bmg-2/igt@kms_color@ctm-signed.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-2/igt@kms_color@ctm-signed.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create:
    - shard-bmg:          NOTRUN -> [ABORT][3]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-5/igt@xe_fault_injection@exec-queue-create-fail-xe_exec_queue_create.html

  
Known issues
------------

  Here are the changes found in xe-pw-158017v4_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-linear:
    - shard-lnl:          [PASS][4] -> [FAIL][5] ([Intel XE#5993]) +3 other tests fail
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-lnl-8/igt@kms_async_flips@async-flip-with-page-flip-events-linear.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-8/igt@kms_async_flips@async-flip-with-page-flip-events-linear.html

  * igt@kms_async_flips@test-cursor:
    - shard-lnl:          NOTRUN -> [SKIP][6] ([Intel XE#664])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-1/igt@kms_async_flips@test-cursor.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2370])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-7/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#1407]) +2 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#3658])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][10] ([Intel XE#7059])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-2/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#7059])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-5/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#1124]) +4 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-4/igt@kms_big_fb@y-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-0:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#1124]) +7 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-2/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2328])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-9/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@y-tiled-addfb-size-overflow:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#1428])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-7/igt@kms_big_fb@y-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#1477])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-4/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2314] / [Intel XE#2894])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-4/igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#2191])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-8/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-3-displays-2560x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#367])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-3/igt@kms_bw@linear-tiling-3-displays-2560x1440p.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][20] ([Intel XE#2887]) +12 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-2/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2887]) +5 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-2/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][22] ([Intel XE#3432])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-4/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#3432]) +2 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-1:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2652]) +7 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-5/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-1.html

  * igt@kms_cdclk@mode-transition:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#2724])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-5/igt@kms_cdclk@mode-transition.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-lnl:          NOTRUN -> [SKIP][26] ([Intel XE#306])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-2/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_color@ctm-limited-range:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2325])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-4/igt@kms_chamelium_color@ctm-limited-range.html

  * igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2252]) +4 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-7/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html

  * igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode:
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#373]) +9 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-8/igt@kms_chamelium_hpd@vga-hpd-enable-disable-mode.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#3278]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-3/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@atomic-hdcp14:
    - shard-bmg:          NOTRUN -> [FAIL][31] ([Intel XE#3304]) +1 other test fail
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-4/igt@kms_content_protection@atomic-hdcp14.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#307] / [Intel XE#6974]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-3/igt@kms_content_protection@dp-mst-type-1.html
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#2390] / [Intel XE#6974])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-9/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@srm@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][34] ([Intel XE#1178] / [Intel XE#3304]) +2 other tests fail
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-1/igt@kms_content_protection@srm@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-offscreen-256x85:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#2320])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-2/igt@kms_cursor_crc@cursor-offscreen-256x85.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#2321]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-2/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-128x42:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#1424]) +2 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-2/igt@kms_cursor_crc@cursor-onscreen-128x42.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#2321]) +2 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-8/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#309]) +6 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-5/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#4354])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-3/igt@kms_dp_link_training@non-uhbr-mst.html
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#4354])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-9/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#4331])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-8/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#2244])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-8/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#4422])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-7/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html

  * igt@kms_feature_discovery@chamelium:
    - shard-lnl:          NOTRUN -> [SKIP][45] ([Intel XE#701])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-4/igt@kms_feature_discovery@chamelium.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#1421]) +4 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-3/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
    - shard-bmg:          [PASS][47] -> [FAIL][48] ([Intel XE#3098]) +1 other test fail
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-bmg-1/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-4/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#7178]) +2 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#7178]) +3 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html

  * igt@kms_force_connector_basic@force-edid:
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#352])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-7/igt@kms_force_connector_basic@force-edid.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#651]) +7 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-3/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#2311]) +19 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#4141]) +9 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#656]) +33 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#7061]) +6 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-1/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#6312]) +1 other test skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-argb161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#7061]) +1 other test skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcpsr-argb161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#2313]) +15 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][60] -> [SKIP][61] ([Intel XE#1503])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-bmg-1/igt@kms_hdr@invalid-hdr.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-6/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@static-toggle:
    - shard-lnl:          NOTRUN -> [SKIP][62] ([Intel XE#1503])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-4/igt@kms_hdr@static-toggle.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#2501])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier:
    - shard-lnl:          NOTRUN -> [SKIP][64] ([Intel XE#7283]) +2 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-1/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][65] ([Intel XE#7283]) +3 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-3/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#2393])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-2/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#2763] / [Intel XE#6886]) +7 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-3/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-bmg:          NOTRUN -> [SKIP][68] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836]) +1 other test skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-8/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@package-g7:
    - shard-bmg:          NOTRUN -> [SKIP][69] ([Intel XE#6814])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-6/igt@kms_pm_rpm@package-g7.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#1406] / [Intel XE#2893] / [Intel XE#4608]) +2 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-5/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][71] ([Intel XE#1406] / [Intel XE#4608]) +5 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-5/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area@pipe-a-edp-1.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
    - shard-lnl:          NOTRUN -> [SKIP][72] ([Intel XE#1406] / [Intel XE#2893]) +1 other test skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-5/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#1406] / [Intel XE#1489]) +3 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-5/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr@fbc-psr2-sprite-plane-move:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#1406]) +3 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-7/igt@kms_psr@fbc-psr2-sprite-plane-move.html

  * igt@kms_psr@fbc-psr2-sprite-plane-move@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][75] ([Intel XE#1406] / [Intel XE#4609])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-7/igt@kms_psr@fbc-psr2-sprite-plane-move@edp-1.html

  * igt@kms_psr@psr2-no-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +10 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-5/igt@kms_psr@psr2-no-drrs.html

  * igt@kms_rotation_crc@sprite-rotation-270:
    - shard-bmg:          NOTRUN -> [SKIP][77] ([Intel XE#3414] / [Intel XE#3904])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-9/igt@kms_rotation_crc@sprite-rotation-270.html

  * igt@kms_setmode@invalid-clone-exclusive-crtc:
    - shard-bmg:          NOTRUN -> [SKIP][78] ([Intel XE#1435])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-6/igt@kms_setmode@invalid-clone-exclusive-crtc.html

  * igt@kms_sharpness_filter@invalid-filter-with-plane:
    - shard-bmg:          NOTRUN -> [SKIP][79] ([Intel XE#6503]) +2 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-2/igt@kms_sharpness_filter@invalid-filter-with-plane.html

  * igt@kms_vrr@lobf:
    - shard-bmg:          NOTRUN -> [SKIP][80] ([Intel XE#2168])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-8/igt@kms_vrr@lobf.html

  * igt@xe_compute@eu-busy-10s:
    - shard-bmg:          NOTRUN -> [SKIP][81] ([Intel XE#6599])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-2/igt@xe_compute@eu-busy-10s.html

  * igt@xe_create@multigpu-create-massive-size:
    - shard-bmg:          NOTRUN -> [SKIP][82] ([Intel XE#2504])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-6/igt@xe_create@multigpu-create-massive-size.html

  * igt@xe_eudebug@basic-vm-access-parameters:
    - shard-bmg:          NOTRUN -> [SKIP][83] ([Intel XE#4837]) +2 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-8/igt@xe_eudebug@basic-vm-access-parameters.html

  * igt@xe_eudebug@read-metadata:
    - shard-lnl:          NOTRUN -> [SKIP][84] ([Intel XE#4837]) +6 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-4/igt@xe_eudebug@read-metadata.html

  * igt@xe_eudebug_online@breakpoint-many-sessions-single-tile:
    - shard-bmg:          NOTRUN -> [SKIP][85] ([Intel XE#4837] / [Intel XE#6665]) +4 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-1/igt@xe_eudebug_online@breakpoint-many-sessions-single-tile.html

  * igt@xe_eudebug_online@debugger-reopen:
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#4837] / [Intel XE#6665]) +3 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-8/igt@xe_eudebug_online@debugger-reopen.html

  * igt@xe_eudebug_online@pagefault-read-stress:
    - shard-lnl:          NOTRUN -> [SKIP][87] ([Intel XE#6665])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-5/igt@xe_eudebug_online@pagefault-read-stress.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [PASS][88] -> [INCOMPLETE][89] ([Intel XE#6321])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-bmg-5/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-9/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_evict_ccs@evict-overcommit-parallel-nofree-samefd:
    - shard-lnl:          NOTRUN -> [SKIP][90] ([Intel XE#6540] / [Intel XE#688]) +7 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-3/igt@xe_evict_ccs@evict-overcommit-parallel-nofree-samefd.html

  * igt@xe_exec_basic@many-execqueues-null-rebind:
    - shard-bmg:          [PASS][91] -> [INCOMPLETE][92] ([Intel XE#2594])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-bmg-4/igt@xe_exec_basic@many-execqueues-null-rebind.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-3/igt@xe_exec_basic@many-execqueues-null-rebind.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][93] ([Intel XE#2322]) +4 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-1/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate.html

  * igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap:
    - shard-lnl:          NOTRUN -> [SKIP][94] ([Intel XE#1392]) +7 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-3/igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap.html

  * igt@xe_exec_fault_mode@many-multi-queue-userptr-rebind-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][95] ([Intel XE#7136]) +3 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-4/igt@xe_exec_fault_mode@many-multi-queue-userptr-rebind-prefetch.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm:
    - shard-lnl:          NOTRUN -> [SKIP][96] ([Intel XE#7136]) +10 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-1/igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm.html

  * igt@xe_exec_multi_queue@many-execs-basic-smem:
    - shard-bmg:          NOTRUN -> [SKIP][97] ([Intel XE#6874]) +12 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-6/igt@xe_exec_multi_queue@many-execs-basic-smem.html

  * igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-basic-smem:
    - shard-lnl:          NOTRUN -> [SKIP][98] ([Intel XE#6874]) +22 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-4/igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-basic-smem.html

  * igt@xe_exec_threads@threads-multi-queue-fd-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][99] ([Intel XE#7138]) +4 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-fd-userptr-invalidate-race.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][100] ([Intel XE#7138]) +5 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-2/igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-userptr-invalidate-race.html

  * igt@xe_mmap@pci-membarrier:
    - shard-lnl:          NOTRUN -> [SKIP][101] ([Intel XE#5100])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-4/igt@xe_mmap@pci-membarrier.html

  * igt@xe_multigpu_svm@mgpu-atomic-op-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][102] ([Intel XE#6964]) +1 other test skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-4/igt@xe_multigpu_svm@mgpu-atomic-op-prefetch.html

  * igt@xe_multigpu_svm@mgpu-concurrent-access-basic:
    - shard-bmg:          NOTRUN -> [SKIP][103] ([Intel XE#6964])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-9/igt@xe_multigpu_svm@mgpu-concurrent-access-basic.html

  * igt@xe_pat@pat-index-xelp:
    - shard-lnl:          NOTRUN -> [SKIP][104] ([Intel XE#977])
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-4/igt@xe_pat@pat-index-xelp.html
    - shard-bmg:          NOTRUN -> [SKIP][105] ([Intel XE#2245])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-2/igt@xe_pat@pat-index-xelp.html

  * igt@xe_pm@d3cold-multiple-execs:
    - shard-bmg:          NOTRUN -> [SKIP][106] ([Intel XE#2284]) +1 other test skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-7/igt@xe_pm@d3cold-multiple-execs.html

  * igt@xe_pm@s2idle-d3cold-basic-exec:
    - shard-lnl:          NOTRUN -> [SKIP][107] ([Intel XE#2284] / [Intel XE#366])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-8/igt@xe_pm@s2idle-d3cold-basic-exec.html

  * igt@xe_pm@s3-vm-bind-unbind-all:
    - shard-lnl:          NOTRUN -> [SKIP][108] ([Intel XE#584])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-2/igt@xe_pm@s3-vm-bind-unbind-all.html

  * igt@xe_pxp@pxp-termination-key-update-post-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][109] ([Intel XE#4733]) +2 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-6/igt@xe_pxp@pxp-termination-key-update-post-suspend.html

  * igt@xe_query@multigpu-query-cs-cycles:
    - shard-lnl:          NOTRUN -> [SKIP][110] ([Intel XE#944])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-5/igt@xe_query@multigpu-query-cs-cycles.html

  * igt@xe_sriov_admin@bulk-exec-quantum-vfs-disabled:
    - shard-lnl:          NOTRUN -> [SKIP][111] ([Intel XE#7174]) +1 other test skip
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-3/igt@xe_sriov_admin@bulk-exec-quantum-vfs-disabled.html

  * igt@xe_sriov_auto_provisioning@exclusive-ranges@numvfs-random:
    - shard-bmg:          [PASS][112] -> [FAIL][113] ([Intel XE#5937]) +1 other test fail
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-bmg-6/igt@xe_sriov_auto_provisioning@exclusive-ranges@numvfs-random.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-2/igt@xe_sriov_auto_provisioning@exclusive-ranges@numvfs-random.html

  * igt@xe_sriov_flr@flr-vf1-clear:
    - shard-lnl:          NOTRUN -> [SKIP][114] ([Intel XE#3342])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-5/igt@xe_sriov_flr@flr-vf1-clear.html

  * igt@xe_waitfence@abstime:
    - shard-bmg:          [PASS][115] -> [TIMEOUT][116] ([Intel XE#6506])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-bmg-3/igt@xe_waitfence@abstime.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-3/igt@xe_waitfence@abstime.html

  
#### Possible fixes ####

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [INCOMPLETE][117] ([Intel XE#7084]) -> [PASS][118]
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-bmg-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-hdmi-a-3:
    - shard-bmg:          [INCOMPLETE][119] -> [PASS][120]
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-bmg-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-hdmi-a-3.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-hdmi-a-3.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [FAIL][121] ([Intel XE#6715]) -> [PASS][122]
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-bmg-9/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][123] ([Intel XE#5299]) -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][125] ([Intel XE#301]) -> [PASS][126] +1 other test pass
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-bmg:          [INCOMPLETE][127] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][128] +1 other test pass
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-bmg-9/igt@kms_flip@flip-vs-suspend-interruptible.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-9/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [FAIL][129] ([Intel XE#2142]) -> [PASS][130] +1 other test pass
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-lnl-7/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-lnl-8/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  * igt@xe_exec_threads@threads-bal-mixed-fd-userptr:
    - shard-bmg:          [FAIL][131] ([Intel XE#5625]) -> [PASS][132]
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-bmg-5/igt@xe_exec_threads@threads-bal-mixed-fd-userptr.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-7/igt@xe_exec_threads@threads-bal-mixed-fd-userptr.html

  
#### Warnings ####

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][133] ([Intel XE#3544]) -> [SKIP][134] ([Intel XE#3374] / [Intel XE#3544])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-7/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][135] ([Intel XE#2426]) -> [SKIP][136] ([Intel XE#2509])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-bmg:          [ABORT][137] ([Intel XE#5466] / [Intel XE#6652]) -> [ABORT][138] ([Intel XE#5466])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120/shard-bmg-2/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/shard-bmg-1/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1428
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1477]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1477
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
  [Intel XE#2370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2370
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2501]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2501
  [Intel XE#2504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2504
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2594
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3278]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3278
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/352
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5937
  [Intel XE#5993]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5993
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6506]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6506
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6599
  [Intel XE#664]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/664
  [Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6715]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6715
  [Intel XE#6814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6814
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7174
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977


Build changes
-------------

  * IGT: IGT_8763 -> IGT_8764
  * Linux: xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120 -> xe-pw-158017v4

  IGT_8763: 8763
  IGT_8764: 8764
  xe-4577-157c1f59af33fb9acf6e0e055e7317b634711120: 157c1f59af33fb9acf6e0e055e7317b634711120
  xe-pw-158017v4: 158017v4

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158017v4/index.html

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