[v4 00/20] Make Display free from i915_reg.h

[v4 00/20] Make Display free from i915_reg.h

[Uma Shankar]

Move the common register definition to per feature header
which makes display files free from including i915_reg.h.
This will help avoid dupicate definitions and includes and can
serve as a common file for xe, i915 and display module.

v4:
- Add granular include instead of putting in common header (Jani)
- Drop redundant includes (Jani)
- Create oprom_regs header (Ville)
- Other minor fixes based on review comments from Jani and Ville

v3:
- Create per feature modular headers instead of 1 common header (Jani)
- Commit message and header fixes (Jani)

v2:
- Moved display definitions needed for gvt and clock gating
  to display header (Jani)
- Fixed redundant includes

Uma Shankar (20):
  drm/i915: Extract display registers from i915_reg.h to display
  drm/i915: Extract South chicken registers from i915_reg.h to display
  drm/i915: Extract display interrupt definitions
  drm/i915: Extract DSPCLK_GATE_D from i915_reg to display
  drm/{i915, xe}: Extract pcode definitions to common header
  drm/i915: Remove i915_reg.h from intel_display_device.c
  drm/i915: Move GMD_ID and mask to intel_gt header
  drm/i915: Remove i915_reg.h from intel_dram.c
  drm/i915: Remove i915_reg.h from intel_display.c
  drm/i915: Remove i915_reg.h from intel_overlay.c
  drm/i915: Remove i915_reg.h from g4x_dp.c
  drm/i915: Remove i915_reg.h from i9xx_wm.c
  drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c
  drm/i915: Remove i915_reg.h from intel_rom.c
  drm/i915: Remove i915_reg.h from intel_psr.c
  drm/i915: Remove i915_reg.h from intel_fifo_underrun.c
  drm/i915: Remove i915_reg.h from intel_display_irq.c
  drm/i915: Remove i915_reg.h from intel_display_power_well.c
  drm/i915: Remove i915_reg.h from intel_modeset_setup.c
  drm/{i915, xe}: Remove i915_reg.h from display

 drivers/gpu/drm/i915/display/g4x_dp.c         |   1 -
 drivers/gpu/drm/i915/display/g4x_hdmi.c       |   1 -
 drivers/gpu/drm/i915/display/hsw_ips.c        |   2 +-
 drivers/gpu/drm/i915/display/i9xx_plane.c     |   1 -
 drivers/gpu/drm/i915/display/i9xx_wm.c        |   2 +-
 drivers/gpu/drm/i915/display/icl_dsi.c        |   1 -
 .../gpu/drm/i915/display/intel_backlight.c    |   1 -
 drivers/gpu/drm/i915/display/intel_bw.c       |   2 +-
 drivers/gpu/drm/i915/display/intel_casf.c     |   1 -
 drivers/gpu/drm/i915/display/intel_cdclk.c    |   2 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |   1 -
 drivers/gpu/drm/i915/display/intel_display.c  |   1 -
 .../drm/i915/display/intel_display_debugfs.c  |   2 +-
 .../drm/i915/display/intel_display_device.c   |   7 +-
 .../gpu/drm/i915/display/intel_display_irq.c  |   2 +-
 .../drm/i915/display/intel_display_power.c    |   2 +-
 .../i915/display/intel_display_power_well.c   |   4 +-
 .../gpu/drm/i915/display/intel_display_regs.h | 263 +++++++++-
 .../gpu/drm/i915/display/intel_display_rps.c  |   2 +-
 .../gpu/drm/i915/display/intel_display_wa.c   |   1 -
 drivers/gpu/drm/i915/display/intel_dmc.c      |   1 -
 drivers/gpu/drm/i915/display/intel_dram.c     |   3 +-
 drivers/gpu/drm/i915/display/intel_fdi.c      |   1 -
 .../drm/i915/display/intel_fifo_underrun.c    |   1 -
 drivers/gpu/drm/i915/display/intel_gmbus.c    |   1 -
 drivers/gpu/drm/i915/display/intel_hdcp.c     |   2 +-
 .../gpu/drm/i915/display/intel_hotplug_irq.c  |   1 -
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |   1 -
 .../drm/i915/display/intel_modeset_setup.c    |   1 -
 .../gpu/drm/i915/display/intel_oprom_regs.h   |  36 ++
 drivers/gpu/drm/i915/display/intel_overlay.c  |   2 +-
 .../gpu/drm/i915/display/intel_pch_display.c  |   1 -
 .../gpu/drm/i915/display/intel_pch_refclk.c   |   1 -
 drivers/gpu/drm/i915/display/intel_pps.c      |   1 -
 drivers/gpu/drm/i915/display/intel_psr.c      |   1 -
 drivers/gpu/drm/i915/display/intel_rom.c      |   3 +-
 drivers/gpu/drm/i915/display/intel_tc.c       |   1 -
 drivers/gpu/drm/i915/display/skl_watermark.c  |   2 +-
 drivers/gpu/drm/i915/display/vlv_dsi.c        |   1 -
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c  |   1 +
 drivers/gpu/drm/i915/gt/intel_gt.c            |   1 +
 drivers/gpu/drm/i915/gt/intel_gt_irq.c        |   2 +
 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c |   1 +
 drivers/gpu/drm/i915/gt/intel_gt_regs.h       |   3 +
 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c   |   2 +
 drivers/gpu/drm/i915/gt/intel_llc.c           |   2 +
 drivers/gpu/drm/i915/gt/intel_rc6.c           |   2 +
 .../gpu/drm/i915/gt/intel_ring_submission.c   |   2 +
 drivers/gpu/drm/i915/gt/intel_rps.c           |   1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |   2 +
 drivers/gpu/drm/i915/gvt/cmd_parser.c         |   1 +
 drivers/gpu/drm/i915/gvt/handlers.c           |   2 +
 drivers/gpu/drm/i915/gvt/interrupt.c          |   1 +
 drivers/gpu/drm/i915/gvt/mmio_context.c       |   1 +
 drivers/gpu/drm/i915/i915_debugfs.c           |   1 +
 drivers/gpu/drm/i915/i915_driver.c            |   1 +
 drivers/gpu/drm/i915/i915_hwmon.c             |   2 +
 drivers/gpu/drm/i915/i915_irq.c               |   1 +
 drivers/gpu/drm/i915/i915_reg.h               | 464 ------------------
 drivers/gpu/drm/i915/intel_clock_gating.c     |   4 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |   5 +
 drivers/gpu/drm/i915/intel_pcode.c            |   1 +
 drivers/gpu/drm/i915/vlv_suspend.c            |   1 +
 include/drm/intel/intel_gmd_interrupt_regs.h  |  92 ++++
 include/drm/intel/intel_gmd_misc_regs.h       |  21 +
 include/drm/intel/intel_pcode_regs.h          | 108 ++++
 66 files changed, 577 insertions(+), 508 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_oprom_regs.h
 create mode 100644 include/drm/intel/intel_gmd_interrupt_regs.h
 create mode 100644 include/drm/intel/intel_gmd_misc_regs.h
 create mode 100644 include/drm/intel/intel_pcode_regs.h

-- 
2.50.1

[v4 01/20] drm/i915: Extract display registers from i915_reg.h to display

[Uma Shankar]

There are certain register definitions which are defined in i915_reg.h
which are exclusively needed by display. Move the same to display
headers to remove i915_reg.h includes from display. This is a step
towards making display independent of i915.

intel_clock_gating.c can include display header directly, since its
usage is planned to be re-factored and will be moved within display.

v3: Updated subject and commit message (Jani)

v2: Drop common header in include and use display_regs.h (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_regs.h | 10 ++++++++++
 drivers/gpu/drm/i915/display/intel_pch_display.c  |  1 -
 drivers/gpu/drm/i915/i915_reg.h                   | 10 ----------
 drivers/gpu/drm/i915/intel_clock_gating.c         |  2 +-
 4 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9740f32ced24..a9bbd20c27ec 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2021,6 +2021,16 @@
 #define  TRANS_BPC_6			REG_FIELD_PREP(TRANS_BPC_MASK, 2)
 #define  TRANS_BPC_12			REG_FIELD_PREP(TRANS_BPC_MASK, 3)
 
+#define _TRANSA_CHICKEN2	0xf0064
+#define _TRANSB_CHICKEN2	0xf1064
+#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
+#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)
+#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED		REG_BIT(29)
+#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK		REG_GENMASK(28, 27)
+#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
+#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	REG_BIT(26)
+#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	REG_BIT(25)
+
 #define PCH_DP_B		_MMIO(0xe4100)
 #define PCH_DP_C		_MMIO(0xe4200)
 #define PCH_DP_D		_MMIO(0xe4300)
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 16619f7be5f8..69c7952a1413 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -6,7 +6,6 @@
 #include <drm/drm_print.h>
 
 #include "g4x_dp.h"
-#include "i915_reg.h"
 #include "intel_crt.h"
 #include "intel_crt_regs.h"
 #include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f928db78a3fa..f65f50bf44ba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1023,16 +1023,6 @@
 #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
 #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
 
-#define _TRANSA_CHICKEN2	 0xf0064
-#define _TRANSB_CHICKEN2	 0xf1064
-#define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
-#define   TRANS_CHICKEN2_TIMING_OVERRIDE		REG_BIT(31)
-#define   TRANS_CHICKEN2_FDI_POLARITY_REVERSED		REG_BIT(29)
-#define   TRANS_CHICKEN2_FRAME_START_DELAY_MASK		REG_GENMASK(28, 27)
-#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
-#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER	REG_BIT(26)
-#define   TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH	REG_BIT(25)
-
 #define SOUTH_CHICKEN1		_MMIO(0xc2000)
 #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
 #define  FDIA_PHASE_SYNC_SHIFT_EN	18
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 7336934bb934..4e18d5a22112 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -30,7 +30,7 @@
 #include "display/i9xx_plane_regs.h"
 #include "display/intel_display.h"
 #include "display/intel_display_core.h"
-
+#include "display/intel_display_regs.h"
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_mcr.h"
-- 
2.50.1

[v4 02/20] drm/i915: Extract South chicken registers from i915_reg.h to display

[Uma Shankar]

Extract South Chicken registers from i915_reg.h to display header.
This allows intel_pch_refclk.c not to include i915_reg.h

v3: Drop whitespace changes, commit header updated (Jani)

v2: Drop common header in include and use display_regs.h (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_display_regs.h | 27 +++++++++++++++++++
 .../gpu/drm/i915/display/intel_pch_refclk.c   |  1 -
 drivers/gpu/drm/i915/i915_reg.h               | 27 -------------------
 3 files changed, 27 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index a9bbd20c27ec..cf02e567cf99 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2871,6 +2871,33 @@ enum skl_power_gate {
 #define  SFUSE_STRAP_DDIC_DETECTED	(1 << 1)
 #define  SFUSE_STRAP_DDID_DETECTED	(1 << 0)
 
+#define SOUTH_CHICKEN1		_MMIO(0xc2000)
+#define  FDIA_PHASE_SYNC_SHIFT_OVR	19
+#define  FDIA_PHASE_SYNC_SHIFT_EN	18
+#define  INVERT_DDIE_HPD			REG_BIT(28)
+#define  INVERT_DDID_HPD_MTP			REG_BIT(27)
+#define  INVERT_TC4_HPD				REG_BIT(26)
+#define  INVERT_TC3_HPD				REG_BIT(25)
+#define  INVERT_TC2_HPD				REG_BIT(24)
+#define  INVERT_TC1_HPD				REG_BIT(23)
+#define  INVERT_DDID_HPD			(1 << 18)
+#define  INVERT_DDIC_HPD			(1 << 17)
+#define  INVERT_DDIB_HPD			(1 << 16)
+#define  INVERT_DDIA_HPD			(1 << 15)
+#define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
+#define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
+#define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
+#define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
+#define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)
+#define  SBCLK_RUN_REFCLK_DIS		(1 << 7)
+#define  ICP_SECOND_PPS_IO_SELECT	REG_BIT(2)
+#define  SPT_PWM_GRANULARITY		(1 << 0)
+#define SOUTH_CHICKEN2		_MMIO(0xc2004)
+#define  FDI_MPHY_IOSFSB_RESET_STATUS	(1 << 13)
+#define  FDI_MPHY_IOSFSB_RESET_CTL	(1 << 12)
+#define  LPT_PWM_GRANULARITY		(1 << 5)
+#define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
+
 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
 #define GEN4_TIMESTAMP		_MMIO(0x2358)
 #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 9a89bb6dcf65..5f88663ef5e8 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -5,7 +5,6 @@
 
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f65f50bf44ba..c2efa50f080d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1023,33 +1023,6 @@
 #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
 #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
 
-#define SOUTH_CHICKEN1		_MMIO(0xc2000)
-#define  FDIA_PHASE_SYNC_SHIFT_OVR	19
-#define  FDIA_PHASE_SYNC_SHIFT_EN	18
-#define  INVERT_DDIE_HPD			REG_BIT(28)
-#define  INVERT_DDID_HPD_MTP			REG_BIT(27)
-#define  INVERT_TC4_HPD				REG_BIT(26)
-#define  INVERT_TC3_HPD				REG_BIT(25)
-#define  INVERT_TC2_HPD				REG_BIT(24)
-#define  INVERT_TC1_HPD				REG_BIT(23)
-#define  INVERT_DDID_HPD			(1 << 18)
-#define  INVERT_DDIC_HPD			(1 << 17)
-#define  INVERT_DDIB_HPD			(1 << 16)
-#define  INVERT_DDIA_HPD			(1 << 15)
-#define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
-#define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
-#define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
-#define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
-#define  CHASSIS_CLK_REQ_DURATION(x)	((x) << 8)
-#define  SBCLK_RUN_REFCLK_DIS		(1 << 7)
-#define  ICP_SECOND_PPS_IO_SELECT	REG_BIT(2)
-#define  SPT_PWM_GRANULARITY		(1 << 0)
-#define SOUTH_CHICKEN2		_MMIO(0xc2004)
-#define  FDI_MPHY_IOSFSB_RESET_STATUS	(1 << 13)
-#define  FDI_MPHY_IOSFSB_RESET_CTL	(1 << 12)
-#define  LPT_PWM_GRANULARITY		(1 << 5)
-#define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
-
 #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
 #define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
 #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
-- 
2.50.1

[v4 03/20] drm/i915: Extract display interrupt definitions

[Uma Shankar]

Extract DE Interrupt registers from i915_reg.h to display header.
This allows intel_display_rps.c not to include i915_reg.h

v2: Update commit message (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_display_regs.h | 33 +++++++++++++++++++
 .../gpu/drm/i915/display/intel_display_rps.c  |  2 +-
 drivers/gpu/drm/i915/i915_reg.h               | 33 -------------------
 3 files changed, 34 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index cf02e567cf99..add9cae3ea30 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1333,6 +1333,39 @@
 						      GEN8_DE_PORT_IER, \
 						      GEN8_DE_PORT_IIR)
 
+/* interrupts */
+#define DE_MASTER_IRQ_CONTROL   (1 << 31)
+#define DE_SPRITEB_FLIP_DONE    (1 << 29)
+#define DE_SPRITEA_FLIP_DONE    (1 << 28)
+#define DE_PLANEB_FLIP_DONE     (1 << 27)
+#define DE_PLANEA_FLIP_DONE     (1 << 26)
+#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
+#define DE_PCU_EVENT            (1 << 25)
+#define DE_GTT_FAULT            (1 << 24)
+#define DE_POISON               (1 << 23)
+#define DE_PERFORM_COUNTER      (1 << 22)
+#define DE_PCH_EVENT            (1 << 21)
+#define DE_AUX_CHANNEL_A        (1 << 20)
+#define DE_DP_A_HOTPLUG         (1 << 19)
+#define DE_GSE                  (1 << 18)
+#define DE_PIPEB_VBLANK         (1 << 15)
+#define DE_PIPEB_EVEN_FIELD     (1 << 14)
+#define DE_PIPEB_ODD_FIELD      (1 << 13)
+#define DE_PIPEB_LINE_COMPARE   (1 << 12)
+#define DE_PIPEB_VSYNC          (1 << 11)
+#define DE_PIPEB_CRC_DONE	(1 << 10)
+#define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
+#define DE_PIPEA_VBLANK         (1 << 7)
+#define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8 * (pipe)))
+#define DE_PIPEA_EVEN_FIELD     (1 << 6)
+#define DE_PIPEA_ODD_FIELD      (1 << 5)
+#define DE_PIPEA_LINE_COMPARE   (1 << 4)
+#define DE_PIPEA_VSYNC          (1 << 3)
+#define DE_PIPEA_CRC_DONE	(1 << 2)
+#define DE_PIPE_CRC_DONE(pipe)	(1 << (2 + 8 * (pipe)))
+#define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
+#define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
+
 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
diff --git a/drivers/gpu/drm/i915/display/intel_display_rps.c b/drivers/gpu/drm/i915/display/intel_display_rps.c
index e77811396474..bf00266dae4b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_rps.c
+++ b/drivers/gpu/drm/i915/display/intel_display_rps.c
@@ -8,8 +8,8 @@
 #include <drm/drm_crtc.h>
 #include <drm/drm_vblank.h>
 
-#include "i915_reg.h"
 #include "intel_display_core.h"
+#include "intel_display_regs.h"
 #include "intel_display_irq.h"
 #include "intel_display_rps.h"
 #include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2efa50f080d..3f4203a69bcd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -805,39 +805,6 @@
 #define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
 #define  MMIO_TIMEOUT_US(us)	((us) << 0)
 
-/* interrupts */
-#define DE_MASTER_IRQ_CONTROL   (1 << 31)
-#define DE_SPRITEB_FLIP_DONE    (1 << 29)
-#define DE_SPRITEA_FLIP_DONE    (1 << 28)
-#define DE_PLANEB_FLIP_DONE     (1 << 27)
-#define DE_PLANEA_FLIP_DONE     (1 << 26)
-#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
-#define DE_PCU_EVENT            (1 << 25)
-#define DE_GTT_FAULT            (1 << 24)
-#define DE_POISON               (1 << 23)
-#define DE_PERFORM_COUNTER      (1 << 22)
-#define DE_PCH_EVENT            (1 << 21)
-#define DE_AUX_CHANNEL_A        (1 << 20)
-#define DE_DP_A_HOTPLUG         (1 << 19)
-#define DE_GSE                  (1 << 18)
-#define DE_PIPEB_VBLANK         (1 << 15)
-#define DE_PIPEB_EVEN_FIELD     (1 << 14)
-#define DE_PIPEB_ODD_FIELD      (1 << 13)
-#define DE_PIPEB_LINE_COMPARE   (1 << 12)
-#define DE_PIPEB_VSYNC          (1 << 11)
-#define DE_PIPEB_CRC_DONE	(1 << 10)
-#define DE_PIPEB_FIFO_UNDERRUN  (1 << 8)
-#define DE_PIPEA_VBLANK         (1 << 7)
-#define DE_PIPE_VBLANK(pipe)    (1 << (7 + 8 * (pipe)))
-#define DE_PIPEA_EVEN_FIELD     (1 << 6)
-#define DE_PIPEA_ODD_FIELD      (1 << 5)
-#define DE_PIPEA_LINE_COMPARE   (1 << 4)
-#define DE_PIPEA_VSYNC          (1 << 3)
-#define DE_PIPEA_CRC_DONE	(1 << 2)
-#define DE_PIPE_CRC_DONE(pipe)	(1 << (2 + 8 * (pipe)))
-#define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
-#define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
-
 #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
 #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
 
-- 
2.50.1

[v4 04/20] drm/i915: Extract DSPCLK_GATE_D from i915_reg to display

[Uma Shankar]

Move DSPCLK_GATE_D register definition to display header.
This allows intel_gmbus.c not to include i915_reg.h.

v3: Update commit header and message (Jani)

v2: Drop common header in include and use display_regs.h (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_display_regs.h | 50 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_gmbus.c    |  1 -
 drivers/gpu/drm/i915/i915_reg.h               | 50 -------------------
 3 files changed, 50 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index add9cae3ea30..ab184670c845 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -160,6 +160,47 @@
 
 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
 
+#define DSPCLK_GATE_D			_MMIO(0x6200)
+#define VLV_DSPCLK_GATE_D		_MMIO(VLV_DISPLAY_BASE + 0x6200)
+# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
+# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
+# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
+# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
+# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
+# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
+# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
+# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */
+# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
+# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
+# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
+# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
+# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
+# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
+# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
+# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
+# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
+# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
+# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
+# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
+# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
+# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
+# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
+# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
+# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
+# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
+# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
+# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
+# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
+/*
+ * This bit must be set on the 830 to prevent hangs when turning off the
+ * overlay scaler.
+ */
+# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
+# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
+# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
+# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
+# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
+
 /* Additional CHV pll/phy registers */
 #define DPIO_PHY_STATUS			_MMIO(VLV_DISPLAY_BASE + 0x6240)
 #define   DPLL_PORTD_READY_MASK		(0xf)
@@ -2931,6 +2972,15 @@ enum skl_power_gate {
 #define  LPT_PWM_GRANULARITY		(1 << 5)
 #define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
 
+#define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
+#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
+#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
+#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
+#define  PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
+#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
+#define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
+#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
+
 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
 #define GEN4_TIMESTAMP		_MMIO(0x2358)
 #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 2caff677600c..81b6c6991323 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -35,7 +35,6 @@
 #include <drm/drm_print.h>
 #include <drm/display/drm_hdcp_helper.h>
 
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f4203a69bcd..26e5504dbc67 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -613,47 +613,6 @@
 #define  DSTATE_GFX_CLOCK_GATING		(1 << 1)
 #define  DSTATE_DOT_CLOCK_GATING		(1 << 0)
 
-#define DSPCLK_GATE_D			_MMIO(0x6200)
-#define VLV_DSPCLK_GATE_D		_MMIO(VLV_DISPLAY_BASE + 0x6200)
-# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
-# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
-# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
-# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
-# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
-# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
-# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
-# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */
-# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
-# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
-# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
-# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
-# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
-# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
-# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
-# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
-# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
-# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
-# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
-# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
-# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
-# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
-# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
-# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
-# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
-# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
-# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
-# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
-# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
-/*
- * This bit must be set on the 830 to prevent hangs when turning off the
- * overlay scaler.
- */
-# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
-# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
-# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
-# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
-# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
-
 #define RENCLK_GATE_D1		_MMIO(0x6204)
 # define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
 # define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
@@ -990,15 +949,6 @@
 #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
 #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
 
-#define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
-#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
-#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
-#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
-#define  PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
-#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
-#define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
-#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
-
 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
 
 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
-- 
2.50.1

[v4 05/20] drm/{i915, xe}: Extract pcode definitions to common header

[Uma Shankar]

There are certain register definitions which are commonly shared
by i915, xe and display. Extract the same to a common header to
avoid duplication.

Move GEN6_PCODE_MAILBOX to common pcode header to make intel_cdclk.c
free from including i915_reg.h.

v3: Include pcode header as required, instead in i915_reg.h (Jani)

v2: Make the header granular and per feature (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/hsw_ips.c        |   1 +
 drivers/gpu/drm/i915/display/intel_bw.c       |   1 +
 drivers/gpu/drm/i915/display/intel_cdclk.c    |   2 +-
 .../drm/i915/display/intel_display_power.c    |   1 +
 .../i915/display/intel_display_power_well.c   |   1 +
 drivers/gpu/drm/i915/display/intel_dram.c     |   1 +
 drivers/gpu/drm/i915/display/intel_hdcp.c     |   1 +
 drivers/gpu/drm/i915/display/skl_watermark.c  |   1 +
 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c |   1 +
 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c   |   2 +
 drivers/gpu/drm/i915/gt/intel_llc.c           |   2 +
 drivers/gpu/drm/i915/gt/intel_rc6.c           |   1 +
 drivers/gpu/drm/i915/gt/intel_rps.c           |   1 +
 drivers/gpu/drm/i915/gvt/handlers.c           |   1 +
 drivers/gpu/drm/i915/i915_driver.c            |   1 +
 drivers/gpu/drm/i915/i915_hwmon.c             |   2 +
 drivers/gpu/drm/i915/i915_reg.h               | 100 ----------------
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |   2 +
 drivers/gpu/drm/i915/intel_pcode.c            |   1 +
 include/drm/intel/intel_pcode_regs.h          | 108 ++++++++++++++++++
 20 files changed, 130 insertions(+), 101 deletions(-)
 create mode 100644 include/drm/intel/intel_pcode_regs.h

diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 0caaea2e64e1..8658872ed86f 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -6,6 +6,7 @@
 #include <linux/debugfs.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "hsw_ips.h"
 #include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 8d84445c69f1..618da1dfb671 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -5,6 +5,7 @@
 
 #include <drm/drm_atomic_state_helper.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "i915_reg.h"
 #include "intel_bw.h"
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9217050a76e0..29d90d612bb2 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -27,9 +27,9 @@
 
 #include <drm/drm_fixed.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "hsw_ips.h"
-#include "i915_reg.h"
 #include "intel_atomic.h"
 #include "intel_audio.h"
 #include "intel_cdclk.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 06adf6afbec0..cb9256f72aa9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -7,6 +7,7 @@
 #include <linux/string_helpers.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "i915_reg.h"
 #include "intel_backlight_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 78f707b00550..45c4313e6900 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -6,6 +6,7 @@
 #include <linux/iopoll.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "i915_reg.h"
 #include "intel_backlight_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c
index 3b9879714ea9..61aefe77f90f 100644
--- a/drivers/gpu/drm/i915/display/intel_dram.c
+++ b/drivers/gpu/drm/i915/display/intel_dram.c
@@ -7,6 +7,7 @@
 
 #include <drm/drm_managed.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "i915_reg.h"
 #include "intel_display_core.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b7479ced7871..c96f51d88186 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -17,6 +17,7 @@
 #include <drm/display/drm_hdcp_helper.h>
 #include <drm/drm_print.h>
 #include <drm/intel/i915_component.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "i915_reg.h"
 #include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index b41da10f0f85..1455ea068d22 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -7,6 +7,7 @@
 
 #include <drm/drm_blend.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "i915_reg.h"
 #include "i9xx_wm.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index c0aff4b3cbba..babaf16e72f2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -8,6 +8,7 @@
 #include <linux/string_helpers.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "i915_drv.h"
 #include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 1154cd2b7c34..a48601395dce 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -7,6 +7,8 @@
 #include <linux/sysfs.h>
 #include <linux/printk.h>
 
+#include <drm/intel/intel_pcode_regs.h>
+
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "i915_sysfs.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c
index 1d19c073ba2e..bcd707e3d436 100644
--- a/drivers/gpu/drm/i915/gt/intel_llc.c
+++ b/drivers/gpu/drm/i915/gt/intel_llc.c
@@ -6,6 +6,8 @@
 #include <asm/tsc.h>
 #include <linux/cpufreq.h>
 
+#include <drm/intel/intel_pcode_regs.h>
+
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "intel_gt.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 286d49ecc449..942ac1ebecee 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -7,6 +7,7 @@
 #include <linux/string_helpers.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "display/vlv_clock.h"
 #include "gem/i915_gem_region.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 90b7eee78f1f..844f2716a386 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -7,6 +7,7 @@
 
 #include <drm/intel/i915_drm.h>
 #include <drm/intel/display_parent_interface.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "display/intel_display_rps.h"
 #include "display/vlv_clock.h"
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 6f860c320afc..2e9d9d0638ae 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -40,6 +40,7 @@
 
 #include <drm/display/drm_dp.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "display/bxt_dpio_phy_regs.h"
 #include "display/i9xx_plane_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index c01a35ecfa2f..6d8fbf845bc2 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -48,6 +48,7 @@
 #include <drm/drm_probe_helper.h>
 #include <drm/intel/display_member.h>
 #include <drm/intel/display_parent_interface.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "display/i9xx_display_sr.h"
 #include "display/intel_bw.h"
diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c
index 7dfe1784153f..a94f26e3b6bf 100644
--- a/drivers/gpu/drm/i915/i915_hwmon.c
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -9,6 +9,8 @@
 #include <linux/types.h>
 #include <linux/units.h>
 
+#include <drm/intel/intel_pcode_regs.h>
+
 #include "i915_drv.h"
 #include "i915_hwmon.h"
 #include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 26e5504dbc67..bb87af7d3c22 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -957,106 +957,6 @@
 #define    EDRAM_WAYS_IDX(cap)			(((cap) >> 5) & 0x7)
 #define    EDRAM_SETS_IDX(cap)			(((cap) >> 8) & 0x3)
 
-#define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
-#define   GEN6_PCODE_READY			(1 << 31)
-#define   GEN6_PCODE_MB_PARAM2			REG_GENMASK(23, 16)
-#define   GEN6_PCODE_MB_PARAM1			REG_GENMASK(15, 8)
-#define   GEN6_PCODE_MB_COMMAND			REG_GENMASK(7, 0)
-#define   GEN6_PCODE_ERROR_MASK			0xFF
-#define     GEN6_PCODE_SUCCESS			0x0
-#define     GEN6_PCODE_ILLEGAL_CMD		0x1
-#define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
-#define     GEN6_PCODE_TIMEOUT			0x3
-#define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
-#define     GEN7_PCODE_TIMEOUT			0x2
-#define     GEN7_PCODE_ILLEGAL_DATA		0x3
-#define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
-#define     GEN11_PCODE_LOCKED			0x6
-#define     GEN11_PCODE_REJECTED		0x11
-#define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
-#define   GEN6_PCODE_WRITE_RC6VIDS		0x4
-#define   GEN6_PCODE_READ_RC6VIDS		0x5
-#define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
-#define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
-#define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
-#define   GEN9_PCODE_READ_MEM_LATENCY		0x6
-#define     GEN9_MEM_LATENCY_LEVEL_3_7_MASK	REG_GENMASK(31, 24)
-#define     GEN9_MEM_LATENCY_LEVEL_2_6_MASK	REG_GENMASK(23, 16)
-#define     GEN9_MEM_LATENCY_LEVEL_1_5_MASK	REG_GENMASK(15, 8)
-#define     GEN9_MEM_LATENCY_LEVEL_0_4_MASK	REG_GENMASK(7, 0)
-#define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
-#define   SKL_PCODE_CDCLK_CONTROL		0x7
-#define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
-#define     SKL_CDCLK_READY_FOR_CHANGE		0x1
-#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
-#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
-#define   GEN6_READ_OC_PARAMS			0xc
-#define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
-#define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
-#define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
-#define     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO	((0) | (0x2 << 8))
-#define   DISPLAY_TO_PCODE_CDCLK_MAX		0x28D
-#define   DISPLAY_TO_PCODE_VOLTAGE_MASK		REG_GENMASK(1, 0)
-#define	  DISPLAY_TO_PCODE_VOLTAGE_MAX		DISPLAY_TO_PCODE_VOLTAGE_MASK
-#define   DISPLAY_TO_PCODE_CDCLK_VALID		REG_BIT(27)
-#define   DISPLAY_TO_PCODE_PIPE_COUNT_VALID	REG_BIT(31)
-#define   DISPLAY_TO_PCODE_CDCLK_MASK		REG_GENMASK(25, 16)
-#define   DISPLAY_TO_PCODE_PIPE_COUNT_MASK	REG_GENMASK(30, 28)
-#define   DISPLAY_TO_PCODE_CDCLK(x)		REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
-#define   DISPLAY_TO_PCODE_PIPE_COUNT(x)	REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
-#define   DISPLAY_TO_PCODE_VOLTAGE(x)		REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
-#define   DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
-		((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
-		(DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
-		(DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
-#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
-#define     ICL_PCODE_REP_QGV_MASK		REG_GENMASK(1, 0)
-#define     ICL_PCODE_REP_QGV_SAFE		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
-#define     ICL_PCODE_REP_QGV_POLL		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
-#define     ICL_PCODE_REP_QGV_REJECTED		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
-#define     ADLS_PCODE_REP_PSF_MASK		REG_GENMASK(3, 2)
-#define     ADLS_PCODE_REP_PSF_SAFE		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
-#define     ADLS_PCODE_REP_PSF_POLL		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
-#define     ADLS_PCODE_REP_PSF_REJECTED		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
-#define     ICL_PCODE_REQ_QGV_PT_MASK		REG_GENMASK(7, 0)
-#define     ICL_PCODE_REQ_QGV_PT(x)		REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
-#define     ADLS_PCODE_REQ_PSF_PT_MASK		REG_GENMASK(10, 8)
-#define     ADLS_PCODE_REQ_PSF_PT(x)		REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
-#define   GEN6_PCODE_READ_D_COMP		0x10
-#define   GEN6_PCODE_WRITE_D_COMP		0x11
-#define   ICL_PCODE_EXIT_TCCOLD			0x12
-#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
-#define   DISPLAY_IPS_CONTROL			0x19
-#define   TGL_PCODE_TCCOLD			0x26
-#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED	REG_BIT(0)
-#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ	0
-#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ	REG_BIT(0)
-            /* See also IPS_CTL */
-#define     IPS_PCODE_CONTROL			(1 << 30)
-#define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
-#define   GEN9_PCODE_SAGV_CONTROL		0x21
-#define     GEN9_SAGV_DISABLE			0x0
-#define     GEN9_SAGV_IS_DISABLED		0x1
-#define     GEN9_SAGV_ENABLE			0x3
-#define   DG1_PCODE_STATUS			0x7E
-#define     DG1_UNCORE_GET_INIT_STATUS		0x0
-#define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
-#define   PCODE_POWER_SETUP			0x7C
-#define     POWER_SETUP_SUBCOMMAND_READ_I1	0x4
-#define     POWER_SETUP_SUBCOMMAND_WRITE_I1	0x5
-#define	    POWER_SETUP_I1_WATTS		REG_BIT(31)
-#define	    POWER_SETUP_I1_SHIFT		6	/* 10.6 fixed point format */
-#define	    POWER_SETUP_I1_DATA_MASK		REG_GENMASK(15, 0)
-#define     POWER_SETUP_SUBCOMMAND_G8_ENABLE	0x6
-#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
-#define   XEHP_PCODE_FREQUENCY_CONFIG		0x6e	/* pvc */
-/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
-#define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
-#define     PCODE_MBOX_FC_SC_READ_FUSED_PN	0x1
-/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
-/*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
-#define     PCODE_MBOX_DOMAIN_NONE		0x0
-#define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
 #define GEN6_PCODE_DATA				_MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index c0154fd77fc9..8cfe9b56f1d0 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -3,6 +3,8 @@
  * Copyright © 2020 Intel Corporation
  */
 
+#include <drm/intel/intel_pcode_regs.h>
+
 #include "display/bxt_dpio_phy_regs.h"
 #include "display/i9xx_plane_regs.h"
 #include "display/i9xx_wm_regs.h"
diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
index 76c5916b28f4..c07d48fc1b35 100644
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu/drm/i915/intel_pcode.c
@@ -5,6 +5,7 @@
 
 #include <drm/drm_print.h>
 #include <drm/intel/display_parent_interface.h>
+#include <drm/intel/intel_pcode_regs.h>
 
 #include "i915_drv.h"
 #include "i915_reg.h"
diff --git a/include/drm/intel/intel_pcode_regs.h b/include/drm/intel/intel_pcode_regs.h
new file mode 100644
index 000000000000..db989ee7c488
--- /dev/null
+++ b/include/drm/intel/intel_pcode_regs.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2026 Intel Corporation */
+
+#ifndef _INTEL_PCODE_REGS_H_
+#define _INTEL_PCODE_REGS_H_
+
+#define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
+#define   GEN6_PCODE_READY			(1 << 31)
+#define   GEN6_PCODE_MB_PARAM2			REG_GENMASK(23, 16)
+#define   GEN6_PCODE_MB_PARAM1			REG_GENMASK(15, 8)
+#define   GEN6_PCODE_MB_COMMAND			REG_GENMASK(7, 0)
+#define   GEN6_PCODE_ERROR_MASK			0xFF
+#define     GEN6_PCODE_SUCCESS			0x0
+#define     GEN6_PCODE_ILLEGAL_CMD		0x1
+#define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
+#define     GEN6_PCODE_TIMEOUT			0x3
+#define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
+#define     GEN7_PCODE_TIMEOUT			0x2
+#define     GEN7_PCODE_ILLEGAL_DATA		0x3
+#define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
+#define     GEN11_PCODE_LOCKED			0x6
+#define     GEN11_PCODE_REJECTED		0x11
+#define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
+#define   GEN6_PCODE_WRITE_RC6VIDS		0x4
+#define   GEN6_PCODE_READ_RC6VIDS		0x5
+#define     GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
+#define     GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
+#define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
+#define   GEN9_PCODE_READ_MEM_LATENCY		0x6
+#define     GEN9_MEM_LATENCY_LEVEL_3_7_MASK	REG_GENMASK(31, 24)
+#define     GEN9_MEM_LATENCY_LEVEL_2_6_MASK	REG_GENMASK(23, 16)
+#define     GEN9_MEM_LATENCY_LEVEL_1_5_MASK	REG_GENMASK(15, 8)
+#define     GEN9_MEM_LATENCY_LEVEL_0_4_MASK	REG_GENMASK(7, 0)
+#define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
+#define   SKL_PCODE_CDCLK_CONTROL		0x7
+#define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
+#define     SKL_CDCLK_READY_FOR_CHANGE		0x1
+#define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
+#define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
+#define   GEN6_READ_OC_PARAMS			0xc
+#define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
+#define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
+#define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
+#define     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO	((0) | (0x2 << 8))
+#define   DISPLAY_TO_PCODE_CDCLK_MAX		0x28D
+#define   DISPLAY_TO_PCODE_VOLTAGE_MASK		REG_GENMASK(1, 0)
+#define	  DISPLAY_TO_PCODE_VOLTAGE_MAX		DISPLAY_TO_PCODE_VOLTAGE_MASK
+#define   DISPLAY_TO_PCODE_CDCLK_VALID		REG_BIT(27)
+#define   DISPLAY_TO_PCODE_PIPE_COUNT_VALID	REG_BIT(31)
+#define   DISPLAY_TO_PCODE_CDCLK_MASK		REG_GENMASK(25, 16)
+#define   DISPLAY_TO_PCODE_PIPE_COUNT_MASK	REG_GENMASK(30, 28)
+#define   DISPLAY_TO_PCODE_CDCLK(x)		REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
+#define   DISPLAY_TO_PCODE_PIPE_COUNT(x)	REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
+#define   DISPLAY_TO_PCODE_VOLTAGE(x)		REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
+#define   DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
+		((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
+		(DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
+		(DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
+#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
+#define     ICL_PCODE_REP_QGV_MASK		REG_GENMASK(1, 0)
+#define     ICL_PCODE_REP_QGV_SAFE		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
+#define     ICL_PCODE_REP_QGV_POLL		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
+#define     ICL_PCODE_REP_QGV_REJECTED		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
+#define     ADLS_PCODE_REP_PSF_MASK		REG_GENMASK(3, 2)
+#define     ADLS_PCODE_REP_PSF_SAFE		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
+#define     ADLS_PCODE_REP_PSF_POLL		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
+#define     ADLS_PCODE_REP_PSF_REJECTED		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
+#define     ICL_PCODE_REQ_QGV_PT_MASK		REG_GENMASK(7, 0)
+#define     ICL_PCODE_REQ_QGV_PT(x)		REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
+#define     ADLS_PCODE_REQ_PSF_PT_MASK		REG_GENMASK(10, 8)
+#define     ADLS_PCODE_REQ_PSF_PT(x)		REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
+#define   GEN6_PCODE_READ_D_COMP		0x10
+#define   GEN6_PCODE_WRITE_D_COMP		0x11
+#define   ICL_PCODE_EXIT_TCCOLD			0x12
+#define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
+#define   DISPLAY_IPS_CONTROL			0x19
+#define   TGL_PCODE_TCCOLD			0x26
+#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED	REG_BIT(0)
+#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ	0
+#define     TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ	REG_BIT(0)
+/* See also IPS_CTL */
+#define     IPS_PCODE_CONTROL			(1 << 30)
+#define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
+#define   GEN9_PCODE_SAGV_CONTROL		0x21
+#define     GEN9_SAGV_DISABLE			0x0
+#define     GEN9_SAGV_IS_DISABLED		0x1
+#define     GEN9_SAGV_ENABLE			0x3
+#define   DG1_PCODE_STATUS			0x7E
+#define     DG1_UNCORE_GET_INIT_STATUS		0x0
+#define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
+#define   PCODE_POWER_SETUP			0x7C
+#define     POWER_SETUP_SUBCOMMAND_READ_I1	0x4
+#define     POWER_SETUP_SUBCOMMAND_WRITE_I1	0x5
+#define	    POWER_SETUP_I1_WATTS		REG_BIT(31)
+#define	    POWER_SETUP_I1_SHIFT		6	/* 10.6 fixed point format */
+#define	    POWER_SETUP_I1_DATA_MASK		REG_GENMASK(15, 0)
+#define     POWER_SETUP_SUBCOMMAND_G8_ENABLE	0x6
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
+#define   XEHP_PCODE_FREQUENCY_CONFIG		0x6e	/* pvc */
+/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
+#define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
+#define     PCODE_MBOX_FC_SC_READ_FUSED_PN	0x1
+/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
+/*   XEHP_PCODE_FREQUENCY_CONFIG param2 */
+#define     PCODE_MBOX_DOMAIN_NONE		0x0
+#define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
+
+#endif
-- 
2.50.1

[v4 06/20] drm/i915: Remove i915_reg.h from intel_display_device.c

[Uma Shankar]

Move GU_CNTL_PROTECTED and GMD_ID_DISPLAY to common header,
this helps intel_display_device.c free from i915_reg.h dependency.

v2: Move GMD_ID_DISPLAY to display header instead of common (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 7 +++----
 drivers/gpu/drm/i915/display/intel_display_regs.h   | 8 ++++++++
 drivers/gpu/drm/i915/i915_reg.h                     | 4 ----
 3 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 471f236c9ddf..d449528bfc7f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -10,7 +10,6 @@
 #include <drm/drm_print.h>
 #include <drm/intel/pciids.h>
 
-#include "i915_reg.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_de.h"
 #include "intel_display.h"
@@ -1539,9 +1538,9 @@ probe_gmdid_display(struct intel_display *display, struct intel_display_ip_ver *
 		return NULL;
 	}
 
-	gmd_id.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
-	gmd_id.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
-	gmd_id.step = REG_FIELD_GET(GMD_ID_STEP, val);
+	gmd_id.ver = REG_FIELD_GET(GMD_ID_DISPLAY_ARCH_MASK, val);
+	gmd_id.rel = REG_FIELD_GET(GMD_ID_DISPLAY_RELEASE_MASK, val);
+	gmd_id.step = REG_FIELD_GET(GMD_ID_DISPLAY_STEP, val);
 
 	for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) {
 		if (gmd_id.ver == gmdid_display_map[i].ver &&
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index ab184670c845..c598ccb3c78b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -6,6 +6,9 @@
 
 #include "intel_display_reg_defs.h"
 
+#define GU_CNTL_PROTECTED		_MMIO(0x10100C)
+#define   DEPRESENT			REG_BIT(9)
+
 #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
 #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
@@ -1626,6 +1629,11 @@
 #define   GLK_DFSM_DISPLAY_DSC_DISABLE	(1 << 7)
 #define   XE2LPD_DFSM_DBUF_OVERLAP_DISABLE	(1 << 3)
 
+#define GMD_ID_DISPLAY				_MMIO(0x510a0)
+#define   GMD_ID_DISPLAY_ARCH_MASK		REG_GENMASK(31, 22)
+#define   GMD_ID_DISPLAY_RELEASE_MASK		REG_GENMASK(21, 14)
+#define   GMD_ID_DISPLAY_STEP			REG_GENMASK(5, 0)
+
 #define XE2LPD_DE_CAP			_MMIO(0x41100)
 #define   XE2LPD_DE_CAP_3DLUT_MASK	REG_GENMASK(31, 30)
 #define   XE2LPD_DE_CAP_DSC_MASK	REG_GENMASK(29, 28)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bb87af7d3c22..90a5c60e7667 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -116,9 +116,6 @@
  *  #define GEN8_BAR                    _MMIO(0xb888)
  */
 
-#define GU_CNTL_PROTECTED		_MMIO(0x10100C)
-#define   DEPRESENT			REG_BIT(9)
-
 #define GU_CNTL				_MMIO(0x101010)
 #define   LMEM_INIT			REG_BIT(7)
 #define   DRIVERFLR			REG_BIT(31)
@@ -925,7 +922,6 @@
 #define   MASK_WAKEMEM				REG_BIT(13)
 #define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
 
-#define GMD_ID_DISPLAY				_MMIO(0x510a0)
 #define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
 #define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
 #define   GMD_ID_STEP				REG_GENMASK(5, 0)
-- 
2.50.1

[v4 07/20] drm/i915: Move GMD_ID and mask to intel_gt header

[Uma Shankar]

GMD_ID* is relevant only for GT, hence moving the same
together in gt/intel_gt_regs.h

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
 drivers/gpu/drm/i915/i915_reg.h         | 4 ----
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 7421ed18d8d1..14d31882e9e7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -61,6 +61,9 @@
 
 #define GMD_ID_GRAPHICS				_MMIO(0xd8c)
 #define GMD_ID_MEDIA				_MMIO(MTL_MEDIA_GSI_BASE + 0xd8c)
+#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
+#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
+#define   GMD_ID_STEP				REG_GENMASK(5, 0)
 
 #define MCFG_MCR_SELECTOR			_MMIO(0xfd0)
 #define MTL_STEER_SEMAPHORE			_MMIO(0xfd0)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 90a5c60e7667..b12c6bf68a2c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -922,10 +922,6 @@
 #define   MASK_WAKEMEM				REG_BIT(13)
 #define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
 
-#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
-#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
-#define   GMD_ID_STEP				REG_GENMASK(5, 0)
-
 /* PCH */
 
 #define SDEISR  _MMIO(0xc4000)
-- 
2.50.1

[v4 08/20] drm/i915: Remove i915_reg.h from intel_dram.c

[Uma Shankar]

Make intel_dram.c free from including i915_reg.h.

v3: Move MEM_SS info reg to display instead of pcode header (Jani)

v2: Move mem config register to newly added pcode header (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_regs.h | 6 ++++++
 drivers/gpu/drm/i915/display/intel_dram.c         | 2 +-
 drivers/gpu/drm/i915/i915_reg.h                   | 6 ------
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index c598ccb3c78b..42aef6300320 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -3075,6 +3075,12 @@ enum skl_power_gate {
 #define MTL_PIPE_CLKGATE_DIS2(pipe)		_MMIO_PIPE(pipe, _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B)
 #define   MTL_DPFC_GATING_DIS			REG_BIT(6)
 
+#define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
+#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
+#define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
+#define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
+#define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
+
 #define MTL_MEM_SS_INFO_QGV_POINT_OFFSET	0x45710
 #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point)	_MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8)
 #define   MTL_TRCD_MASK			REG_GENMASK(31, 24)
diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c
index 61aefe77f90f..bd281d4b4c05 100644
--- a/drivers/gpu/drm/i915/display/intel_dram.c
+++ b/drivers/gpu/drm/i915/display/intel_dram.c
@@ -9,9 +9,9 @@
 #include <drm/drm_print.h>
 #include <drm/intel/intel_pcode_regs.h>
 
-#include "i915_reg.h"
 #include "intel_display_core.h"
 #include "intel_display_utils.h"
+#include "intel_display_regs.h"
 #include "intel_dram.h"
 #include "intel_mchbar_regs.h"
 #include "intel_parent.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b12c6bf68a2c..e905250f4fa5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1005,12 +1005,6 @@
 #define OROM_OFFSET				_MMIO(0x1020c0)
 #define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
 
-#define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
-#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
-#define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
-#define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
-#define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
-
 #define MTL_MEDIA_GSI_BASE		0x380000
 
 #endif /* _I915_REG_H_ */
-- 
2.50.1

[v4 09/20] drm/i915: Remove i915_reg.h from intel_display.c

[Uma Shankar]

Move CHICKEN_PIPESL_1 register definition to display header.
This allows intel_display.c free of i915_reg.h include.

v3: Fix commit header (Jani)

v2: Drop common header in include and use display_regs.h (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  1 -
 .../gpu/drm/i915/display/intel_display_regs.h | 23 +++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h               | 22 ------------------
 3 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 295f14416be7..bd93add5101b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -50,7 +50,6 @@
 #include "g4x_hdmi.h"
 #include "hsw_ips.h"
 #include "i915_config.h"
-#include "i915_reg.h"
 #include "i9xx_plane.h"
 #include "i9xx_plane_regs.h"
 #include "i9xx_wm.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 42aef6300320..0ee7295e1d4e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1543,6 +1543,29 @@
 #define   CHICKEN_FBC_STRIDE_MASK	REG_GENMASK(12, 0)
 #define   CHICKEN_FBC_STRIDE(x)		REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
 
+#define _CHICKEN_PIPESL_1_A	0x420b0
+#define _CHICKEN_PIPESL_1_B	0x420b4
+#define CHICKEN_PIPESL_1(pipe)	_MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define   HSW_PRI_STRETCH_MAX_MASK	REG_GENMASK(28, 27)
+#define   HSW_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
+#define   HSW_PRI_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
+#define   HSW_PRI_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
+#define   HSW_PRI_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
+#define   HSW_SPR_STRETCH_MAX_MASK	REG_GENMASK(26, 25)
+#define   HSW_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
+#define   HSW_SPR_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
+#define   HSW_SPR_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
+#define   HSW_SPR_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
+#define   HSW_FBCQ_DIS			REG_BIT(22)
+#define   HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
+#define   SKL_PSR_MASK_PLANE_FLIP	REG_BIT(11) /* skl+ */
+#define   SKL_PLANE1_STRETCH_MAX_MASK	REG_GENMASK(1, 0)
+#define   SKL_PLANE1_STRETCH_MAX_X8	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
+#define   SKL_PLANE1_STRETCH_MAX_X4	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
+#define   SKL_PLANE1_STRETCH_MAX_X2	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
+#define   SKL_PLANE1_STRETCH_MAX_X1	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
+#define   BDW_UNMASK_VBL_TO_REGS_IN_SRD	REG_BIT(0) /* bdw */
+
 #define _CHICKEN_TRANS_A	0x420c0
 #define _CHICKEN_TRANS_B	0x420c4
 #define _CHICKEN_TRANS_C	0x420c8
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e905250f4fa5..2be799ffbc2b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -878,28 +878,6 @@
 #define CHICKEN_PAR2_1		_MMIO(0x42090)
 #define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	REG_BIT(14)
 
-#define _CHICKEN_PIPESL_1_A	0x420b0
-#define _CHICKEN_PIPESL_1_B	0x420b4
-#define CHICKEN_PIPESL_1(pipe)	_MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
-#define   HSW_PRI_STRETCH_MAX_MASK	REG_GENMASK(28, 27)
-#define   HSW_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
-#define   HSW_PRI_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
-#define   HSW_PRI_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
-#define   HSW_PRI_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
-#define   HSW_SPR_STRETCH_MAX_MASK	REG_GENMASK(26, 25)
-#define   HSW_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
-#define   HSW_SPR_STRETCH_MAX_X4	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
-#define   HSW_SPR_STRETCH_MAX_X2	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
-#define   HSW_SPR_STRETCH_MAX_X1	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
-#define   HSW_FBCQ_DIS			REG_BIT(22)
-#define   HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
-#define   SKL_PSR_MASK_PLANE_FLIP	REG_BIT(11) /* skl+ */
-#define   SKL_PLANE1_STRETCH_MAX_MASK	REG_GENMASK(1, 0)
-#define   SKL_PLANE1_STRETCH_MAX_X8	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
-#define   SKL_PLANE1_STRETCH_MAX_X4	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
-#define   SKL_PLANE1_STRETCH_MAX_X2	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
-#define   SKL_PLANE1_STRETCH_MAX_X1	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
-#define   BDW_UNMASK_VBL_TO_REGS_IN_SRD	REG_BIT(0) /* bdw */
 
 #define DISP_ARB_CTL	_MMIO(0x45000)
 #define   DISP_FBC_MEMORY_WAKE		REG_BIT(31)
-- 
2.50.1

[v4 10/20] drm/i915: Remove i915_reg.h from intel_overlay.c

[Uma Shankar]

Move GEN2_ISR and some interrupt definitions to common header.
This removes dependency of i915_reg.h from intel_overlay.c.

v3: Rename interrupt header with regs suffix (Jani)

v2: Create a separate file for common interrupts (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_display_irq.c  |  1 +
 .../gpu/drm/i915/display/intel_display_regs.h |  2 +
 drivers/gpu/drm/i915/display/intel_overlay.c  |  2 +-
 drivers/gpu/drm/i915/gt/intel_gt.c            |  1 +
 .../gpu/drm/i915/gt/intel_ring_submission.c   |  1 +
 drivers/gpu/drm/i915/i915_irq.c               |  1 +
 drivers/gpu/drm/i915/i915_reg.h               | 37 ----------------
 include/drm/intel/intel_gmd_interrupt_regs.h  | 43 +++++++++++++++++++
 8 files changed, 50 insertions(+), 38 deletions(-)
 create mode 100644 include/drm/intel/intel_gmd_interrupt_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 0a71840041de..432a9c895c39 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -5,6 +5,7 @@
 
 #include <drm/drm_print.h>
 #include <drm/drm_vblank.h>
+#include <drm/intel/intel_gmd_interrupt_regs.h>
 
 #include "i915_reg.h"
 #include "icl_dsi_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 0ee7295e1d4e..d03f554ecd7e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -94,6 +94,8 @@
 #define   VLV_ERROR_PAGE_TABLE				(1 << 4)
 #define   VLV_ERROR_CLAIM				(1 << 0)
 
+#define GEN2_ISR	_MMIO(0x20ac)
+
 #define VLV_ERROR_REGS		I915_ERROR_REGS(VLV_EMR, VLV_EIR)
 
 #define _MBUS_ABOX0_CTL			0x45038
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 88eb7ae5765c..ed033e51f1d3 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -28,6 +28,7 @@
 
 #include <drm/drm_fourcc.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_interrupt_regs.h>
 
 #include "gem/i915_gem_internal.h"
 #include "gem/i915_gem_object_frontbuffer.h"
@@ -37,7 +38,6 @@
 #include "gt/intel_ring.h"
 
 #include "i915_drv.h"
-#include "i915_reg.h"
 #include "intel_color_regs.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index ac527d878820..d76121e117e1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -5,6 +5,7 @@
 
 #include <drm/drm_managed.h>
 #include <drm/intel/intel-gtt.h>
+#include <drm/intel/intel_gmd_interrupt_regs.h>
 
 #include "gem/i915_gem_internal.h"
 #include "gem/i915_gem_lmem.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 8314a4b0505e..c1797e49811d 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -4,6 +4,7 @@
  */
 
 #include <drm/drm_cache.h>
+#include <drm/intel/intel_gmd_interrupt_regs.h>
 
 #include "gem/i915_gem_internal.h"
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3fe978d4ea53..d4d8dd0a4174 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -34,6 +34,7 @@
 #include <drm/drm_drv.h>
 #include <drm/drm_print.h>
 #include <drm/intel/display_parent_interface.h>
+#include <drm/intel/intel_gmd_interrupt_regs.h>
 
 #include "display/intel_display_irq.h"
 #include "display/intel_hotplug.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2be799ffbc2b..1be8426b6a91 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -364,7 +364,6 @@
 #define GEN2_IER	_MMIO(0x20a0)
 #define GEN2_IIR	_MMIO(0x20a4)
 #define GEN2_IMR	_MMIO(0x20a8)
-#define GEN2_ISR	_MMIO(0x20ac)
 
 #define GEN2_IRQ_REGS		I915_IRQ_REGS(GEN2_IMR, \
 					      GEN2_IER, \
@@ -521,42 +520,6 @@
 /* These are all the "old" interrupts */
 #define ILK_BSD_USER_INTERRUPT				(1 << 5)
 
-#define I915_PM_INTERRUPT				(1 << 31)
-#define I915_ISP_INTERRUPT				(1 << 22)
-#define I915_LPE_PIPE_B_INTERRUPT			(1 << 21)
-#define I915_LPE_PIPE_A_INTERRUPT			(1 << 20)
-#define I915_MIPIC_INTERRUPT				(1 << 19)
-#define I915_MIPIA_INTERRUPT				(1 << 18)
-#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1 << 18)
-#define I915_DISPLAY_PORT_INTERRUPT			(1 << 17)
-#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1 << 16)
-#define I915_MASTER_ERROR_INTERRUPT			(1 << 15)
-#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1 << 14)
-#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1 << 14) /* p-state */
-#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1 << 13)
-#define I915_HWB_OOM_INTERRUPT				(1 << 13)
-#define I915_LPE_PIPE_C_INTERRUPT			(1 << 12)
-#define I915_SYNC_STATUS_INTERRUPT			(1 << 12)
-#define I915_MISC_INTERRUPT				(1 << 11)
-#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1 << 11)
-#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1 << 10)
-#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1 << 10)
-#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1 << 9)
-#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1 << 9)
-#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1 << 8)
-#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1 << 8)
-#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1 << 7)
-#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1 << 6)
-#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1 << 5)
-#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1 << 4)
-#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1 << 3)
-#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1 << 2)
-#define I915_DEBUG_INTERRUPT				(1 << 2)
-#define I915_WINVALID_INTERRUPT				(1 << 1)
-#define I915_USER_INTERRUPT				(1 << 1)
-#define I915_ASLE_INTERRUPT				(1 << 0)
-#define I915_BSD_USER_INTERRUPT				(1 << 25)
-
 #define GEN6_BSD_RNCID			_MMIO(0x12198)
 
 #define GEN7_FF_THREAD_MODE		_MMIO(0x20a0)
diff --git a/include/drm/intel/intel_gmd_interrupt_regs.h b/include/drm/intel/intel_gmd_interrupt_regs.h
new file mode 100644
index 000000000000..dc9d5fc29ff6
--- /dev/null
+++ b/include/drm/intel/intel_gmd_interrupt_regs.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2026 Intel Corporation */
+
+#ifndef _INTEL_GMD_INTERRUPT_REGS_H_
+#define _INTEL_GMD_INTERRUPT_REGS_H_
+
+#define I915_PM_INTERRUPT				(1 << 31)
+#define I915_ISP_INTERRUPT				(1 << 22)
+#define I915_LPE_PIPE_B_INTERRUPT			(1 << 21)
+#define I915_LPE_PIPE_A_INTERRUPT			(1 << 20)
+#define I915_MIPIC_INTERRUPT				(1 << 19)
+#define I915_MIPIA_INTERRUPT				(1 << 18)
+#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT		(1 << 18)
+#define I915_DISPLAY_PORT_INTERRUPT			(1 << 17)
+#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT		(1 << 16)
+#define I915_MASTER_ERROR_INTERRUPT			(1 << 15)
+#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT		(1 << 14)
+#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT	(1 << 14) /* p-state */
+#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT		(1 << 13)
+#define I915_HWB_OOM_INTERRUPT				(1 << 13)
+#define I915_LPE_PIPE_C_INTERRUPT			(1 << 12)
+#define I915_SYNC_STATUS_INTERRUPT			(1 << 12)
+#define I915_MISC_INTERRUPT				(1 << 11)
+#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT	(1 << 11)
+#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT		(1 << 10)
+#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT	(1 << 10)
+#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT		(1 << 9)
+#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT	(1 << 9)
+#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT		(1 << 8)
+#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT	(1 << 8)
+#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT		(1 << 7)
+#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT		(1 << 6)
+#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT		(1 << 5)
+#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT		(1 << 4)
+#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT		(1 << 3)
+#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT		(1 << 2)
+#define I915_DEBUG_INTERRUPT				(1 << 2)
+#define I915_WINVALID_INTERRUPT				(1 << 1)
+#define I915_USER_INTERRUPT				(1 << 1)
+#define I915_ASLE_INTERRUPT				(1 << 0)
+#define I915_BSD_USER_INTERRUPT				(1 << 25)
+
+#endif
-- 
2.50.1

[v4 11/20] drm/i915: Remove i915_reg.h from g4x_dp.c

[Uma Shankar]

Move DE_IRQ_REGS to display header to make g4x_dp.c
free from i915_reg.h dependency. These registers are
only used by display and gvt.

v3: Drop a superfluous include (Jani)

v2: Move DE interrupt regs from common to display header (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_dp.c            |  1 -
 .../gpu/drm/i915/display/intel_display_regs.h    | 16 ++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h                  | 15 ---------------
 3 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 4cb753177fd8..d7de329abf19 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -10,7 +10,6 @@
 #include <drm/drm_print.h>
 
 #include "g4x_dp.h"
-#include "i915_reg.h"
 #include "intel_audio.h"
 #include "intel_backlight.h"
 #include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index d03f554ecd7e..5bc891f6de57 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1049,6 +1049,15 @@
 #define SWF3(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
 #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
 
+#define DEISR   _MMIO(0x44000)
+#define DEIMR   _MMIO(0x44004)
+#define DEIIR   _MMIO(0x44008)
+#define DEIER   _MMIO(0x4400c)
+
+#define DE_IRQ_REGS		I915_IRQ_REGS(DEIMR, \
+					      DEIER, \
+					      DEIIR)
+
 #define DIGITAL_PORT_HOTPLUG_CNTRL	_MMIO(0x44030)
 #define  DIGITAL_PORTA_HOTPLUG_ENABLE		(1 << 4)
 #define  DIGITAL_PORTA_PULSE_DURATION_2ms	(0 << 2) /* pre-HSW */
@@ -1792,6 +1801,13 @@
 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
 					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
 
+/* PCH */
+
+#define SDEISR  _MMIO(0xc4000)
+#define SDEIMR  _MMIO(0xc4004)
+#define SDEIIR  _MMIO(0xc4008)
+#define SDEIER  _MMIO(0xc400c)
+
 #define SDE_IRQ_REGS			I915_IRQ_REGS(SDEIMR, \
 						      SDEIER, \
 						      SDEIIR)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1be8426b6a91..b808d1ec5387 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -727,15 +727,6 @@
 #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
 #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
 
-#define DEISR   _MMIO(0x44000)
-#define DEIMR   _MMIO(0x44004)
-#define DEIIR   _MMIO(0x44008)
-#define DEIER   _MMIO(0x4400c)
-
-#define DE_IRQ_REGS		I915_IRQ_REGS(DEIMR, \
-					      DEIER, \
-					      DEIIR)
-
 #define GTISR   _MMIO(0x44010)
 #define GTIMR   _MMIO(0x44014)
 #define GTIIR   _MMIO(0x44018)
@@ -863,12 +854,6 @@
 #define   MASK_WAKEMEM				REG_BIT(13)
 #define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
 
-/* PCH */
-
-#define SDEISR  _MMIO(0xc4000)
-#define SDEIMR  _MMIO(0xc4004)
-#define SDEIIR  _MMIO(0xc4008)
-#define SDEIER  _MMIO(0xc400c)
 
 /* Icelake PPS_DATA and _ECC DIP Registers.
  * These are available for transcoders B,C and eDP.
-- 
2.50.1

[v4 12/20] drm/i915: Remove i915_reg.h from i9xx_wm.c

[Uma Shankar]

Move FW_BLC_SELF to common header to make i9xx_wm.c
free from i915_reg.h include. Introduce a common
intel_gmd_misc_regs.h to define common miscellaneous
register definitions across graphics and display.

v3: MISC header included as needed, drop from i915_reg (Jani)

v2: Introdue a common misc header for GMD

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_wm.c        |  2 +-
 .../drm/i915/display/intel_display_debugfs.c  |  1 +
 .../gpu/drm/i915/display/intel_display_regs.h |  7 ++++++-
 drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c  |  1 +
 .../gpu/drm/i915/gt/intel_ring_submission.c   |  1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |  2 ++
 drivers/gpu/drm/i915/gvt/cmd_parser.c         |  1 +
 drivers/gpu/drm/i915/gvt/mmio_context.c       |  1 +
 drivers/gpu/drm/i915/i915_debugfs.c           |  1 +
 drivers/gpu/drm/i915/i915_reg.h               | 19 -----------------
 drivers/gpu/drm/i915/intel_clock_gating.c     |  1 +
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |  1 +
 include/drm/intel/intel_gmd_misc_regs.h       | 21 +++++++++++++++++++
 13 files changed, 38 insertions(+), 21 deletions(-)
 create mode 100644 include/drm/intel/intel_gmd_misc_regs.h

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 39dfceb438ae..24f898efa9dd 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -6,8 +6,8 @@
 #include <linux/iopoll.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
-#include "i915_reg.h"
 #include "i9xx_wm.h"
 #include "i9xx_wm_regs.h"
 #include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index aba13e8a9051..f041a7102317 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -13,6 +13,7 @@
 #include <drm/drm_file.h>
 #include <drm/drm_fourcc.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "hsw_ips.h"
 #include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 5bc891f6de57..9f241655aa99 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -3132,6 +3132,11 @@ enum skl_power_gate {
 #define   MTL_TRAS_MASK			REG_GENMASK(16, 8)
 #define   MTL_TRDPRE_MASK		REG_GENMASK(7, 0)
 
-
+#define FW_BLC		_MMIO(0x20d8)
+#define FW_BLC2		_MMIO(0x20dc)
+#define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
+#define   FW_BLC_SELF_EN_MASK      REG_BIT(31)
+#define   FW_BLC_SELF_FIFO_MASK    REG_BIT(16) /* 945 only */
+#define   FW_BLC_SELF_EN           REG_BIT(15) /* 945 only */
 
 #endif /* __INTEL_DISPLAY_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index 5eda98ebc1ae..ee90f5323da7 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -6,6 +6,7 @@
 #include <linux/highmem.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "display/intel_display.h"
 #include "i915_drv.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index c1797e49811d..099453dd9cd5 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -5,6 +5,7 @@
 
 #include <drm/drm_cache.h>
 #include <drm/intel/intel_gmd_interrupt_regs.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "gem/i915_gem_internal.h"
 
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index ece88c612e27..4427812b2438 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -3,6 +3,8 @@
  * Copyright © 2014-2018 Intel Corporation
  */
 
+#include <drm/intel/intel_gmd_misc_regs.h>
+
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "i915_mmio_range.h"
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index bf7c3d3f5f8a..98c35c78a4ed 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -37,6 +37,7 @@
 #include <linux/slab.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "display/i9xx_plane_regs.h"
 #include "display/intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index d4e9d485d382..3eb442acdf8d 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -34,6 +34,7 @@
  */
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "gt/intel_context.h"
 #include "gt/intel_engine_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 42f6b44f0027..4778ba664ec7 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -33,6 +33,7 @@
 
 #include <drm/drm_debugfs.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "gem/i915_gem_context.h"
 #include "gt/intel_gt.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b808d1ec5387..2bac216bd2b9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -393,24 +393,10 @@
 
 #define GEN2_ERROR_REGS		I915_ERROR_REGS(EMR, EIR)
 
-#define INSTPM	        _MMIO(0x20c0)
-#define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
-#define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
-					will not assert AGPBUSY# and will only
-					be delivered when out of C3. */
-#define   INSTPM_FORCE_ORDERING				(1 << 7) /* GEN6+ */
-#define   INSTPM_TLB_INVALIDATE	(1 << 9)
-#define   INSTPM_SYNC_FLUSH	(1 << 5)
 #define MEM_MODE	_MMIO(0x20cc)
 #define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
 #define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
 #define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
-#define FW_BLC		_MMIO(0x20d8)
-#define FW_BLC2		_MMIO(0x20dc)
-#define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
-#define   FW_BLC_SELF_EN_MASK      REG_BIT(31)
-#define   FW_BLC_SELF_FIFO_MASK    REG_BIT(16) /* 945 only */
-#define   FW_BLC_SELF_EN           REG_BIT(15) /* 945 only */
 #define MM_BURST_LENGTH     0x00700000
 #define MM_FIFO_WATERMARK   0x0001F000
 #define LM_BURST_LENGTH     0x00000700
@@ -833,11 +819,6 @@
 #define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	REG_BIT(14)
 
 
-#define DISP_ARB_CTL	_MMIO(0x45000)
-#define   DISP_FBC_MEMORY_WAKE		REG_BIT(31)
-#define   DISP_TILE_SURFACE_SWIZZLING	REG_BIT(13)
-#define   DISP_FBC_WM_DIS		REG_BIT(15)
-
 #define GEN8_CHICKEN_DCPR_1			_MMIO(0x46430)
 #define   _LATENCY_REPORTING_REMOVED_PIPE_D	REG_BIT(31)
 #define   SKL_SELECT_ALTERNATE_DC_EXIT		REG_BIT(30)
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 4e18d5a22112..1ad31435bd3f 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -26,6 +26,7 @@
  */
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "display/i9xx_plane_regs.h"
 #include "display/intel_display.h"
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 8cfe9b56f1d0..c8a51e773086 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -4,6 +4,7 @@
  */
 
 #include <drm/intel/intel_pcode_regs.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "display/bxt_dpio_phy_regs.h"
 #include "display/i9xx_plane_regs.h"
diff --git a/include/drm/intel/intel_gmd_misc_regs.h b/include/drm/intel/intel_gmd_misc_regs.h
new file mode 100644
index 000000000000..763d7711f21c
--- /dev/null
+++ b/include/drm/intel/intel_gmd_misc_regs.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2026 Intel Corporation */
+
+#ifndef _INTEL_GMD_MISC_REGS_H_
+#define _INTEL_GMD_MISC_REGS_H_
+
+#define DISP_ARB_CTL	_MMIO(0x45000)
+#define   DISP_FBC_MEMORY_WAKE		REG_BIT(31)
+#define   DISP_TILE_SURFACE_SWIZZLING	REG_BIT(13)
+#define   DISP_FBC_WM_DIS		REG_BIT(15)
+
+#define INSTPM	        _MMIO(0x20c0)
+#define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
+#define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
+					will not assert AGPBUSY# and will only
+					be delivered when out of C3. */
+#define   INSTPM_FORCE_ORDERING				(1 << 7) /* GEN6+ */
+#define   INSTPM_TLB_INVALIDATE	(1 << 9)
+#define   INSTPM_SYNC_FLUSH	(1 << 5)
+
+#endif
-- 
2.50.1

[v4 13/20] drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c

[Uma Shankar]

Move TRANS_CHICKEN1 reg to display header to make g4x_hdmi.c
free from i915_reg.h dependency.

v2: Remove from common header in include and use display_regs.h (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/g4x_hdmi.c           |  1 -
 drivers/gpu/drm/i915/display/intel_display_regs.h | 12 ++++++++++++
 drivers/gpu/drm/i915/i915_reg.h                   | 12 ------------
 3 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 8b22447e8e23..5fe5067c4237 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -8,7 +8,6 @@
 #include <drm/drm_print.h>
 
 #include "g4x_hdmi.h"
-#include "i915_reg.h"
 #include "intel_atomic.h"
 #include "intel_audio.h"
 #include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9f241655aa99..d4c5fd975b1b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2144,6 +2144,18 @@
 #define  TRANS_BPC_6			REG_FIELD_PREP(TRANS_BPC_MASK, 2)
 #define  TRANS_BPC_12			REG_FIELD_PREP(TRANS_BPC_MASK, 3)
 
+/* Icelake PPS_DATA and _ECC DIP Registers.
+ * These are available for transcoders B,C and eDP.
+ * Adding the _A so as to reuse the _MMIO_TRANS2
+ * definition, with which it offsets to the right location.
+ */
+
+#define _TRANSA_CHICKEN1	 0xf0060
+#define _TRANSB_CHICKEN1	 0xf1060
+#define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
+#define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
+#define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
+
 #define _TRANSA_CHICKEN2	0xf0064
 #define _TRANSB_CHICKEN2	0xf1064
 #define TRANS_CHICKEN2(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2bac216bd2b9..2c279bd3342d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -836,18 +836,6 @@
 #define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
 
 
-/* Icelake PPS_DATA and _ECC DIP Registers.
- * These are available for transcoders B,C and eDP.
- * Adding the _A so as to reuse the _MMIO_TRANS2
- * definition, with which it offsets to the right location.
- */
-
-#define _TRANSA_CHICKEN1	 0xf0060
-#define _TRANSB_CHICKEN1	 0xf1060
-#define TRANS_CHICKEN1(pipe)	_MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
-#define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
-#define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
-
 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
 
 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
-- 
2.50.1

[v4 14/20] drm/i915: Remove i915_reg.h from intel_rom.c

[Uma Shankar]

Make intel_rom.c free from including i915_reg.h.

v4: Move oprom reg to separate header (Ville)

v3: Update patch header

v2: Use display header instead of gmd common include (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_oprom_regs.h   | 36 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_rom.c      |  3 +-
 drivers/gpu/drm/i915/i915_reg.h               |  8 -----
 3 files changed, 37 insertions(+), 10 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_oprom_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_oprom_regs.h b/drivers/gpu/drm/i915/display/intel_oprom_regs.h
new file mode 100644
index 000000000000..2cf723aa4ab0
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_oprom_regs.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright © 2026 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _INTEL_OPROM_REGS_H_
+#define _INTEL_OPROM_REGS_H_
+
+#define PRIMARY_SPI_TRIGGER			_MMIO(0x102040)
+#define PRIMARY_SPI_ADDRESS			_MMIO(0x102080)
+#define PRIMARY_SPI_REGIONID			_MMIO(0x102084)
+#define SPI_STATIC_REGIONS			_MMIO(0x102090)
+#define   OPTIONROM_SPI_REGIONID_MASK		REG_GENMASK(7, 0)
+#define OROM_OFFSET				_MMIO(0x1020c0)
+#define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
+
+#endif
diff --git a/drivers/gpu/drm/i915/display/intel_rom.c b/drivers/gpu/drm/i915/display/intel_rom.c
index c8f615315310..024db7b1a1c6 100644
--- a/drivers/gpu/drm/i915/display/intel_rom.c
+++ b/drivers/gpu/drm/i915/display/intel_rom.c
@@ -7,10 +7,9 @@
 
 #include <drm/drm_device.h>
 
-#include "i915_reg.h"
-
 #include "intel_rom.h"
 #include "intel_uncore.h"
+#include "intel_oprom_regs.h"
 
 struct intel_rom {
 	/* for PCI ROM */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2c279bd3342d..9cb753b65bc2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -892,14 +892,6 @@
 #define   SGGI_DIS			REG_BIT(15)
 #define   SGR_DIS			REG_BIT(13)
 
-#define PRIMARY_SPI_TRIGGER			_MMIO(0x102040)
-#define PRIMARY_SPI_ADDRESS			_MMIO(0x102080)
-#define PRIMARY_SPI_REGIONID			_MMIO(0x102084)
-#define SPI_STATIC_REGIONS			_MMIO(0x102090)
-#define   OPTIONROM_SPI_REGIONID_MASK		REG_GENMASK(7, 0)
-#define OROM_OFFSET				_MMIO(0x1020c0)
-#define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
-
 #define MTL_MEDIA_GSI_BASE		0x380000
 
 #endif /* _I915_REG_H_ */
-- 
2.50.1

[v4 15/20] drm/i915: Remove i915_reg.h from intel_psr.c

[Uma Shankar]

Move some chicken registers to display header to make
intel_psr.c free from including i915_reg.h.

v3: Update commit header

v2: Use display header instead of gmd common include (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_display_regs.h | 26 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_psr.c      |  1 -
 drivers/gpu/drm/i915/i915_reg.h               | 28 -------------------
 3 files changed, 26 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index d4c5fd975b1b..9a7005e125a9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -357,6 +357,32 @@
 #define OGAMC1			_MMIO(0x30020)
 #define OGAMC0			_MMIO(0x30024)
 
+#define GEN8_CHICKEN_DCPR_1			_MMIO(0x46430)
+#define   _LATENCY_REPORTING_REMOVED_PIPE_D	REG_BIT(31)
+#define   SKL_SELECT_ALTERNATE_DC_EXIT		REG_BIT(30)
+#define   _LATENCY_REPORTING_REMOVED_PIPE_C	REG_BIT(25)
+#define   _LATENCY_REPORTING_REMOVED_PIPE_B	REG_BIT(24)
+#define   _LATENCY_REPORTING_REMOVED_PIPE_A	REG_BIT(23)
+#define   LATENCY_REPORTING_REMOVED(pipe)	_PICK((pipe), \
+						      _LATENCY_REPORTING_REMOVED_PIPE_A, \
+						      _LATENCY_REPORTING_REMOVED_PIPE_B, \
+						      _LATENCY_REPORTING_REMOVED_PIPE_C, \
+						      _LATENCY_REPORTING_REMOVED_PIPE_D)
+#define   ICL_DELAY_PMRSP			REG_BIT(22)
+#define   DISABLE_FLR_SRC			REG_BIT(15)
+#define   MASK_WAKEMEM				REG_BIT(13)
+#define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
+
+#define CHICKEN_PAR1_1		_MMIO(0x42080)
+#define   IGNORE_KVMR_PIPE_A		REG_BIT(23)
+#define   KBL_ARB_FILL_SPARE_22		REG_BIT(22)
+#define   DIS_RAM_BYPASS_PSR2_MAN_TRACK	REG_BIT(16)
+#define   SKL_DE_COMPRESSED_HASH_MODE	REG_BIT(15)
+#define   HSW_MASK_VBL_TO_PIPE_IN_SRD	REG_BIT(15) /* hsw/bdw */
+#define   FORCE_ARB_IDLE_PLANES		REG_BIT(14)
+#define   SKL_EDP_PSR_FIX_RDWRAP	REG_BIT(3)
+#define   IGNORE_PSR2_HW_TRACKING	REG_BIT(1)
+
 #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
 #define   BXT_GMBUS_GATING_DIS		(1 << 14)
 #define   DG2_DPFC_GATING_DIS		REG_BIT(31)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4e644711c571..5bea2eda744b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -29,7 +29,6 @@
 #include <drm/drm_print.h>
 #include <drm/drm_vblank.h>
 
-#include "i915_reg.h"
 #include "intel_alpm.h"
 #include "intel_atomic.h"
 #include "intel_crtc.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9cb753b65bc2..3a54b31bc072 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -805,37 +805,9 @@
 #define   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	REG_BIT(5)
 #define   CHICKEN3_DGMG_DONE_FIX_DISABLE	REG_BIT(2)
 
-#define CHICKEN_PAR1_1		_MMIO(0x42080)
-#define   IGNORE_KVMR_PIPE_A		REG_BIT(23)
-#define   KBL_ARB_FILL_SPARE_22		REG_BIT(22)
-#define   DIS_RAM_BYPASS_PSR2_MAN_TRACK	REG_BIT(16)
-#define   SKL_DE_COMPRESSED_HASH_MODE	REG_BIT(15)
-#define   HSW_MASK_VBL_TO_PIPE_IN_SRD	REG_BIT(15) /* hsw/bdw */
-#define   FORCE_ARB_IDLE_PLANES		REG_BIT(14)
-#define   SKL_EDP_PSR_FIX_RDWRAP	REG_BIT(3)
-#define   IGNORE_PSR2_HW_TRACKING	REG_BIT(1)
-
 #define CHICKEN_PAR2_1		_MMIO(0x42090)
 #define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	REG_BIT(14)
 
-
-#define GEN8_CHICKEN_DCPR_1			_MMIO(0x46430)
-#define   _LATENCY_REPORTING_REMOVED_PIPE_D	REG_BIT(31)
-#define   SKL_SELECT_ALTERNATE_DC_EXIT		REG_BIT(30)
-#define   _LATENCY_REPORTING_REMOVED_PIPE_C	REG_BIT(25)
-#define   _LATENCY_REPORTING_REMOVED_PIPE_B	REG_BIT(24)
-#define   _LATENCY_REPORTING_REMOVED_PIPE_A	REG_BIT(23)
-#define   LATENCY_REPORTING_REMOVED(pipe)	_PICK((pipe), \
-						      _LATENCY_REPORTING_REMOVED_PIPE_A, \
-						      _LATENCY_REPORTING_REMOVED_PIPE_B, \
-						      _LATENCY_REPORTING_REMOVED_PIPE_C, \
-						      _LATENCY_REPORTING_REMOVED_PIPE_D)
-#define   ICL_DELAY_PMRSP			REG_BIT(22)
-#define   DISABLE_FLR_SRC			REG_BIT(15)
-#define   MASK_WAKEMEM				REG_BIT(13)
-#define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
-
-
 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
 
 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
-- 
2.50.1

[v4 16/20] drm/i915: Remove i915_reg.h from intel_fifo_underrun.c

[Uma Shankar]

Move GEN7_ERR_INT reg to common header to make intel_fifo_underrun.c
free from including i915_reg.h.

v2: Move GEN7_ERR_INT regs to display header (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_display_regs.h | 23 +++++++++++++++++++
 .../drm/i915/display/intel_fifo_underrun.c    |  1 -
 drivers/gpu/drm/i915/i915_reg.h               | 23 -------------------
 3 files changed, 23 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9a7005e125a9..dcb8cab7b30b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -82,6 +82,29 @@
 #define   DERRMR_PIPEC_VBLANK		(1 << 21)
 #define   DERRMR_PIPEC_HBLANK		(1 << 22)
 
+#define GEN7_ERR_INT	_MMIO(0x44040)
+#define   ERR_INT_POISON		(1 << 31)
+#define   ERR_INT_INVALID_GTT_PTE	(1 << 29)
+#define   ERR_INT_INVALID_PTE_DATA	(1 << 28)
+#define   ERR_INT_SPRITE_C_FAULT	(1 << 23)
+#define   ERR_INT_PRIMARY_C_FAULT	(1 << 22)
+#define   ERR_INT_CURSOR_C_FAULT	(1 << 21)
+#define   ERR_INT_SPRITE_B_FAULT	(1 << 20)
+#define   ERR_INT_PRIMARY_B_FAULT	(1 << 19)
+#define   ERR_INT_CURSOR_B_FAULT	(1 << 18)
+#define   ERR_INT_SPRITE_A_FAULT	(1 << 17)
+#define   ERR_INT_PRIMARY_A_FAULT	(1 << 16)
+#define   ERR_INT_CURSOR_A_FAULT	(1 << 15)
+#define   ERR_INT_MMIO_UNCLAIMED	(1 << 13)
+#define   ERR_INT_PIPE_CRC_DONE_C	(1 << 8)
+#define   ERR_INT_FIFO_UNDERRUN_C	(1 << 6)
+#define   ERR_INT_PIPE_CRC_DONE_B	(1 << 5)
+#define   ERR_INT_FIFO_UNDERRUN_B	(1 << 3)
+#define   ERR_INT_PIPE_CRC_DONE_A	(1 << 2)
+#define   ERR_INT_PIPE_CRC_DONE(pipe)	(1 << (2 + (pipe) * 3))
+#define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
+#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
+
 #define VLV_IRQ_REGS		I915_IRQ_REGS(VLV_IMR, \
 					      VLV_IER, \
 					      VLV_IIR)
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index b413b3e871d8..bf047180def9 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -29,7 +29,6 @@
 
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_irq.h"
 #include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3a54b31bc072..5cb53a8c451a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -325,29 +325,6 @@
 #define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
 #define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
 
-#define GEN7_ERR_INT	_MMIO(0x44040)
-#define   ERR_INT_POISON		(1 << 31)
-#define   ERR_INT_INVALID_GTT_PTE	(1 << 29)
-#define   ERR_INT_INVALID_PTE_DATA	(1 << 28)
-#define   ERR_INT_SPRITE_C_FAULT	(1 << 23)
-#define   ERR_INT_PRIMARY_C_FAULT	(1 << 22)
-#define   ERR_INT_CURSOR_C_FAULT	(1 << 21)
-#define   ERR_INT_SPRITE_B_FAULT	(1 << 20)
-#define   ERR_INT_PRIMARY_B_FAULT	(1 << 19)
-#define   ERR_INT_CURSOR_B_FAULT	(1 << 18)
-#define   ERR_INT_SPRITE_A_FAULT	(1 << 17)
-#define   ERR_INT_PRIMARY_A_FAULT	(1 << 16)
-#define   ERR_INT_CURSOR_A_FAULT	(1 << 15)
-#define   ERR_INT_MMIO_UNCLAIMED	(1 << 13)
-#define   ERR_INT_PIPE_CRC_DONE_C	(1 << 8)
-#define   ERR_INT_FIFO_UNDERRUN_C	(1 << 6)
-#define   ERR_INT_PIPE_CRC_DONE_B	(1 << 5)
-#define   ERR_INT_FIFO_UNDERRUN_B	(1 << 3)
-#define   ERR_INT_PIPE_CRC_DONE_A	(1 << 2)
-#define   ERR_INT_PIPE_CRC_DONE(pipe)	(1 << (2 + (pipe) * 3))
-#define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
-#define   ERR_INT_FIFO_UNDERRUN(pipe)	(1 << ((pipe) * 3))
-
 #define FPGA_DBG		_MMIO(0x42300)
 #define   FPGA_DBG_RM_NOCLAIM	REG_BIT(31)
 
-- 
2.50.1

[v4 17/20] drm/i915: Remove i915_reg.h from intel_display_irq.c

[Uma Shankar]

Move VLV_IRQ_REGS to common header for interrupt to make
intel_display_irq.c free from including i915_reg.h.

v2: Move interrupt to dedicated header (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_display_irq.c  |  1 -
 .../gpu/drm/i915/display/intel_display_regs.h |  5 ++
 drivers/gpu/drm/i915/gt/intel_gt_irq.c        |  2 +
 drivers/gpu/drm/i915/gt/intel_rc6.c           |  1 +
 drivers/gpu/drm/i915/gvt/handlers.c           |  1 +
 drivers/gpu/drm/i915/gvt/interrupt.c          |  1 +
 drivers/gpu/drm/i915/i915_reg.h               | 52 -------------------
 drivers/gpu/drm/i915/intel_clock_gating.c     |  1 +
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |  2 +
 drivers/gpu/drm/i915/vlv_suspend.c            |  1 +
 include/drm/intel/intel_gmd_interrupt_regs.h  | 49 +++++++++++++++++
 11 files changed, 63 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 432a9c895c39..bd0eb1f46919 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -7,7 +7,6 @@
 #include <drm/drm_vblank.h>
 #include <drm/intel/intel_gmd_interrupt_regs.h>
 
-#include "i915_reg.h"
 #include "icl_dsi_regs.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index dcb8cab7b30b..1c77a7de2d6e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1470,6 +1470,11 @@
 #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
 #define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
 
+/* Display Internal Timeout Register */
+#define RM_TIMEOUT		_MMIO(0x42060)
+#define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
+#define  MMIO_TIMEOUT_US(us)	((us) << 0)
+
 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 75e802e10be2..d85c849c0081 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -5,6 +5,8 @@
 
 #include <linux/sched/clock.h>
 
+#include <drm/intel/intel_gmd_interrupt_regs.h>
+
 #include "i915_drv.h"
 #include "i915_irq.h"
 #include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 942ac1ebecee..5c316f734c4a 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -8,6 +8,7 @@
 
 #include <drm/drm_print.h>
 #include <drm/intel/intel_pcode_regs.h>
+#include <drm/intel/intel_gmd_interrupt_regs.h>
 
 #include "display/vlv_clock.h"
 #include "gem/i915_gem_region.h"
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 2e9d9d0638ae..4f65ced906da 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -41,6 +41,7 @@
 #include <drm/display/drm_dp.h>
 #include <drm/drm_print.h>
 #include <drm/intel/intel_pcode_regs.h>
+#include <drm/intel/intel_gmd_interrupt_regs.h>
 
 #include "display/bxt_dpio_phy_regs.h"
 #include "display/i9xx_plane_regs.h"
diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c
index 91d22b1c62e2..f85113218037 100644
--- a/drivers/gpu/drm/i915/gvt/interrupt.c
+++ b/drivers/gpu/drm/i915/gvt/interrupt.c
@@ -32,6 +32,7 @@
 #include <linux/eventfd.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_interrupt_regs.h>
 
 #include "display/intel_display_regs.h"
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5cb53a8c451a..7f3d5b7f7abd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -335,9 +335,6 @@
 
 #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
 #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
-#define SCPD0		_MMIO(0x209c) /* 915+ only */
-#define  SCPD_FBC_IGNORE_3D			(1 << 6)
-#define  CSTATE_RENDER_CLOCK_GATE_DISABLE	(1 << 5)
 #define GEN2_IER	_MMIO(0x20a0)
 #define GEN2_IIR	_MMIO(0x20a4)
 #define GEN2_IMR	_MMIO(0x20a8)
@@ -350,13 +347,6 @@
 #define   GINT_DIS		(1 << 22)
 #define   GCFG_DIS		(1 << 8)
 #define VLV_GUNIT_CLOCK_GATE2	_MMIO(VLV_DISPLAY_BASE + 0x2064)
-#define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
-#define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
-#define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
-#define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
-#define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
-#define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
-#define VLV_PCBR_ADDR_SHIFT	12
 
 #define EIR		_MMIO(0x20b0)
 #define EMR		_MMIO(0x20b4)
@@ -682,11 +672,6 @@
 #define PCH_3DCGDIS1		_MMIO(0x46024)
 # define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
 
-/* Display Internal Timeout Register */
-#define RM_TIMEOUT		_MMIO(0x42060)
-#define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
-#define  MMIO_TIMEOUT_US(us)	((us) << 0)
-
 #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
 #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
 
@@ -699,24 +684,6 @@
 					      GTIER, \
 					      GTIIR)
 
-#define GEN8_MASTER_IRQ			_MMIO(0x44200)
-#define  GEN8_MASTER_IRQ_CONTROL	(1 << 31)
-#define  GEN8_PCU_IRQ			(1 << 30)
-#define  GEN8_DE_PCH_IRQ		(1 << 23)
-#define  GEN8_DE_MISC_IRQ		(1 << 22)
-#define  GEN8_DE_PORT_IRQ		(1 << 20)
-#define  GEN8_DE_PIPE_C_IRQ		(1 << 18)
-#define  GEN8_DE_PIPE_B_IRQ		(1 << 17)
-#define  GEN8_DE_PIPE_A_IRQ		(1 << 16)
-#define  GEN8_DE_PIPE_IRQ(pipe)		(1 << (16 + (pipe)))
-#define  GEN8_GT_VECS_IRQ		(1 << 6)
-#define  GEN8_GT_GUC_IRQ		(1 << 5)
-#define  GEN8_GT_PM_IRQ			(1 << 4)
-#define  GEN8_GT_VCS1_IRQ		(1 << 3) /* NB: VCS2 in bspec! */
-#define  GEN8_GT_VCS0_IRQ		(1 << 2) /* NB: VCS1 in bpsec! */
-#define  GEN8_GT_BCS_IRQ		(1 << 1)
-#define  GEN8_GT_RCS_IRQ		(1 << 0)
-
 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
@@ -742,25 +709,6 @@
 						      GEN8_PCU_IER, \
 						      GEN8_PCU_IIR)
 
-#define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
-#define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
-#define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
-#define GEN11_GU_MISC_IER	_MMIO(0x444fc)
-#define  GEN11_GU_MISC_GSE	(1 << 27)
-
-#define GEN11_GU_MISC_IRQ_REGS		I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
-						      GEN11_GU_MISC_IER, \
-						      GEN11_GU_MISC_IIR)
-
-#define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
-#define  GEN11_MASTER_IRQ		(1 << 31)
-#define  GEN11_PCU_IRQ			(1 << 30)
-#define  GEN11_GU_MISC_IRQ		(1 << 29)
-#define  GEN11_DISPLAY_IRQ		(1 << 16)
-#define  GEN11_GT_DW_IRQ(x)		(1 << (x))
-#define  GEN11_GT_DW1_IRQ		(1 << 1)
-#define  GEN11_GT_DW0_IRQ		(1 << 0)
-
 #define DG1_MSTR_TILE_INTR		_MMIO(0x190008)
 #define   DG1_MSTR_IRQ			REG_BIT(31)
 #define   DG1_MSTR_TILE(t)		REG_BIT(t)
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 1ad31435bd3f..d0400ea2ffc7 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -27,6 +27,7 @@
 
 #include <drm/drm_print.h>
 #include <drm/intel/intel_gmd_misc_regs.h>
+#include <drm/intel/intel_gmd_interrupt_regs.h>
 
 #include "display/i9xx_plane_regs.h"
 #include "display/intel_display.h"
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index c8a51e773086..ae42818ab6e0 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -6,6 +6,8 @@
 #include <drm/intel/intel_pcode_regs.h>
 #include <drm/intel/intel_gmd_misc_regs.h>
 
+#include <drm/intel/intel_gmd_interrupt_regs.h>
+
 #include "display/bxt_dpio_phy_regs.h"
 #include "display/i9xx_plane_regs.h"
 #include "display/i9xx_wm_regs.h"
diff --git a/drivers/gpu/drm/i915/vlv_suspend.c b/drivers/gpu/drm/i915/vlv_suspend.c
index bace7b38329b..1e4343fe5574 100644
--- a/drivers/gpu/drm/i915/vlv_suspend.c
+++ b/drivers/gpu/drm/i915/vlv_suspend.c
@@ -7,6 +7,7 @@
 #include <linux/kernel.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_interrupt_regs.h>
 
 #include "gt/intel_gt_regs.h"
 
diff --git a/include/drm/intel/intel_gmd_interrupt_regs.h b/include/drm/intel/intel_gmd_interrupt_regs.h
index dc9d5fc29ff6..ce66c4151e76 100644
--- a/include/drm/intel/intel_gmd_interrupt_regs.h
+++ b/include/drm/intel/intel_gmd_interrupt_regs.h
@@ -40,4 +40,53 @@
 #define I915_ASLE_INTERRUPT				(1 << 0)
 #define I915_BSD_USER_INTERRUPT				(1 << 25)
 
+#define GEN8_MASTER_IRQ			_MMIO(0x44200)
+#define  GEN8_MASTER_IRQ_CONTROL	(1 << 31)
+#define  GEN8_PCU_IRQ			(1 << 30)
+#define  GEN8_DE_PCH_IRQ		(1 << 23)
+#define  GEN8_DE_MISC_IRQ		(1 << 22)
+#define  GEN8_DE_PORT_IRQ		(1 << 20)
+#define  GEN8_DE_PIPE_C_IRQ		(1 << 18)
+#define  GEN8_DE_PIPE_B_IRQ		(1 << 17)
+#define  GEN8_DE_PIPE_A_IRQ		(1 << 16)
+#define  GEN8_DE_PIPE_IRQ(pipe)		(1 << (16 + (pipe)))
+#define  GEN8_GT_VECS_IRQ		(1 << 6)
+#define  GEN8_GT_GUC_IRQ		(1 << 5)
+#define  GEN8_GT_PM_IRQ			(1 << 4)
+#define  GEN8_GT_VCS1_IRQ		(1 << 3) /* NB: VCS2 in bspec! */
+#define  GEN8_GT_VCS0_IRQ		(1 << 2) /* NB: VCS1 in bpsec! */
+#define  GEN8_GT_BCS_IRQ		(1 << 1)
+#define  GEN8_GT_RCS_IRQ		(1 << 0)
+
+#define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
+#define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
+#define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
+#define GEN11_GU_MISC_IER	_MMIO(0x444fc)
+#define  GEN11_GU_MISC_GSE	(1 << 27)
+
+#define GEN11_GU_MISC_IRQ_REGS		I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
+						      GEN11_GU_MISC_IER, \
+						      GEN11_GU_MISC_IIR)
+
+#define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
+#define  GEN11_MASTER_IRQ		(1 << 31)
+#define  GEN11_PCU_IRQ			(1 << 30)
+#define  GEN11_GU_MISC_IRQ		(1 << 29)
+#define  GEN11_DISPLAY_IRQ		(1 << 16)
+#define  GEN11_GT_DW_IRQ(x)		(1 << (x))
+#define  GEN11_GT_DW1_IRQ		(1 << 1)
+#define  GEN11_GT_DW0_IRQ		(1 << 0)
+
+#define SCPD0		_MMIO(0x209c) /* 915+ only */
+#define  SCPD_FBC_IGNORE_3D			(1 << 6)
+#define  CSTATE_RENDER_CLOCK_GATE_DISABLE	(1 << 5)
+
+#define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
+#define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
+#define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
+#define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
+#define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
+#define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
+#define VLV_PCBR_ADDR_SHIFT	12
+
 #endif
-- 
2.50.1

[v4 18/20] drm/i915: Remove i915_reg.h from intel_display_power_well.c

[Uma Shankar]

Make intel_display_power_well.c free from including i915_reg.h.

v3: Separate bit field for VLV (Ville)

v2: Include specific pcode header, drop common header (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power_well.c | 3 +--
 drivers/gpu/drm/i915/display/intel_display_regs.h       | 1 +
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 45c4313e6900..9c8d29839caf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -8,7 +8,6 @@
 #include <drm/drm_print.h>
 #include <drm/intel/intel_pcode_regs.h>
 
-#include "i915_reg.h"
 #include "intel_backlight_regs.h"
 #include "intel_combo_phy.h"
 #include "intel_combo_phy_regs.h"
@@ -1277,7 +1276,7 @@ static void vlv_init_display_clock_gating(struct intel_display *display)
 	 * Disable trickle feed and enable pnd deadline calculation
 	 */
 	intel_de_write(display, MI_ARB_VLV,
-		       MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
+		       MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE_VLV);
 	intel_de_write(display, CBR1_VLV, 0);
 
 	drm_WARN_ON(display->drm, DISPLAY_RUNTIME_INFO(display)->rawclk_freq == 0);
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 1c77a7de2d6e..d661385a1edd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -350,6 +350,7 @@
 #define  FW_CSPWRDWNEN		(1 << 15)
 
 #define MI_ARB_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6504)
+#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE_VLV	(1 << 2)
 
 #define CZCLK_CDCLK_FREQ_RATIO	_MMIO(VLV_DISPLAY_BASE + 0x6508)
 #define   CDCLK_FREQ_SHIFT	4
-- 
2.50.1

[v4 19/20] drm/i915: Remove i915_reg.h from intel_modeset_setup.c

[Uma Shankar]

Move GEN9_CLKGATE_DIS_0 reg to display header to make
intel_modeset_setup.c free from i915_reg.h include.

v2: Remove from gmd common header and use display_regs.h (Jani)

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_regs.h  | 14 ++++++++++++++
 drivers/gpu/drm/i915/display/intel_modeset_setup.c |  1 -
 drivers/gpu/drm/i915/i915_reg.h                    | 14 --------------
 3 files changed, 14 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index d661385a1edd..49e2a9e3ee0e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -407,6 +407,20 @@
 #define   SKL_EDP_PSR_FIX_RDWRAP	REG_BIT(3)
 #define   IGNORE_PSR2_HW_TRACKING	REG_BIT(1)
 
+/*
+ * GEN9 clock gating regs
+ */
+#define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
+#define   DARBF_GATING_DIS		REG_BIT(27)
+#define   DMG_GATING_DIS		REG_BIT(21)
+#define   MTL_PIPEDMC_GATING_DIS(pipe)	REG_BIT(15 - (pipe))
+#define   PWM2_GATING_DIS		REG_BIT(14)
+#define   PWM1_GATING_DIS		REG_BIT(13)
+
+#define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
+#define   TGL_VRH_GATING_DIS		REG_BIT(31)
+#define   DPT_GATING_DIS		REG_BIT(22)
+
 #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
 #define   BXT_GMBUS_GATING_DIS		(1 << 14)
 #define   DG2_DPFC_GATING_DIS		REG_BIT(31)
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index d10cbf69a5f8..9b0becee221c 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -11,7 +11,6 @@
 #include <drm/drm_print.h>
 #include <drm/drm_vblank.h>
 
-#include "i915_reg.h"
 #include "i9xx_wm.h"
 #include "intel_atomic.h"
 #include "intel_bw.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7f3d5b7f7abd..784d99afde64 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -630,20 +630,6 @@
 #define VLV_CLK_CTL2			_MMIO(0x101104)
 #define   CLK_CTL2_CZCOUNT_30NS_SHIFT	28
 
-/*
- * GEN9 clock gating regs
- */
-#define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
-#define   DARBF_GATING_DIS		REG_BIT(27)
-#define   DMG_GATING_DIS		REG_BIT(21)
-#define   MTL_PIPEDMC_GATING_DIS(pipe)	REG_BIT(15 - (pipe))
-#define   PWM2_GATING_DIS		REG_BIT(14)
-#define   PWM1_GATING_DIS		REG_BIT(13)
-
-#define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
-#define   TGL_VRH_GATING_DIS		REG_BIT(31)
-#define   DPT_GATING_DIS		REG_BIT(22)
-
 #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
 #define   PIPEB_LINE_COMPARE_INT_EN			REG_BIT(29)
 #define   PIPEB_HLINE_INT_EN			REG_BIT(28)
-- 
2.50.1

[v4 20/20] drm/{i915, xe}: Remove i915_reg.h from display

[Uma Shankar]

Make display files free from including i915_reg.h.

v2: Move pcode_regs.h out of i915_reg.h (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/hsw_ips.c               | 1 -
 drivers/gpu/drm/i915/display/i9xx_plane.c            | 1 -
 drivers/gpu/drm/i915/display/icl_dsi.c               | 1 -
 drivers/gpu/drm/i915/display/intel_backlight.c       | 1 -
 drivers/gpu/drm/i915/display/intel_bw.c              | 1 -
 drivers/gpu/drm/i915/display/intel_casf.c            | 1 -
 drivers/gpu/drm/i915/display/intel_ddi.c             | 1 -
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 1 -
 drivers/gpu/drm/i915/display/intel_display_power.c   | 1 -
 drivers/gpu/drm/i915/display/intel_display_wa.c      | 1 -
 drivers/gpu/drm/i915/display/intel_dmc.c             | 1 -
 drivers/gpu/drm/i915/display/intel_fdi.c             | 1 -
 drivers/gpu/drm/i915/display/intel_hdcp.c            | 1 -
 drivers/gpu/drm/i915/display/intel_hotplug_irq.c     | 1 -
 drivers/gpu/drm/i915/display/intel_lt_phy.c          | 1 -
 drivers/gpu/drm/i915/display/intel_pps.c             | 1 -
 drivers/gpu/drm/i915/display/intel_tc.c              | 1 -
 drivers/gpu/drm/i915/display/skl_watermark.c         | 1 -
 drivers/gpu/drm/i915/display/vlv_dsi.c               | 1 -
 19 files changed, 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 8658872ed86f..cbaef3f13f00 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -9,7 +9,6 @@
 #include <drm/intel/intel_pcode_regs.h>
 
 #include "hsw_ips.h"
-#include "i915_reg.h"
 #include "intel_color_regs.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index b1fecf178906..9c16753a1f3b 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -10,7 +10,6 @@
 #include <drm/drm_fourcc.h>
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "i9xx_plane.h"
 #include "i9xx_plane_regs.h"
 #include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index c8e0333706c1..7cf511a6c0f9 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -34,7 +34,6 @@
 #include <drm/drm_print.h>
 #include <drm/drm_probe_helper.h>
 
-#include "i915_reg.h"
 #include "icl_dsi.h"
 #include "icl_dsi_regs.h"
 #include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index a68fdbd2acb9..34e95f05936e 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -12,7 +12,6 @@
 #include <drm/drm_file.h>
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_backlight.h"
 #include "intel_backlight_regs.h"
 #include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 618da1dfb671..6808fb9b4ab3 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -7,7 +7,6 @@
 #include <drm/drm_print.h>
 #include <drm/intel/intel_pcode_regs.h>
 
-#include "i915_reg.h"
 #include "intel_bw.h"
 #include "intel_crtc.h"
 #include "intel_display_core.h"
diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
index 0fe4398a1a4e..b167af31de5b 100644
--- a/drivers/gpu/drm/i915/display/intel_casf.c
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -3,7 +3,6 @@
 
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_casf.h"
 #include "intel_casf_regs.h"
 #include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index f92323664162..94ae583e907f 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -34,7 +34,6 @@
 #include <drm/drm_print.h>
 #include <drm/drm_privacy_screen_consumer.h>
 
-#include "i915_reg.h"
 #include "icl_dsi.h"
 #include "intel_alpm.h"
 #include "intel_audio.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index f041a7102317..2614c4863c87 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -16,7 +16,6 @@
 #include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "hsw_ips.h"
-#include "i915_reg.h"
 #include "i9xx_wm_regs.h"
 #include "intel_alpm.h"
 #include "intel_bo.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index cb9256f72aa9..755935dcfe23 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -9,7 +9,6 @@
 #include <drm/drm_print.h>
 #include <drm/intel/intel_pcode_regs.h>
 
-#include "i915_reg.h"
 #include "intel_backlight_regs.h"
 #include "intel_cdclk.h"
 #include "intel_clock_gating.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index b1979ee9d836..c2ccdca2c2f3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -5,7 +5,6 @@
 
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_core.h"
 #include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 1182bc9a2e6d..8df06b993890 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -29,7 +29,6 @@
 #include <drm/drm_file.h>
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_power_well.h"
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 5bb0090dd5ed..24ce8a7842c7 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -8,7 +8,6 @@
 #include <drm/drm_fixed.h>
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_atomic.h"
 #include "intel_crtc.h"
 #include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index c96f51d88186..0058098d3c3e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -19,7 +19,6 @@
 #include <drm/intel/i915_component.h>
 #include <drm/intel/intel_pcode_regs.h>
 
-#include "i915_reg.h"
 #include "intel_connector.h"
 #include "intel_de.h"
 #include "intel_display_jiffies.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 82c39e4ffa37..8865cb2ac569 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -5,7 +5,6 @@
 
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_irq.h"
 #include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 27ad8407606b..eced8493e566 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -5,7 +5,6 @@
 
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index b217ec7aa758..2d799af73bb7 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -9,7 +9,6 @@
 #include <drm/drm_print.h>
 
 #include "g4x_dp.h"
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_jiffies.h"
 #include "intel_display_power_well.h"
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 064f572bbc85..78ed9c58a72f 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -7,7 +7,6 @@
 
 #include <drm/drm_print.h>
 
-#include "i915_reg.h"
 #include "intel_atomic.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 1455ea068d22..8e3031adb09f 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -9,7 +9,6 @@
 #include <drm/drm_print.h>
 #include <drm/intel/intel_pcode_regs.h>
 
-#include "i915_reg.h"
 #include "i9xx_wm.h"
 #include "intel_atomic.h"
 #include "intel_bw.h"
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index d705af3bf8ba..67f0082d3a69 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -33,7 +33,6 @@
 #include <drm/drm_print.h>
 #include <drm/drm_probe_helper.h>
 
-#include "i915_reg.h"
 #include "intel_atomic.h"
 #include "intel_backlight.h"
 #include "intel_connector.h"
-- 
2.50.1

✗ CI.checkpatch: warning for Make Display free from i915_reg.h (rev4)

[Patchwork]

== Series Details ==

Series: Make Display free from i915_reg.h (rev4)
URL   : https://patchwork.freedesktop.org/series/159130/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 1a49bad26f5f6d30dde8e6d6203535feb05c1f7f
Author: Uma Shankar <uma.shankar@intel.com>
Date:   Thu Feb 5 15:13:41 2026 +0530

    drm/{i915, xe}: Remove i915_reg.h from display
    
    Make display files free from including i915_reg.h.
    
    v2: Move pcode_regs.h out of i915_reg.h (Jani)
    
    Signed-off-by: Uma Shankar <uma.shankar@intel.com>
+ /mt/dim checkpatch 05230cfcdb1abc225c8e085cd4de470c4b97232f drm-intel
2a4826cf215a drm/i915: Extract display registers from i915_reg.h to display
-:36: WARNING:LONG_LINE: line length of 124 exceeds 100 columns
#36: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2030:
+#define   TRANS_CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */

total: 0 errors, 1 warnings, 0 checks, 47 lines checked
7d8a20e53a88 drm/i915: Extract South chicken registers from i915_reg.h to display
9ba16c81c230 drm/i915: Extract display interrupt definitions
6919da50353b drm/i915: Extract DSPCLK_GATE_D from i915_reg to display
79b340b75753 drm/{i915, xe}: Extract pcode definitions to common header
-:354: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#354: 
new file mode 100644

-:411: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#411: FILE: include/drm/intel/intel_pcode_regs.h:53:
+#define   DISPLAY_TO_PCODE_PIPE_COUNT(x)	REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))

total: 0 errors, 2 warnings, 0 checks, 347 lines checked
6bc40b39b659 drm/i915: Remove i915_reg.h from intel_display_device.c
65512718ae06 drm/i915: Move GMD_ID and mask to intel_gt header
b2e99d1bfea6 drm/i915: Remove i915_reg.h from intel_dram.c
2586a24df58e drm/i915: Remove i915_reg.h from intel_display.c
3b912b0ccb0f drm/i915: Remove i915_reg.h from intel_overlay.c
-:153: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#153: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 142 lines checked
365bc1a9a7c4 drm/i915: Remove i915_reg.h from g4x_dp.c
7ca91b3fe48b drm/i915: Remove i915_reg.h from i9xx_wm.c
-:199: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#199: 
new file mode 100644

-:218: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#218: FILE: include/drm/intel/intel_gmd_misc_regs.h:15:
+#define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
+					will not assert AGPBUSY# and will only

-:219: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#219: FILE: include/drm/intel/intel_gmd_misc_regs.h:16:
+					be delivered when out of C3. */

total: 0 errors, 3 warnings, 0 checks, 141 lines checked
d2e95ff93f8a drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c
ce831c672ba4 drm/i915: Remove i915_reg.h from intel_rom.c
-:18: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#18: 
new file mode 100644

-:23: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#23: FILE: drivers/gpu/drm/i915/display/intel_oprom_regs.h:1:
+/*

total: 0 errors, 2 warnings, 0 checks, 61 lines checked
3855b610a010 drm/i915: Remove i915_reg.h from intel_psr.c
f22b61f48ddf drm/i915: Remove i915_reg.h from intel_fifo_underrun.c
6926cc2c025c drm/i915: Remove i915_reg.h from intel_display_irq.c
a008bd9b978f drm/i915: Remove i915_reg.h from intel_display_power_well.c
338a78224354 drm/i915: Remove i915_reg.h from intel_modeset_setup.c
1a49bad26f5f drm/{i915, xe}: Remove i915_reg.h from display

✓ CI.KUnit: success for Make Display free from i915_reg.h (rev4)

[Patchwork]

== Series Details ==

Series: Make Display free from i915_reg.h (rev4)
URL   : https://patchwork.freedesktop.org/series/159130/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[10:22:20] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:22:24] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[10:23:03] Starting KUnit Kernel (1/1)...
[10:23:03] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:23:03] ================== guc_buf (11 subtests) ===================
[10:23:03] [PASSED] test_smallest
[10:23:03] [PASSED] test_largest
[10:23:03] [PASSED] test_granular
[10:23:03] [PASSED] test_unique
[10:23:03] [PASSED] test_overlap
[10:23:03] [PASSED] test_reusable
[10:23:03] [PASSED] test_too_big
[10:23:03] [PASSED] test_flush
[10:23:03] [PASSED] test_lookup
[10:23:03] [PASSED] test_data
[10:23:03] [PASSED] test_class
[10:23:03] ===================== [PASSED] guc_buf =====================
[10:23:03] =================== guc_dbm (7 subtests) ===================
[10:23:03] [PASSED] test_empty
[10:23:03] [PASSED] test_default
[10:23:03] ======================== test_size  ========================
[10:23:03] [PASSED] 4
[10:23:03] [PASSED] 8
[10:23:03] [PASSED] 32
[10:23:03] [PASSED] 256
[10:23:03] ==================== [PASSED] test_size ====================
[10:23:03] ======================= test_reuse  ========================
[10:23:03] [PASSED] 4
[10:23:03] [PASSED] 8
[10:23:03] [PASSED] 32
[10:23:03] [PASSED] 256
[10:23:03] =================== [PASSED] test_reuse ====================
[10:23:03] =================== test_range_overlap  ====================
[10:23:03] [PASSED] 4
[10:23:03] [PASSED] 8
[10:23:03] [PASSED] 32
[10:23:03] [PASSED] 256
[10:23:03] =============== [PASSED] test_range_overlap ================
[10:23:03] =================== test_range_compact  ====================
[10:23:03] [PASSED] 4
[10:23:03] [PASSED] 8
[10:23:03] [PASSED] 32
[10:23:03] [PASSED] 256
[10:23:03] =============== [PASSED] test_range_compact ================
[10:23:03] ==================== test_range_spare  =====================
[10:23:03] [PASSED] 4
[10:23:03] [PASSED] 8
[10:23:03] [PASSED] 32
[10:23:03] [PASSED] 256
[10:23:03] ================ [PASSED] test_range_spare =================
[10:23:03] ===================== [PASSED] guc_dbm =====================
[10:23:03] =================== guc_idm (6 subtests) ===================
[10:23:03] [PASSED] bad_init
[10:23:03] [PASSED] no_init
[10:23:03] [PASSED] init_fini
[10:23:03] [PASSED] check_used
[10:23:03] [PASSED] check_quota
[10:23:03] [PASSED] check_all
[10:23:03] ===================== [PASSED] guc_idm =====================
[10:23:03] ================== no_relay (3 subtests) ===================
[10:23:03] [PASSED] xe_drops_guc2pf_if_not_ready
[10:23:03] [PASSED] xe_drops_guc2vf_if_not_ready
[10:23:03] [PASSED] xe_rejects_send_if_not_ready
[10:23:03] ==================== [PASSED] no_relay =====================
[10:23:03] ================== pf_relay (14 subtests) ==================
[10:23:03] [PASSED] pf_rejects_guc2pf_too_short
[10:23:03] [PASSED] pf_rejects_guc2pf_too_long
[10:23:03] [PASSED] pf_rejects_guc2pf_no_payload
[10:23:03] [PASSED] pf_fails_no_payload
[10:23:03] [PASSED] pf_fails_bad_origin
[10:23:03] [PASSED] pf_fails_bad_type
[10:23:03] [PASSED] pf_txn_reports_error
[10:23:03] [PASSED] pf_txn_sends_pf2guc
[10:23:03] [PASSED] pf_sends_pf2guc
[10:23:03] [SKIPPED] pf_loopback_nop
[10:23:03] [SKIPPED] pf_loopback_echo
[10:23:03] [SKIPPED] pf_loopback_fail
[10:23:03] [SKIPPED] pf_loopback_busy
[10:23:03] [SKIPPED] pf_loopback_retry
[10:23:03] ==================== [PASSED] pf_relay =====================
[10:23:03] ================== vf_relay (3 subtests) ===================
[10:23:03] [PASSED] vf_rejects_guc2vf_too_short
[10:23:03] [PASSED] vf_rejects_guc2vf_too_long
[10:23:03] [PASSED] vf_rejects_guc2vf_no_payload
[10:23:03] ==================== [PASSED] vf_relay =====================
[10:23:03] ================ pf_gt_config (6 subtests) =================
[10:23:03] [PASSED] fair_contexts_1vf
[10:23:03] [PASSED] fair_doorbells_1vf
[10:23:03] [PASSED] fair_ggtt_1vf
[10:23:03] ====================== fair_contexts  ======================
[10:23:03] [PASSED] 1 VF
[10:23:03] [PASSED] 2 VFs
[10:23:03] [PASSED] 3 VFs
[10:23:03] [PASSED] 4 VFs
[10:23:03] [PASSED] 5 VFs
[10:23:03] [PASSED] 6 VFs
[10:23:03] [PASSED] 7 VFs
[10:23:03] [PASSED] 8 VFs
[10:23:03] [PASSED] 9 VFs
[10:23:03] [PASSED] 10 VFs
[10:23:03] [PASSED] 11 VFs
[10:23:03] [PASSED] 12 VFs
[10:23:03] [PASSED] 13 VFs
[10:23:03] [PASSED] 14 VFs
[10:23:03] [PASSED] 15 VFs
[10:23:03] [PASSED] 16 VFs
[10:23:03] [PASSED] 17 VFs
[10:23:03] [PASSED] 18 VFs
[10:23:03] [PASSED] 19 VFs
[10:23:03] [PASSED] 20 VFs
[10:23:03] [PASSED] 21 VFs
[10:23:03] [PASSED] 22 VFs
[10:23:03] [PASSED] 23 VFs
[10:23:03] [PASSED] 24 VFs
[10:23:03] [PASSED] 25 VFs
[10:23:03] [PASSED] 26 VFs
[10:23:03] [PASSED] 27 VFs
[10:23:03] [PASSED] 28 VFs
[10:23:03] [PASSED] 29 VFs
[10:23:03] [PASSED] 30 VFs
[10:23:03] [PASSED] 31 VFs
[10:23:03] [PASSED] 32 VFs
[10:23:03] [PASSED] 33 VFs
[10:23:03] [PASSED] 34 VFs
[10:23:03] [PASSED] 35 VFs
[10:23:03] [PASSED] 36 VFs
[10:23:03] [PASSED] 37 VFs
[10:23:03] [PASSED] 38 VFs
[10:23:03] [PASSED] 39 VFs
[10:23:03] [PASSED] 40 VFs
[10:23:03] [PASSED] 41 VFs
[10:23:03] [PASSED] 42 VFs
[10:23:03] [PASSED] 43 VFs
[10:23:03] [PASSED] 44 VFs
[10:23:03] [PASSED] 45 VFs
[10:23:03] [PASSED] 46 VFs
[10:23:03] [PASSED] 47 VFs
[10:23:03] [PASSED] 48 VFs
[10:23:03] [PASSED] 49 VFs
[10:23:03] [PASSED] 50 VFs
[10:23:03] [PASSED] 51 VFs
[10:23:03] [PASSED] 52 VFs
[10:23:03] [PASSED] 53 VFs
[10:23:03] [PASSED] 54 VFs
[10:23:03] [PASSED] 55 VFs
[10:23:03] [PASSED] 56 VFs
[10:23:03] [PASSED] 57 VFs
[10:23:03] [PASSED] 58 VFs
[10:23:03] [PASSED] 59 VFs
[10:23:03] [PASSED] 60 VFs
[10:23:03] [PASSED] 61 VFs
[10:23:03] [PASSED] 62 VFs
[10:23:03] [PASSED] 63 VFs
[10:23:03] ================== [PASSED] fair_contexts ==================
[10:23:03] ===================== fair_doorbells  ======================
[10:23:03] [PASSED] 1 VF
[10:23:03] [PASSED] 2 VFs
[10:23:03] [PASSED] 3 VFs
[10:23:03] [PASSED] 4 VFs
[10:23:03] [PASSED] 5 VFs
[10:23:03] [PASSED] 6 VFs
[10:23:03] [PASSED] 7 VFs
[10:23:03] [PASSED] 8 VFs
[10:23:03] [PASSED] 9 VFs
[10:23:03] [PASSED] 10 VFs
[10:23:03] [PASSED] 11 VFs
[10:23:03] [PASSED] 12 VFs
[10:23:03] [PASSED] 13 VFs
[10:23:03] [PASSED] 14 VFs
[10:23:03] [PASSED] 15 VFs
[10:23:03] [PASSED] 16 VFs
[10:23:03] [PASSED] 17 VFs
[10:23:03] [PASSED] 18 VFs
[10:23:03] [PASSED] 19 VFs
[10:23:03] [PASSED] 20 VFs
[10:23:03] [PASSED] 21 VFs
[10:23:03] [PASSED] 22 VFs
[10:23:03] [PASSED] 23 VFs
[10:23:03] [PASSED] 24 VFs
[10:23:03] [PASSED] 25 VFs
[10:23:03] [PASSED] 26 VFs
[10:23:03] [PASSED] 27 VFs
[10:23:03] [PASSED] 28 VFs
[10:23:03] [PASSED] 29 VFs
[10:23:03] [PASSED] 30 VFs
[10:23:03] [PASSED] 31 VFs
[10:23:03] [PASSED] 32 VFs
[10:23:03] [PASSED] 33 VFs
[10:23:03] [PASSED] 34 VFs
[10:23:03] [PASSED] 35 VFs
[10:23:03] [PASSED] 36 VFs
[10:23:03] [PASSED] 37 VFs
[10:23:03] [PASSED] 38 VFs
[10:23:03] [PASSED] 39 VFs
[10:23:03] [PASSED] 40 VFs
[10:23:03] [PASSED] 41 VFs
[10:23:03] [PASSED] 42 VFs
[10:23:03] [PASSED] 43 VFs
[10:23:03] [PASSED] 44 VFs
[10:23:03] [PASSED] 45 VFs
[10:23:03] [PASSED] 46 VFs
[10:23:03] [PASSED] 47 VFs
[10:23:03] [PASSED] 48 VFs
[10:23:03] [PASSED] 49 VFs
[10:23:03] [PASSED] 50 VFs
[10:23:03] [PASSED] 51 VFs
[10:23:03] [PASSED] 52 VFs
[10:23:03] [PASSED] 53 VFs
[10:23:03] [PASSED] 54 VFs
[10:23:03] [PASSED] 55 VFs
[10:23:03] [PASSED] 56 VFs
[10:23:03] [PASSED] 57 VFs
[10:23:03] [PASSED] 58 VFs
[10:23:03] [PASSED] 59 VFs
[10:23:03] [PASSED] 60 VFs
[10:23:03] [PASSED] 61 VFs
[10:23:03] [PASSED] 62 VFs
[10:23:03] [PASSED] 63 VFs
[10:23:03] ================= [PASSED] fair_doorbells ==================
[10:23:03] ======================== fair_ggtt  ========================
[10:23:03] [PASSED] 1 VF
[10:23:03] [PASSED] 2 VFs
[10:23:03] [PASSED] 3 VFs
[10:23:03] [PASSED] 4 VFs
[10:23:03] [PASSED] 5 VFs
[10:23:03] [PASSED] 6 VFs
[10:23:03] [PASSED] 7 VFs
[10:23:03] [PASSED] 8 VFs
[10:23:03] [PASSED] 9 VFs
[10:23:03] [PASSED] 10 VFs
[10:23:03] [PASSED] 11 VFs
[10:23:03] [PASSED] 12 VFs
[10:23:03] [PASSED] 13 VFs
[10:23:03] [PASSED] 14 VFs
[10:23:03] [PASSED] 15 VFs
[10:23:03] [PASSED] 16 VFs
[10:23:03] [PASSED] 17 VFs
[10:23:03] [PASSED] 18 VFs
[10:23:03] [PASSED] 19 VFs
[10:23:03] [PASSED] 20 VFs
[10:23:03] [PASSED] 21 VFs
[10:23:03] [PASSED] 22 VFs
[10:23:03] [PASSED] 23 VFs
[10:23:03] [PASSED] 24 VFs
[10:23:03] [PASSED] 25 VFs
[10:23:03] [PASSED] 26 VFs
[10:23:03] [PASSED] 27 VFs
[10:23:03] [PASSED] 28 VFs
[10:23:03] [PASSED] 29 VFs
[10:23:03] [PASSED] 30 VFs
[10:23:03] [PASSED] 31 VFs
[10:23:03] [PASSED] 32 VFs
[10:23:03] [PASSED] 33 VFs
[10:23:03] [PASSED] 34 VFs
[10:23:03] [PASSED] 35 VFs
[10:23:03] [PASSED] 36 VFs
[10:23:03] [PASSED] 37 VFs
[10:23:03] [PASSED] 38 VFs
[10:23:03] [PASSED] 39 VFs
[10:23:03] [PASSED] 40 VFs
[10:23:03] [PASSED] 41 VFs
[10:23:03] [PASSED] 42 VFs
[10:23:03] [PASSED] 43 VFs
[10:23:03] [PASSED] 44 VFs
[10:23:03] [PASSED] 45 VFs
[10:23:03] [PASSED] 46 VFs
[10:23:03] [PASSED] 47 VFs
[10:23:03] [PASSED] 48 VFs
[10:23:03] [PASSED] 49 VFs
[10:23:03] [PASSED] 50 VFs
[10:23:03] [PASSED] 51 VFs
[10:23:03] [PASSED] 52 VFs
[10:23:03] [PASSED] 53 VFs
[10:23:03] [PASSED] 54 VFs
[10:23:03] [PASSED] 55 VFs
[10:23:03] [PASSED] 56 VFs
[10:23:03] [PASSED] 57 VFs
[10:23:03] [PASSED] 58 VFs
[10:23:03] [PASSED] 59 VFs
[10:23:03] [PASSED] 60 VFs
[10:23:03] [PASSED] 61 VFs
[10:23:03] [PASSED] 62 VFs
[10:23:03] [PASSED] 63 VFs
[10:23:03] ==================== [PASSED] fair_ggtt ====================
[10:23:03] ================== [PASSED] pf_gt_config ===================
[10:23:03] ===================== lmtt (1 subtest) =====================
[10:23:03] ======================== test_ops  =========================
[10:23:03] [PASSED] 2-level
[10:23:03] [PASSED] multi-level
[10:23:03] ==================== [PASSED] test_ops =====================
[10:23:03] ====================== [PASSED] lmtt =======================
[10:23:03] ================= pf_service (11 subtests) =================
[10:23:03] [PASSED] pf_negotiate_any
[10:23:03] [PASSED] pf_negotiate_base_match
[10:23:03] [PASSED] pf_negotiate_base_newer
[10:23:03] [PASSED] pf_negotiate_base_next
[10:23:03] [SKIPPED] pf_negotiate_base_older
[10:23:03] [PASSED] pf_negotiate_base_prev
[10:23:03] [PASSED] pf_negotiate_latest_match
[10:23:03] [PASSED] pf_negotiate_latest_newer
[10:23:03] [PASSED] pf_negotiate_latest_next
[10:23:03] [SKIPPED] pf_negotiate_latest_older
[10:23:03] [SKIPPED] pf_negotiate_latest_prev
[10:23:03] =================== [PASSED] pf_service ====================
[10:23:03] ================= xe_guc_g2g (2 subtests) ==================
[10:23:03] ============== xe_live_guc_g2g_kunit_default  ==============
[10:23:03] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[10:23:03] ============== xe_live_guc_g2g_kunit_allmem  ===============
[10:23:03] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[10:23:03] =================== [SKIPPED] xe_guc_g2g ===================
[10:23:03] =================== xe_mocs (2 subtests) ===================
[10:23:03] ================ xe_live_mocs_kernel_kunit  ================
[10:23:03] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[10:23:03] ================ xe_live_mocs_reset_kunit  =================
[10:23:03] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[10:23:03] ==================== [SKIPPED] xe_mocs =====================
[10:23:03] ================= xe_migrate (2 subtests) ==================
[10:23:03] ================= xe_migrate_sanity_kunit  =================
[10:23:03] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[10:23:03] ================== xe_validate_ccs_kunit  ==================
[10:23:03] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[10:23:03] =================== [SKIPPED] xe_migrate ===================
[10:23:03] ================== xe_dma_buf (1 subtest) ==================
[10:23:03] ==================== xe_dma_buf_kunit  =====================
[10:23:03] ================ [SKIPPED] xe_dma_buf_kunit ================
[10:23:03] =================== [SKIPPED] xe_dma_buf ===================
[10:23:03] ================= xe_bo_shrink (1 subtest) =================
[10:23:03] =================== xe_bo_shrink_kunit  ====================
[10:23:03] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[10:23:03] ================== [SKIPPED] xe_bo_shrink ==================
[10:23:03] ==================== xe_bo (2 subtests) ====================
[10:23:03] ================== xe_ccs_migrate_kunit  ===================
[10:23:03] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[10:23:03] ==================== xe_bo_evict_kunit  ====================
[10:23:03] =============== [SKIPPED] xe_bo_evict_kunit ================
[10:23:03] ===================== [SKIPPED] xe_bo ======================
[10:23:03] ==================== args (13 subtests) ====================
[10:23:03] [PASSED] count_args_test
[10:23:03] [PASSED] call_args_example
[10:23:03] [PASSED] call_args_test
[10:23:03] [PASSED] drop_first_arg_example
[10:23:03] [PASSED] drop_first_arg_test
[10:23:03] [PASSED] first_arg_example
[10:23:03] [PASSED] first_arg_test
[10:23:03] [PASSED] last_arg_example
[10:23:03] [PASSED] last_arg_test
[10:23:03] [PASSED] pick_arg_example
[10:23:03] [PASSED] if_args_example
[10:23:03] [PASSED] if_args_test
[10:23:03] [PASSED] sep_comma_example
[10:23:03] ====================== [PASSED] args =======================
[10:23:03] =================== xe_pci (3 subtests) ====================
[10:23:03] ==================== check_graphics_ip  ====================
[10:23:03] [PASSED] 12.00 Xe_LP
[10:23:03] [PASSED] 12.10 Xe_LP+
[10:23:03] [PASSED] 12.55 Xe_HPG
[10:23:03] [PASSED] 12.60 Xe_HPC
[10:23:03] [PASSED] 12.70 Xe_LPG
[10:23:03] [PASSED] 12.71 Xe_LPG
[10:23:03] [PASSED] 12.74 Xe_LPG+
[10:23:03] [PASSED] 20.01 Xe2_HPG
[10:23:03] [PASSED] 20.02 Xe2_HPG
[10:23:03] [PASSED] 20.04 Xe2_LPG
[10:23:03] [PASSED] 30.00 Xe3_LPG
[10:23:03] [PASSED] 30.01 Xe3_LPG
[10:23:03] [PASSED] 30.03 Xe3_LPG
[10:23:03] [PASSED] 30.04 Xe3_LPG
[10:23:03] [PASSED] 30.05 Xe3_LPG
[10:23:03] [PASSED] 35.11 Xe3p_XPC
[10:23:03] ================ [PASSED] check_graphics_ip ================
[10:23:03] ===================== check_media_ip  ======================
[10:23:03] [PASSED] 12.00 Xe_M
[10:23:03] [PASSED] 12.55 Xe_HPM
[10:23:03] [PASSED] 13.00 Xe_LPM+
[10:23:03] [PASSED] 13.01 Xe2_HPM
[10:23:03] [PASSED] 20.00 Xe2_LPM
[10:23:03] [PASSED] 30.00 Xe3_LPM
[10:23:03] [PASSED] 30.02 Xe3_LPM
[10:23:03] [PASSED] 35.00 Xe3p_LPM
[10:23:03] [PASSED] 35.03 Xe3p_HPM
[10:23:03] ================= [PASSED] check_media_ip ==================
[10:23:03] =================== check_platform_desc  ===================
[10:23:03] [PASSED] 0x9A60 (TIGERLAKE)
[10:23:03] [PASSED] 0x9A68 (TIGERLAKE)
[10:23:03] [PASSED] 0x9A70 (TIGERLAKE)
[10:23:03] [PASSED] 0x9A40 (TIGERLAKE)
[10:23:03] [PASSED] 0x9A49 (TIGERLAKE)
[10:23:03] [PASSED] 0x9A59 (TIGERLAKE)
[10:23:03] [PASSED] 0x9A78 (TIGERLAKE)
[10:23:03] [PASSED] 0x9AC0 (TIGERLAKE)
[10:23:03] [PASSED] 0x9AC9 (TIGERLAKE)
[10:23:03] [PASSED] 0x9AD9 (TIGERLAKE)
[10:23:03] [PASSED] 0x9AF8 (TIGERLAKE)
[10:23:03] [PASSED] 0x4C80 (ROCKETLAKE)
[10:23:03] [PASSED] 0x4C8A (ROCKETLAKE)
[10:23:03] [PASSED] 0x4C8B (ROCKETLAKE)
[10:23:03] [PASSED] 0x4C8C (ROCKETLAKE)
[10:23:03] [PASSED] 0x4C90 (ROCKETLAKE)
[10:23:03] [PASSED] 0x4C9A (ROCKETLAKE)
[10:23:03] [PASSED] 0x4680 (ALDERLAKE_S)
[10:23:03] [PASSED] 0x4682 (ALDERLAKE_S)
[10:23:03] [PASSED] 0x4688 (ALDERLAKE_S)
[10:23:03] [PASSED] 0x468A (ALDERLAKE_S)
[10:23:03] [PASSED] 0x468B (ALDERLAKE_S)
[10:23:03] [PASSED] 0x4690 (ALDERLAKE_S)
[10:23:03] [PASSED] 0x4692 (ALDERLAKE_S)
[10:23:03] [PASSED] 0x4693 (ALDERLAKE_S)
[10:23:03] [PASSED] 0x46A0 (ALDERLAKE_P)
[10:23:03] [PASSED] 0x46A1 (ALDERLAKE_P)
[10:23:03] [PASSED] 0x46A2 (ALDERLAKE_P)
[10:23:03] [PASSED] 0x46A3 (ALDERLAKE_P)
[10:23:03] [PASSED] 0x46A6 (ALDERLAKE_P)
[10:23:03] [PASSED] 0x46A8 (ALDERLAKE_P)
[10:23:03] [PASSED] 0x46AA (ALDERLAKE_P)
[10:23:03] [PASSED] 0x462A (ALDERLAKE_P)
[10:23:03] [PASSED] 0x4626 (ALDERLAKE_P)
[10:23:03] [PASSED] 0x4628 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[10:23:03] [PASSED] 0x46B0 (ALDERLAKE_P)
[10:23:03] [PASSED] 0x46B1 (ALDERLAKE_P)
[10:23:03] [PASSED] 0x46B2 (ALDERLAKE_P)
[10:23:03] [PASSED] 0x46B3 (ALDERLAKE_P)
[10:23:03] [PASSED] 0x46C0 (ALDERLAKE_P)
[10:23:03] [PASSED] 0x46C1 (ALDERLAKE_P)
[10:23:03] [PASSED] 0x46C2 (ALDERLAKE_P)
[10:23:03] [PASSED] 0x46C3 (ALDERLAKE_P)
[10:23:03] [PASSED] 0x46D0 (ALDERLAKE_N)
[10:23:03] [PASSED] 0x46D1 (ALDERLAKE_N)
[10:23:03] [PASSED] 0x46D2 (ALDERLAKE_N)
[10:23:03] [PASSED] 0x46D3 (ALDERLAKE_N)
[10:23:03] [PASSED] 0x46D4 (ALDERLAKE_N)
[10:23:03] [PASSED] 0xA721 (ALDERLAKE_P)
[10:23:03] [PASSED] 0xA7A1 (ALDERLAKE_P)
[10:23:03] [PASSED] 0xA7A9 (ALDERLAKE_P)
[10:23:03] [PASSED] 0xA7AC (ALDERLAKE_P)
[10:23:03] [PASSED] 0xA7AD (ALDERLAKE_P)
[10:23:03] [PASSED] 0xA720 (ALDERLAKE_P)
[10:23:03] [PASSED] 0xA7A0 (ALDERLAKE_P)
[10:23:03] [PASSED] 0xA7A8 (ALDERLAKE_P)
[10:23:03] [PASSED] 0xA7AA (ALDERLAKE_P)
[10:23:03] [PASSED] 0xA7AB (ALDERLAKE_P)
[10:23:03] [PASSED] 0xA780 (ALDERLAKE_S)
[10:23:03] [PASSED] 0xA781 (ALDERLAKE_S)
[10:23:03] [PASSED] 0xA782 (ALDERLAKE_S)
[10:23:03] [PASSED] 0xA783 (ALDERLAKE_S)
[10:23:03] [PASSED] 0xA788 (ALDERLAKE_S)
[10:23:03] [PASSED] 0xA789 (ALDERLAKE_S)
[10:23:03] [PASSED] 0xA78A (ALDERLAKE_S)
[10:23:03] [PASSED] 0xA78B (ALDERLAKE_S)
[10:23:03] [PASSED] 0x4905 (DG1)
[10:23:03] [PASSED] 0x4906 (DG1)
[10:23:03] [PASSED] 0x4907 (DG1)
[10:23:03] [PASSED] 0x4908 (DG1)
[10:23:03] [PASSED] 0x4909 (DG1)
[10:23:03] [PASSED] 0x56C0 (DG2)
[10:23:03] [PASSED] 0x56C2 (DG2)
[10:23:03] [PASSED] 0x56C1 (DG2)
[10:23:03] [PASSED] 0x7D51 (METEORLAKE)
[10:23:03] [PASSED] 0x7DD1 (METEORLAKE)
[10:23:03] [PASSED] 0x7D41 (METEORLAKE)
[10:23:03] [PASSED] 0x7D67 (METEORLAKE)
[10:23:03] [PASSED] 0xB640 (METEORLAKE)
[10:23:03] [PASSED] 0x56A0 (DG2)
[10:23:03] [PASSED] 0x56A1 (DG2)
[10:23:03] [PASSED] 0x56A2 (DG2)
[10:23:03] [PASSED] 0x56BE (DG2)
[10:23:03] [PASSED] 0x56BF (DG2)
[10:23:03] [PASSED] 0x5690 (DG2)
[10:23:03] [PASSED] 0x5691 (DG2)
[10:23:03] [PASSED] 0x5692 (DG2)
[10:23:03] [PASSED] 0x56A5 (DG2)
[10:23:03] [PASSED] 0x56A6 (DG2)
[10:23:03] [PASSED] 0x56B0 (DG2)
[10:23:03] [PASSED] 0x56B1 (DG2)
[10:23:03] [PASSED] 0x56BA (DG2)
[10:23:03] [PASSED] 0x56BB (DG2)
[10:23:03] [PASSED] 0x56BC (DG2)
[10:23:03] [PASSED] 0x56BD (DG2)
[10:23:03] [PASSED] 0x5693 (DG2)
[10:23:03] [PASSED] 0x5694 (DG2)
[10:23:03] [PASSED] 0x5695 (DG2)
[10:23:03] [PASSED] 0x56A3 (DG2)
[10:23:03] [PASSED] 0x56A4 (DG2)
[10:23:03] [PASSED] 0x56B2 (DG2)
[10:23:03] [PASSED] 0x56B3 (DG2)
[10:23:03] [PASSED] 0x5696 (DG2)
[10:23:03] [PASSED] 0x5697 (DG2)
[10:23:03] [PASSED] 0xB69 (PVC)
[10:23:03] [PASSED] 0xB6E (PVC)
[10:23:03] [PASSED] 0xBD4 (PVC)
[10:23:03] [PASSED] 0xBD5 (PVC)
[10:23:03] [PASSED] 0xBD6 (PVC)
[10:23:03] [PASSED] 0xBD7 (PVC)
[10:23:03] [PASSED] 0xBD8 (PVC)
[10:23:03] [PASSED] 0xBD9 (PVC)
[10:23:03] [PASSED] 0xBDA (PVC)
[10:23:03] [PASSED] 0xBDB (PVC)
[10:23:03] [PASSED] 0xBE0 (PVC)
[10:23:03] [PASSED] 0xBE1 (PVC)
[10:23:03] [PASSED] 0xBE5 (PVC)
[10:23:03] [PASSED] 0x7D40 (METEORLAKE)
[10:23:03] [PASSED] 0x7D45 (METEORLAKE)
[10:23:03] [PASSED] 0x7D55 (METEORLAKE)
[10:23:03] [PASSED] 0x7D60 (METEORLAKE)
[10:23:03] [PASSED] 0x7DD5 (METEORLAKE)
[10:23:03] [PASSED] 0x6420 (LUNARLAKE)
[10:23:03] [PASSED] 0x64A0 (LUNARLAKE)
[10:23:03] [PASSED] 0x64B0 (LUNARLAKE)
[10:23:03] [PASSED] 0xE202 (BATTLEMAGE)
[10:23:03] [PASSED] 0xE209 (BATTLEMAGE)
[10:23:03] [PASSED] 0xE20B (BATTLEMAGE)
[10:23:03] [PASSED] 0xE20C (BATTLEMAGE)
[10:23:03] [PASSED] 0xE20D (BATTLEMAGE)
[10:23:03] [PASSED] 0xE210 (BATTLEMAGE)
[10:23:03] [PASSED] 0xE211 (BATTLEMAGE)
[10:23:03] [PASSED] 0xE212 (BATTLEMAGE)
[10:23:03] [PASSED] 0xE216 (BATTLEMAGE)
[10:23:03] [PASSED] 0xE220 (BATTLEMAGE)
[10:23:03] [PASSED] 0xE221 (BATTLEMAGE)
[10:23:03] [PASSED] 0xE222 (BATTLEMAGE)
[10:23:03] [PASSED] 0xE223 (BATTLEMAGE)
[10:23:03] [PASSED] 0xB080 (PANTHERLAKE)
[10:23:03] [PASSED] 0xB081 (PANTHERLAKE)
[10:23:03] [PASSED] 0xB082 (PANTHERLAKE)
[10:23:03] [PASSED] 0xB083 (PANTHERLAKE)
[10:23:03] [PASSED] 0xB084 (PANTHERLAKE)
[10:23:03] [PASSED] 0xB085 (PANTHERLAKE)
[10:23:03] [PASSED] 0xB086 (PANTHERLAKE)
[10:23:03] [PASSED] 0xB087 (PANTHERLAKE)
[10:23:03] [PASSED] 0xB08F (PANTHERLAKE)
[10:23:03] [PASSED] 0xB090 (PANTHERLAKE)
[10:23:03] [PASSED] 0xB0A0 (PANTHERLAKE)
[10:23:03] [PASSED] 0xB0B0 (PANTHERLAKE)
[10:23:03] [PASSED] 0xFD80 (PANTHERLAKE)
[10:23:03] [PASSED] 0xFD81 (PANTHERLAKE)
[10:23:03] [PASSED] 0xD740 (NOVALAKE_S)
[10:23:03] [PASSED] 0xD741 (NOVALAKE_S)
[10:23:03] [PASSED] 0xD742 (NOVALAKE_S)
[10:23:03] [PASSED] 0xD743 (NOVALAKE_S)
[10:23:03] [PASSED] 0xD744 (NOVALAKE_S)
[10:23:03] [PASSED] 0xD745 (NOVALAKE_S)
[10:23:03] [PASSED] 0x674C (CRESCENTISLAND)
[10:23:03] =============== [PASSED] check_platform_desc ===============
[10:23:03] ===================== [PASSED] xe_pci ======================
[10:23:03] =================== xe_rtp (2 subtests) ====================
[10:23:03] =============== xe_rtp_process_to_sr_tests  ================
[10:23:03] [PASSED] coalesce-same-reg
[10:23:03] [PASSED] no-match-no-add
[10:23:03] [PASSED] match-or
[10:23:03] [PASSED] match-or-xfail
[10:23:03] [PASSED] no-match-no-add-multiple-rules
[10:23:03] [PASSED] two-regs-two-entries
[10:23:03] [PASSED] clr-one-set-other
[10:23:03] [PASSED] set-field
[10:23:03] [PASSED] conflict-duplicate
[10:23:03] [PASSED] conflict-not-disjoint
[10:23:03] [PASSED] conflict-reg-type
[10:23:03] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[10:23:03] ================== xe_rtp_process_tests  ===================
[10:23:03] [PASSED] active1
[10:23:03] [PASSED] active2
[10:23:03] [PASSED] active-inactive
[10:23:03] [PASSED] inactive-active
[10:23:03] [PASSED] inactive-1st_or_active-inactive
[10:23:03] [PASSED] inactive-2nd_or_active-inactive
[10:23:03] [PASSED] inactive-last_or_active-inactive
[10:23:03] [PASSED] inactive-no_or_active-inactive
[10:23:03] ============== [PASSED] xe_rtp_process_tests ===============
[10:23:03] ===================== [PASSED] xe_rtp ======================
[10:23:03] ==================== xe_wa (1 subtest) =====================
[10:23:03] ======================== xe_wa_gt  =========================
[10:23:03] [PASSED] TIGERLAKE B0
[10:23:03] [PASSED] DG1 A0
[10:23:03] [PASSED] DG1 B0
[10:23:03] [PASSED] ALDERLAKE_S A0
[10:23:03] [PASSED] ALDERLAKE_S B0
[10:23:03] [PASSED] ALDERLAKE_S C0
[10:23:03] [PASSED] ALDERLAKE_S D0
[10:23:03] [PASSED] ALDERLAKE_P A0
[10:23:03] [PASSED] ALDERLAKE_P B0
[10:23:03] [PASSED] ALDERLAKE_P C0
[10:23:03] [PASSED] ALDERLAKE_S RPLS D0
[10:23:03] [PASSED] ALDERLAKE_P RPLU E0
[10:23:03] [PASSED] DG2 G10 C0
[10:23:03] [PASSED] DG2 G11 B1
[10:23:03] [PASSED] DG2 G12 A1
[10:23:03] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:23:03] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[10:23:03] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[10:23:03] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[10:23:03] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[10:23:03] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[10:23:03] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[10:23:03] ==================== [PASSED] xe_wa_gt =====================
[10:23:03] ====================== [PASSED] xe_wa ======================
[10:23:03] ============================================================
[10:23:03] Testing complete. Ran 512 tests: passed: 494, skipped: 18
[10:23:03] Elapsed time: 43.330s total, 4.254s configuring, 38.559s building, 0.480s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:23:03] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:23:05] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[10:23:35] Starting KUnit Kernel (1/1)...
[10:23:35] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:23:36] ============ drm_test_pick_cmdline (2 subtests) ============
[10:23:36] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[10:23:36] =============== drm_test_pick_cmdline_named  ===============
[10:23:36] [PASSED] NTSC
[10:23:36] [PASSED] NTSC-J
[10:23:36] [PASSED] PAL
[10:23:36] [PASSED] PAL-M
[10:23:36] =========== [PASSED] drm_test_pick_cmdline_named ===========
[10:23:36] ============== [PASSED] drm_test_pick_cmdline ==============
[10:23:36] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[10:23:36] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[10:23:36] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[10:23:36] =========== drm_validate_clone_mode (2 subtests) ===========
[10:23:36] ============== drm_test_check_in_clone_mode  ===============
[10:23:36] [PASSED] in_clone_mode
[10:23:36] [PASSED] not_in_clone_mode
[10:23:36] ========== [PASSED] drm_test_check_in_clone_mode ===========
[10:23:36] =============== drm_test_check_valid_clones  ===============
[10:23:36] [PASSED] not_in_clone_mode
[10:23:36] [PASSED] valid_clone
[10:23:36] [PASSED] invalid_clone
[10:23:36] =========== [PASSED] drm_test_check_valid_clones ===========
[10:23:36] ============= [PASSED] drm_validate_clone_mode =============
[10:23:36] ============= drm_validate_modeset (1 subtest) =============
[10:23:36] [PASSED] drm_test_check_connector_changed_modeset
[10:23:36] ============== [PASSED] drm_validate_modeset ===============
[10:23:36] ====== drm_test_bridge_get_current_state (2 subtests) ======
[10:23:36] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[10:23:36] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[10:23:36] ======== [PASSED] drm_test_bridge_get_current_state ========
[10:23:36] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[10:23:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[10:23:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[10:23:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[10:23:36] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[10:23:36] ============== drm_bridge_alloc (2 subtests) ===============
[10:23:36] [PASSED] drm_test_drm_bridge_alloc_basic
[10:23:36] [PASSED] drm_test_drm_bridge_alloc_get_put
[10:23:36] ================ [PASSED] drm_bridge_alloc =================
[10:23:36] ================== drm_buddy (9 subtests) ==================
[10:23:36] [PASSED] drm_test_buddy_alloc_limit
[10:23:36] [PASSED] drm_test_buddy_alloc_optimistic
[10:23:36] [PASSED] drm_test_buddy_alloc_pessimistic
[10:23:36] [PASSED] drm_test_buddy_alloc_pathological
[10:23:36] [PASSED] drm_test_buddy_alloc_contiguous
[10:23:36] [PASSED] drm_test_buddy_alloc_clear
[10:23:36] [PASSED] drm_test_buddy_alloc_range_bias
[10:23:36] [PASSED] drm_test_buddy_fragmentation_performance
[10:23:36] [PASSED] drm_test_buddy_alloc_exceeds_max_order
[10:23:36] ==================== [PASSED] drm_buddy ====================
[10:23:36] ============= drm_cmdline_parser (40 subtests) =============
[10:23:36] [PASSED] drm_test_cmdline_force_d_only
[10:23:36] [PASSED] drm_test_cmdline_force_D_only_dvi
[10:23:36] [PASSED] drm_test_cmdline_force_D_only_hdmi
[10:23:36] [PASSED] drm_test_cmdline_force_D_only_not_digital
[10:23:36] [PASSED] drm_test_cmdline_force_e_only
[10:23:36] [PASSED] drm_test_cmdline_res
[10:23:36] [PASSED] drm_test_cmdline_res_vesa
[10:23:36] [PASSED] drm_test_cmdline_res_vesa_rblank
[10:23:36] [PASSED] drm_test_cmdline_res_rblank
[10:23:36] [PASSED] drm_test_cmdline_res_bpp
[10:23:36] [PASSED] drm_test_cmdline_res_refresh
[10:23:36] [PASSED] drm_test_cmdline_res_bpp_refresh
[10:23:36] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[10:23:36] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[10:23:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[10:23:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[10:23:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[10:23:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[10:23:36] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[10:23:36] [PASSED] drm_test_cmdline_res_margins_force_on
[10:23:36] [PASSED] drm_test_cmdline_res_vesa_margins
[10:23:36] [PASSED] drm_test_cmdline_name
[10:23:36] [PASSED] drm_test_cmdline_name_bpp
[10:23:36] [PASSED] drm_test_cmdline_name_option
[10:23:36] [PASSED] drm_test_cmdline_name_bpp_option
[10:23:36] [PASSED] drm_test_cmdline_rotate_0
[10:23:36] [PASSED] drm_test_cmdline_rotate_90
[10:23:36] [PASSED] drm_test_cmdline_rotate_180
[10:23:36] [PASSED] drm_test_cmdline_rotate_270
[10:23:36] [PASSED] drm_test_cmdline_hmirror
[10:23:36] [PASSED] drm_test_cmdline_vmirror
[10:23:36] [PASSED] drm_test_cmdline_margin_options
[10:23:36] [PASSED] drm_test_cmdline_multiple_options
[10:23:36] [PASSED] drm_test_cmdline_bpp_extra_and_option
[10:23:36] [PASSED] drm_test_cmdline_extra_and_option
[10:23:36] [PASSED] drm_test_cmdline_freestanding_options
[10:23:36] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[10:23:36] [PASSED] drm_test_cmdline_panel_orientation
[10:23:36] ================ drm_test_cmdline_invalid  =================
[10:23:36] [PASSED] margin_only
[10:23:36] [PASSED] interlace_only
[10:23:36] [PASSED] res_missing_x
[10:23:36] [PASSED] res_missing_y
[10:23:36] [PASSED] res_bad_y
[10:23:36] [PASSED] res_missing_y_bpp
[10:23:36] [PASSED] res_bad_bpp
[10:23:36] [PASSED] res_bad_refresh
[10:23:36] [PASSED] res_bpp_refresh_force_on_off
[10:23:36] [PASSED] res_invalid_mode
[10:23:36] [PASSED] res_bpp_wrong_place_mode
[10:23:36] [PASSED] name_bpp_refresh
[10:23:36] [PASSED] name_refresh
[10:23:36] [PASSED] name_refresh_wrong_mode
[10:23:36] [PASSED] name_refresh_invalid_mode
[10:23:36] [PASSED] rotate_multiple
[10:23:36] [PASSED] rotate_invalid_val
[10:23:36] [PASSED] rotate_truncated
[10:23:36] [PASSED] invalid_option
[10:23:36] [PASSED] invalid_tv_option
[10:23:36] [PASSED] truncated_tv_option
[10:23:36] ============ [PASSED] drm_test_cmdline_invalid =============
[10:23:36] =============== drm_test_cmdline_tv_options  ===============
[10:23:36] [PASSED] NTSC
[10:23:36] [PASSED] NTSC_443
[10:23:36] [PASSED] NTSC_J
[10:23:36] [PASSED] PAL
[10:23:36] [PASSED] PAL_M
[10:23:36] [PASSED] PAL_N
[10:23:36] [PASSED] SECAM
[10:23:36] [PASSED] MONO_525
[10:23:36] [PASSED] MONO_625
[10:23:36] =========== [PASSED] drm_test_cmdline_tv_options ===========
[10:23:36] =============== [PASSED] drm_cmdline_parser ================
[10:23:36] ========== drmm_connector_hdmi_init (20 subtests) ==========
[10:23:36] [PASSED] drm_test_connector_hdmi_init_valid
[10:23:36] [PASSED] drm_test_connector_hdmi_init_bpc_8
[10:23:36] [PASSED] drm_test_connector_hdmi_init_bpc_10
[10:23:36] [PASSED] drm_test_connector_hdmi_init_bpc_12
[10:23:36] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[10:23:36] [PASSED] drm_test_connector_hdmi_init_bpc_null
[10:23:36] [PASSED] drm_test_connector_hdmi_init_formats_empty
[10:23:36] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[10:23:36] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[10:23:36] [PASSED] supported_formats=0x9 yuv420_allowed=1
[10:23:36] [PASSED] supported_formats=0x9 yuv420_allowed=0
[10:23:36] [PASSED] supported_formats=0x3 yuv420_allowed=1
[10:23:36] [PASSED] supported_formats=0x3 yuv420_allowed=0
[10:23:36] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[10:23:36] [PASSED] drm_test_connector_hdmi_init_null_ddc
[10:23:36] [PASSED] drm_test_connector_hdmi_init_null_product
[10:23:36] [PASSED] drm_test_connector_hdmi_init_null_vendor
[10:23:36] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[10:23:36] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[10:23:36] [PASSED] drm_test_connector_hdmi_init_product_valid
[10:23:36] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[10:23:36] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[10:23:36] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[10:23:36] ========= drm_test_connector_hdmi_init_type_valid  =========
[10:23:36] [PASSED] HDMI-A
[10:23:36] [PASSED] HDMI-B
[10:23:36] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[10:23:36] ======== drm_test_connector_hdmi_init_type_invalid  ========
[10:23:36] [PASSED] Unknown
[10:23:36] [PASSED] VGA
[10:23:36] [PASSED] DVI-I
[10:23:36] [PASSED] DVI-D
[10:23:36] [PASSED] DVI-A
[10:23:36] [PASSED] Composite
[10:23:36] [PASSED] SVIDEO
[10:23:36] [PASSED] LVDS
[10:23:36] [PASSED] Component
[10:23:36] [PASSED] DIN
[10:23:36] [PASSED] DP
[10:23:36] [PASSED] TV
[10:23:36] [PASSED] eDP
[10:23:36] [PASSED] Virtual
[10:23:36] [PASSED] DSI
[10:23:36] [PASSED] DPI
[10:23:36] [PASSED] Writeback
[10:23:36] [PASSED] SPI
[10:23:36] [PASSED] USB
[10:23:36] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[10:23:36] ============ [PASSED] drmm_connector_hdmi_init =============
[10:23:36] ============= drmm_connector_init (3 subtests) =============
[10:23:36] [PASSED] drm_test_drmm_connector_init
[10:23:36] [PASSED] drm_test_drmm_connector_init_null_ddc
[10:23:36] ========= drm_test_drmm_connector_init_type_valid  =========
[10:23:36] [PASSED] Unknown
[10:23:36] [PASSED] VGA
[10:23:36] [PASSED] DVI-I
[10:23:36] [PASSED] DVI-D
[10:23:36] [PASSED] DVI-A
[10:23:36] [PASSED] Composite
[10:23:36] [PASSED] SVIDEO
[10:23:36] [PASSED] LVDS
[10:23:36] [PASSED] Component
[10:23:36] [PASSED] DIN
[10:23:36] [PASSED] DP
[10:23:36] [PASSED] HDMI-A
[10:23:36] [PASSED] HDMI-B
[10:23:36] [PASSED] TV
[10:23:36] [PASSED] eDP
[10:23:36] [PASSED] Virtual
[10:23:36] [PASSED] DSI
[10:23:36] [PASSED] DPI
[10:23:36] [PASSED] Writeback
[10:23:36] [PASSED] SPI
[10:23:36] [PASSED] USB
[10:23:36] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[10:23:36] =============== [PASSED] drmm_connector_init ===============
[10:23:36] ========= drm_connector_dynamic_init (6 subtests) ==========
[10:23:36] [PASSED] drm_test_drm_connector_dynamic_init
[10:23:36] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[10:23:36] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[10:23:36] [PASSED] drm_test_drm_connector_dynamic_init_properties
[10:23:36] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[10:23:36] [PASSED] Unknown
[10:23:36] [PASSED] VGA
[10:23:36] [PASSED] DVI-I
[10:23:36] [PASSED] DVI-D
[10:23:36] [PASSED] DVI-A
[10:23:36] [PASSED] Composite
[10:23:36] [PASSED] SVIDEO
[10:23:36] [PASSED] LVDS
[10:23:36] [PASSED] Component
[10:23:36] [PASSED] DIN
[10:23:36] [PASSED] DP
[10:23:36] [PASSED] HDMI-A
[10:23:36] [PASSED] HDMI-B
[10:23:36] [PASSED] TV
[10:23:36] [PASSED] eDP
[10:23:36] [PASSED] Virtual
[10:23:36] [PASSED] DSI
[10:23:36] [PASSED] DPI
[10:23:36] [PASSED] Writeback
[10:23:36] [PASSED] SPI
[10:23:36] [PASSED] USB
[10:23:36] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[10:23:36] ======== drm_test_drm_connector_dynamic_init_name  =========
[10:23:36] [PASSED] Unknown
[10:23:36] [PASSED] VGA
[10:23:36] [PASSED] DVI-I
[10:23:36] [PASSED] DVI-D
[10:23:36] [PASSED] DVI-A
[10:23:36] [PASSED] Composite
[10:23:36] [PASSED] SVIDEO
[10:23:36] [PASSED] LVDS
[10:23:36] [PASSED] Component
[10:23:36] [PASSED] DIN
[10:23:36] [PASSED] DP
[10:23:36] [PASSED] HDMI-A
[10:23:36] [PASSED] HDMI-B
[10:23:36] [PASSED] TV
[10:23:36] [PASSED] eDP
[10:23:36] [PASSED] Virtual
[10:23:36] [PASSED] DSI
[10:23:36] [PASSED] DPI
[10:23:36] [PASSED] Writeback
[10:23:36] [PASSED] SPI
[10:23:36] [PASSED] USB
[10:23:36] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[10:23:36] =========== [PASSED] drm_connector_dynamic_init ============
[10:23:36] ==== drm_connector_dynamic_register_early (4 subtests) =====
[10:23:36] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[10:23:36] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[10:23:36] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[10:23:36] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[10:23:36] ====== [PASSED] drm_connector_dynamic_register_early =======
[10:23:36] ======= drm_connector_dynamic_register (7 subtests) ========
[10:23:36] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[10:23:36] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[10:23:36] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[10:23:36] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[10:23:36] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[10:23:36] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[10:23:36] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[10:23:36] ========= [PASSED] drm_connector_dynamic_register ==========
[10:23:36] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[10:23:36] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[10:23:36] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[10:23:36] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[10:23:36] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[10:23:36] ========== drm_test_get_tv_mode_from_name_valid  ===========
[10:23:36] [PASSED] NTSC
[10:23:36] [PASSED] NTSC-443
[10:23:36] [PASSED] NTSC-J
[10:23:36] [PASSED] PAL
[10:23:36] [PASSED] PAL-M
[10:23:36] [PASSED] PAL-N
[10:23:36] [PASSED] SECAM
[10:23:36] [PASSED] Mono
[10:23:36] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[10:23:36] [PASSED] drm_test_get_tv_mode_from_name_truncated
[10:23:36] ============ [PASSED] drm_get_tv_mode_from_name ============
[10:23:36] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[10:23:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[10:23:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[10:23:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[10:23:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[10:23:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[10:23:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[10:23:36] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[10:23:36] [PASSED] VIC 96
[10:23:36] [PASSED] VIC 97
[10:23:36] [PASSED] VIC 101
[10:23:36] [PASSED] VIC 102
[10:23:36] [PASSED] VIC 106
[10:23:36] [PASSED] VIC 107
[10:23:36] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[10:23:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[10:23:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[10:23:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[10:23:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[10:23:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[10:23:36] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[10:23:36] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[10:23:36] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[10:23:36] [PASSED] Automatic
[10:23:36] [PASSED] Full
[10:23:36] [PASSED] Limited 16:235
[10:23:36] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[10:23:36] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[10:23:36] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[10:23:36] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[10:23:36] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[10:23:36] [PASSED] RGB
[10:23:36] [PASSED] YUV 4:2:0
[10:23:36] [PASSED] YUV 4:2:2
[10:23:36] [PASSED] YUV 4:4:4
[10:23:36] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[10:23:36] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[10:23:36] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[10:23:36] ============= drm_damage_helper (21 subtests) ==============
[10:23:36] [PASSED] drm_test_damage_iter_no_damage
[10:23:36] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[10:23:36] [PASSED] drm_test_damage_iter_no_damage_src_moved
[10:23:36] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[10:23:36] [PASSED] drm_test_damage_iter_no_damage_not_visible
[10:23:36] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[10:23:36] [PASSED] drm_test_damage_iter_no_damage_no_fb
[10:23:36] [PASSED] drm_test_damage_iter_simple_damage
[10:23:36] [PASSED] drm_test_damage_iter_single_damage
[10:23:36] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[10:23:36] [PASSED] drm_test_damage_iter_single_damage_outside_src
[10:23:36] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[10:23:36] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[10:23:36] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[10:23:36] [PASSED] drm_test_damage_iter_single_damage_src_moved
[10:23:36] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[10:23:36] [PASSED] drm_test_damage_iter_damage
[10:23:36] [PASSED] drm_test_damage_iter_damage_one_intersect
[10:23:36] [PASSED] drm_test_damage_iter_damage_one_outside
[10:23:36] [PASSED] drm_test_damage_iter_damage_src_moved
[10:23:36] [PASSED] drm_test_damage_iter_damage_not_visible
[10:23:36] ================ [PASSED] drm_damage_helper ================
[10:23:36] ============== drm_dp_mst_helper (3 subtests) ==============
[10:23:36] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[10:23:36] [PASSED] Clock 154000 BPP 30 DSC disabled
[10:23:36] [PASSED] Clock 234000 BPP 30 DSC disabled
[10:23:36] [PASSED] Clock 297000 BPP 24 DSC disabled
[10:23:36] [PASSED] Clock 332880 BPP 24 DSC enabled
[10:23:36] [PASSED] Clock 324540 BPP 24 DSC enabled
[10:23:36] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[10:23:36] ============== drm_test_dp_mst_calc_pbn_div  ===============
[10:23:36] [PASSED] Link rate 2000000 lane count 4
[10:23:36] [PASSED] Link rate 2000000 lane count 2
[10:23:36] [PASSED] Link rate 2000000 lane count 1
[10:23:36] [PASSED] Link rate 1350000 lane count 4
[10:23:36] [PASSED] Link rate 1350000 lane count 2
[10:23:36] [PASSED] Link rate 1350000 lane count 1
[10:23:36] [PASSED] Link rate 1000000 lane count 4
[10:23:36] [PASSED] Link rate 1000000 lane count 2
[10:23:36] [PASSED] Link rate 1000000 lane count 1
[10:23:36] [PASSED] Link rate 810000 lane count 4
[10:23:36] [PASSED] Link rate 810000 lane count 2
[10:23:36] [PASSED] Link rate 810000 lane count 1
[10:23:36] [PASSED] Link rate 540000 lane count 4
[10:23:36] [PASSED] Link rate 540000 lane count 2
[10:23:36] [PASSED] Link rate 540000 lane count 1
[10:23:36] [PASSED] Link rate 270000 lane count 4
[10:23:36] [PASSED] Link rate 270000 lane count 2
[10:23:36] [PASSED] Link rate 270000 lane count 1
[10:23:36] [PASSED] Link rate 162000 lane count 4
[10:23:36] [PASSED] Link rate 162000 lane count 2
[10:23:36] [PASSED] Link rate 162000 lane count 1
[10:23:36] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[10:23:36] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[10:23:36] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[10:23:36] [PASSED] DP_POWER_UP_PHY with port number
[10:23:36] [PASSED] DP_POWER_DOWN_PHY with port number
[10:23:36] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[10:23:36] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[10:23:36] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[10:23:36] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[10:23:36] [PASSED] DP_QUERY_PAYLOAD with port number
[10:23:36] [PASSED] DP_QUERY_PAYLOAD with VCPI
[10:23:36] [PASSED] DP_REMOTE_DPCD_READ with port number
[10:23:36] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[10:23:36] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[10:23:36] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[10:23:36] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[10:23:36] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[10:23:36] [PASSED] DP_REMOTE_I2C_READ with port number
[10:23:36] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[10:23:36] [PASSED] DP_REMOTE_I2C_READ with transactions array
[10:23:36] [PASSED] DP_REMOTE_I2C_WRITE with port number
[10:23:36] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[10:23:36] [PASSED] DP_REMOTE_I2C_WRITE with data array
[10:23:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[10:23:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[10:23:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[10:23:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[10:23:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[10:23:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[10:23:36] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[10:23:36] ================ [PASSED] drm_dp_mst_helper ================
[10:23:36] ================== drm_exec (7 subtests) ===================
[10:23:36] [PASSED] sanitycheck
[10:23:36] [PASSED] test_lock
[10:23:36] [PASSED] test_lock_unlock
[10:23:36] [PASSED] test_duplicates
[10:23:36] [PASSED] test_prepare
[10:23:36] [PASSED] test_prepare_array
[10:23:36] [PASSED] test_multiple_loops
[10:23:36] ==================== [PASSED] drm_exec =====================
[10:23:36] =========== drm_format_helper_test (17 subtests) ===========
[10:23:36] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[10:23:36] [PASSED] single_pixel_source_buffer
[10:23:36] [PASSED] single_pixel_clip_rectangle
[10:23:36] [PASSED] well_known_colors
[10:23:36] [PASSED] destination_pitch
[10:23:36] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[10:23:36] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[10:23:36] [PASSED] single_pixel_source_buffer
[10:23:36] [PASSED] single_pixel_clip_rectangle
[10:23:36] [PASSED] well_known_colors
[10:23:36] [PASSED] destination_pitch
[10:23:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[10:23:36] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[10:23:36] [PASSED] single_pixel_source_buffer
[10:23:36] [PASSED] single_pixel_clip_rectangle
[10:23:36] [PASSED] well_known_colors
[10:23:36] [PASSED] destination_pitch
[10:23:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[10:23:36] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[10:23:36] [PASSED] single_pixel_source_buffer
[10:23:36] [PASSED] single_pixel_clip_rectangle
[10:23:36] [PASSED] well_known_colors
[10:23:36] [PASSED] destination_pitch
[10:23:36] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[10:23:36] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[10:23:36] [PASSED] single_pixel_source_buffer
[10:23:36] [PASSED] single_pixel_clip_rectangle
[10:23:36] [PASSED] well_known_colors
[10:23:36] [PASSED] destination_pitch
[10:23:36] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[10:23:36] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[10:23:36] [PASSED] single_pixel_source_buffer
[10:23:36] [PASSED] single_pixel_clip_rectangle
[10:23:36] [PASSED] well_known_colors
[10:23:36] [PASSED] destination_pitch
[10:23:36] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[10:23:36] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[10:23:36] [PASSED] single_pixel_source_buffer
[10:23:36] [PASSED] single_pixel_clip_rectangle
[10:23:36] [PASSED] well_known_colors
[10:23:36] [PASSED] destination_pitch
[10:23:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[10:23:36] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[10:23:36] [PASSED] single_pixel_source_buffer
[10:23:36] [PASSED] single_pixel_clip_rectangle
[10:23:36] [PASSED] well_known_colors
[10:23:36] [PASSED] destination_pitch
[10:23:36] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[10:23:36] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[10:23:36] [PASSED] single_pixel_source_buffer
[10:23:36] [PASSED] single_pixel_clip_rectangle
[10:23:36] [PASSED] well_known_colors
[10:23:36] [PASSED] destination_pitch
[10:23:36] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[10:23:36] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[10:23:36] [PASSED] single_pixel_source_buffer
[10:23:36] [PASSED] single_pixel_clip_rectangle
[10:23:36] [PASSED] well_known_colors
[10:23:36] [PASSED] destination_pitch
[10:23:36] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[10:23:36] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[10:23:36] [PASSED] single_pixel_source_buffer
[10:23:36] [PASSED] single_pixel_clip_rectangle
[10:23:36] [PASSED] well_known_colors
[10:23:36] [PASSED] destination_pitch
[10:23:36] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[10:23:36] ============== drm_test_fb_xrgb8888_to_mono  ===============
[10:23:36] [PASSED] single_pixel_source_buffer
[10:23:36] [PASSED] single_pixel_clip_rectangle
[10:23:36] [PASSED] well_known_colors
[10:23:36] [PASSED] destination_pitch
[10:23:36] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[10:23:36] ==================== drm_test_fb_swab  =====================
[10:23:36] [PASSED] single_pixel_source_buffer
[10:23:36] [PASSED] single_pixel_clip_rectangle
[10:23:36] [PASSED] well_known_colors
[10:23:36] [PASSED] destination_pitch
[10:23:36] ================ [PASSED] drm_test_fb_swab =================
[10:23:36] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[10:23:36] [PASSED] single_pixel_source_buffer
[10:23:36] [PASSED] single_pixel_clip_rectangle
[10:23:36] [PASSED] well_known_colors
[10:23:36] [PASSED] destination_pitch
[10:23:36] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[10:23:36] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[10:23:36] [PASSED] single_pixel_source_buffer
[10:23:36] [PASSED] single_pixel_clip_rectangle
[10:23:36] [PASSED] well_known_colors
[10:23:36] [PASSED] destination_pitch
[10:23:36] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[10:23:36] ================= drm_test_fb_clip_offset  =================
[10:23:36] [PASSED] pass through
[10:23:36] [PASSED] horizontal offset
[10:23:36] [PASSED] vertical offset
[10:23:36] [PASSED] horizontal and vertical offset
[10:23:36] [PASSED] horizontal offset (custom pitch)
[10:23:36] [PASSED] vertical offset (custom pitch)
[10:23:36] [PASSED] horizontal and vertical offset (custom pitch)
[10:23:36] ============= [PASSED] drm_test_fb_clip_offset =============
[10:23:36] =================== drm_test_fb_memcpy  ====================
[10:23:36] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[10:23:36] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[10:23:36] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[10:23:36] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[10:23:36] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[10:23:36] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[10:23:36] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[10:23:36] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[10:23:36] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[10:23:36] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[10:23:36] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[10:23:36] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[10:23:36] =============== [PASSED] drm_test_fb_memcpy ================
[10:23:36] ============= [PASSED] drm_format_helper_test ==============
[10:23:36] ================= drm_format (18 subtests) =================
[10:23:36] [PASSED] drm_test_format_block_width_invalid
[10:23:36] [PASSED] drm_test_format_block_width_one_plane
[10:23:36] [PASSED] drm_test_format_block_width_two_plane
[10:23:36] [PASSED] drm_test_format_block_width_three_plane
[10:23:36] [PASSED] drm_test_format_block_width_tiled
[10:23:36] [PASSED] drm_test_format_block_height_invalid
[10:23:36] [PASSED] drm_test_format_block_height_one_plane
[10:23:36] [PASSED] drm_test_format_block_height_two_plane
[10:23:36] [PASSED] drm_test_format_block_height_three_plane
[10:23:36] [PASSED] drm_test_format_block_height_tiled
[10:23:36] [PASSED] drm_test_format_min_pitch_invalid
[10:23:36] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[10:23:36] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[10:23:36] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[10:23:36] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[10:23:36] [PASSED] drm_test_format_min_pitch_two_plane
[10:23:36] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[10:23:36] [PASSED] drm_test_format_min_pitch_tiled
[10:23:36] =================== [PASSED] drm_format ====================
[10:23:36] ============== drm_framebuffer (10 subtests) ===============
[10:23:36] ========== drm_test_framebuffer_check_src_coords  ==========
[10:23:36] [PASSED] Success: source fits into fb
[10:23:36] [PASSED] Fail: overflowing fb with x-axis coordinate
[10:23:36] [PASSED] Fail: overflowing fb with y-axis coordinate
[10:23:36] [PASSED] Fail: overflowing fb with source width
[10:23:36] [PASSED] Fail: overflowing fb with source height
[10:23:36] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[10:23:36] [PASSED] drm_test_framebuffer_cleanup
[10:23:36] =============== drm_test_framebuffer_create  ===============
[10:23:36] [PASSED] ABGR8888 normal sizes
[10:23:36] [PASSED] ABGR8888 max sizes
[10:23:36] [PASSED] ABGR8888 pitch greater than min required
[10:23:36] [PASSED] ABGR8888 pitch less than min required
[10:23:36] [PASSED] ABGR8888 Invalid width
[10:23:36] [PASSED] ABGR8888 Invalid buffer handle
[10:23:36] [PASSED] No pixel format
[10:23:36] [PASSED] ABGR8888 Width 0
[10:23:36] [PASSED] ABGR8888 Height 0
[10:23:36] [PASSED] ABGR8888 Out of bound height * pitch combination
[10:23:36] [PASSED] ABGR8888 Large buffer offset
[10:23:36] [PASSED] ABGR8888 Buffer offset for inexistent plane
[10:23:36] [PASSED] ABGR8888 Invalid flag
[10:23:36] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[10:23:36] [PASSED] ABGR8888 Valid buffer modifier
[10:23:36] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[10:23:36] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[10:23:36] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[10:23:36] [PASSED] NV12 Normal sizes
[10:23:36] [PASSED] NV12 Max sizes
[10:23:36] [PASSED] NV12 Invalid pitch
[10:23:36] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[10:23:36] [PASSED] NV12 different  modifier per-plane
[10:23:36] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[10:23:36] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[10:23:36] [PASSED] NV12 Modifier for inexistent plane
[10:23:36] [PASSED] NV12 Handle for inexistent plane
[10:23:36] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[10:23:36] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[10:23:36] [PASSED] YVU420 Normal sizes
[10:23:36] [PASSED] YVU420 Max sizes
[10:23:36] [PASSED] YVU420 Invalid pitch
[10:23:36] [PASSED] YVU420 Different pitches
[10:23:36] [PASSED] YVU420 Different buffer offsets/pitches
[10:23:36] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[10:23:36] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[10:23:36] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[10:23:36] [PASSED] YVU420 Valid modifier
[10:23:36] [PASSED] YVU420 Different modifiers per plane
[10:23:36] [PASSED] YVU420 Modifier for inexistent plane
[10:23:36] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[10:23:36] [PASSED] X0L2 Normal sizes
[10:23:36] [PASSED] X0L2 Max sizes
[10:23:36] [PASSED] X0L2 Invalid pitch
[10:23:36] [PASSED] X0L2 Pitch greater than minimum required
[10:23:36] [PASSED] X0L2 Handle for inexistent plane
[10:23:36] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[10:23:36] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[10:23:36] [PASSED] X0L2 Valid modifier
[10:23:36] [PASSED] X0L2 Modifier for inexistent plane
[10:23:36] =========== [PASSED] drm_test_framebuffer_create ===========
[10:23:36] [PASSED] drm_test_framebuffer_free
[10:23:36] [PASSED] drm_test_framebuffer_init
[10:23:36] [PASSED] drm_test_framebuffer_init_bad_format
[10:23:36] [PASSED] drm_test_framebuffer_init_dev_mismatch
[10:23:36] [PASSED] drm_test_framebuffer_lookup
[10:23:36] [PASSED] drm_test_framebuffer_lookup_inexistent
[10:23:36] [PASSED] drm_test_framebuffer_modifiers_not_supported
[10:23:36] ================= [PASSED] drm_framebuffer =================
[10:23:36] ================ drm_gem_shmem (8 subtests) ================
[10:23:36] [PASSED] drm_gem_shmem_test_obj_create
[10:23:36] [PASSED] drm_gem_shmem_test_obj_create_private
[10:23:36] [PASSED] drm_gem_shmem_test_pin_pages
[10:23:36] [PASSED] drm_gem_shmem_test_vmap
[10:23:36] [PASSED] drm_gem_shmem_test_get_sg_table
[10:23:36] [PASSED] drm_gem_shmem_test_get_pages_sgt
[10:23:36] [PASSED] drm_gem_shmem_test_madvise
[10:23:36] [PASSED] drm_gem_shmem_test_purge
[10:23:36] ================== [PASSED] drm_gem_shmem ==================
[10:23:36] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[10:23:36] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[10:23:36] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[10:23:36] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[10:23:36] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[10:23:36] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[10:23:36] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[10:23:36] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[10:23:36] [PASSED] Automatic
[10:23:36] [PASSED] Full
[10:23:36] [PASSED] Limited 16:235
[10:23:36] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[10:23:36] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[10:23:36] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[10:23:36] [PASSED] drm_test_check_disable_connector
[10:23:36] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[10:23:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[10:23:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[10:23:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[10:23:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[10:23:36] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[10:23:36] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[10:23:36] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[10:23:36] [PASSED] drm_test_check_output_bpc_dvi
[10:23:36] [PASSED] drm_test_check_output_bpc_format_vic_1
[10:23:36] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[10:23:36] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[10:23:36] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[10:23:36] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[10:23:36] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[10:23:36] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[10:23:36] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[10:23:36] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[10:23:36] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[10:23:36] [PASSED] drm_test_check_broadcast_rgb_value
[10:23:36] [PASSED] drm_test_check_bpc_8_value
[10:23:36] [PASSED] drm_test_check_bpc_10_value
[10:23:36] [PASSED] drm_test_check_bpc_12_value
[10:23:36] [PASSED] drm_test_check_format_value
[10:23:36] [PASSED] drm_test_check_tmds_char_value
[10:23:36] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[10:23:36] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[10:23:36] [PASSED] drm_test_check_mode_valid
[10:23:36] [PASSED] drm_test_check_mode_valid_reject
[10:23:36] [PASSED] drm_test_check_mode_valid_reject_rate
[10:23:36] [PASSED] drm_test_check_mode_valid_reject_max_clock
[10:23:36] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[10:23:36] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[10:23:36] [PASSED] drm_test_check_infoframes
[10:23:36] [PASSED] drm_test_check_reject_avi_infoframe
[10:23:36] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[10:23:36] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[10:23:36] [PASSED] drm_test_check_reject_audio_infoframe
[10:23:36] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[10:23:36] ================= drm_managed (2 subtests) =================
[10:23:36] [PASSED] drm_test_managed_release_action
[10:23:36] [PASSED] drm_test_managed_run_action
[10:23:36] =================== [PASSED] drm_managed ===================
[10:23:36] =================== drm_mm (6 subtests) ====================
[10:23:36] [PASSED] drm_test_mm_init
[10:23:36] [PASSED] drm_test_mm_debug
[10:23:36] [PASSED] drm_test_mm_align32
[10:23:36] [PASSED] drm_test_mm_align64
[10:23:36] [PASSED] drm_test_mm_lowest
[10:23:36] [PASSED] drm_test_mm_highest
[10:23:36] ===================== [PASSED] drm_mm ======================
[10:23:36] ============= drm_modes_analog_tv (5 subtests) =============
[10:23:36] [PASSED] drm_test_modes_analog_tv_mono_576i
[10:23:36] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[10:23:36] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[10:23:36] [PASSED] drm_test_modes_analog_tv_pal_576i
[10:23:36] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[10:23:36] =============== [PASSED] drm_modes_analog_tv ===============
[10:23:36] ============== drm_plane_helper (2 subtests) ===============
[10:23:36] =============== drm_test_check_plane_state  ================
[10:23:36] [PASSED] clipping_simple
[10:23:36] [PASSED] clipping_rotate_reflect
[10:23:36] [PASSED] positioning_simple
[10:23:36] [PASSED] upscaling
[10:23:36] [PASSED] downscaling
[10:23:36] [PASSED] rounding1
[10:23:36] [PASSED] rounding2
[10:23:36] [PASSED] rounding3
[10:23:36] [PASSED] rounding4
[10:23:36] =========== [PASSED] drm_test_check_plane_state ============
[10:23:36] =========== drm_test_check_invalid_plane_state  ============
[10:23:36] [PASSED] positioning_invalid
[10:23:36] [PASSED] upscaling_invalid
[10:23:36] [PASSED] downscaling_invalid
[10:23:36] ======= [PASSED] drm_test_check_invalid_plane_state ========
[10:23:36] ================ [PASSED] drm_plane_helper =================
[10:23:36] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[10:23:36] ====== drm_test_connector_helper_tv_get_modes_check  =======
[10:23:36] [PASSED] None
[10:23:36] [PASSED] PAL
[10:23:36] [PASSED] NTSC
[10:23:36] [PASSED] Both, NTSC Default
[10:23:36] [PASSED] Both, PAL Default
[10:23:36] [PASSED] Both, NTSC Default, with PAL on command-line
[10:23:36] [PASSED] Both, PAL Default, with NTSC on command-line
[10:23:36] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[10:23:36] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[10:23:36] ================== drm_rect (9 subtests) ===================
[10:23:36] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[10:23:36] [PASSED] drm_test_rect_clip_scaled_not_clipped
[10:23:36] [PASSED] drm_test_rect_clip_scaled_clipped
[10:23:36] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[10:23:36] ================= drm_test_rect_intersect  =================
[10:23:36] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[10:23:36] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[10:23:36] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[10:23:36] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[10:23:36] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[10:23:36] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[10:23:36] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[10:23:36] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[10:23:36] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[10:23:36] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[10:23:36] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[10:23:36] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[10:23:36] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[10:23:36] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[10:23:36] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
stty: 'standard input': Inappropriate ioctl for device
[10:23:36] ============= [PASSED] drm_test_rect_intersect =============
[10:23:36] ================ drm_test_rect_calc_hscale  ================
[10:23:36] [PASSED] normal use
[10:23:36] [PASSED] out of max range
[10:23:36] [PASSED] out of min range
[10:23:36] [PASSED] zero dst
[10:23:36] [PASSED] negative src
[10:23:36] [PASSED] negative dst
[10:23:36] ============ [PASSED] drm_test_rect_calc_hscale ============
[10:23:36] ================ drm_test_rect_calc_vscale  ================
[10:23:36] [PASSED] normal use
[10:23:36] [PASSED] out of max range
[10:23:36] [PASSED] out of min range
[10:23:36] [PASSED] zero dst
[10:23:36] [PASSED] negative src
[10:23:36] [PASSED] negative dst
[10:23:36] ============ [PASSED] drm_test_rect_calc_vscale ============
[10:23:36] ================== drm_test_rect_rotate  ===================
[10:23:36] [PASSED] reflect-x
[10:23:36] [PASSED] reflect-y
[10:23:36] [PASSED] rotate-0
[10:23:36] [PASSED] rotate-90
[10:23:36] [PASSED] rotate-180
[10:23:36] [PASSED] rotate-270
[10:23:36] ============== [PASSED] drm_test_rect_rotate ===============
[10:23:36] ================ drm_test_rect_rotate_inv  =================
[10:23:36] [PASSED] reflect-x
[10:23:36] [PASSED] reflect-y
[10:23:36] [PASSED] rotate-0
[10:23:36] [PASSED] rotate-90
[10:23:36] [PASSED] rotate-180
[10:23:36] [PASSED] rotate-270
[10:23:36] ============ [PASSED] drm_test_rect_rotate_inv =============
[10:23:36] ==================== [PASSED] drm_rect =====================
[10:23:36] ============ drm_sysfb_modeset_test (1 subtest) ============
[10:23:36] ============ drm_test_sysfb_build_fourcc_list  =============
[10:23:36] [PASSED] no native formats
[10:23:36] [PASSED] XRGB8888 as native format
[10:23:36] [PASSED] remove duplicates
[10:23:36] [PASSED] convert alpha formats
[10:23:36] [PASSED] random formats
[10:23:36] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[10:23:36] ============= [PASSED] drm_sysfb_modeset_test ==============
[10:23:36] ================== drm_fixp (2 subtests) ===================
[10:23:36] [PASSED] drm_test_int2fixp
[10:23:36] [PASSED] drm_test_sm2fixp
[10:23:36] ==================== [PASSED] drm_fixp =====================
[10:23:36] ============================================================
[10:23:36] Testing complete. Ran 630 tests: passed: 630
[10:23:36] Elapsed time: 32.731s total, 1.595s configuring, 30.668s building, 0.453s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[10:23:36] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:23:38] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[10:23:47] Starting KUnit Kernel (1/1)...
[10:23:47] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[10:23:47] ================= ttm_device (5 subtests) ==================
[10:23:47] [PASSED] ttm_device_init_basic
[10:23:47] [PASSED] ttm_device_init_multiple
[10:23:47] [PASSED] ttm_device_fini_basic
[10:23:47] [PASSED] ttm_device_init_no_vma_man
[10:23:47] ================== ttm_device_init_pools  ==================
[10:23:47] [PASSED] No DMA allocations, no DMA32 required
[10:23:47] [PASSED] DMA allocations, DMA32 required
[10:23:47] [PASSED] No DMA allocations, DMA32 required
[10:23:47] [PASSED] DMA allocations, no DMA32 required
[10:23:47] ============== [PASSED] ttm_device_init_pools ==============
[10:23:47] =================== [PASSED] ttm_device ====================
[10:23:47] ================== ttm_pool (8 subtests) ===================
[10:23:47] ================== ttm_pool_alloc_basic  ===================
[10:23:47] [PASSED] One page
[10:23:47] [PASSED] More than one page
[10:23:47] [PASSED] Above the allocation limit
[10:23:47] [PASSED] One page, with coherent DMA mappings enabled
[10:23:47] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:23:47] ============== [PASSED] ttm_pool_alloc_basic ===============
[10:23:47] ============== ttm_pool_alloc_basic_dma_addr  ==============
[10:23:47] [PASSED] One page
[10:23:47] [PASSED] More than one page
[10:23:47] [PASSED] Above the allocation limit
[10:23:47] [PASSED] One page, with coherent DMA mappings enabled
[10:23:47] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[10:23:47] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[10:23:47] [PASSED] ttm_pool_alloc_order_caching_match
[10:23:47] [PASSED] ttm_pool_alloc_caching_mismatch
[10:23:47] [PASSED] ttm_pool_alloc_order_mismatch
[10:23:47] [PASSED] ttm_pool_free_dma_alloc
[10:23:47] [PASSED] ttm_pool_free_no_dma_alloc
[10:23:47] [PASSED] ttm_pool_fini_basic
[10:23:47] ==================== [PASSED] ttm_pool =====================
[10:23:47] ================ ttm_resource (8 subtests) =================
[10:23:47] ================= ttm_resource_init_basic  =================
[10:23:47] [PASSED] Init resource in TTM_PL_SYSTEM
[10:23:47] [PASSED] Init resource in TTM_PL_VRAM
[10:23:47] [PASSED] Init resource in a private placement
[10:23:47] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[10:23:47] ============= [PASSED] ttm_resource_init_basic =============
[10:23:47] [PASSED] ttm_resource_init_pinned
[10:23:47] [PASSED] ttm_resource_fini_basic
[10:23:47] [PASSED] ttm_resource_manager_init_basic
[10:23:47] [PASSED] ttm_resource_manager_usage_basic
[10:23:47] [PASSED] ttm_resource_manager_set_used_basic
[10:23:47] [PASSED] ttm_sys_man_alloc_basic
[10:23:47] [PASSED] ttm_sys_man_free_basic
[10:23:47] ================== [PASSED] ttm_resource ===================
[10:23:47] =================== ttm_tt (15 subtests) ===================
[10:23:47] ==================== ttm_tt_init_basic  ====================
[10:23:47] [PASSED] Page-aligned size
[10:23:47] [PASSED] Extra pages requested
[10:23:47] ================ [PASSED] ttm_tt_init_basic ================
[10:23:47] [PASSED] ttm_tt_init_misaligned
[10:23:47] [PASSED] ttm_tt_fini_basic
[10:23:47] [PASSED] ttm_tt_fini_sg
[10:23:47] [PASSED] ttm_tt_fini_shmem
[10:23:47] [PASSED] ttm_tt_create_basic
[10:23:47] [PASSED] ttm_tt_create_invalid_bo_type
[10:23:47] [PASSED] ttm_tt_create_ttm_exists
[10:23:47] [PASSED] ttm_tt_create_failed
[10:23:47] [PASSED] ttm_tt_destroy_basic
[10:23:47] [PASSED] ttm_tt_populate_null_ttm
[10:23:47] [PASSED] ttm_tt_populate_populated_ttm
[10:23:47] [PASSED] ttm_tt_unpopulate_basic
[10:23:47] [PASSED] ttm_tt_unpopulate_empty_ttm
[10:23:47] [PASSED] ttm_tt_swapin_basic
[10:23:47] ===================== [PASSED] ttm_tt ======================
[10:23:47] =================== ttm_bo (14 subtests) ===================
[10:23:47] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[10:23:47] [PASSED] Cannot be interrupted and sleeps
[10:23:47] [PASSED] Cannot be interrupted, locks straight away
[10:23:47] [PASSED] Can be interrupted, sleeps
[10:23:47] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[10:23:47] [PASSED] ttm_bo_reserve_locked_no_sleep
[10:23:47] [PASSED] ttm_bo_reserve_no_wait_ticket
[10:23:47] [PASSED] ttm_bo_reserve_double_resv
[10:23:47] [PASSED] ttm_bo_reserve_interrupted
[10:23:47] [PASSED] ttm_bo_reserve_deadlock
[10:23:47] [PASSED] ttm_bo_unreserve_basic
[10:23:47] [PASSED] ttm_bo_unreserve_pinned
[10:23:47] [PASSED] ttm_bo_unreserve_bulk
[10:23:47] [PASSED] ttm_bo_fini_basic
[10:23:47] [PASSED] ttm_bo_fini_shared_resv
[10:23:47] [PASSED] ttm_bo_pin_basic
[10:23:47] [PASSED] ttm_bo_pin_unpin_resource
[10:23:47] [PASSED] ttm_bo_multiple_pin_one_unpin
[10:23:47] ===================== [PASSED] ttm_bo ======================
[10:23:47] ============== ttm_bo_validate (21 subtests) ===============
[10:23:47] ============== ttm_bo_init_reserved_sys_man  ===============
[10:23:47] [PASSED] Buffer object for userspace
[10:23:47] [PASSED] Kernel buffer object
[10:23:47] [PASSED] Shared buffer object
[10:23:47] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[10:23:47] ============== ttm_bo_init_reserved_mock_man  ==============
[10:23:47] [PASSED] Buffer object for userspace
[10:23:47] [PASSED] Kernel buffer object
[10:23:47] [PASSED] Shared buffer object
[10:23:47] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[10:23:47] [PASSED] ttm_bo_init_reserved_resv
[10:23:47] ================== ttm_bo_validate_basic  ==================
[10:23:47] [PASSED] Buffer object for userspace
[10:23:47] [PASSED] Kernel buffer object
[10:23:47] [PASSED] Shared buffer object
[10:23:47] ============== [PASSED] ttm_bo_validate_basic ==============
[10:23:47] [PASSED] ttm_bo_validate_invalid_placement
[10:23:47] ============= ttm_bo_validate_same_placement  ==============
[10:23:47] [PASSED] System manager
[10:23:47] [PASSED] VRAM manager
[10:23:47] ========= [PASSED] ttm_bo_validate_same_placement ==========
[10:23:47] [PASSED] ttm_bo_validate_failed_alloc
[10:23:47] [PASSED] ttm_bo_validate_pinned
[10:23:47] [PASSED] ttm_bo_validate_busy_placement
[10:23:47] ================ ttm_bo_validate_multihop  =================
[10:23:47] [PASSED] Buffer object for userspace
[10:23:47] [PASSED] Kernel buffer object
[10:23:47] [PASSED] Shared buffer object
[10:23:47] ============ [PASSED] ttm_bo_validate_multihop =============
[10:23:47] ========== ttm_bo_validate_no_placement_signaled  ==========
[10:23:47] [PASSED] Buffer object in system domain, no page vector
[10:23:47] [PASSED] Buffer object in system domain with an existing page vector
[10:23:47] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[10:23:47] ======== ttm_bo_validate_no_placement_not_signaled  ========
[10:23:47] [PASSED] Buffer object for userspace
[10:23:47] [PASSED] Kernel buffer object
[10:23:47] [PASSED] Shared buffer object
[10:23:47] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[10:23:47] [PASSED] ttm_bo_validate_move_fence_signaled
[10:23:47] ========= ttm_bo_validate_move_fence_not_signaled  =========
[10:23:47] [PASSED] Waits for GPU
[10:23:47] [PASSED] Tries to lock straight away
[10:23:47] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[10:23:47] [PASSED] ttm_bo_validate_happy_evict
[10:23:47] [PASSED] ttm_bo_validate_all_pinned_evict
[10:23:47] [PASSED] ttm_bo_validate_allowed_only_evict
[10:23:47] [PASSED] ttm_bo_validate_deleted_evict
[10:23:47] [PASSED] ttm_bo_validate_busy_domain_evict
[10:23:47] [PASSED] ttm_bo_validate_evict_gutting
[10:23:47] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[10:23:47] ================= [PASSED] ttm_bo_validate =================
[10:23:47] ============================================================
[10:23:47] Testing complete. Ran 101 tests: passed: 101
[10:23:47] Elapsed time: 11.106s total, 1.615s configuring, 9.275s building, 0.184s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for Make Display free from i915_reg.h (rev4)

[Patchwork]

== Series Details ==

Series: Make Display free from i915_reg.h (rev4)
URL   : https://patchwork.freedesktop.org/series/159130/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 05230cfcdb1abc225c8e085cd4de470c4b97232f
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/g4x_dp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/g4x_hdmi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/i9xx_wm.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_combo_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_crt.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_cx0_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_device.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_irq.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_display_power_map.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_power_well.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_display_rps.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_hdcp.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpio_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpll.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpll_mgr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_mst.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dpt_common.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dp_test.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_drrs.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsb.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dsi_vbt.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_dvo.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_fbc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_fifo_underrun.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_gmbus.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_hdmi.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_lspcon.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_modeset_setup.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_overlay.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pch_display.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pch_refclk.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pfit.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pipe_crc.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_pmdemand.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_sdvo.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_snps_phy.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_tv.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vblank.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/intel_vrr.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/display/skl_scaler.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h, drivers/gpu/drm/i915/display/intel_display_trace.h):
+drivers/gpu/drm/i915/display/skl_universal_plane.c: note: in included file (through drivers/gpu/drm/i915/display/intel_display_types.h):
+drivers/gpu/drm/i915/gt/intel_reset.c:1569:12: warning: context imbalance in '_intel_gt_reset_lock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_sseu.c:600:17: error: too long token expansion
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:191:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:192:1: error: bad constant expression
+drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c:193:1: error: bad constant expression
+drivers/gpu/drm/i915/i915_irq.c:468:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:468:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:476:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:476:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:481:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:481:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:481:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:519:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:519:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:527:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:527:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:532:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:532:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:532:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:576:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:576:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:579:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:579:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:583:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:583:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:590:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:590:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:590:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:590:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1932:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1933:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1999:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2000:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2021:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2022:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression
+./include/linux/pwm.h:13:1: error: bad constant expression

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Make Display free from i915_reg.h (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1420 bytes --]

== Series Details ==

Series: Make Display free from i915_reg.h (rev4)
URL   : https://patchwork.freedesktop.org/series/159130/
State : success

== Summary ==

CI Bug Log - changes from xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441_BAT -> xe-pw-159130v4_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 11)
------------------------------

  Additional (1): bat-bmg-3 

Known issues
------------

  Here are the changes found in xe-pw-159130v4_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p:
    - bat-bmg-3:          NOTRUN -> [SKIP][1] ([Intel XE#6566]) +3 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/bat-bmg-3/igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p.html

  
  [Intel XE#6566]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6566


Build changes
-------------

  * Linux: xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441 -> xe-pw-159130v4

  IGT_8738: b3fc8fb534a27517f2a49e63ef993e7550b9b959 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441: 461a70dd5bd9b765de46c7f57d299d6d92d2f441
  xe-pw-159130v4: 159130v4

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/index.html

[-- Attachment #2: Type: text/html, Size: 1984 bytes --]

✓ Xe.CI.FULL: success for Make Display free from i915_reg.h (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30396 bytes --]

== Series Details ==

Series: Make Display free from i915_reg.h (rev4)
URL   : https://patchwork.freedesktop.org/series/159130/
State : success

== Summary ==

CI Bug Log - changes from xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441_FULL -> xe-pw-159130v4_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-159130v4_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][1] ([Intel XE#7059])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][2] ([Intel XE#2327])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#1124]) +1 other test skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#607])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
    - shard-bmg:          [PASS][5] -> [SKIP][6] ([Intel XE#2314] / [Intel XE#2894])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-9/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-5/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2314] / [Intel XE#2894]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-6/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2887]) +4 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs.html

  * igt@kms_chamelium_color@ctm-0-50:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2325]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_chamelium_color@ctm-0-50.html

  * igt@kms_chamelium_hpd@dp-hpd-after-hibernate:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#2252]) +3 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_chamelium_hpd@dp-hpd-after-hibernate.html

  * igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][11] ([Intel XE#3304])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-10/igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2.html

  * igt@kms_content_protection@legacy:
    - shard-bmg:          NOTRUN -> [FAIL][12] ([Intel XE#1178] / [Intel XE#3304]) +2 other tests fail
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@uevent@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][13] ([Intel XE#6707])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-10/igt@kms_content_protection@uevent@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-offscreen-32x10:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2320])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_cursor_crc@cursor-offscreen-32x10.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-bmg:          [PASS][15] -> [SKIP][16] ([Intel XE#2291]) +3 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-9/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2244])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-10/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_feature_discovery@chamelium:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2372])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-6/igt@kms_feature_discovery@chamelium.html

  * igt@kms_flip@2x-dpms-vs-vblank-race:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2316])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-6/igt@kms_flip@2x-dpms-vs-vblank-race.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-bmg:          [PASS][20] -> [SKIP][21] ([Intel XE#2316]) +7 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-9/igt@kms_flip@2x-plain-flip-fb-recreate.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-5/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@flip-vs-suspend@c-hdmi-a3:
    - shard-bmg:          [PASS][22] -> [INCOMPLETE][23] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-5/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-2/igt@kms_flip@flip-vs-suspend@c-hdmi-a3.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#7178])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#4141]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2311]) +7 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#7061]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2313]) +10 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2312]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][30] -> [SKIP][31] ([Intel XE#1503])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-1/igt@kms_hdr@invalid-hdr.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-4/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#7086])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-6/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#7111] / [Intel XE#7130] / [Intel XE#7131])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping@pipe-a-plane-0:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#7130]) +3 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping@pipe-a-plane-0.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping@pipe-a-plane-5:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#7131])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping@pipe-a-plane-5.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping@pipe-b-plane-5:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#7111] / [Intel XE#7131])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping@pipe-b-plane-5.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-bmg:          [PASS][37] -> [SKIP][38] ([Intel XE#4596])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-7/igt@kms_plane_multiple@2x-tiling-none.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#1406] / [Intel XE#2387])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@fbc-pr-sprite-plane-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-6/igt@kms_psr@fbc-pr-sprite-plane-onoff.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-bmg:          [PASS][42] -> [SKIP][43] ([Intel XE#1435])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-9/igt@kms_setmode@invalid-clone-single-crtc.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-5/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_vrr@negative-basic:
    - shard-bmg:          [PASS][44] -> [SKIP][45] ([Intel XE#1499])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-9/igt@kms_vrr@negative-basic.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-5/igt@kms_vrr@negative-basic.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [PASS][46] -> [FAIL][47] ([Intel XE#2142]) +1 other test fail
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-lnl-5/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-lnl-2/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  * igt@xe_eudebug@multigpu-basic-client:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#4837]) +2 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@xe_eudebug@multigpu-basic-client.html

  * igt@xe_evict@evict-small-external-multi-queue-cm:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#7140])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-6/igt@xe_evict@evict-small-external-multi-queue-cm.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#2322]) +2 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-rebind.html

  * igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-imm:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#7136]) +5 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-6/igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-imm.html

  * igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-dyn-priority-smem:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#6874]) +12 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@xe_exec_multi_queue@two-queues-preempt-mode-fault-dyn-priority-smem.html

  * igt@xe_exec_system_allocator@process-many-execqueues-mmap-free-huge:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#4943]) +6 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@xe_exec_system_allocator@process-many-execqueues-mmap-free-huge.html

  * igt@xe_exec_threads@threads-multi-queue-fd-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#7138]) +4 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-10/igt@xe_exec_threads@threads-multi-queue-fd-userptr-invalidate-race.html

  * igt@xe_multigpu_svm@mgpu-coherency-fail-basic:
    - shard-bmg:          NOTRUN -> [SKIP][55] ([Intel XE#6964]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@xe_multigpu_svm@mgpu-coherency-fail-basic.html

  * igt@xe_pxp@regular-src-to-pxp-dest-rendercopy:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#4733])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-10/igt@xe_pxp@regular-src-to-pxp-dest-rendercopy.html

  
#### Possible fixes ####

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-bmg:          [INCOMPLETE][57] ([Intel XE#6819] / [Intel XE#6891] / [Intel XE#6904]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-dp-2:
    - shard-bmg:          [INCOMPLETE][59] ([Intel XE#6819]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-dp-2.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-a-dp-2.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-bmg:          [SKIP][61] ([Intel XE#2291]) -> [PASS][62] +1 other test pass
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-bmg:          [SKIP][63] ([Intel XE#2316]) -> [PASS][64] +4 other tests pass
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-5/igt@kms_flip@2x-blocking-wf_vblank.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-10/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [FAIL][65] ([Intel XE#301]) -> [PASS][66] +1 other test pass
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-bmg:          [DMESG-WARN][67] ([Intel XE#3428] / [Intel XE#5208]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-3/igt@kms_flip@flip-vs-suspend-interruptible.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-5/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a3:
    - shard-bmg:          [DMESG-WARN][69] ([Intel XE#3428]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-3/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a3.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-5/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a3.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-bmg:          [SKIP][71] ([Intel XE#1503]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-5/igt@kms_hdr@invalid-metadata-sizes.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-1/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-bmg:          [SKIP][73] ([Intel XE#4596]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-4.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-1/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][75] ([Intel XE#6321]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-4/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-1/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma:
    - shard-lnl:          [FAIL][77] ([Intel XE#5625]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-lnl-3/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-lnl-6/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html

  * igt@xe_pm@s4-exec-after:
    - shard-lnl:          [DMESG-WARN][79] -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-lnl-3/igt@xe_pm@s4-exec-after.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-lnl-6/igt@xe_pm@s4-exec-after.html

  
#### Warnings ####

  * igt@kms_content_protection@atomic:
    - shard-bmg:          [SKIP][81] ([Intel XE#2341]) -> [FAIL][82] ([Intel XE#1178] / [Intel XE#3304])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-6/igt@kms_content_protection@atomic.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-8/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@atomic-dpms-hdcp14:
    - shard-bmg:          [SKIP][83] ([Intel XE#7194]) -> [FAIL][84] ([Intel XE#3304])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-5/igt@kms_content_protection@atomic-dpms-hdcp14.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-10/igt@kms_content_protection@atomic-dpms-hdcp14.html

  * igt@kms_content_protection@uevent:
    - shard-bmg:          [SKIP][85] ([Intel XE#2341]) -> [FAIL][86] ([Intel XE#6707])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-5/igt@kms_content_protection@uevent.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-10/igt@kms_content_protection@uevent.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][87] ([Intel XE#4141]) -> [SKIP][88] ([Intel XE#2312]) +6 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          [SKIP][89] ([Intel XE#2312]) -> [SKIP][90] ([Intel XE#4141]) +3 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt:
    - shard-bmg:          [SKIP][91] ([Intel XE#2312]) -> [SKIP][92] ([Intel XE#2311]) +10 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render:
    - shard-bmg:          [SKIP][93] ([Intel XE#2311]) -> [SKIP][94] ([Intel XE#2312]) +16 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          [SKIP][95] ([Intel XE#2312]) -> [SKIP][96] ([Intel XE#2313]) +10 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][97] ([Intel XE#2313]) -> [SKIP][98] ([Intel XE#2312]) +15 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-9/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][99] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][100] ([Intel XE#3544])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-bmg:          [SKIP][101] ([Intel XE#4596]) -> [SKIP][102] ([Intel XE#5021])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-y.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-y.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2372
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3428
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
  [Intel XE#6819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6819
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6891]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6891
  [Intel XE#6904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6904
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7086]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7086
  [Intel XE#7111]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7111
  [Intel XE#7130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7130
  [Intel XE#7131]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7131
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7194]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7194


Build changes
-------------

  * Linux: xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441 -> xe-pw-159130v4

  IGT_8738: b3fc8fb534a27517f2a49e63ef993e7550b9b959 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4504-461a70dd5bd9b765de46c7f57d299d6d92d2f441: 461a70dd5bd9b765de46c7f57d299d6d92d2f441
  xe-pw-159130v4: 159130v4

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159130v4/index.html

[-- Attachment #2: Type: text/html, Size: 34957 bytes --]

Re: [v4 05/20] drm/{i915, xe}: Extract pcode definitions to common header

[Jani Nikula]

On Thu, 05 Feb 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> There are certain register definitions which are commonly shared
> by i915, xe and display. Extract the same to a common header to
> avoid duplication.
>
> Move GEN6_PCODE_MAILBOX to common pcode header to make intel_cdclk.c
> free from including i915_reg.h.
>
> v3: Include pcode header as required, instead in i915_reg.h (Jani)
>
> v2: Make the header granular and per feature (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


-- 
Jani Nikula, Intel

Re: [v4 07/20] drm/i915: Move GMD_ID and mask to intel_gt header

[Jani Nikula]

On Thu, 05 Feb 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> GMD_ID* is relevant only for GT, hence moving the same
> together in gt/intel_gt_regs.h
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++
>  drivers/gpu/drm/i915/i915_reg.h         | 4 ----
>  2 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 7421ed18d8d1..14d31882e9e7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -61,6 +61,9 @@
>  
>  #define GMD_ID_GRAPHICS				_MMIO(0xd8c)
>  #define GMD_ID_MEDIA				_MMIO(MTL_MEDIA_GSI_BASE + 0xd8c)
> +#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
> +#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
> +#define   GMD_ID_STEP				REG_GENMASK(5, 0)
>  
>  #define MCFG_MCR_SELECTOR			_MMIO(0xfd0)
>  #define MTL_STEER_SEMAPHORE			_MMIO(0xfd0)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 90a5c60e7667..b12c6bf68a2c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -922,10 +922,6 @@
>  #define   MASK_WAKEMEM				REG_BIT(13)
>  #define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
>  
> -#define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
> -#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
> -#define   GMD_ID_STEP				REG_GENMASK(5, 0)
> -
>  /* PCH */
>  
>  #define SDEISR  _MMIO(0xc4000)

-- 
Jani Nikula, Intel

Re: [v4 08/20] drm/i915: Remove i915_reg.h from intel_dram.c

[Jani Nikula]

On Thu, 05 Feb 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Make intel_dram.c free from including i915_reg.h.
>
> v3: Move MEM_SS info reg to display instead of pcode header (Jani)
>
> v2: Move mem config register to newly added pcode header (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_regs.h | 6 ++++++
>  drivers/gpu/drm/i915/display/intel_dram.c         | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h                   | 6 ------
>  3 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index c598ccb3c78b..42aef6300320 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -3075,6 +3075,12 @@ enum skl_power_gate {
>  #define MTL_PIPE_CLKGATE_DIS2(pipe)		_MMIO_PIPE(pipe, _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B)
>  #define   MTL_DPFC_GATING_DIS			REG_BIT(6)
>  
> +#define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
> +#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
> +#define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
> +#define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
> +#define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
> +
>  #define MTL_MEM_SS_INFO_QGV_POINT_OFFSET	0x45710
>  #define MTL_MEM_SS_INFO_QGV_POINT_LOW(point)	_MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8)
>  #define   MTL_TRCD_MASK			REG_GENMASK(31, 24)
> diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c
> index 61aefe77f90f..bd281d4b4c05 100644
> --- a/drivers/gpu/drm/i915/display/intel_dram.c
> +++ b/drivers/gpu/drm/i915/display/intel_dram.c
> @@ -9,9 +9,9 @@
>  #include <drm/drm_print.h>
>  #include <drm/intel/intel_pcode_regs.h>
>  
> -#include "i915_reg.h"
>  #include "intel_display_core.h"
>  #include "intel_display_utils.h"
> +#include "intel_display_regs.h"
>  #include "intel_dram.h"
>  #include "intel_mchbar_regs.h"
>  #include "intel_parent.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b12c6bf68a2c..e905250f4fa5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1005,12 +1005,6 @@
>  #define OROM_OFFSET				_MMIO(0x1020c0)
>  #define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
>  
> -#define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
> -#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
> -#define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
> -#define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
> -#define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
> -
>  #define MTL_MEDIA_GSI_BASE		0x380000
>  
>  #endif /* _I915_REG_H_ */

-- 
Jani Nikula, Intel

Re: [v4 11/20] drm/i915: Remove i915_reg.h from g4x_dp.c

[Jani Nikula]

On Thu, 05 Feb 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move DE_IRQ_REGS to display header to make g4x_dp.c
> free from i915_reg.h dependency. These registers are
> only used by display and gvt.
>
> v3: Drop a superfluous include (Jani)
>
> v2: Move DE interrupt regs from common to display header (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/g4x_dp.c            |  1 -
>  .../gpu/drm/i915/display/intel_display_regs.h    | 16 ++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h                  | 15 ---------------
>  3 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 4cb753177fd8..d7de329abf19 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -10,7 +10,6 @@
>  #include <drm/drm_print.h>
>  
>  #include "g4x_dp.h"
> -#include "i915_reg.h"
>  #include "intel_audio.h"
>  #include "intel_backlight.h"
>  #include "intel_connector.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index d03f554ecd7e..5bc891f6de57 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -1049,6 +1049,15 @@
>  #define SWF3(dev_priv, i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
>  #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
>  
> +#define DEISR   _MMIO(0x44000)
> +#define DEIMR   _MMIO(0x44004)
> +#define DEIIR   _MMIO(0x44008)
> +#define DEIER   _MMIO(0x4400c)
> +
> +#define DE_IRQ_REGS		I915_IRQ_REGS(DEIMR, \
> +					      DEIER, \
> +					      DEIIR)
> +
>  #define DIGITAL_PORT_HOTPLUG_CNTRL	_MMIO(0x44030)
>  #define  DIGITAL_PORTA_HOTPLUG_ENABLE		(1 << 4)
>  #define  DIGITAL_PORTA_PULSE_DURATION_2ms	(0 << 2) /* pre-HSW */
> @@ -1792,6 +1801,13 @@
>  					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
>  					 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
>  
> +/* PCH */
> +
> +#define SDEISR  _MMIO(0xc4000)
> +#define SDEIMR  _MMIO(0xc4004)
> +#define SDEIIR  _MMIO(0xc4008)
> +#define SDEIER  _MMIO(0xc400c)
> +
>  #define SDE_IRQ_REGS			I915_IRQ_REGS(SDEIMR, \
>  						      SDEIER, \
>  						      SDEIIR)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1be8426b6a91..b808d1ec5387 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -727,15 +727,6 @@
>  #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
>  #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
>  
> -#define DEISR   _MMIO(0x44000)
> -#define DEIMR   _MMIO(0x44004)
> -#define DEIIR   _MMIO(0x44008)
> -#define DEIER   _MMIO(0x4400c)
> -
> -#define DE_IRQ_REGS		I915_IRQ_REGS(DEIMR, \
> -					      DEIER, \
> -					      DEIIR)
> -
>  #define GTISR   _MMIO(0x44010)
>  #define GTIMR   _MMIO(0x44014)
>  #define GTIIR   _MMIO(0x44018)
> @@ -863,12 +854,6 @@
>  #define   MASK_WAKEMEM				REG_BIT(13)
>  #define   DDI_CLOCK_REG_ACCESS			REG_BIT(7)
>  
> -/* PCH */
> -
> -#define SDEISR  _MMIO(0xc4000)
> -#define SDEIMR  _MMIO(0xc4004)
> -#define SDEIIR  _MMIO(0xc4008)
> -#define SDEIER  _MMIO(0xc400c)
>  
>  /* Icelake PPS_DATA and _ECC DIP Registers.
>   * These are available for transcoders B,C and eDP.

-- 
Jani Nikula, Intel

Re: [v4 14/20] drm/i915: Remove i915_reg.h from intel_rom.c

[Jani Nikula]

On Thu, 05 Feb 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Make intel_rom.c free from including i915_reg.h.
>
> v4: Move oprom reg to separate header (Ville)
>
> v3: Update patch header
>
> v2: Use display header instead of gmd common include (Jani)
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_oprom_regs.h   | 36 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_rom.c      |  3 +-
>  drivers/gpu/drm/i915/i915_reg.h               |  8 -----
>  3 files changed, 37 insertions(+), 10 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_oprom_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_oprom_regs.h b/drivers/gpu/drm/i915/display/intel_oprom_regs.h
> new file mode 100644
> index 000000000000..2cf723aa4ab0
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_oprom_regs.h
> @@ -0,0 +1,36 @@
> +/*
> + * Copyright © 2026 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + *
> + */

Please use SPDX for new files. Can be fixed while applying if there's no
other reason to resend.

> +
> +#ifndef _INTEL_OPROM_REGS_H_
> +#define _INTEL_OPROM_REGS_H_
> +
> +#define PRIMARY_SPI_TRIGGER			_MMIO(0x102040)
> +#define PRIMARY_SPI_ADDRESS			_MMIO(0x102080)
> +#define PRIMARY_SPI_REGIONID			_MMIO(0x102084)
> +#define SPI_STATIC_REGIONS			_MMIO(0x102090)
> +#define   OPTIONROM_SPI_REGIONID_MASK		REG_GENMASK(7, 0)
> +#define OROM_OFFSET				_MMIO(0x1020c0)
> +#define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/display/intel_rom.c b/drivers/gpu/drm/i915/display/intel_rom.c
> index c8f615315310..024db7b1a1c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_rom.c
> +++ b/drivers/gpu/drm/i915/display/intel_rom.c
> @@ -7,10 +7,9 @@
>  
>  #include <drm/drm_device.h>
>  
> -#include "i915_reg.h"
> -
>  #include "intel_rom.h"
>  #include "intel_uncore.h"
> +#include "intel_oprom_regs.h"
>  
>  struct intel_rom {
>  	/* for PCI ROM */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2c279bd3342d..9cb753b65bc2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -892,14 +892,6 @@
>  #define   SGGI_DIS			REG_BIT(15)
>  #define   SGR_DIS			REG_BIT(13)
>  
> -#define PRIMARY_SPI_TRIGGER			_MMIO(0x102040)
> -#define PRIMARY_SPI_ADDRESS			_MMIO(0x102080)
> -#define PRIMARY_SPI_REGIONID			_MMIO(0x102084)
> -#define SPI_STATIC_REGIONS			_MMIO(0x102090)
> -#define   OPTIONROM_SPI_REGIONID_MASK		REG_GENMASK(7, 0)
> -#define OROM_OFFSET				_MMIO(0x1020c0)
> -#define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
> -
>  #define MTL_MEDIA_GSI_BASE		0x380000
>  
>  #endif /* _I915_REG_H_ */

-- 
Jani Nikula, Intel

Re: [v4 17/20] drm/i915: Remove i915_reg.h from intel_display_irq.c

[Jani Nikula]

On Thu, 05 Feb 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move VLV_IRQ_REGS to common header for interrupt to make
> intel_display_irq.c free from including i915_reg.h.
>
> v2: Move interrupt to dedicated header (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_display_irq.c  |  1 -
>  .../gpu/drm/i915/display/intel_display_regs.h |  5 ++
>  drivers/gpu/drm/i915/gt/intel_gt_irq.c        |  2 +
>  drivers/gpu/drm/i915/gt/intel_rc6.c           |  1 +
>  drivers/gpu/drm/i915/gvt/handlers.c           |  1 +
>  drivers/gpu/drm/i915/gvt/interrupt.c          |  1 +
>  drivers/gpu/drm/i915/i915_reg.h               | 52 -------------------
>  drivers/gpu/drm/i915/intel_clock_gating.c     |  1 +
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |  2 +
>  drivers/gpu/drm/i915/vlv_suspend.c            |  1 +
>  include/drm/intel/intel_gmd_interrupt_regs.h  | 49 +++++++++++++++++
>  11 files changed, 63 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 432a9c895c39..bd0eb1f46919 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -7,7 +7,6 @@
>  #include <drm/drm_vblank.h>
>  #include <drm/intel/intel_gmd_interrupt_regs.h>
>  
> -#include "i915_reg.h"
>  #include "icl_dsi_regs.h"
>  #include "intel_crtc.h"
>  #include "intel_de.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index dcb8cab7b30b..1c77a7de2d6e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -1470,6 +1470,11 @@
>  #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
>  #define DE_PIPE_FIFO_UNDERRUN(pipe)  (1 << (8 * (pipe)))
>  
> +/* Display Internal Timeout Register */
> +#define RM_TIMEOUT		_MMIO(0x42060)
> +#define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
> +#define  MMIO_TIMEOUT_US(us)	((us) << 0)
> +
>  #define GEN8_DE_MISC_ISR _MMIO(0x44460)
>  #define GEN8_DE_MISC_IMR _MMIO(0x44464)
>  #define GEN8_DE_MISC_IIR _MMIO(0x44468)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index 75e802e10be2..d85c849c0081 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -5,6 +5,8 @@
>  
>  #include <linux/sched/clock.h>
>  
> +#include <drm/intel/intel_gmd_interrupt_regs.h>
> +
>  #include "i915_drv.h"
>  #include "i915_irq.h"
>  #include "i915_reg.h"
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 942ac1ebecee..5c316f734c4a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -8,6 +8,7 @@
>  
>  #include <drm/drm_print.h>
>  #include <drm/intel/intel_pcode_regs.h>
> +#include <drm/intel/intel_gmd_interrupt_regs.h>
>  
>  #include "display/vlv_clock.h"
>  #include "gem/i915_gem_region.h"
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 2e9d9d0638ae..4f65ced906da 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -41,6 +41,7 @@
>  #include <drm/display/drm_dp.h>
>  #include <drm/drm_print.h>
>  #include <drm/intel/intel_pcode_regs.h>
> +#include <drm/intel/intel_gmd_interrupt_regs.h>
>  
>  #include "display/bxt_dpio_phy_regs.h"
>  #include "display/i9xx_plane_regs.h"
> diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c
> index 91d22b1c62e2..f85113218037 100644
> --- a/drivers/gpu/drm/i915/gvt/interrupt.c
> +++ b/drivers/gpu/drm/i915/gvt/interrupt.c
> @@ -32,6 +32,7 @@
>  #include <linux/eventfd.h>
>  
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_interrupt_regs.h>
>  
>  #include "display/intel_display_regs.h"
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5cb53a8c451a..7f3d5b7f7abd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -335,9 +335,6 @@
>  
>  #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
>  #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
> -#define SCPD0		_MMIO(0x209c) /* 915+ only */
> -#define  SCPD_FBC_IGNORE_3D			(1 << 6)
> -#define  CSTATE_RENDER_CLOCK_GATE_DISABLE	(1 << 5)
>  #define GEN2_IER	_MMIO(0x20a0)
>  #define GEN2_IIR	_MMIO(0x20a4)
>  #define GEN2_IMR	_MMIO(0x20a8)
> @@ -350,13 +347,6 @@
>  #define   GINT_DIS		(1 << 22)
>  #define   GCFG_DIS		(1 << 8)
>  #define VLV_GUNIT_CLOCK_GATE2	_MMIO(VLV_DISPLAY_BASE + 0x2064)
> -#define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
> -#define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
> -#define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
> -#define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
> -#define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
> -#define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
> -#define VLV_PCBR_ADDR_SHIFT	12
>  
>  #define EIR		_MMIO(0x20b0)
>  #define EMR		_MMIO(0x20b4)
> @@ -682,11 +672,6 @@
>  #define PCH_3DCGDIS1		_MMIO(0x46024)
>  # define VFMUNIT_CLOCK_GATE_DISABLE		(1 << 11)
>  
> -/* Display Internal Timeout Register */
> -#define RM_TIMEOUT		_MMIO(0x42060)
> -#define RM_TIMEOUT_REG_CAPTURE	_MMIO(0x420E0)
> -#define  MMIO_TIMEOUT_US(us)	((us) << 0)
> -
>  #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
>  #define   MASTER_INTERRUPT_ENABLE	(1 << 31)
>  
> @@ -699,24 +684,6 @@
>  					      GTIER, \
>  					      GTIIR)
>  
> -#define GEN8_MASTER_IRQ			_MMIO(0x44200)
> -#define  GEN8_MASTER_IRQ_CONTROL	(1 << 31)
> -#define  GEN8_PCU_IRQ			(1 << 30)
> -#define  GEN8_DE_PCH_IRQ		(1 << 23)
> -#define  GEN8_DE_MISC_IRQ		(1 << 22)
> -#define  GEN8_DE_PORT_IRQ		(1 << 20)
> -#define  GEN8_DE_PIPE_C_IRQ		(1 << 18)
> -#define  GEN8_DE_PIPE_B_IRQ		(1 << 17)
> -#define  GEN8_DE_PIPE_A_IRQ		(1 << 16)
> -#define  GEN8_DE_PIPE_IRQ(pipe)		(1 << (16 + (pipe)))
> -#define  GEN8_GT_VECS_IRQ		(1 << 6)
> -#define  GEN8_GT_GUC_IRQ		(1 << 5)
> -#define  GEN8_GT_PM_IRQ			(1 << 4)
> -#define  GEN8_GT_VCS1_IRQ		(1 << 3) /* NB: VCS2 in bspec! */
> -#define  GEN8_GT_VCS0_IRQ		(1 << 2) /* NB: VCS1 in bpsec! */
> -#define  GEN8_GT_BCS_IRQ		(1 << 1)
> -#define  GEN8_GT_RCS_IRQ		(1 << 0)
> -
>  #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
>  #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
>  #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
> @@ -742,25 +709,6 @@
>  						      GEN8_PCU_IER, \
>  						      GEN8_PCU_IIR)
>  
> -#define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
> -#define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
> -#define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
> -#define GEN11_GU_MISC_IER	_MMIO(0x444fc)
> -#define  GEN11_GU_MISC_GSE	(1 << 27)
> -
> -#define GEN11_GU_MISC_IRQ_REGS		I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
> -						      GEN11_GU_MISC_IER, \
> -						      GEN11_GU_MISC_IIR)
> -
> -#define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
> -#define  GEN11_MASTER_IRQ		(1 << 31)
> -#define  GEN11_PCU_IRQ			(1 << 30)
> -#define  GEN11_GU_MISC_IRQ		(1 << 29)
> -#define  GEN11_DISPLAY_IRQ		(1 << 16)
> -#define  GEN11_GT_DW_IRQ(x)		(1 << (x))
> -#define  GEN11_GT_DW1_IRQ		(1 << 1)
> -#define  GEN11_GT_DW0_IRQ		(1 << 0)
> -
>  #define DG1_MSTR_TILE_INTR		_MMIO(0x190008)
>  #define   DG1_MSTR_IRQ			REG_BIT(31)
>  #define   DG1_MSTR_TILE(t)		REG_BIT(t)
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index 1ad31435bd3f..d0400ea2ffc7 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -27,6 +27,7 @@
>  
>  #include <drm/drm_print.h>
>  #include <drm/intel/intel_gmd_misc_regs.h>
> +#include <drm/intel/intel_gmd_interrupt_regs.h>
>  
>  #include "display/i9xx_plane_regs.h"
>  #include "display/intel_display.h"
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index c8a51e773086..ae42818ab6e0 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -6,6 +6,8 @@
>  #include <drm/intel/intel_pcode_regs.h>
>  #include <drm/intel/intel_gmd_misc_regs.h>
>  
> +#include <drm/intel/intel_gmd_interrupt_regs.h>
> +
>  #include "display/bxt_dpio_phy_regs.h"
>  #include "display/i9xx_plane_regs.h"
>  #include "display/i9xx_wm_regs.h"
> diff --git a/drivers/gpu/drm/i915/vlv_suspend.c b/drivers/gpu/drm/i915/vlv_suspend.c
> index bace7b38329b..1e4343fe5574 100644
> --- a/drivers/gpu/drm/i915/vlv_suspend.c
> +++ b/drivers/gpu/drm/i915/vlv_suspend.c
> @@ -7,6 +7,7 @@
>  #include <linux/kernel.h>
>  
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_interrupt_regs.h>
>  
>  #include "gt/intel_gt_regs.h"
>  
> diff --git a/include/drm/intel/intel_gmd_interrupt_regs.h b/include/drm/intel/intel_gmd_interrupt_regs.h
> index dc9d5fc29ff6..ce66c4151e76 100644
> --- a/include/drm/intel/intel_gmd_interrupt_regs.h
> +++ b/include/drm/intel/intel_gmd_interrupt_regs.h
> @@ -40,4 +40,53 @@
>  #define I915_ASLE_INTERRUPT				(1 << 0)
>  #define I915_BSD_USER_INTERRUPT				(1 << 25)
>  
> +#define GEN8_MASTER_IRQ			_MMIO(0x44200)
> +#define  GEN8_MASTER_IRQ_CONTROL	(1 << 31)
> +#define  GEN8_PCU_IRQ			(1 << 30)
> +#define  GEN8_DE_PCH_IRQ		(1 << 23)
> +#define  GEN8_DE_MISC_IRQ		(1 << 22)
> +#define  GEN8_DE_PORT_IRQ		(1 << 20)
> +#define  GEN8_DE_PIPE_C_IRQ		(1 << 18)
> +#define  GEN8_DE_PIPE_B_IRQ		(1 << 17)
> +#define  GEN8_DE_PIPE_A_IRQ		(1 << 16)
> +#define  GEN8_DE_PIPE_IRQ(pipe)		(1 << (16 + (pipe)))
> +#define  GEN8_GT_VECS_IRQ		(1 << 6)
> +#define  GEN8_GT_GUC_IRQ		(1 << 5)
> +#define  GEN8_GT_PM_IRQ			(1 << 4)
> +#define  GEN8_GT_VCS1_IRQ		(1 << 3) /* NB: VCS2 in bspec! */
> +#define  GEN8_GT_VCS0_IRQ		(1 << 2) /* NB: VCS1 in bpsec! */
> +#define  GEN8_GT_BCS_IRQ		(1 << 1)
> +#define  GEN8_GT_RCS_IRQ		(1 << 0)
> +
> +#define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
> +#define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
> +#define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
> +#define GEN11_GU_MISC_IER	_MMIO(0x444fc)
> +#define  GEN11_GU_MISC_GSE	(1 << 27)
> +
> +#define GEN11_GU_MISC_IRQ_REGS		I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
> +						      GEN11_GU_MISC_IER, \
> +						      GEN11_GU_MISC_IIR)
> +
> +#define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
> +#define  GEN11_MASTER_IRQ		(1 << 31)
> +#define  GEN11_PCU_IRQ			(1 << 30)
> +#define  GEN11_GU_MISC_IRQ		(1 << 29)
> +#define  GEN11_DISPLAY_IRQ		(1 << 16)
> +#define  GEN11_GT_DW_IRQ(x)		(1 << (x))
> +#define  GEN11_GT_DW1_IRQ		(1 << 1)
> +#define  GEN11_GT_DW0_IRQ		(1 << 0)
> +
> +#define SCPD0		_MMIO(0x209c) /* 915+ only */
> +#define  SCPD_FBC_IGNORE_3D			(1 << 6)
> +#define  CSTATE_RENDER_CLOCK_GATE_DISABLE	(1 << 5)
> +
> +#define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
> +#define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
> +#define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
> +#define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
> +#define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
> +#define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
> +#define VLV_PCBR_ADDR_SHIFT	12
> +
>  #endif

-- 
Jani Nikula, Intel

Re: [v4 18/20] drm/i915: Remove i915_reg.h from intel_display_power_well.c

[Jani Nikula]

On Thu, 05 Feb 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Make intel_display_power_well.c free from including i915_reg.h.
>
> v3: Separate bit field for VLV (Ville)
>
> v2: Include specific pcode header, drop common header (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 3 +--
>  drivers/gpu/drm/i915/display/intel_display_regs.h       | 1 +
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 45c4313e6900..9c8d29839caf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -8,7 +8,6 @@
>  #include <drm/drm_print.h>
>  #include <drm/intel/intel_pcode_regs.h>
>  
> -#include "i915_reg.h"
>  #include "intel_backlight_regs.h"
>  #include "intel_combo_phy.h"
>  #include "intel_combo_phy_regs.h"
> @@ -1277,7 +1276,7 @@ static void vlv_init_display_clock_gating(struct intel_display *display)
>  	 * Disable trickle feed and enable pnd deadline calculation
>  	 */
>  	intel_de_write(display, MI_ARB_VLV,
> -		       MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> +		       MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE_VLV);
>  	intel_de_write(display, CBR1_VLV, 0);
>  
>  	drm_WARN_ON(display->drm, DISPLAY_RUNTIME_INFO(display)->rawclk_freq == 0);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 1c77a7de2d6e..d661385a1edd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -350,6 +350,7 @@
>  #define  FW_CSPWRDWNEN		(1 << 15)
>  
>  #define MI_ARB_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6504)
> +#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE_VLV	(1 << 2)
>  
>  #define CZCLK_CDCLK_FREQ_RATIO	_MMIO(VLV_DISPLAY_BASE + 0x6508)
>  #define   CDCLK_FREQ_SHIFT	4

-- 
Jani Nikula, Intel

Re: [v4 20/20] drm/{i915, xe}: Remove i915_reg.h from display

[Jani Nikula]

On Thu, 05 Feb 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Make display files free from including i915_reg.h.
>
> v2: Move pcode_regs.h out of i915_reg.h (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/hsw_ips.c               | 1 -
>  drivers/gpu/drm/i915/display/i9xx_plane.c            | 1 -
>  drivers/gpu/drm/i915/display/icl_dsi.c               | 1 -
>  drivers/gpu/drm/i915/display/intel_backlight.c       | 1 -
>  drivers/gpu/drm/i915/display/intel_bw.c              | 1 -
>  drivers/gpu/drm/i915/display/intel_casf.c            | 1 -
>  drivers/gpu/drm/i915/display/intel_ddi.c             | 1 -
>  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 1 -
>  drivers/gpu/drm/i915/display/intel_display_power.c   | 1 -
>  drivers/gpu/drm/i915/display/intel_display_wa.c      | 1 -
>  drivers/gpu/drm/i915/display/intel_dmc.c             | 1 -
>  drivers/gpu/drm/i915/display/intel_fdi.c             | 1 -
>  drivers/gpu/drm/i915/display/intel_hdcp.c            | 1 -
>  drivers/gpu/drm/i915/display/intel_hotplug_irq.c     | 1 -
>  drivers/gpu/drm/i915/display/intel_lt_phy.c          | 1 -
>  drivers/gpu/drm/i915/display/intel_pps.c             | 1 -
>  drivers/gpu/drm/i915/display/intel_tc.c              | 1 -
>  drivers/gpu/drm/i915/display/skl_watermark.c         | 1 -
>  drivers/gpu/drm/i915/display/vlv_dsi.c               | 1 -
>  19 files changed, 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
> index 8658872ed86f..cbaef3f13f00 100644
> --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> @@ -9,7 +9,6 @@
>  #include <drm/intel/intel_pcode_regs.h>
>  
>  #include "hsw_ips.h"
> -#include "i915_reg.h"
>  #include "intel_color_regs.h"
>  #include "intel_de.h"
>  #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index b1fecf178906..9c16753a1f3b 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -10,7 +10,6 @@
>  #include <drm/drm_fourcc.h>
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "i9xx_plane.h"
>  #include "i9xx_plane_regs.h"
>  #include "intel_atomic.h"
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index c8e0333706c1..7cf511a6c0f9 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -34,7 +34,6 @@
>  #include <drm/drm_print.h>
>  #include <drm/drm_probe_helper.h>
>  
> -#include "i915_reg.h"
>  #include "icl_dsi.h"
>  #include "icl_dsi_regs.h"
>  #include "intel_atomic.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
> index a68fdbd2acb9..34e95f05936e 100644
> --- a/drivers/gpu/drm/i915/display/intel_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_backlight.c
> @@ -12,7 +12,6 @@
>  #include <drm/drm_file.h>
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "intel_backlight.h"
>  #include "intel_backlight_regs.h"
>  #include "intel_connector.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 618da1dfb671..6808fb9b4ab3 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -7,7 +7,6 @@
>  #include <drm/drm_print.h>
>  #include <drm/intel/intel_pcode_regs.h>
>  
> -#include "i915_reg.h"
>  #include "intel_bw.h"
>  #include "intel_crtc.h"
>  #include "intel_display_core.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
> index 0fe4398a1a4e..b167af31de5b 100644
> --- a/drivers/gpu/drm/i915/display/intel_casf.c
> +++ b/drivers/gpu/drm/i915/display/intel_casf.c
> @@ -3,7 +3,6 @@
>  
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "intel_casf.h"
>  #include "intel_casf_regs.h"
>  #include "intel_de.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index f92323664162..94ae583e907f 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -34,7 +34,6 @@
>  #include <drm/drm_print.h>
>  #include <drm/drm_privacy_screen_consumer.h>
>  
> -#include "i915_reg.h"
>  #include "icl_dsi.h"
>  #include "intel_alpm.h"
>  #include "intel_audio.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index f041a7102317..2614c4863c87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -16,7 +16,6 @@
>  #include <drm/intel/intel_gmd_misc_regs.h>
>  
>  #include "hsw_ips.h"
> -#include "i915_reg.h"
>  #include "i9xx_wm_regs.h"
>  #include "intel_alpm.h"
>  #include "intel_bo.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index cb9256f72aa9..755935dcfe23 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -9,7 +9,6 @@
>  #include <drm/drm_print.h>
>  #include <drm/intel/intel_pcode_regs.h>
>  
> -#include "i915_reg.h"
>  #include "intel_backlight_regs.h"
>  #include "intel_cdclk.h"
>  #include "intel_clock_gating.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
> index b1979ee9d836..c2ccdca2c2f3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> @@ -5,7 +5,6 @@
>  
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "intel_de.h"
>  #include "intel_display_core.h"
>  #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 1182bc9a2e6d..8df06b993890 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -29,7 +29,6 @@
>  #include <drm/drm_file.h>
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "intel_crtc.h"
>  #include "intel_de.h"
>  #include "intel_display_power_well.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index 5bb0090dd5ed..24ce8a7842c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -8,7 +8,6 @@
>  #include <drm/drm_fixed.h>
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "intel_atomic.h"
>  #include "intel_crtc.h"
>  #include "intel_ddi.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index c96f51d88186..0058098d3c3e 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -19,7 +19,6 @@
>  #include <drm/intel/i915_component.h>
>  #include <drm/intel/intel_pcode_regs.h>
>  
> -#include "i915_reg.h"
>  #include "intel_connector.h"
>  #include "intel_de.h"
>  #include "intel_display_jiffies.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index 82c39e4ffa37..8865cb2ac569 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -5,7 +5,6 @@
>  
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "intel_de.h"
>  #include "intel_display_irq.h"
>  #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 27ad8407606b..eced8493e566 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -5,7 +5,6 @@
>  
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "intel_cx0_phy.h"
>  #include "intel_cx0_phy_regs.h"
>  #include "intel_ddi.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index b217ec7aa758..2d799af73bb7 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -9,7 +9,6 @@
>  #include <drm/drm_print.h>
>  
>  #include "g4x_dp.h"
> -#include "i915_reg.h"
>  #include "intel_de.h"
>  #include "intel_display_jiffies.h"
>  #include "intel_display_power_well.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 064f572bbc85..78ed9c58a72f 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -7,7 +7,6 @@
>  
>  #include <drm/drm_print.h>
>  
> -#include "i915_reg.h"
>  #include "intel_atomic.h"
>  #include "intel_cx0_phy_regs.h"
>  #include "intel_ddi.h"
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 1455ea068d22..8e3031adb09f 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -9,7 +9,6 @@
>  #include <drm/drm_print.h>
>  #include <drm/intel/intel_pcode_regs.h>
>  
> -#include "i915_reg.h"
>  #include "i9xx_wm.h"
>  #include "intel_atomic.h"
>  #include "intel_bw.h"
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index d705af3bf8ba..67f0082d3a69 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -33,7 +33,6 @@
>  #include <drm/drm_print.h>
>  #include <drm/drm_probe_helper.h>
>  
> -#include "i915_reg.h"
>  #include "intel_atomic.h"
>  #include "intel_backlight.h"
>  #include "intel_connector.h"

-- 
Jani Nikula, Intel

Re: [v4 12/20] drm/i915: Remove i915_reg.h from i9xx_wm.c

[Jani Nikula]

On Thu, 05 Feb 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move FW_BLC_SELF to common header to make i9xx_wm.c
> free from i915_reg.h include. Introduce a common
> intel_gmd_misc_regs.h to define common miscellaneous
> register definitions across graphics and display.
>
> v3: MISC header included as needed, drop from i915_reg (Jani)
>
> v2: Introdue a common misc header for GMD
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>

Having something "misc" is always a bit suspect, because it has the risk
of becoming a dumping ground, just because of the name. But let's go
with this anyway for now.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/i9xx_wm.c        |  2 +-
>  .../drm/i915/display/intel_display_debugfs.c  |  1 +
>  .../gpu/drm/i915/display/intel_display_regs.h |  7 ++++++-
>  drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c  |  1 +
>  .../gpu/drm/i915/gt/intel_ring_submission.c   |  1 +
>  drivers/gpu/drm/i915/gt/intel_workarounds.c   |  2 ++
>  drivers/gpu/drm/i915/gvt/cmd_parser.c         |  1 +
>  drivers/gpu/drm/i915/gvt/mmio_context.c       |  1 +
>  drivers/gpu/drm/i915/i915_debugfs.c           |  1 +
>  drivers/gpu/drm/i915/i915_reg.h               | 19 -----------------
>  drivers/gpu/drm/i915/intel_clock_gating.c     |  1 +
>  drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |  1 +
>  include/drm/intel/intel_gmd_misc_regs.h       | 21 +++++++++++++++++++
>  13 files changed, 38 insertions(+), 21 deletions(-)
>  create mode 100644 include/drm/intel/intel_gmd_misc_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 39dfceb438ae..24f898efa9dd 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -6,8 +6,8 @@
>  #include <linux/iopoll.h>
>  
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_misc_regs.h>
>  
> -#include "i915_reg.h"
>  #include "i9xx_wm.h"
>  #include "i9xx_wm_regs.h"
>  #include "intel_atomic.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index aba13e8a9051..f041a7102317 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -13,6 +13,7 @@
>  #include <drm/drm_file.h>
>  #include <drm/drm_fourcc.h>
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_misc_regs.h>
>  
>  #include "hsw_ips.h"
>  #include "i915_reg.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 5bc891f6de57..9f241655aa99 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -3132,6 +3132,11 @@ enum skl_power_gate {
>  #define   MTL_TRAS_MASK			REG_GENMASK(16, 8)
>  #define   MTL_TRDPRE_MASK		REG_GENMASK(7, 0)
>  
> -
> +#define FW_BLC		_MMIO(0x20d8)
> +#define FW_BLC2		_MMIO(0x20dc)
> +#define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
> +#define   FW_BLC_SELF_EN_MASK      REG_BIT(31)
> +#define   FW_BLC_SELF_FIFO_MASK    REG_BIT(16) /* 945 only */
> +#define   FW_BLC_SELF_EN           REG_BIT(15) /* 945 only */
>  
>  #endif /* __INTEL_DISPLAY_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> index 5eda98ebc1ae..ee90f5323da7 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
> @@ -6,6 +6,7 @@
>  #include <linux/highmem.h>
>  
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_misc_regs.h>
>  
>  #include "display/intel_display.h"
>  #include "i915_drv.h"
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index c1797e49811d..099453dd9cd5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -5,6 +5,7 @@
>  
>  #include <drm/drm_cache.h>
>  #include <drm/intel/intel_gmd_interrupt_regs.h>
> +#include <drm/intel/intel_gmd_misc_regs.h>
>  
>  #include "gem/i915_gem_internal.h"
>  
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index ece88c612e27..4427812b2438 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -3,6 +3,8 @@
>   * Copyright © 2014-2018 Intel Corporation
>   */
>  
> +#include <drm/intel/intel_gmd_misc_regs.h>
> +
>  #include "i915_drv.h"
>  #include "i915_reg.h"
>  #include "i915_mmio_range.h"
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index bf7c3d3f5f8a..98c35c78a4ed 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -37,6 +37,7 @@
>  #include <linux/slab.h>
>  
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_misc_regs.h>
>  
>  #include "display/i9xx_plane_regs.h"
>  #include "display/intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index d4e9d485d382..3eb442acdf8d 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -34,6 +34,7 @@
>   */
>  
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_misc_regs.h>
>  
>  #include "gt/intel_context.h"
>  #include "gt/intel_engine_regs.h"
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 42f6b44f0027..4778ba664ec7 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -33,6 +33,7 @@
>  
>  #include <drm/drm_debugfs.h>
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_misc_regs.h>
>  
>  #include "gem/i915_gem_context.h"
>  #include "gt/intel_gt.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b808d1ec5387..2bac216bd2b9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -393,24 +393,10 @@
>  
>  #define GEN2_ERROR_REGS		I915_ERROR_REGS(EMR, EIR)
>  
> -#define INSTPM	        _MMIO(0x20c0)
> -#define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
> -#define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
> -					will not assert AGPBUSY# and will only
> -					be delivered when out of C3. */
> -#define   INSTPM_FORCE_ORDERING				(1 << 7) /* GEN6+ */
> -#define   INSTPM_TLB_INVALIDATE	(1 << 9)
> -#define   INSTPM_SYNC_FLUSH	(1 << 5)
>  #define MEM_MODE	_MMIO(0x20cc)
>  #define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
>  #define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
>  #define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
> -#define FW_BLC		_MMIO(0x20d8)
> -#define FW_BLC2		_MMIO(0x20dc)
> -#define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
> -#define   FW_BLC_SELF_EN_MASK      REG_BIT(31)
> -#define   FW_BLC_SELF_FIFO_MASK    REG_BIT(16) /* 945 only */
> -#define   FW_BLC_SELF_EN           REG_BIT(15) /* 945 only */
>  #define MM_BURST_LENGTH     0x00700000
>  #define MM_FIFO_WATERMARK   0x0001F000
>  #define LM_BURST_LENGTH     0x00000700
> @@ -833,11 +819,6 @@
>  #define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	REG_BIT(14)
>  
>  
> -#define DISP_ARB_CTL	_MMIO(0x45000)
> -#define   DISP_FBC_MEMORY_WAKE		REG_BIT(31)
> -#define   DISP_TILE_SURFACE_SWIZZLING	REG_BIT(13)
> -#define   DISP_FBC_WM_DIS		REG_BIT(15)
> -
>  #define GEN8_CHICKEN_DCPR_1			_MMIO(0x46430)
>  #define   _LATENCY_REPORTING_REMOVED_PIPE_D	REG_BIT(31)
>  #define   SKL_SELECT_ALTERNATE_DC_EXIT		REG_BIT(30)
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index 4e18d5a22112..1ad31435bd3f 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -26,6 +26,7 @@
>   */
>  
>  #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_misc_regs.h>
>  
>  #include "display/i9xx_plane_regs.h"
>  #include "display/intel_display.h"
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 8cfe9b56f1d0..c8a51e773086 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -4,6 +4,7 @@
>   */
>  
>  #include <drm/intel/intel_pcode_regs.h>
> +#include <drm/intel/intel_gmd_misc_regs.h>
>  
>  #include "display/bxt_dpio_phy_regs.h"
>  #include "display/i9xx_plane_regs.h"
> diff --git a/include/drm/intel/intel_gmd_misc_regs.h b/include/drm/intel/intel_gmd_misc_regs.h
> new file mode 100644
> index 000000000000..763d7711f21c
> --- /dev/null
> +++ b/include/drm/intel/intel_gmd_misc_regs.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2026 Intel Corporation */
> +
> +#ifndef _INTEL_GMD_MISC_REGS_H_
> +#define _INTEL_GMD_MISC_REGS_H_
> +
> +#define DISP_ARB_CTL	_MMIO(0x45000)
> +#define   DISP_FBC_MEMORY_WAKE		REG_BIT(31)
> +#define   DISP_TILE_SURFACE_SWIZZLING	REG_BIT(13)
> +#define   DISP_FBC_WM_DIS		REG_BIT(15)
> +
> +#define INSTPM	        _MMIO(0x20c0)
> +#define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
> +#define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
> +					will not assert AGPBUSY# and will only
> +					be delivered when out of C3. */
> +#define   INSTPM_FORCE_ORDERING				(1 << 7) /* GEN6+ */
> +#define   INSTPM_TLB_INVALIDATE	(1 << 9)
> +#define   INSTPM_SYNC_FLUSH	(1 << 5)
> +
> +#endif

-- 
Jani Nikula, Intel

Re: [v4 00/20] Make Display free from i915_reg.h

[Jani Nikula]

On Thu, 05 Feb 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move the common register definition to per feature header
> which makes display files free from including i915_reg.h.
> This will help avoid dupicate definitions and includes and can
> serve as a common file for xe, i915 and display module.

Good stuff, thanks. I think it's all R-b now. Please use SPDX in patch
14 while applying.

Oh, and a follow-up patch could remove
drivers/gpu/drm/xe/compat-i915-headers/i915_reg.h.

BR,
Jani.

-- 
Jani Nikula, Intel

RE: [v4 00/20] Make Display free from i915_reg.h

[Shankar, Uma]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Wednesday, February 11, 2026 6:29 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v4 00/20] Make Display free from i915_reg.h
> 
> On Thu, 05 Feb 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Move the common register definition to per feature header which makes
> > display files free from including i915_reg.h.
> > This will help avoid dupicate definitions and includes and can serve
> > as a common file for xe, i915 and display module.
> 
> Good stuff, thanks. I think it's all R-b now. Please use SPDX in patch
> 14 while applying.

Sure, will use SPDX while merging in patch14.

Thanks a lot Jani for the review, valuable feedback and suggestions.

> Oh, and a follow-up patch could remove
> drivers/gpu/drm/xe/compat-i915-headers/i915_reg.h.

Sure, will send that out. 

Regards,
Uma Shankar

> BR,
> Jani.
> 
> --
> Jani Nikula, Intel

RE: [v4 00/20] Make Display free from i915_reg.h

[Shankar, Uma]

> -----Original Message-----
> From: Shankar, Uma
> Sent: Wednesday, February 11, 2026 9:03 PM
> To: Nikula, Jani <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org; intel-
> xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com
> Subject: RE: [v4 00/20] Make Display free from i915_reg.h
> 
> 
> 
> > -----Original Message-----
> > From: Nikula, Jani <jani.nikula@intel.com>
> > Sent: Wednesday, February 11, 2026 6:29 PM
> > To: Shankar, Uma <uma.shankar@intel.com>;
> > intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > Cc: ville.syrjala@linux.intel.com; Shankar, Uma
> > <uma.shankar@intel.com>
> > Subject: Re: [v4 00/20] Make Display free from i915_reg.h
> >
> > On Thu, 05 Feb 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > > Move the common register definition to per feature header which
> > > makes display files free from including i915_reg.h.
> > > This will help avoid dupicate definitions and includes and can serve
> > > as a common file for xe, i915 and display module.
> >
> > Good stuff, thanks. I think it's all R-b now. Please use SPDX in patch
> > 14 while applying.
> 
> Sure, will use SPDX while merging in patch14.
> 
> Thanks a lot Jani for the review, valuable feedback and suggestions.

Changes pushed to drm-intel-next. Thanks for the review and feedback.

Regards,
Uma Shankar

> > Oh, and a follow-up patch could remove
> > drivers/gpu/drm/xe/compat-i915-headers/i915_reg.h.
> 
> Sure, will send that out.
> 
> Regards,
> Uma Shankar
> 
> > BR,
> > Jani.
> >
> > --
> > Jani Nikula, Intel