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From: "Poosa, Karthik" <karthik.poosa@intel.com>
To: <mallesh.koujalagi@intel.com>, <intel-xe@lists.freedesktop.org>
Cc: <anshuman.gupta@intel.com>, <badal.nilawar@intel.com>,
	<riana.tauro@intel.com>, <sk.anirban@intel.com>,
	<raag.jadav@intel.com>, <rodrigo.vivi@intel.com>
Subject: Re: drm/xe/hwmon: Resolved incompatible cast
Date: Mon, 8 Sep 2025 20:17:15 +0530	[thread overview]
Message-ID: <13646b1e-118b-4a97-983b-48e2c162fec1@intel.com> (raw)
In-Reply-To: <20250904105857.2293034-1-mallesh.koujalagi@intel.com>

1. Commit title and message, should not be in past tense, it shall be in 
imperative present tense. viz: Resolve incompatible cast.

2. Title can be rephrase as : Ensure endian-safe casting

On 04-09-2025 16:28, mallesh.koujalagi@intel.com wrote:
> From: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
>
> The issue is that casting of u64* to u32* cause an endianness
> problem because on little-endian systems, the function will
> write to the lower 32 bits, but on big-endian systems,
> it will write to the upper 32 bits

Commit message can also be rephased to -

Handle endianness when casting u64* to u32*.

On little-endian systems, writes will go to the lower 32 bits; on 
big-endian systems, they affect the upper 32 bits.

Avoid this by using u32* pointer instead of u64*.

3. You can mention the Fixes tag.

  Fixes: 7596d839f6228 ("drm/xe/hwmon: Add support to manage power 
limits though mailbox")

> Signed-off-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_hwmon.c | 10 ++++++++--
>   1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index f08fc4377d25..d21f8f8678ab 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -294,7 +294,11 @@ static void xe_hwmon_power_max_read(struct xe_hwmon *hwmon, u32 attr, int channe
>   	mutex_lock(&hwmon->hwmon_lock);
>   
>   	if (hwmon->xe->info.has_mbx_power_limits) {
> -		xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, (u32 *)&reg_val);
> +		u32 reg_val_32 = 0;
> +
> +		xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &reg_val_32);
> +		/* Explicit, endian-safe conversion */
> +		reg_val = reg_val_32;
>   	} else {
>   		rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel);
>   		pkg_power_sku = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel);
> @@ -490,7 +494,9 @@ xe_hwmon_power_max_interval_show(struct device *dev, struct device_attribute *at
>   	mutex_lock(&hwmon->hwmon_lock);
>   
>   	if (hwmon->xe->info.has_mbx_power_limits) {
> -		ret = xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, (u32 *)&r);
> +		ret = xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, &x);
> +		/* Explicit, endian-safe conversion */
> +		r = x;
>   		if (ret) {
>   			drm_err(&hwmon->xe->drm,
>   				"power interval read fail, ch %d, attr %d, r 0%llx, ret %d\n",

      parent reply	other threads:[~2025-09-08 14:47 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-04 10:58 [PATCH] drm/xe/hwmon: Resolved incompatible cast mallesh.koujalagi
2025-09-04 11:37 ` ✓ CI.KUnit: success for " Patchwork
2025-09-04 12:14 ` ✓ Xe.CI.BAT: " Patchwork
2025-09-04 23:59 ` ✗ Xe.CI.Full: failure " Patchwork
2025-09-08 14:47 ` Poosa, Karthik [this message]

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