* [PATCH v4 1/8] drm/xe: Add per-engine-class activity support
2025-01-29 10:16 [PATCH v4 0/8] PMU Support for per-engine-class activity Riana Tauro
@ 2025-01-29 10:16 ` Riana Tauro
2025-01-30 0:28 ` Umesh Nerlige Ramappa
2025-01-29 10:16 ` [PATCH v4 2/8] drm/xe/trace: Add trace for engine activity Riana Tauro
` (15 subsequent siblings)
16 siblings, 1 reply; 45+ messages in thread
From: Riana Tauro @ 2025-01-29 10:16 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, umesh.nerlige.ramappa,
lucas.demarchi, vinay.belgaumkar, soham.purkait
GuC provides support to read engine counters to calculate the
engine activity. KMD exposes two counters via the PMU interface to
calculate engine activity
Engine Active Ticks(engine-active-ticks) - number of active ticks for engine
Engine Total Ticks (engine-total-ticks) - total ticks of engine
Engine activity percentage can be calculated as below
Engine activity % = (engine active ticks/engine total ticks) * 100.
v2: fix cosmetic review comments
add forcewake for gpm_ts (Umesh)
v3: fix CI hooks error
change function parameters and unpin bo on error
of allocate_activity_buffers
fix kernel-doc (Umesh)
use engine activity (Umesh, Lucas)
rename xe_engine_activity to xe_guc_engine_*
fix commit message to use per-engine class(Lucas)
v4: remove forcewake as engine is already running
when reading gpm timestamp
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/abi/guc_actions_abi.h | 1 +
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
drivers/gpu/drm/xe/xe_guc_engine_activity.c | 317 ++++++++++++++++++
drivers/gpu/drm/xe/xe_guc_engine_activity.h | 18 +
.../gpu/drm/xe/xe_guc_engine_activity_types.h | 89 +++++
drivers/gpu/drm/xe/xe_guc_fwif.h | 19 ++
drivers/gpu/drm/xe/xe_guc_types.h | 4 +
8 files changed, 451 insertions(+)
create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.c
create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.h
create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 328aff36831b..7e93461c60bd 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -33,6 +33,7 @@ xe-y += xe_bb.o \
xe_device_sysfs.o \
xe_dma_buf.o \
xe_drm_client.o \
+ xe_guc_engine_activity.o \
xe_exec.o \
xe_execlist.o \
xe_exec_queue.o \
diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
index fee385532fb0..ec516e838ee8 100644
--- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
@@ -140,6 +140,7 @@ enum xe_guc_action {
XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
+ XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 096859072396..124cc398798e 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -358,6 +358,8 @@
#define RENDER_AWAKE_STATUS REG_BIT(1)
#define MEDIA_SLICE0_AWAKE_STATUS REG_BIT(0)
+#define MISC_STATUS_0 XE_REG(0xa500)
+
#define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4)
#define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4)
#define FORCEWAKE_GSC XE_REG(0xa618)
diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
new file mode 100644
index 000000000000..088209b9c228
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
@@ -0,0 +1,317 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+#include "xe_guc_engine_activity.h"
+
+#include "abi/guc_actions_abi.h"
+#include "regs/xe_gt_regs.h"
+
+#include "xe_bo.h"
+#include "xe_force_wake.h"
+#include "xe_gt_printk.h"
+#include "xe_guc.h"
+#include "xe_guc_ct.h"
+#include "xe_hw_engine.h"
+#include "xe_map.h"
+#include "xe_mmio.h"
+
+#define TOTAL_QUANTA 0x8000
+
+static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_engine *hwe)
+{
+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
+ struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
+ u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
+ size_t offset = 0;
+
+ offset = offsetof(struct guc_engine_activity_data,
+ engine_activity[guc_class][hwe->logical_instance]);
+
+ return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap, offset);
+}
+
+static struct iosys_map engine_metadata_map(struct xe_guc *guc)
+{
+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
+ struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
+
+ return buffer->metadata_bo->vmap;
+}
+
+static int allocate_engine_activity_group(struct xe_guc *guc)
+{
+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
+ u32 num_activity_group = 1;
+
+ engine_activity->eag = kmalloc_array(num_activity_group,
+ sizeof(struct engine_activity_group),
+ GFP_KERNEL);
+
+ if (!engine_activity->eag)
+ return -ENOMEM;
+
+ memset(engine_activity->eag, 0, num_activity_group * sizeof(struct engine_activity_group));
+ engine_activity->num_activity_group = num_activity_group;
+
+ return 0;
+}
+
+static int allocate_engine_activity_buffers(struct xe_guc *guc,
+ struct engine_activity_buffer *buffer)
+{
+ u32 metadata_size = sizeof(struct guc_engine_activity_metadata);
+ u32 size = sizeof(struct guc_engine_activity_data);
+ struct xe_gt *gt = guc_to_gt(guc);
+ struct xe_tile *tile = gt_to_tile(gt);
+ struct xe_bo *bo, *metadata_bo;
+
+ metadata_bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(metadata_size),
+ XE_BO_FLAG_SYSTEM |
+ XE_BO_FLAG_GGTT |
+ XE_BO_FLAG_GGTT_INVALIDATE);
+ if (IS_ERR(metadata_bo))
+ return PTR_ERR(metadata_bo);
+
+ bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(size),
+ XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+ XE_BO_FLAG_GGTT |
+ XE_BO_FLAG_GGTT_INVALIDATE);
+
+ if (IS_ERR(bo)) {
+ xe_bo_unpin_map_no_vm(metadata_bo);
+ return PTR_ERR(bo);
+ }
+
+ buffer->metadata_bo = metadata_bo;
+ buffer->activity_bo = bo;
+ return 0;
+}
+
+static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine *hwe)
+{
+ struct xe_guc *guc = &hwe->gt->uc.guc;
+ struct engine_activity_group *eag = &guc->engine_activity.eag[0];
+ u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
+
+ return &eag->engine[guc_class][hwe->logical_instance];
+}
+
+static u64 cpu_ns_to_guc_tsc_tick(ktime_t ns, u32 freq)
+{
+ return mul_u64_u32_div(ns, freq, NSEC_PER_SEC);
+}
+
+#define read_engine_activity_record(xe_, map_, field_) \
+ xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity, field_)
+
+#define read_metadata_record(xe_, map_, field_) \
+ xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity_metadata, field_)
+
+static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
+{
+ struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
+ struct guc_engine_activity *cached_activity = &ea->activity;
+ struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
+ struct iosys_map activity_map, metadata_map;
+ struct xe_device *xe = guc_to_xe(guc);
+ struct xe_gt *gt = guc_to_gt(guc);
+ u32 last_update_tick, global_change_num;
+ u64 active_ticks, gpm_ts;
+ u16 change_num;
+
+ activity_map = engine_activity_map(guc, hwe);
+ metadata_map = engine_metadata_map(guc);
+ global_change_num = read_metadata_record(xe, &metadata_map, global_change_num);
+
+ /* GuC has not initialized activity data yet, return 0 */
+ if (!global_change_num)
+ goto update;
+
+ if (global_change_num == cached_metadata->global_change_num)
+ goto update;
+ else
+ cached_metadata->global_change_num = global_change_num;
+
+ change_num = read_engine_activity_record(xe, &activity_map, change_num);
+
+ if (!change_num || change_num == cached_activity->change_num)
+ goto update;
+
+ /* read engine activity values */
+ last_update_tick = read_engine_activity_record(xe, &activity_map, last_update_tick);
+ active_ticks = read_engine_activity_record(xe, &activity_map, active_ticks);
+
+ /* activity calculations */
+ ea->running = !!last_update_tick;
+ ea->total += active_ticks - cached_activity->active_ticks;
+ ea->active = 0;
+
+ /* cache the counter */
+ cached_activity->change_num = change_num;
+ cached_activity->last_update_tick = last_update_tick;
+ cached_activity->active_ticks = active_ticks;
+
+update:
+ if (ea->running) {
+ gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
+ engine_activity->gpm_timestamp_shift;
+ ea->active = lower_32_bits(gpm_ts) - cached_activity->last_update_tick;
+ }
+
+ return ea->total + ea->active;
+}
+
+static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
+{
+ struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
+ struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
+ struct guc_engine_activity *cached_activity = &ea->activity;
+ struct iosys_map activity_map, metadata_map;
+ struct xe_device *xe = guc_to_xe(guc);
+ ktime_t now, cpu_delta;
+ u64 numerator;
+ u16 quanta_ratio;
+
+ activity_map = engine_activity_map(guc, hwe);
+ metadata_map = engine_metadata_map(guc);
+
+ if (!cached_metadata->guc_tsc_frequency_hz)
+ cached_metadata->guc_tsc_frequency_hz = read_metadata_record(xe, &metadata_map,
+ guc_tsc_frequency_hz);
+
+ quanta_ratio = read_engine_activity_record(xe, &activity_map, quanta_ratio);
+ cached_activity->quanta_ratio = quanta_ratio;
+
+ /* Total ticks calculations */
+ now = ktime_get();
+ cpu_delta = now - ea->last_cpu_ts;
+ ea->last_cpu_ts = now;
+ numerator = (ea->quanta_remainder_ns + cpu_delta) * cached_activity->quanta_ratio;
+ ea->quanta_ns += numerator / TOTAL_QUANTA;
+ ea->quanta_remainder_ns = numerator % TOTAL_QUANTA;
+ ea->quanta = cpu_ns_to_guc_tsc_tick(ea->quanta_ns, cached_metadata->guc_tsc_frequency_hz);
+
+ return ea->quanta;
+}
+
+static int enable_engine_activity_stats(struct xe_guc *guc)
+{
+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
+ struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
+ u32 metadata_ggtt_addr = xe_bo_ggtt_addr(buffer->metadata_bo);
+ u32 ggtt_addr = xe_bo_ggtt_addr(buffer->activity_bo);
+ int len = 0;
+ u32 action[5];
+
+ action[len++] = XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER;
+ action[len++] = metadata_ggtt_addr;
+ action[len++] = 0;
+ action[len++] = ggtt_addr;
+ action[len++] = 0;
+
+ /* Blocking here to ensure the buffers are ready before reading them */
+ return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
+}
+
+static void engine_activity_set_cpu_ts(struct xe_guc *guc)
+{
+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
+ struct engine_activity_group *eag = &engine_activity->eag[0];
+ int i, j;
+
+ for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)
+ for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; j++)
+ eag->engine[i][j].last_cpu_ts = ktime_get();
+}
+
+static u32 gpm_timestamp_shift(struct xe_gt *gt)
+{
+ u32 reg;
+
+ reg = xe_mmio_read32(>->mmio, RPM_CONFIG0);
+
+ return 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
+}
+
+/**
+ * xe_guc_engine_activity_active_ticks - Get engine active ticks
+ * @hwe: The hw_engine object
+ *
+ * Return: accumulated ticks @hwe was active since engine activity stats were enabled.
+ */
+u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe)
+{
+ struct xe_guc *guc = &hwe->gt->uc.guc;
+
+ return get_engine_active_ticks(guc, hwe);
+}
+
+/**
+ * xe_guc_engine_activity_total_ticks - Get engine total ticks
+ * @hwe: The hw_engine object
+ *
+ * Return: accumulated quanta of ticks allocated for the engine
+ */
+u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe)
+{
+ struct xe_guc *guc = &hwe->gt->uc.guc;
+
+ return get_engine_total_ticks(guc, hwe);
+}
+
+/**
+ * xe_guc_engine_activity_enable_stats - Enable engine activity stats
+ * @guc: The GuC object
+ *
+ * Enable engine activity stats and set initial timestamps
+ */
+void xe_guc_engine_activity_enable_stats(struct xe_guc *guc)
+{
+ int ret;
+
+ ret = enable_engine_activity_stats(guc);
+ if (ret)
+ xe_gt_err(guc_to_gt(guc), "failed to enable activity stats%d\n", ret);
+ else
+ engine_activity_set_cpu_ts(guc);
+}
+
+static void engine_activity_fini(void *arg)
+{
+ struct xe_guc_engine_activity *engine_activity = arg;
+
+ kfree(engine_activity->eag);
+}
+
+/**
+ * xe_guc_engine_activity_init - Initialize the engine activity data
+ * @guc: The GuC object
+ *
+ * Return: 0 on success, negative error code otherwise.
+ */
+int xe_guc_engine_activity_init(struct xe_guc *guc)
+{
+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
+ struct xe_gt *gt = guc_to_gt(guc);
+ int ret;
+
+ ret = allocate_engine_activity_group(guc);
+ if (ret) {
+ xe_gt_err(gt, "failed to allocate activity group %d\n", ret);
+ return ret;
+ }
+
+ ret = allocate_engine_activity_buffers(guc, &engine_activity->device_buffer);
+ if (ret) {
+ xe_gt_err(gt, "failed to allocate activity buffers%d\n", ret);
+ kfree(engine_activity->eag);
+ return ret;
+ }
+
+ engine_activity->gpm_timestamp_shift = gpm_timestamp_shift(gt);
+
+ return devm_add_action_or_reset(gt_to_xe(gt)->drm.dev, engine_activity_fini,
+ engine_activity);
+}
diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.h b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
new file mode 100644
index 000000000000..c00f3da5513d
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_GUC_ENGINE_ACTIVITY_H_
+#define _XE_GUC_ENGINE_ACTIVITY_H_
+
+#include <linux/types.h>
+
+struct xe_hw_engine;
+struct xe_guc;
+
+int xe_guc_engine_activity_init(struct xe_guc *guc);
+void xe_guc_engine_activity_enable_stats(struct xe_guc *guc);
+u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe);
+u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe);
+#endif
diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
new file mode 100644
index 000000000000..a2ab327d3eec
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
+#define _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
+
+#include <linux/types.h>
+
+#include "xe_guc_fwif.h"
+/**
+ * struct engine_activity - Engine specific activity data
+ *
+ * Contains engine specific activity data and snapshot of the
+ * structures from GuC
+ */
+struct engine_activity {
+ /** @active: current activity */
+ u64 active;
+
+ /** @last_cpu_ts: cpu timestamp in nsec of previous sample */
+ u64 last_cpu_ts;
+
+ /** @quanta: total quanta used on HW */
+ u64 quanta;
+
+ /** @quanta_ns: total quanta_ns used on HW */
+ u64 quanta_ns;
+
+ /**
+ * @quanta_remainder_ns: remainder when the CPU time is scaled as
+ * per the quanta_ratio. This remainder is used in subsequent
+ * quanta calculations.
+ */
+ u64 quanta_remainder_ns;
+
+ /** @total: total engine activity */
+ u64 total;
+
+ /** @running: true if engine is running some work */
+ bool running;
+
+ /** @metadata: snapshot of engine activity metadata */
+ struct guc_engine_activity_metadata metadata;
+
+ /** @activity: snapshot of engine activity counter */
+ struct guc_engine_activity activity;
+};
+
+/**
+ * struct engine_activity_group - Activity data for all engines
+ */
+struct engine_activity_group {
+ /** @engine: engine specific activity data */
+ struct engine_activity engine[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
+};
+
+/**
+ * struct engine_activity_buffer - engine activity buffers
+ *
+ * This contains the buffers allocated for metadata and activity data
+ */
+struct engine_activity_buffer {
+ /** @activity_bo: object allocated to hold activity data */
+ struct xe_bo *activity_bo;
+
+ /** @metadata_bo: object allocated to hold activity metadata */
+ struct xe_bo *metadata_bo;
+};
+
+/**
+ * struct xe_guc_engine_activity - Data used by engine activity implementation
+ */
+struct xe_guc_engine_activity {
+ /** @gpm_timestamp_shift: Right shift value for the gpm timestamp */
+ u32 gpm_timestamp_shift;
+
+ /** @num_activity_group: number of activity groups */
+ u32 num_activity_group;
+
+ /** @eag: holds the device level engine activity data */
+ struct engine_activity_group *eag;
+
+ /** @device_buffer: buffer object for global engine activity */
+ struct engine_activity_buffer device_buffer;
+};
+#endif
+
diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
index 057153f89b30..6f57578b07cb 100644
--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
@@ -208,6 +208,25 @@ struct guc_engine_usage {
struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
} __packed;
+/* Engine Activity stats */
+struct guc_engine_activity {
+ u16 change_num;
+ u16 quanta_ratio;
+ u32 last_update_tick;
+ u64 active_ticks;
+} __packed;
+
+struct guc_engine_activity_data {
+ struct guc_engine_activity engine_activity[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
+} __packed;
+
+struct guc_engine_activity_metadata {
+ u32 guc_tsc_frequency_hz;
+ u32 lag_latency_usec;
+ u32 global_change_num;
+ u32 reserved;
+} __packed;
+
/* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
enum xe_guc_recv_message {
XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h
index 573aa6308380..63bac64429a5 100644
--- a/drivers/gpu/drm/xe/xe_guc_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_types.h
@@ -13,6 +13,7 @@
#include "xe_guc_ads_types.h"
#include "xe_guc_buf_types.h"
#include "xe_guc_ct_types.h"
+#include "xe_guc_engine_activity_types.h"
#include "xe_guc_fwif.h"
#include "xe_guc_log_types.h"
#include "xe_guc_pc_types.h"
@@ -103,6 +104,9 @@ struct xe_guc {
/** @relay: GuC Relay Communication used in SR-IOV */
struct xe_guc_relay relay;
+ /** @engine_activity: Device specific engine activity */
+ struct xe_guc_engine_activity engine_activity;
+
/**
* @notify_reg: Register which is written to notify GuC of H2G messages
*/
--
2.47.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [PATCH v4 1/8] drm/xe: Add per-engine-class activity support
2025-01-29 10:16 ` [PATCH v4 1/8] drm/xe: Add per-engine-class activity support Riana Tauro
@ 2025-01-30 0:28 ` Umesh Nerlige Ramappa
2025-01-30 2:35 ` Rodrigo Vivi
2025-01-30 20:38 ` Lucas De Marchi
0 siblings, 2 replies; 45+ messages in thread
From: Umesh Nerlige Ramappa @ 2025-01-30 0:28 UTC (permalink / raw)
To: Riana Tauro
Cc: intel-xe, anshuman.gupta, lucas.demarchi, vinay.belgaumkar,
soham.purkait, rodrigo.vivi
On Wed, Jan 29, 2025 at 03:46:44PM +0530, Riana Tauro wrote:
>GuC provides support to read engine counters to calculate the
>engine activity. KMD exposes two counters via the PMU interface to
>calculate engine activity
>
>Engine Active Ticks(engine-active-ticks) - number of active ticks for engine
>Engine Total Ticks (engine-total-ticks) - total ticks of engine
>
>Engine activity percentage can be calculated as below
>Engine activity % = (engine active ticks/engine total ticks) * 100.
>
>v2: fix cosmetic review comments
> add forcewake for gpm_ts (Umesh)
>
>v3: fix CI hooks error
> change function parameters and unpin bo on error
> of allocate_activity_buffers
> fix kernel-doc (Umesh)
> use engine activity (Umesh, Lucas)
> rename xe_engine_activity to xe_guc_engine_*
> fix commit message to use per-engine class(Lucas)
>
>v4: remove forcewake as engine is already running
> when reading gpm timestamp
+ Rodrigo
Sorry, I think I mentioned offline that the runtime pm get is sufficient
for reading this register, but it's not. It does need a forcewake of the
GT domain. At the same time, we cannot use the xe_force_wake_get
because of the lockdep issue you mentioned and also I assume that
xe_force_wake_get may sleep and the event may be read from irq context.
I would check if we can add a helper xe_force_wake_get_if_active() and
just use that to bump up the wakeref.
@Rodrigo, @Vinay Any thoughts on this ^ ?
Thanks,
Umesh
>
>Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/abi/guc_actions_abi.h | 1 +
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
> drivers/gpu/drm/xe/xe_guc_engine_activity.c | 317 ++++++++++++++++++
> drivers/gpu/drm/xe/xe_guc_engine_activity.h | 18 +
> .../gpu/drm/xe/xe_guc_engine_activity_types.h | 89 +++++
> drivers/gpu/drm/xe/xe_guc_fwif.h | 19 ++
> drivers/gpu/drm/xe/xe_guc_types.h | 4 +
> 8 files changed, 451 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.c
> create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.h
> create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>
>diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>index 328aff36831b..7e93461c60bd 100644
>--- a/drivers/gpu/drm/xe/Makefile
>+++ b/drivers/gpu/drm/xe/Makefile
>@@ -33,6 +33,7 @@ xe-y += xe_bb.o \
> xe_device_sysfs.o \
> xe_dma_buf.o \
> xe_drm_client.o \
>+ xe_guc_engine_activity.o \
> xe_exec.o \
> xe_execlist.o \
> xe_exec_queue.o \
>diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>index fee385532fb0..ec516e838ee8 100644
>--- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>+++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>@@ -140,6 +140,7 @@ enum xe_guc_action {
> XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
> XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
> XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
>+ XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
> XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
> XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
> XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,
>diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>index 096859072396..124cc398798e 100644
>--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>@@ -358,6 +358,8 @@
> #define RENDER_AWAKE_STATUS REG_BIT(1)
> #define MEDIA_SLICE0_AWAKE_STATUS REG_BIT(0)
>
>+#define MISC_STATUS_0 XE_REG(0xa500)
>+
> #define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4)
> #define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4)
> #define FORCEWAKE_GSC XE_REG(0xa618)
>diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>new file mode 100644
>index 000000000000..088209b9c228
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>@@ -0,0 +1,317 @@
>+// SPDX-License-Identifier: MIT
>+/*
>+ * Copyright © 2025 Intel Corporation
>+ */
>+#include "xe_guc_engine_activity.h"
>+
>+#include "abi/guc_actions_abi.h"
>+#include "regs/xe_gt_regs.h"
>+
>+#include "xe_bo.h"
>+#include "xe_force_wake.h"
>+#include "xe_gt_printk.h"
>+#include "xe_guc.h"
>+#include "xe_guc_ct.h"
>+#include "xe_hw_engine.h"
>+#include "xe_map.h"
>+#include "xe_mmio.h"
>+
>+#define TOTAL_QUANTA 0x8000
>+
>+static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_engine *hwe)
>+{
>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>+ struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>+ u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>+ size_t offset = 0;
>+
>+ offset = offsetof(struct guc_engine_activity_data,
>+ engine_activity[guc_class][hwe->logical_instance]);
>+
>+ return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap, offset);
>+}
>+
>+static struct iosys_map engine_metadata_map(struct xe_guc *guc)
>+{
>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>+ struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>+
>+ return buffer->metadata_bo->vmap;
>+}
>+
>+static int allocate_engine_activity_group(struct xe_guc *guc)
>+{
>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>+ u32 num_activity_group = 1;
>+
>+ engine_activity->eag = kmalloc_array(num_activity_group,
>+ sizeof(struct engine_activity_group),
>+ GFP_KERNEL);
>+
>+ if (!engine_activity->eag)
>+ return -ENOMEM;
>+
>+ memset(engine_activity->eag, 0, num_activity_group * sizeof(struct engine_activity_group));
>+ engine_activity->num_activity_group = num_activity_group;
>+
>+ return 0;
>+}
>+
>+static int allocate_engine_activity_buffers(struct xe_guc *guc,
>+ struct engine_activity_buffer *buffer)
>+{
>+ u32 metadata_size = sizeof(struct guc_engine_activity_metadata);
>+ u32 size = sizeof(struct guc_engine_activity_data);
>+ struct xe_gt *gt = guc_to_gt(guc);
>+ struct xe_tile *tile = gt_to_tile(gt);
>+ struct xe_bo *bo, *metadata_bo;
>+
>+ metadata_bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(metadata_size),
>+ XE_BO_FLAG_SYSTEM |
>+ XE_BO_FLAG_GGTT |
>+ XE_BO_FLAG_GGTT_INVALIDATE);
>+ if (IS_ERR(metadata_bo))
>+ return PTR_ERR(metadata_bo);
>+
>+ bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(size),
>+ XE_BO_FLAG_VRAM_IF_DGFX(tile) |
>+ XE_BO_FLAG_GGTT |
>+ XE_BO_FLAG_GGTT_INVALIDATE);
>+
>+ if (IS_ERR(bo)) {
>+ xe_bo_unpin_map_no_vm(metadata_bo);
>+ return PTR_ERR(bo);
>+ }
>+
>+ buffer->metadata_bo = metadata_bo;
>+ buffer->activity_bo = bo;
>+ return 0;
>+}
>+
>+static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine *hwe)
>+{
>+ struct xe_guc *guc = &hwe->gt->uc.guc;
>+ struct engine_activity_group *eag = &guc->engine_activity.eag[0];
>+ u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>+
>+ return &eag->engine[guc_class][hwe->logical_instance];
>+}
>+
>+static u64 cpu_ns_to_guc_tsc_tick(ktime_t ns, u32 freq)
>+{
>+ return mul_u64_u32_div(ns, freq, NSEC_PER_SEC);
>+}
>+
>+#define read_engine_activity_record(xe_, map_, field_) \
>+ xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity, field_)
>+
>+#define read_metadata_record(xe_, map_, field_) \
>+ xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity_metadata, field_)
>+
>+static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>+{
>+ struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>+ struct guc_engine_activity *cached_activity = &ea->activity;
>+ struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>+ struct iosys_map activity_map, metadata_map;
>+ struct xe_device *xe = guc_to_xe(guc);
>+ struct xe_gt *gt = guc_to_gt(guc);
>+ u32 last_update_tick, global_change_num;
>+ u64 active_ticks, gpm_ts;
>+ u16 change_num;
>+
>+ activity_map = engine_activity_map(guc, hwe);
>+ metadata_map = engine_metadata_map(guc);
>+ global_change_num = read_metadata_record(xe, &metadata_map, global_change_num);
>+
>+ /* GuC has not initialized activity data yet, return 0 */
>+ if (!global_change_num)
>+ goto update;
>+
>+ if (global_change_num == cached_metadata->global_change_num)
>+ goto update;
>+ else
>+ cached_metadata->global_change_num = global_change_num;
>+
>+ change_num = read_engine_activity_record(xe, &activity_map, change_num);
>+
>+ if (!change_num || change_num == cached_activity->change_num)
>+ goto update;
>+
>+ /* read engine activity values */
>+ last_update_tick = read_engine_activity_record(xe, &activity_map, last_update_tick);
>+ active_ticks = read_engine_activity_record(xe, &activity_map, active_ticks);
>+
>+ /* activity calculations */
>+ ea->running = !!last_update_tick;
>+ ea->total += active_ticks - cached_activity->active_ticks;
>+ ea->active = 0;
>+
>+ /* cache the counter */
>+ cached_activity->change_num = change_num;
>+ cached_activity->last_update_tick = last_update_tick;
>+ cached_activity->active_ticks = active_ticks;
>+
>+update:
>+ if (ea->running) {
>+ gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
>+ engine_activity->gpm_timestamp_shift;
>+ ea->active = lower_32_bits(gpm_ts) - cached_activity->last_update_tick;
>+ }
>+
>+ return ea->total + ea->active;
>+}
>+
>+static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>+{
>+ struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>+ struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>+ struct guc_engine_activity *cached_activity = &ea->activity;
>+ struct iosys_map activity_map, metadata_map;
>+ struct xe_device *xe = guc_to_xe(guc);
>+ ktime_t now, cpu_delta;
>+ u64 numerator;
>+ u16 quanta_ratio;
>+
>+ activity_map = engine_activity_map(guc, hwe);
>+ metadata_map = engine_metadata_map(guc);
>+
>+ if (!cached_metadata->guc_tsc_frequency_hz)
>+ cached_metadata->guc_tsc_frequency_hz = read_metadata_record(xe, &metadata_map,
>+ guc_tsc_frequency_hz);
>+
>+ quanta_ratio = read_engine_activity_record(xe, &activity_map, quanta_ratio);
>+ cached_activity->quanta_ratio = quanta_ratio;
>+
>+ /* Total ticks calculations */
>+ now = ktime_get();
>+ cpu_delta = now - ea->last_cpu_ts;
>+ ea->last_cpu_ts = now;
>+ numerator = (ea->quanta_remainder_ns + cpu_delta) * cached_activity->quanta_ratio;
>+ ea->quanta_ns += numerator / TOTAL_QUANTA;
>+ ea->quanta_remainder_ns = numerator % TOTAL_QUANTA;
>+ ea->quanta = cpu_ns_to_guc_tsc_tick(ea->quanta_ns, cached_metadata->guc_tsc_frequency_hz);
>+
>+ return ea->quanta;
>+}
>+
>+static int enable_engine_activity_stats(struct xe_guc *guc)
>+{
>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>+ struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>+ u32 metadata_ggtt_addr = xe_bo_ggtt_addr(buffer->metadata_bo);
>+ u32 ggtt_addr = xe_bo_ggtt_addr(buffer->activity_bo);
>+ int len = 0;
>+ u32 action[5];
>+
>+ action[len++] = XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER;
>+ action[len++] = metadata_ggtt_addr;
>+ action[len++] = 0;
>+ action[len++] = ggtt_addr;
>+ action[len++] = 0;
>+
>+ /* Blocking here to ensure the buffers are ready before reading them */
>+ return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
>+}
>+
>+static void engine_activity_set_cpu_ts(struct xe_guc *guc)
>+{
>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>+ struct engine_activity_group *eag = &engine_activity->eag[0];
>+ int i, j;
>+
>+ for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)
>+ for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; j++)
>+ eag->engine[i][j].last_cpu_ts = ktime_get();
>+}
>+
>+static u32 gpm_timestamp_shift(struct xe_gt *gt)
>+{
>+ u32 reg;
>+
>+ reg = xe_mmio_read32(>->mmio, RPM_CONFIG0);
>+
>+ return 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
>+}
>+
>+/**
>+ * xe_guc_engine_activity_active_ticks - Get engine active ticks
>+ * @hwe: The hw_engine object
>+ *
>+ * Return: accumulated ticks @hwe was active since engine activity stats were enabled.
>+ */
>+u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe)
>+{
>+ struct xe_guc *guc = &hwe->gt->uc.guc;
>+
>+ return get_engine_active_ticks(guc, hwe);
>+}
>+
>+/**
>+ * xe_guc_engine_activity_total_ticks - Get engine total ticks
>+ * @hwe: The hw_engine object
>+ *
>+ * Return: accumulated quanta of ticks allocated for the engine
>+ */
>+u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe)
>+{
>+ struct xe_guc *guc = &hwe->gt->uc.guc;
>+
>+ return get_engine_total_ticks(guc, hwe);
>+}
>+
>+/**
>+ * xe_guc_engine_activity_enable_stats - Enable engine activity stats
>+ * @guc: The GuC object
>+ *
>+ * Enable engine activity stats and set initial timestamps
>+ */
>+void xe_guc_engine_activity_enable_stats(struct xe_guc *guc)
>+{
>+ int ret;
>+
>+ ret = enable_engine_activity_stats(guc);
>+ if (ret)
>+ xe_gt_err(guc_to_gt(guc), "failed to enable activity stats%d\n", ret);
>+ else
>+ engine_activity_set_cpu_ts(guc);
>+}
>+
>+static void engine_activity_fini(void *arg)
>+{
>+ struct xe_guc_engine_activity *engine_activity = arg;
>+
>+ kfree(engine_activity->eag);
>+}
>+
>+/**
>+ * xe_guc_engine_activity_init - Initialize the engine activity data
>+ * @guc: The GuC object
>+ *
>+ * Return: 0 on success, negative error code otherwise.
>+ */
>+int xe_guc_engine_activity_init(struct xe_guc *guc)
>+{
>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>+ struct xe_gt *gt = guc_to_gt(guc);
>+ int ret;
>+
>+ ret = allocate_engine_activity_group(guc);
>+ if (ret) {
>+ xe_gt_err(gt, "failed to allocate activity group %d\n", ret);
>+ return ret;
>+ }
>+
>+ ret = allocate_engine_activity_buffers(guc, &engine_activity->device_buffer);
>+ if (ret) {
>+ xe_gt_err(gt, "failed to allocate activity buffers%d\n", ret);
>+ kfree(engine_activity->eag);
>+ return ret;
>+ }
>+
>+ engine_activity->gpm_timestamp_shift = gpm_timestamp_shift(gt);
>+
>+ return devm_add_action_or_reset(gt_to_xe(gt)->drm.dev, engine_activity_fini,
>+ engine_activity);
>+}
>diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.h b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>new file mode 100644
>index 000000000000..c00f3da5513d
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>@@ -0,0 +1,18 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2025 Intel Corporation
>+ */
>+
>+#ifndef _XE_GUC_ENGINE_ACTIVITY_H_
>+#define _XE_GUC_ENGINE_ACTIVITY_H_
>+
>+#include <linux/types.h>
>+
>+struct xe_hw_engine;
>+struct xe_guc;
>+
>+int xe_guc_engine_activity_init(struct xe_guc *guc);
>+void xe_guc_engine_activity_enable_stats(struct xe_guc *guc);
>+u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe);
>+u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe);
>+#endif
>diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>new file mode 100644
>index 000000000000..a2ab327d3eec
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>@@ -0,0 +1,89 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2025 Intel Corporation
>+ */
>+
>+#ifndef _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>+#define _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>+
>+#include <linux/types.h>
>+
>+#include "xe_guc_fwif.h"
>+/**
>+ * struct engine_activity - Engine specific activity data
>+ *
>+ * Contains engine specific activity data and snapshot of the
>+ * structures from GuC
>+ */
>+struct engine_activity {
>+ /** @active: current activity */
>+ u64 active;
>+
>+ /** @last_cpu_ts: cpu timestamp in nsec of previous sample */
>+ u64 last_cpu_ts;
>+
>+ /** @quanta: total quanta used on HW */
>+ u64 quanta;
>+
>+ /** @quanta_ns: total quanta_ns used on HW */
>+ u64 quanta_ns;
>+
>+ /**
>+ * @quanta_remainder_ns: remainder when the CPU time is scaled as
>+ * per the quanta_ratio. This remainder is used in subsequent
>+ * quanta calculations.
>+ */
>+ u64 quanta_remainder_ns;
>+
>+ /** @total: total engine activity */
>+ u64 total;
>+
>+ /** @running: true if engine is running some work */
>+ bool running;
>+
>+ /** @metadata: snapshot of engine activity metadata */
>+ struct guc_engine_activity_metadata metadata;
>+
>+ /** @activity: snapshot of engine activity counter */
>+ struct guc_engine_activity activity;
>+};
>+
>+/**
>+ * struct engine_activity_group - Activity data for all engines
>+ */
>+struct engine_activity_group {
>+ /** @engine: engine specific activity data */
>+ struct engine_activity engine[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>+};
>+
>+/**
>+ * struct engine_activity_buffer - engine activity buffers
>+ *
>+ * This contains the buffers allocated for metadata and activity data
>+ */
>+struct engine_activity_buffer {
>+ /** @activity_bo: object allocated to hold activity data */
>+ struct xe_bo *activity_bo;
>+
>+ /** @metadata_bo: object allocated to hold activity metadata */
>+ struct xe_bo *metadata_bo;
>+};
>+
>+/**
>+ * struct xe_guc_engine_activity - Data used by engine activity implementation
>+ */
>+struct xe_guc_engine_activity {
>+ /** @gpm_timestamp_shift: Right shift value for the gpm timestamp */
>+ u32 gpm_timestamp_shift;
>+
>+ /** @num_activity_group: number of activity groups */
>+ u32 num_activity_group;
>+
>+ /** @eag: holds the device level engine activity data */
>+ struct engine_activity_group *eag;
>+
>+ /** @device_buffer: buffer object for global engine activity */
>+ struct engine_activity_buffer device_buffer;
>+};
>+#endif
>+
>diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
>index 057153f89b30..6f57578b07cb 100644
>--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
>+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
>@@ -208,6 +208,25 @@ struct guc_engine_usage {
> struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
> } __packed;
>
>+/* Engine Activity stats */
>+struct guc_engine_activity {
>+ u16 change_num;
>+ u16 quanta_ratio;
>+ u32 last_update_tick;
>+ u64 active_ticks;
>+} __packed;
>+
>+struct guc_engine_activity_data {
>+ struct guc_engine_activity engine_activity[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>+} __packed;
>+
>+struct guc_engine_activity_metadata {
>+ u32 guc_tsc_frequency_hz;
>+ u32 lag_latency_usec;
>+ u32 global_change_num;
>+ u32 reserved;
>+} __packed;
>+
> /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
> enum xe_guc_recv_message {
> XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
>diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h
>index 573aa6308380..63bac64429a5 100644
>--- a/drivers/gpu/drm/xe/xe_guc_types.h
>+++ b/drivers/gpu/drm/xe/xe_guc_types.h
>@@ -13,6 +13,7 @@
> #include "xe_guc_ads_types.h"
> #include "xe_guc_buf_types.h"
> #include "xe_guc_ct_types.h"
>+#include "xe_guc_engine_activity_types.h"
> #include "xe_guc_fwif.h"
> #include "xe_guc_log_types.h"
> #include "xe_guc_pc_types.h"
>@@ -103,6 +104,9 @@ struct xe_guc {
> /** @relay: GuC Relay Communication used in SR-IOV */
> struct xe_guc_relay relay;
>
>+ /** @engine_activity: Device specific engine activity */
>+ struct xe_guc_engine_activity engine_activity;
>+
> /**
> * @notify_reg: Register which is written to notify GuC of H2G messages
> */
>--
>2.47.1
>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 1/8] drm/xe: Add per-engine-class activity support
2025-01-30 0:28 ` Umesh Nerlige Ramappa
@ 2025-01-30 2:35 ` Rodrigo Vivi
2025-01-30 4:49 ` Riana Tauro
` (2 more replies)
2025-01-30 20:38 ` Lucas De Marchi
1 sibling, 3 replies; 45+ messages in thread
From: Rodrigo Vivi @ 2025-01-30 2:35 UTC (permalink / raw)
To: Umesh Nerlige Ramappa
Cc: Riana Tauro, intel-xe, anshuman.gupta, lucas.demarchi,
vinay.belgaumkar, soham.purkait, Himal Prasad Ghimiray
On Wed, Jan 29, 2025 at 04:28:36PM -0800, Umesh Nerlige Ramappa wrote:
> On Wed, Jan 29, 2025 at 03:46:44PM +0530, Riana Tauro wrote:
> > GuC provides support to read engine counters to calculate the
> > engine activity. KMD exposes two counters via the PMU interface to
> > calculate engine activity
> >
> > Engine Active Ticks(engine-active-ticks) - number of active ticks for engine
> > Engine Total Ticks (engine-total-ticks) - total ticks of engine
> >
> > Engine activity percentage can be calculated as below
> > Engine activity % = (engine active ticks/engine total ticks) * 100.
> >
> > v2: fix cosmetic review comments
> > add forcewake for gpm_ts (Umesh)
> >
> > v3: fix CI hooks error
> > change function parameters and unpin bo on error
> > of allocate_activity_buffers
> > fix kernel-doc (Umesh)
> > use engine activity (Umesh, Lucas)
> > rename xe_engine_activity to xe_guc_engine_*
> > fix commit message to use per-engine class(Lucas)
> >
> > v4: remove forcewake as engine is already running
> > when reading gpm timestamp
>
> + Rodrigo
>
> Sorry, I think I mentioned offline that the runtime pm get is sufficient for
> reading this register, but it's not. It does need a forcewake of the GT
> domain. At the same time, we cannot use the xe_force_wake_get because of
> the lockdep issue you mentioned and also I assume that xe_force_wake_get may
> sleep and the event may be read from irq context.
I don't understand this statement entirely. force wake get cannot sleep.
It is based on spin locks. It should not be issuing any lockdep here.
It is quite simple flow with minimal or none interdependency. Remember
that in i915 for instance it exists and lives in the middle of every
mmio read and write call...
>
> I would check if we can add a helper xe_force_wake_get_if_active() and just
> use that to bump up the wakeref.
I would prefer to not complicate things...
>
> @Rodrigo, @Vinay Any thoughts on this ^ ?
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>
> Thanks,
> Umesh
>
> >
> > Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> > Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> > ---
> > drivers/gpu/drm/xe/Makefile | 1 +
> > drivers/gpu/drm/xe/abi/guc_actions_abi.h | 1 +
> > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
> > drivers/gpu/drm/xe/xe_guc_engine_activity.c | 317 ++++++++++++++++++
> > drivers/gpu/drm/xe/xe_guc_engine_activity.h | 18 +
> > .../gpu/drm/xe/xe_guc_engine_activity_types.h | 89 +++++
> > drivers/gpu/drm/xe/xe_guc_fwif.h | 19 ++
> > drivers/gpu/drm/xe/xe_guc_types.h | 4 +
> > 8 files changed, 451 insertions(+)
> > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.c
> > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.h
> > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
> >
> > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > index 328aff36831b..7e93461c60bd 100644
> > --- a/drivers/gpu/drm/xe/Makefile
> > +++ b/drivers/gpu/drm/xe/Makefile
> > @@ -33,6 +33,7 @@ xe-y += xe_bb.o \
> > xe_device_sysfs.o \
> > xe_dma_buf.o \
> > xe_drm_client.o \
> > + xe_guc_engine_activity.o \
> > xe_exec.o \
> > xe_execlist.o \
> > xe_exec_queue.o \
> > diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
> > index fee385532fb0..ec516e838ee8 100644
> > --- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
> > +++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
> > @@ -140,6 +140,7 @@ enum xe_guc_action {
> > XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
> > XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
> > XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
> > + XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
> > XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
> > XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
> > XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,
> > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > index 096859072396..124cc398798e 100644
> > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > @@ -358,6 +358,8 @@
> > #define RENDER_AWAKE_STATUS REG_BIT(1)
> > #define MEDIA_SLICE0_AWAKE_STATUS REG_BIT(0)
> >
> > +#define MISC_STATUS_0 XE_REG(0xa500)
> > +
> > #define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4)
> > #define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4)
> > #define FORCEWAKE_GSC XE_REG(0xa618)
> > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
> > new file mode 100644
> > index 000000000000..088209b9c228
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
> > @@ -0,0 +1,317 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2025 Intel Corporation
> > + */
> > +#include "xe_guc_engine_activity.h"
> > +
> > +#include "abi/guc_actions_abi.h"
> > +#include "regs/xe_gt_regs.h"
> > +
> > +#include "xe_bo.h"
> > +#include "xe_force_wake.h"
> > +#include "xe_gt_printk.h"
> > +#include "xe_guc.h"
> > +#include "xe_guc_ct.h"
> > +#include "xe_hw_engine.h"
> > +#include "xe_map.h"
> > +#include "xe_mmio.h"
> > +
> > +#define TOTAL_QUANTA 0x8000
> > +
> > +static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_engine *hwe)
> > +{
> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
> > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
> > + u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
> > + size_t offset = 0;
> > +
> > + offset = offsetof(struct guc_engine_activity_data,
> > + engine_activity[guc_class][hwe->logical_instance]);
> > +
> > + return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap, offset);
> > +}
> > +
> > +static struct iosys_map engine_metadata_map(struct xe_guc *guc)
> > +{
> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
> > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
> > +
> > + return buffer->metadata_bo->vmap;
> > +}
> > +
> > +static int allocate_engine_activity_group(struct xe_guc *guc)
> > +{
> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
> > + u32 num_activity_group = 1;
> > +
> > + engine_activity->eag = kmalloc_array(num_activity_group,
> > + sizeof(struct engine_activity_group),
> > + GFP_KERNEL);
> > +
> > + if (!engine_activity->eag)
> > + return -ENOMEM;
> > +
> > + memset(engine_activity->eag, 0, num_activity_group * sizeof(struct engine_activity_group));
> > + engine_activity->num_activity_group = num_activity_group;
> > +
> > + return 0;
> > +}
> > +
> > +static int allocate_engine_activity_buffers(struct xe_guc *guc,
> > + struct engine_activity_buffer *buffer)
> > +{
> > + u32 metadata_size = sizeof(struct guc_engine_activity_metadata);
> > + u32 size = sizeof(struct guc_engine_activity_data);
> > + struct xe_gt *gt = guc_to_gt(guc);
> > + struct xe_tile *tile = gt_to_tile(gt);
> > + struct xe_bo *bo, *metadata_bo;
> > +
> > + metadata_bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(metadata_size),
> > + XE_BO_FLAG_SYSTEM |
> > + XE_BO_FLAG_GGTT |
> > + XE_BO_FLAG_GGTT_INVALIDATE);
> > + if (IS_ERR(metadata_bo))
> > + return PTR_ERR(metadata_bo);
> > +
> > + bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(size),
> > + XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> > + XE_BO_FLAG_GGTT |
> > + XE_BO_FLAG_GGTT_INVALIDATE);
> > +
> > + if (IS_ERR(bo)) {
> > + xe_bo_unpin_map_no_vm(metadata_bo);
> > + return PTR_ERR(bo);
> > + }
> > +
> > + buffer->metadata_bo = metadata_bo;
> > + buffer->activity_bo = bo;
> > + return 0;
> > +}
> > +
> > +static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine *hwe)
> > +{
> > + struct xe_guc *guc = &hwe->gt->uc.guc;
> > + struct engine_activity_group *eag = &guc->engine_activity.eag[0];
> > + u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
> > +
> > + return &eag->engine[guc_class][hwe->logical_instance];
> > +}
> > +
> > +static u64 cpu_ns_to_guc_tsc_tick(ktime_t ns, u32 freq)
> > +{
> > + return mul_u64_u32_div(ns, freq, NSEC_PER_SEC);
> > +}
> > +
> > +#define read_engine_activity_record(xe_, map_, field_) \
> > + xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity, field_)
> > +
> > +#define read_metadata_record(xe_, map_, field_) \
> > + xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity_metadata, field_)
> > +
> > +static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
> > +{
> > + struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
> > + struct guc_engine_activity *cached_activity = &ea->activity;
> > + struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
> > + struct iosys_map activity_map, metadata_map;
> > + struct xe_device *xe = guc_to_xe(guc);
> > + struct xe_gt *gt = guc_to_gt(guc);
> > + u32 last_update_tick, global_change_num;
> > + u64 active_ticks, gpm_ts;
> > + u16 change_num;
> > +
> > + activity_map = engine_activity_map(guc, hwe);
> > + metadata_map = engine_metadata_map(guc);
> > + global_change_num = read_metadata_record(xe, &metadata_map, global_change_num);
> > +
> > + /* GuC has not initialized activity data yet, return 0 */
> > + if (!global_change_num)
> > + goto update;
> > +
> > + if (global_change_num == cached_metadata->global_change_num)
> > + goto update;
> > + else
> > + cached_metadata->global_change_num = global_change_num;
> > +
> > + change_num = read_engine_activity_record(xe, &activity_map, change_num);
> > +
> > + if (!change_num || change_num == cached_activity->change_num)
> > + goto update;
> > +
> > + /* read engine activity values */
> > + last_update_tick = read_engine_activity_record(xe, &activity_map, last_update_tick);
> > + active_ticks = read_engine_activity_record(xe, &activity_map, active_ticks);
> > +
> > + /* activity calculations */
> > + ea->running = !!last_update_tick;
> > + ea->total += active_ticks - cached_activity->active_ticks;
> > + ea->active = 0;
> > +
> > + /* cache the counter */
> > + cached_activity->change_num = change_num;
> > + cached_activity->last_update_tick = last_update_tick;
> > + cached_activity->active_ticks = active_ticks;
> > +
> > +update:
> > + if (ea->running) {
> > + gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
> > + engine_activity->gpm_timestamp_shift;
> > + ea->active = lower_32_bits(gpm_ts) - cached_activity->last_update_tick;
> > + }
> > +
> > + return ea->total + ea->active;
> > +}
> > +
> > +static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
> > +{
> > + struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
> > + struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
> > + struct guc_engine_activity *cached_activity = &ea->activity;
> > + struct iosys_map activity_map, metadata_map;
> > + struct xe_device *xe = guc_to_xe(guc);
> > + ktime_t now, cpu_delta;
> > + u64 numerator;
> > + u16 quanta_ratio;
> > +
> > + activity_map = engine_activity_map(guc, hwe);
> > + metadata_map = engine_metadata_map(guc);
> > +
> > + if (!cached_metadata->guc_tsc_frequency_hz)
> > + cached_metadata->guc_tsc_frequency_hz = read_metadata_record(xe, &metadata_map,
> > + guc_tsc_frequency_hz);
> > +
> > + quanta_ratio = read_engine_activity_record(xe, &activity_map, quanta_ratio);
> > + cached_activity->quanta_ratio = quanta_ratio;
> > +
> > + /* Total ticks calculations */
> > + now = ktime_get();
> > + cpu_delta = now - ea->last_cpu_ts;
> > + ea->last_cpu_ts = now;
> > + numerator = (ea->quanta_remainder_ns + cpu_delta) * cached_activity->quanta_ratio;
> > + ea->quanta_ns += numerator / TOTAL_QUANTA;
> > + ea->quanta_remainder_ns = numerator % TOTAL_QUANTA;
> > + ea->quanta = cpu_ns_to_guc_tsc_tick(ea->quanta_ns, cached_metadata->guc_tsc_frequency_hz);
> > +
> > + return ea->quanta;
> > +}
> > +
> > +static int enable_engine_activity_stats(struct xe_guc *guc)
> > +{
> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
> > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
> > + u32 metadata_ggtt_addr = xe_bo_ggtt_addr(buffer->metadata_bo);
> > + u32 ggtt_addr = xe_bo_ggtt_addr(buffer->activity_bo);
> > + int len = 0;
> > + u32 action[5];
> > +
> > + action[len++] = XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER;
> > + action[len++] = metadata_ggtt_addr;
> > + action[len++] = 0;
> > + action[len++] = ggtt_addr;
> > + action[len++] = 0;
> > +
> > + /* Blocking here to ensure the buffers are ready before reading them */
> > + return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
> > +}
> > +
> > +static void engine_activity_set_cpu_ts(struct xe_guc *guc)
> > +{
> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
> > + struct engine_activity_group *eag = &engine_activity->eag[0];
> > + int i, j;
> > +
> > + for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)
> > + for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; j++)
> > + eag->engine[i][j].last_cpu_ts = ktime_get();
> > +}
> > +
> > +static u32 gpm_timestamp_shift(struct xe_gt *gt)
> > +{
> > + u32 reg;
> > +
> > + reg = xe_mmio_read32(>->mmio, RPM_CONFIG0);
> > +
> > + return 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
> > +}
> > +
> > +/**
> > + * xe_guc_engine_activity_active_ticks - Get engine active ticks
> > + * @hwe: The hw_engine object
> > + *
> > + * Return: accumulated ticks @hwe was active since engine activity stats were enabled.
> > + */
> > +u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe)
> > +{
> > + struct xe_guc *guc = &hwe->gt->uc.guc;
> > +
> > + return get_engine_active_ticks(guc, hwe);
> > +}
> > +
> > +/**
> > + * xe_guc_engine_activity_total_ticks - Get engine total ticks
> > + * @hwe: The hw_engine object
> > + *
> > + * Return: accumulated quanta of ticks allocated for the engine
> > + */
> > +u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe)
> > +{
> > + struct xe_guc *guc = &hwe->gt->uc.guc;
> > +
> > + return get_engine_total_ticks(guc, hwe);
> > +}
> > +
> > +/**
> > + * xe_guc_engine_activity_enable_stats - Enable engine activity stats
> > + * @guc: The GuC object
> > + *
> > + * Enable engine activity stats and set initial timestamps
> > + */
> > +void xe_guc_engine_activity_enable_stats(struct xe_guc *guc)
> > +{
> > + int ret;
> > +
> > + ret = enable_engine_activity_stats(guc);
> > + if (ret)
> > + xe_gt_err(guc_to_gt(guc), "failed to enable activity stats%d\n", ret);
> > + else
> > + engine_activity_set_cpu_ts(guc);
> > +}
> > +
> > +static void engine_activity_fini(void *arg)
> > +{
> > + struct xe_guc_engine_activity *engine_activity = arg;
> > +
> > + kfree(engine_activity->eag);
> > +}
> > +
> > +/**
> > + * xe_guc_engine_activity_init - Initialize the engine activity data
> > + * @guc: The GuC object
> > + *
> > + * Return: 0 on success, negative error code otherwise.
> > + */
> > +int xe_guc_engine_activity_init(struct xe_guc *guc)
> > +{
> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
> > + struct xe_gt *gt = guc_to_gt(guc);
> > + int ret;
> > +
> > + ret = allocate_engine_activity_group(guc);
> > + if (ret) {
> > + xe_gt_err(gt, "failed to allocate activity group %d\n", ret);
> > + return ret;
> > + }
> > +
> > + ret = allocate_engine_activity_buffers(guc, &engine_activity->device_buffer);
> > + if (ret) {
> > + xe_gt_err(gt, "failed to allocate activity buffers%d\n", ret);
> > + kfree(engine_activity->eag);
> > + return ret;
> > + }
> > +
> > + engine_activity->gpm_timestamp_shift = gpm_timestamp_shift(gt);
> > +
> > + return devm_add_action_or_reset(gt_to_xe(gt)->drm.dev, engine_activity_fini,
> > + engine_activity);
> > +}
> > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.h b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
> > new file mode 100644
> > index 000000000000..c00f3da5513d
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
> > @@ -0,0 +1,18 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2025 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_GUC_ENGINE_ACTIVITY_H_
> > +#define _XE_GUC_ENGINE_ACTIVITY_H_
> > +
> > +#include <linux/types.h>
> > +
> > +struct xe_hw_engine;
> > +struct xe_guc;
> > +
> > +int xe_guc_engine_activity_init(struct xe_guc *guc);
> > +void xe_guc_engine_activity_enable_stats(struct xe_guc *guc);
> > +u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe);
> > +u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe);
> > +#endif
> > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
> > new file mode 100644
> > index 000000000000..a2ab327d3eec
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
> > @@ -0,0 +1,89 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2025 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
> > +#define _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
> > +
> > +#include <linux/types.h>
> > +
> > +#include "xe_guc_fwif.h"
> > +/**
> > + * struct engine_activity - Engine specific activity data
> > + *
> > + * Contains engine specific activity data and snapshot of the
> > + * structures from GuC
> > + */
> > +struct engine_activity {
> > + /** @active: current activity */
> > + u64 active;
> > +
> > + /** @last_cpu_ts: cpu timestamp in nsec of previous sample */
> > + u64 last_cpu_ts;
> > +
> > + /** @quanta: total quanta used on HW */
> > + u64 quanta;
> > +
> > + /** @quanta_ns: total quanta_ns used on HW */
> > + u64 quanta_ns;
> > +
> > + /**
> > + * @quanta_remainder_ns: remainder when the CPU time is scaled as
> > + * per the quanta_ratio. This remainder is used in subsequent
> > + * quanta calculations.
> > + */
> > + u64 quanta_remainder_ns;
> > +
> > + /** @total: total engine activity */
> > + u64 total;
> > +
> > + /** @running: true if engine is running some work */
> > + bool running;
> > +
> > + /** @metadata: snapshot of engine activity metadata */
> > + struct guc_engine_activity_metadata metadata;
> > +
> > + /** @activity: snapshot of engine activity counter */
> > + struct guc_engine_activity activity;
> > +};
> > +
> > +/**
> > + * struct engine_activity_group - Activity data for all engines
> > + */
> > +struct engine_activity_group {
> > + /** @engine: engine specific activity data */
> > + struct engine_activity engine[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
> > +};
> > +
> > +/**
> > + * struct engine_activity_buffer - engine activity buffers
> > + *
> > + * This contains the buffers allocated for metadata and activity data
> > + */
> > +struct engine_activity_buffer {
> > + /** @activity_bo: object allocated to hold activity data */
> > + struct xe_bo *activity_bo;
> > +
> > + /** @metadata_bo: object allocated to hold activity metadata */
> > + struct xe_bo *metadata_bo;
> > +};
> > +
> > +/**
> > + * struct xe_guc_engine_activity - Data used by engine activity implementation
> > + */
> > +struct xe_guc_engine_activity {
> > + /** @gpm_timestamp_shift: Right shift value for the gpm timestamp */
> > + u32 gpm_timestamp_shift;
> > +
> > + /** @num_activity_group: number of activity groups */
> > + u32 num_activity_group;
> > +
> > + /** @eag: holds the device level engine activity data */
> > + struct engine_activity_group *eag;
> > +
> > + /** @device_buffer: buffer object for global engine activity */
> > + struct engine_activity_buffer device_buffer;
> > +};
> > +#endif
> > +
> > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > index 057153f89b30..6f57578b07cb 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > @@ -208,6 +208,25 @@ struct guc_engine_usage {
> > struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
> > } __packed;
> >
> > +/* Engine Activity stats */
> > +struct guc_engine_activity {
> > + u16 change_num;
> > + u16 quanta_ratio;
> > + u32 last_update_tick;
> > + u64 active_ticks;
> > +} __packed;
> > +
> > +struct guc_engine_activity_data {
> > + struct guc_engine_activity engine_activity[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
> > +} __packed;
> > +
> > +struct guc_engine_activity_metadata {
> > + u32 guc_tsc_frequency_hz;
> > + u32 lag_latency_usec;
> > + u32 global_change_num;
> > + u32 reserved;
> > +} __packed;
> > +
> > /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
> > enum xe_guc_recv_message {
> > XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
> > diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h
> > index 573aa6308380..63bac64429a5 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_types.h
> > +++ b/drivers/gpu/drm/xe/xe_guc_types.h
> > @@ -13,6 +13,7 @@
> > #include "xe_guc_ads_types.h"
> > #include "xe_guc_buf_types.h"
> > #include "xe_guc_ct_types.h"
> > +#include "xe_guc_engine_activity_types.h"
> > #include "xe_guc_fwif.h"
> > #include "xe_guc_log_types.h"
> > #include "xe_guc_pc_types.h"
> > @@ -103,6 +104,9 @@ struct xe_guc {
> > /** @relay: GuC Relay Communication used in SR-IOV */
> > struct xe_guc_relay relay;
> >
> > + /** @engine_activity: Device specific engine activity */
> > + struct xe_guc_engine_activity engine_activity;
> > +
> > /**
> > * @notify_reg: Register which is written to notify GuC of H2G messages
> > */
> > --
> > 2.47.1
> >
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 1/8] drm/xe: Add per-engine-class activity support
2025-01-30 2:35 ` Rodrigo Vivi
@ 2025-01-30 4:49 ` Riana Tauro
2025-01-30 22:36 ` Rodrigo Vivi
2025-01-30 23:00 ` Lucas De Marchi
2025-01-30 17:52 ` Umesh Nerlige Ramappa
2025-01-30 20:47 ` Lucas De Marchi
2 siblings, 2 replies; 45+ messages in thread
From: Riana Tauro @ 2025-01-30 4:49 UTC (permalink / raw)
To: Rodrigo Vivi, Umesh Nerlige Ramappa
Cc: intel-xe, anshuman.gupta, lucas.demarchi, vinay.belgaumkar,
soham.purkait, Himal Prasad Ghimiray
Hi Umesh/Rodrigo
On 1/30/2025 8:05 AM, Rodrigo Vivi wrote:
> On Wed, Jan 29, 2025 at 04:28:36PM -0800, Umesh Nerlige Ramappa wrote:
>> On Wed, Jan 29, 2025 at 03:46:44PM +0530, Riana Tauro wrote:
>>> GuC provides support to read engine counters to calculate the
>>> engine activity. KMD exposes two counters via the PMU interface to
>>> calculate engine activity
>>>
>>> Engine Active Ticks(engine-active-ticks) - number of active ticks for engine
>>> Engine Total Ticks (engine-total-ticks) - total ticks of engine
>>>
>>> Engine activity percentage can be calculated as below
>>> Engine activity % = (engine active ticks/engine total ticks) * 100.
>>>
>>> v2: fix cosmetic review comments
>>> add forcewake for gpm_ts (Umesh)
>>>
>>> v3: fix CI hooks error
>>> change function parameters and unpin bo on error
>>> of allocate_activity_buffers
>>> fix kernel-doc (Umesh)
>>> use engine activity (Umesh, Lucas)
>>> rename xe_engine_activity to xe_guc_engine_*
>>> fix commit message to use per-engine class(Lucas)
>>>
>>> v4: remove forcewake as engine is already running
>>> when reading gpm timestamp
>>
>> + Rodrigo
>>
>> Sorry, I think I mentioned offline that the runtime pm get is sufficient for
>> reading this register, but it's not. It does need a forcewake of the GT
>> domain. At the same time, we cannot use the xe_force_wake_get because of
>> the lockdep issue you mentioned and also I assume that xe_force_wake_get may
>> sleep and the event may be read from irq context.
The lockdep issue is due to perf holding a raw_spinlock and forcewake
having a spinlock. In 6.13 due to config PROVE_RAW_LOCK_NESTING being
enabled was seeing this issue. Latest patch has disabled this due to
issues with i915.
[ 465.359017] =============================
[ 465.363050] [ BUG: Invalid wait context ]
[ 465.367063] 6.13.0-rc5-xe #11 Tainted: G U
[ 465.372544] -----------------------------
[ 465.376555] swapper/0/0 is trying to lock:
[ 465.380652] ffff88810d5b8098 (&fw->lock){....}-{3:3}, at:
xe_force_wake_get+0x1f9/0x8c0 [xe]
[ 465.389168] other info that might help us debug this:
[ 465.394221] context-{5:5}
[ 465.396847] 1 lock held by swapper/0/0:
[ 465.400682] #0: ffff88885f031fb8 (&cpuctx_lock){....}-{2:2}, at:
__perf_event_read+0x60/0x230
[ 465.409295] stack backtrace:
Since in this case we are checking mmio only when engine is running
and gt will be active. i thought we could remove it.
>>> + if (ea->running) {
>>> + gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
>>> + engine_activity->gpm_timestamp_shift;
>>> + ea->active = lower_32_bits(gpm_ts) -
cached_activity->last_update_tick;
>>> + }
But yeah, gt might enter c6 just after reading ea->running. To avoid
this,as lucas suggested have to use hr timer.
I thought if needed, will add it as part of a separate series.
I can add the forcewake back as the config is removed and add hr timer
in another series.
Thanks
Riana
>
> I don't understand this statement entirely. force wake get cannot sleep.
> It is based on spin locks. It should not be issuing any lockdep here.
> It is quite simple flow with minimal or none interdependency. Remember
> that in i915 for instance it exists and lives in the middle of every
> mmio read and write call...
>
>>
>> I would check if we can add a helper xe_force_wake_get_if_active() and just
>> use that to bump up the wakeref.
>
> I would prefer to not complicate things...
>
>>
>> @Rodrigo, @Vinay Any thoughts on this ^ ?
>
> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>
>>
>> Thanks,
>> Umesh
>>
>>>
>>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>>> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>> ---
>>> drivers/gpu/drm/xe/Makefile | 1 +
>>> drivers/gpu/drm/xe/abi/guc_actions_abi.h | 1 +
>>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
>>> drivers/gpu/drm/xe/xe_guc_engine_activity.c | 317 ++++++++++++++++++
>>> drivers/gpu/drm/xe/xe_guc_engine_activity.h | 18 +
>>> .../gpu/drm/xe/xe_guc_engine_activity_types.h | 89 +++++
>>> drivers/gpu/drm/xe/xe_guc_fwif.h | 19 ++
>>> drivers/gpu/drm/xe/xe_guc_types.h | 4 +
>>> 8 files changed, 451 insertions(+)
>>> create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>> create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.h
>>> create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>>>
>>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>>> index 328aff36831b..7e93461c60bd 100644
>>> --- a/drivers/gpu/drm/xe/Makefile
>>> +++ b/drivers/gpu/drm/xe/Makefile
>>> @@ -33,6 +33,7 @@ xe-y += xe_bb.o \
>>> xe_device_sysfs.o \
>>> xe_dma_buf.o \
>>> xe_drm_client.o \
>>> + xe_guc_engine_activity.o \
>>> xe_exec.o \
>>> xe_execlist.o \
>>> xe_exec_queue.o \
>>> diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>> index fee385532fb0..ec516e838ee8 100644
>>> --- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>> +++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>> @@ -140,6 +140,7 @@ enum xe_guc_action {
>>> XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
>>> XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
>>> XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
>>> + XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
>>> XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
>>> XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
>>> XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,
>>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>> index 096859072396..124cc398798e 100644
>>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>> @@ -358,6 +358,8 @@
>>> #define RENDER_AWAKE_STATUS REG_BIT(1)
>>> #define MEDIA_SLICE0_AWAKE_STATUS REG_BIT(0)
>>>
>>> +#define MISC_STATUS_0 XE_REG(0xa500)
>>> +
>>> #define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4)
>>> #define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4)
>>> #define FORCEWAKE_GSC XE_REG(0xa618)
>>> diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>> new file mode 100644
>>> index 000000000000..088209b9c228
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>> @@ -0,0 +1,317 @@
>>> +// SPDX-License-Identifier: MIT
>>> +/*
>>> + * Copyright © 2025 Intel Corporation
>>> + */
>>> +#include "xe_guc_engine_activity.h"
>>> +
>>> +#include "abi/guc_actions_abi.h"
>>> +#include "regs/xe_gt_regs.h"
>>> +
>>> +#include "xe_bo.h"
>>> +#include "xe_force_wake.h"
>>> +#include "xe_gt_printk.h"
>>> +#include "xe_guc.h"
>>> +#include "xe_guc_ct.h"
>>> +#include "xe_hw_engine.h"
>>> +#include "xe_map.h"
>>> +#include "xe_mmio.h"
>>> +
>>> +#define TOTAL_QUANTA 0x8000
>>> +
>>> +static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_engine *hwe)
>>> +{
>>> + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>> + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>>> + u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>>> + size_t offset = 0;
>>> +
>>> + offset = offsetof(struct guc_engine_activity_data,
>>> + engine_activity[guc_class][hwe->logical_instance]);
>>> +
>>> + return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap, offset);
>>> +}
>>> +
>>> +static struct iosys_map engine_metadata_map(struct xe_guc *guc)
>>> +{
>>> + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>> + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>>> +
>>> + return buffer->metadata_bo->vmap;
>>> +}
>>> +
>>> +static int allocate_engine_activity_group(struct xe_guc *guc)
>>> +{
>>> + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>> + u32 num_activity_group = 1;
>>> +
>>> + engine_activity->eag = kmalloc_array(num_activity_group,
>>> + sizeof(struct engine_activity_group),
>>> + GFP_KERNEL);
>>> +
>>> + if (!engine_activity->eag)
>>> + return -ENOMEM;
>>> +
>>> + memset(engine_activity->eag, 0, num_activity_group * sizeof(struct engine_activity_group));
>>> + engine_activity->num_activity_group = num_activity_group;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int allocate_engine_activity_buffers(struct xe_guc *guc,
>>> + struct engine_activity_buffer *buffer)
>>> +{
>>> + u32 metadata_size = sizeof(struct guc_engine_activity_metadata);
>>> + u32 size = sizeof(struct guc_engine_activity_data);
>>> + struct xe_gt *gt = guc_to_gt(guc);
>>> + struct xe_tile *tile = gt_to_tile(gt);
>>> + struct xe_bo *bo, *metadata_bo;
>>> +
>>> + metadata_bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(metadata_size),
>>> + XE_BO_FLAG_SYSTEM |
>>> + XE_BO_FLAG_GGTT |
>>> + XE_BO_FLAG_GGTT_INVALIDATE);
>>> + if (IS_ERR(metadata_bo))
>>> + return PTR_ERR(metadata_bo);
>>> +
>>> + bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(size),
>>> + XE_BO_FLAG_VRAM_IF_DGFX(tile) |
>>> + XE_BO_FLAG_GGTT |
>>> + XE_BO_FLAG_GGTT_INVALIDATE);
>>> +
>>> + if (IS_ERR(bo)) {
>>> + xe_bo_unpin_map_no_vm(metadata_bo);
>>> + return PTR_ERR(bo);
>>> + }
>>> +
>>> + buffer->metadata_bo = metadata_bo;
>>> + buffer->activity_bo = bo;
>>> + return 0;
>>> +}
>>> +
>>> +static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine *hwe)
>>> +{
>>> + struct xe_guc *guc = &hwe->gt->uc.guc;
>>> + struct engine_activity_group *eag = &guc->engine_activity.eag[0];
>>> + u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>>> +
>>> + return &eag->engine[guc_class][hwe->logical_instance];
>>> +}
>>> +
>>> +static u64 cpu_ns_to_guc_tsc_tick(ktime_t ns, u32 freq)
>>> +{
>>> + return mul_u64_u32_div(ns, freq, NSEC_PER_SEC);
>>> +}
>>> +
>>> +#define read_engine_activity_record(xe_, map_, field_) \
>>> + xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity, field_)
>>> +
>>> +#define read_metadata_record(xe_, map_, field_) \
>>> + xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity_metadata, field_)
>>> +
>>> +static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>>> +{
>>> + struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>>> + struct guc_engine_activity *cached_activity = &ea->activity;
>>> + struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>>> + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>> + struct iosys_map activity_map, metadata_map;
>>> + struct xe_device *xe = guc_to_xe(guc);
>>> + struct xe_gt *gt = guc_to_gt(guc);
>>> + u32 last_update_tick, global_change_num;
>>> + u64 active_ticks, gpm_ts;
>>> + u16 change_num;
>>> +
>>> + activity_map = engine_activity_map(guc, hwe);
>>> + metadata_map = engine_metadata_map(guc);
>>> + global_change_num = read_metadata_record(xe, &metadata_map, global_change_num);
>>> +
>>> + /* GuC has not initialized activity data yet, return 0 */
>>> + if (!global_change_num)
>>> + goto update;
>>> +
>>> + if (global_change_num == cached_metadata->global_change_num)
>>> + goto update;
>>> + else
>>> + cached_metadata->global_change_num = global_change_num;
>>> +
>>> + change_num = read_engine_activity_record(xe, &activity_map, change_num);
>>> +
>>> + if (!change_num || change_num == cached_activity->change_num)
>>> + goto update;
>>> +
>>> + /* read engine activity values */
>>> + last_update_tick = read_engine_activity_record(xe, &activity_map, last_update_tick);
>>> + active_ticks = read_engine_activity_record(xe, &activity_map, active_ticks);
>>> +
>>> + /* activity calculations */
>>> + ea->running = !!last_update_tick;
>>> + ea->total += active_ticks - cached_activity->active_ticks;
>>> + ea->active = 0;
>>> +
>>> + /* cache the counter */
>>> + cached_activity->change_num = change_num;
>>> + cached_activity->last_update_tick = last_update_tick;
>>> + cached_activity->active_ticks = active_ticks;
>>> +
>>> +update:
>>> + if (ea->running) {
>>> + gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
>>> + engine_activity->gpm_timestamp_shift;
>>> + ea->active = lower_32_bits(gpm_ts) - cached_activity->last_update_tick;
>>> + }
>>> +
>>> + return ea->total + ea->active;
>>> +}
>>> +
>>> +static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>>> +{
>>> + struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>>> + struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>>> + struct guc_engine_activity *cached_activity = &ea->activity;
>>> + struct iosys_map activity_map, metadata_map;
>>> + struct xe_device *xe = guc_to_xe(guc);
>>> + ktime_t now, cpu_delta;
>>> + u64 numerator;
>>> + u16 quanta_ratio;
>>> +
>>> + activity_map = engine_activity_map(guc, hwe);
>>> + metadata_map = engine_metadata_map(guc);
>>> +
>>> + if (!cached_metadata->guc_tsc_frequency_hz)
>>> + cached_metadata->guc_tsc_frequency_hz = read_metadata_record(xe, &metadata_map,
>>> + guc_tsc_frequency_hz);
>>> +
>>> + quanta_ratio = read_engine_activity_record(xe, &activity_map, quanta_ratio);
>>> + cached_activity->quanta_ratio = quanta_ratio;
>>> +
>>> + /* Total ticks calculations */
>>> + now = ktime_get();
>>> + cpu_delta = now - ea->last_cpu_ts;
>>> + ea->last_cpu_ts = now;
>>> + numerator = (ea->quanta_remainder_ns + cpu_delta) * cached_activity->quanta_ratio;
>>> + ea->quanta_ns += numerator / TOTAL_QUANTA;
>>> + ea->quanta_remainder_ns = numerator % TOTAL_QUANTA;
>>> + ea->quanta = cpu_ns_to_guc_tsc_tick(ea->quanta_ns, cached_metadata->guc_tsc_frequency_hz);
>>> +
>>> + return ea->quanta;
>>> +}
>>> +
>>> +static int enable_engine_activity_stats(struct xe_guc *guc)
>>> +{
>>> + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>> + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>>> + u32 metadata_ggtt_addr = xe_bo_ggtt_addr(buffer->metadata_bo);
>>> + u32 ggtt_addr = xe_bo_ggtt_addr(buffer->activity_bo);
>>> + int len = 0;
>>> + u32 action[5];
>>> +
>>> + action[len++] = XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER;
>>> + action[len++] = metadata_ggtt_addr;
>>> + action[len++] = 0;
>>> + action[len++] = ggtt_addr;
>>> + action[len++] = 0;
>>> +
>>> + /* Blocking here to ensure the buffers are ready before reading them */
>>> + return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
>>> +}
>>> +
>>> +static void engine_activity_set_cpu_ts(struct xe_guc *guc)
>>> +{
>>> + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>> + struct engine_activity_group *eag = &engine_activity->eag[0];
>>> + int i, j;
>>> +
>>> + for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)
>>> + for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; j++)
>>> + eag->engine[i][j].last_cpu_ts = ktime_get();
>>> +}
>>> +
>>> +static u32 gpm_timestamp_shift(struct xe_gt *gt)
>>> +{
>>> + u32 reg;
>>> +
>>> + reg = xe_mmio_read32(>->mmio, RPM_CONFIG0);
>>> +
>>> + return 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
>>> +}
>>> +
>>> +/**
>>> + * xe_guc_engine_activity_active_ticks - Get engine active ticks
>>> + * @hwe: The hw_engine object
>>> + *
>>> + * Return: accumulated ticks @hwe was active since engine activity stats were enabled.
>>> + */
>>> +u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe)
>>> +{
>>> + struct xe_guc *guc = &hwe->gt->uc.guc;
>>> +
>>> + return get_engine_active_ticks(guc, hwe);
>>> +}
>>> +
>>> +/**
>>> + * xe_guc_engine_activity_total_ticks - Get engine total ticks
>>> + * @hwe: The hw_engine object
>>> + *
>>> + * Return: accumulated quanta of ticks allocated for the engine
>>> + */
>>> +u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe)
>>> +{
>>> + struct xe_guc *guc = &hwe->gt->uc.guc;
>>> +
>>> + return get_engine_total_ticks(guc, hwe);
>>> +}
>>> +
>>> +/**
>>> + * xe_guc_engine_activity_enable_stats - Enable engine activity stats
>>> + * @guc: The GuC object
>>> + *
>>> + * Enable engine activity stats and set initial timestamps
>>> + */
>>> +void xe_guc_engine_activity_enable_stats(struct xe_guc *guc)
>>> +{
>>> + int ret;
>>> +
>>> + ret = enable_engine_activity_stats(guc);
>>> + if (ret)
>>> + xe_gt_err(guc_to_gt(guc), "failed to enable activity stats%d\n", ret);
>>> + else
>>> + engine_activity_set_cpu_ts(guc);
>>> +}
>>> +
>>> +static void engine_activity_fini(void *arg)
>>> +{
>>> + struct xe_guc_engine_activity *engine_activity = arg;
>>> +
>>> + kfree(engine_activity->eag);
>>> +}
>>> +
>>> +/**
>>> + * xe_guc_engine_activity_init - Initialize the engine activity data
>>> + * @guc: The GuC object
>>> + *
>>> + * Return: 0 on success, negative error code otherwise.
>>> + */
>>> +int xe_guc_engine_activity_init(struct xe_guc *guc)
>>> +{
>>> + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>> + struct xe_gt *gt = guc_to_gt(guc);
>>> + int ret;
>>> +
>>> + ret = allocate_engine_activity_group(guc);
>>> + if (ret) {
>>> + xe_gt_err(gt, "failed to allocate activity group %d\n", ret);
>>> + return ret;
>>> + }
>>> +
>>> + ret = allocate_engine_activity_buffers(guc, &engine_activity->device_buffer);
>>> + if (ret) {
>>> + xe_gt_err(gt, "failed to allocate activity buffers%d\n", ret);
>>> + kfree(engine_activity->eag);
>>> + return ret;
>>> + }
>>> +
>>> + engine_activity->gpm_timestamp_shift = gpm_timestamp_shift(gt);
>>> +
>>> + return devm_add_action_or_reset(gt_to_xe(gt)->drm.dev, engine_activity_fini,
>>> + engine_activity);
>>> +}
>>> diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.h b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>>> new file mode 100644
>>> index 000000000000..c00f3da5513d
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>>> @@ -0,0 +1,18 @@
>>> +/* SPDX-License-Identifier: MIT */
>>> +/*
>>> + * Copyright © 2025 Intel Corporation
>>> + */
>>> +
>>> +#ifndef _XE_GUC_ENGINE_ACTIVITY_H_
>>> +#define _XE_GUC_ENGINE_ACTIVITY_H_
>>> +
>>> +#include <linux/types.h>
>>> +
>>> +struct xe_hw_engine;
>>> +struct xe_guc;
>>> +
>>> +int xe_guc_engine_activity_init(struct xe_guc *guc);
>>> +void xe_guc_engine_activity_enable_stats(struct xe_guc *guc);
>>> +u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe);
>>> +u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe);
>>> +#endif
>>> diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>>> new file mode 100644
>>> index 000000000000..a2ab327d3eec
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>>> @@ -0,0 +1,89 @@
>>> +/* SPDX-License-Identifier: MIT */
>>> +/*
>>> + * Copyright © 2025 Intel Corporation
>>> + */
>>> +
>>> +#ifndef _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>>> +#define _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>>> +
>>> +#include <linux/types.h>
>>> +
>>> +#include "xe_guc_fwif.h"
>>> +/**
>>> + * struct engine_activity - Engine specific activity data
>>> + *
>>> + * Contains engine specific activity data and snapshot of the
>>> + * structures from GuC
>>> + */
>>> +struct engine_activity {
>>> + /** @active: current activity */
>>> + u64 active;
>>> +
>>> + /** @last_cpu_ts: cpu timestamp in nsec of previous sample */
>>> + u64 last_cpu_ts;
>>> +
>>> + /** @quanta: total quanta used on HW */
>>> + u64 quanta;
>>> +
>>> + /** @quanta_ns: total quanta_ns used on HW */
>>> + u64 quanta_ns;
>>> +
>>> + /**
>>> + * @quanta_remainder_ns: remainder when the CPU time is scaled as
>>> + * per the quanta_ratio. This remainder is used in subsequent
>>> + * quanta calculations.
>>> + */
>>> + u64 quanta_remainder_ns;
>>> +
>>> + /** @total: total engine activity */
>>> + u64 total;
>>> +
>>> + /** @running: true if engine is running some work */
>>> + bool running;
>>> +
>>> + /** @metadata: snapshot of engine activity metadata */
>>> + struct guc_engine_activity_metadata metadata;
>>> +
>>> + /** @activity: snapshot of engine activity counter */
>>> + struct guc_engine_activity activity;
>>> +};
>>> +
>>> +/**
>>> + * struct engine_activity_group - Activity data for all engines
>>> + */
>>> +struct engine_activity_group {
>>> + /** @engine: engine specific activity data */
>>> + struct engine_activity engine[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>>> +};
>>> +
>>> +/**
>>> + * struct engine_activity_buffer - engine activity buffers
>>> + *
>>> + * This contains the buffers allocated for metadata and activity data
>>> + */
>>> +struct engine_activity_buffer {
>>> + /** @activity_bo: object allocated to hold activity data */
>>> + struct xe_bo *activity_bo;
>>> +
>>> + /** @metadata_bo: object allocated to hold activity metadata */
>>> + struct xe_bo *metadata_bo;
>>> +};
>>> +
>>> +/**
>>> + * struct xe_guc_engine_activity - Data used by engine activity implementation
>>> + */
>>> +struct xe_guc_engine_activity {
>>> + /** @gpm_timestamp_shift: Right shift value for the gpm timestamp */
>>> + u32 gpm_timestamp_shift;
>>> +
>>> + /** @num_activity_group: number of activity groups */
>>> + u32 num_activity_group;
>>> +
>>> + /** @eag: holds the device level engine activity data */
>>> + struct engine_activity_group *eag;
>>> +
>>> + /** @device_buffer: buffer object for global engine activity */
>>> + struct engine_activity_buffer device_buffer;
>>> +};
>>> +#endif
>>> +
>>> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
>>> index 057153f89b30..6f57578b07cb 100644
>>> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
>>> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
>>> @@ -208,6 +208,25 @@ struct guc_engine_usage {
>>> struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>>> } __packed;
>>>
>>> +/* Engine Activity stats */
>>> +struct guc_engine_activity {
>>> + u16 change_num;
>>> + u16 quanta_ratio;
>>> + u32 last_update_tick;
>>> + u64 active_ticks;
>>> +} __packed;
>>> +
>>> +struct guc_engine_activity_data {
>>> + struct guc_engine_activity engine_activity[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>>> +} __packed;
>>> +
>>> +struct guc_engine_activity_metadata {
>>> + u32 guc_tsc_frequency_hz;
>>> + u32 lag_latency_usec;
>>> + u32 global_change_num;
>>> + u32 reserved;
>>> +} __packed;
>>> +
>>> /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
>>> enum xe_guc_recv_message {
>>> XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
>>> diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h
>>> index 573aa6308380..63bac64429a5 100644
>>> --- a/drivers/gpu/drm/xe/xe_guc_types.h
>>> +++ b/drivers/gpu/drm/xe/xe_guc_types.h
>>> @@ -13,6 +13,7 @@
>>> #include "xe_guc_ads_types.h"
>>> #include "xe_guc_buf_types.h"
>>> #include "xe_guc_ct_types.h"
>>> +#include "xe_guc_engine_activity_types.h"
>>> #include "xe_guc_fwif.h"
>>> #include "xe_guc_log_types.h"
>>> #include "xe_guc_pc_types.h"
>>> @@ -103,6 +104,9 @@ struct xe_guc {
>>> /** @relay: GuC Relay Communication used in SR-IOV */
>>> struct xe_guc_relay relay;
>>>
>>> + /** @engine_activity: Device specific engine activity */
>>> + struct xe_guc_engine_activity engine_activity;
>>> +
>>> /**
>>> * @notify_reg: Register which is written to notify GuC of H2G messages
>>> */
>>> --
>>> 2.47.1
>>>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 1/8] drm/xe: Add per-engine-class activity support
2025-01-30 4:49 ` Riana Tauro
@ 2025-01-30 22:36 ` Rodrigo Vivi
2025-01-30 23:56 ` Lucas De Marchi
2025-01-30 23:00 ` Lucas De Marchi
1 sibling, 1 reply; 45+ messages in thread
From: Rodrigo Vivi @ 2025-01-30 22:36 UTC (permalink / raw)
To: Riana Tauro, Lucas De Marchi
Cc: Umesh Nerlige Ramappa, intel-xe, anshuman.gupta, lucas.demarchi,
vinay.belgaumkar, soham.purkait, Himal Prasad Ghimiray
On Thu, Jan 30, 2025 at 10:19:24AM +0530, Riana Tauro wrote:
> Hi Umesh/Rodrigo
>
> On 1/30/2025 8:05 AM, Rodrigo Vivi wrote:
> > On Wed, Jan 29, 2025 at 04:28:36PM -0800, Umesh Nerlige Ramappa wrote:
> > > On Wed, Jan 29, 2025 at 03:46:44PM +0530, Riana Tauro wrote:
> > > > GuC provides support to read engine counters to calculate the
> > > > engine activity. KMD exposes two counters via the PMU interface to
> > > > calculate engine activity
> > > >
> > > > Engine Active Ticks(engine-active-ticks) - number of active ticks for engine
> > > > Engine Total Ticks (engine-total-ticks) - total ticks of engine
> > > >
> > > > Engine activity percentage can be calculated as below
> > > > Engine activity % = (engine active ticks/engine total ticks) * 100.
> > > >
> > > > v2: fix cosmetic review comments
> > > > add forcewake for gpm_ts (Umesh)
> > > >
> > > > v3: fix CI hooks error
> > > > change function parameters and unpin bo on error
> > > > of allocate_activity_buffers
> > > > fix kernel-doc (Umesh)
> > > > use engine activity (Umesh, Lucas)
> > > > rename xe_engine_activity to xe_guc_engine_*
> > > > fix commit message to use per-engine class(Lucas)
> > > >
> > > > v4: remove forcewake as engine is already running
> > > > when reading gpm timestamp
> > >
> > > + Rodrigo
> > >
> > > Sorry, I think I mentioned offline that the runtime pm get is sufficient for
> > > reading this register, but it's not. It does need a forcewake of the GT
> > > domain. At the same time, we cannot use the xe_force_wake_get because of
> > > the lockdep issue you mentioned and also I assume that xe_force_wake_get may
> > > sleep and the event may be read from irq context.
> The lockdep issue is due to perf holding a raw_spinlock and forcewake having
> a spinlock. In 6.13 due to config PROVE_RAW_LOCK_NESTING being enabled was
> seeing this issue. Latest patch has disabled this due to issues with i915.
>
> [ 465.359017] =============================
> [ 465.363050] [ BUG: Invalid wait context ]
> [ 465.367063] 6.13.0-rc5-xe #11 Tainted: G U
> [ 465.372544] -----------------------------
> [ 465.376555] swapper/0/0 is trying to lock:
> [ 465.380652] ffff88810d5b8098 (&fw->lock){....}-{3:3}, at:
> xe_force_wake_get+0x1f9/0x8c0 [xe]
> [ 465.389168] other info that might help us debug this:
> [ 465.394221] context-{5:5}
> [ 465.396847] 1 lock held by swapper/0/0:
> [ 465.400682] #0: ffff88885f031fb8 (&cpuctx_lock){....}-{2:2}, at:
> __perf_event_read+0x60/0x230
> [ 465.409295] stack backtrace:
hmmm I had forgotten about this...
Lucas, since you were the last one that looked into it,
would be feasible to switch at least the xe_force_wake towards
raw_spinlock?
>
>
> Since in this case we are checking mmio only when engine is running
> and gt will be active. i thought we could remove it.
>
> >>> + if (ea->running) {
> >>> + gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
> >>> + engine_activity->gpm_timestamp_shift;
> >>> + ea->active = lower_32_bits(gpm_ts) -
> cached_activity->last_update_tick;
> >>> + }
>
> But yeah, gt might enter c6 just after reading ea->running. To avoid this,as
> lucas suggested have to use hr timer.
>
> I thought if needed, will add it as part of a separate series.
> I can add the forcewake back as the config is removed and add hr timer in
> another series.
>
> Thanks
> Riana
> >
> > I don't understand this statement entirely. force wake get cannot sleep.
> > It is based on spin locks. It should not be issuing any lockdep here.
> > It is quite simple flow with minimal or none interdependency. Remember
> > that in i915 for instance it exists and lives in the middle of every
> > mmio read and write call...
> >
> > >
> > > I would check if we can add a helper xe_force_wake_get_if_active() and just
> > > use that to bump up the wakeref.
> >
> > I would prefer to not complicate things...
> >
> > >
> > > @Rodrigo, @Vinay Any thoughts on this ^ ?
> >
> > Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> >
> > >
> > > Thanks,
> > > Umesh
> > >
> > > >
> > > > Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> > > > Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> > > > ---
> > > > drivers/gpu/drm/xe/Makefile | 1 +
> > > > drivers/gpu/drm/xe/abi/guc_actions_abi.h | 1 +
> > > > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
> > > > drivers/gpu/drm/xe/xe_guc_engine_activity.c | 317 ++++++++++++++++++
> > > > drivers/gpu/drm/xe/xe_guc_engine_activity.h | 18 +
> > > > .../gpu/drm/xe/xe_guc_engine_activity_types.h | 89 +++++
> > > > drivers/gpu/drm/xe/xe_guc_fwif.h | 19 ++
> > > > drivers/gpu/drm/xe/xe_guc_types.h | 4 +
> > > > 8 files changed, 451 insertions(+)
> > > > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.c
> > > > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.h
> > > > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
> > > >
> > > > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > > > index 328aff36831b..7e93461c60bd 100644
> > > > --- a/drivers/gpu/drm/xe/Makefile
> > > > +++ b/drivers/gpu/drm/xe/Makefile
> > > > @@ -33,6 +33,7 @@ xe-y += xe_bb.o \
> > > > xe_device_sysfs.o \
> > > > xe_dma_buf.o \
> > > > xe_drm_client.o \
> > > > + xe_guc_engine_activity.o \
> > > > xe_exec.o \
> > > > xe_execlist.o \
> > > > xe_exec_queue.o \
> > > > diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
> > > > index fee385532fb0..ec516e838ee8 100644
> > > > --- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
> > > > +++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
> > > > @@ -140,6 +140,7 @@ enum xe_guc_action {
> > > > XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
> > > > XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
> > > > XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
> > > > + XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
> > > > XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
> > > > XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
> > > > XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,
> > > > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > > > index 096859072396..124cc398798e 100644
> > > > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > > > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> > > > @@ -358,6 +358,8 @@
> > > > #define RENDER_AWAKE_STATUS REG_BIT(1)
> > > > #define MEDIA_SLICE0_AWAKE_STATUS REG_BIT(0)
> > > >
> > > > +#define MISC_STATUS_0 XE_REG(0xa500)
> > > > +
> > > > #define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4)
> > > > #define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4)
> > > > #define FORCEWAKE_GSC XE_REG(0xa618)
> > > > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
> > > > new file mode 100644
> > > > index 000000000000..088209b9c228
> > > > --- /dev/null
> > > > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
> > > > @@ -0,0 +1,317 @@
> > > > +// SPDX-License-Identifier: MIT
> > > > +/*
> > > > + * Copyright © 2025 Intel Corporation
> > > > + */
> > > > +#include "xe_guc_engine_activity.h"
> > > > +
> > > > +#include "abi/guc_actions_abi.h"
> > > > +#include "regs/xe_gt_regs.h"
> > > > +
> > > > +#include "xe_bo.h"
> > > > +#include "xe_force_wake.h"
> > > > +#include "xe_gt_printk.h"
> > > > +#include "xe_guc.h"
> > > > +#include "xe_guc_ct.h"
> > > > +#include "xe_hw_engine.h"
> > > > +#include "xe_map.h"
> > > > +#include "xe_mmio.h"
> > > > +
> > > > +#define TOTAL_QUANTA 0x8000
> > > > +
> > > > +static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_engine *hwe)
> > > > +{
> > > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
> > > > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
> > > > + u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
> > > > + size_t offset = 0;
> > > > +
> > > > + offset = offsetof(struct guc_engine_activity_data,
> > > > + engine_activity[guc_class][hwe->logical_instance]);
> > > > +
> > > > + return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap, offset);
> > > > +}
> > > > +
> > > > +static struct iosys_map engine_metadata_map(struct xe_guc *guc)
> > > > +{
> > > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
> > > > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
> > > > +
> > > > + return buffer->metadata_bo->vmap;
> > > > +}
> > > > +
> > > > +static int allocate_engine_activity_group(struct xe_guc *guc)
> > > > +{
> > > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
> > > > + u32 num_activity_group = 1;
> > > > +
> > > > + engine_activity->eag = kmalloc_array(num_activity_group,
> > > > + sizeof(struct engine_activity_group),
> > > > + GFP_KERNEL);
> > > > +
> > > > + if (!engine_activity->eag)
> > > > + return -ENOMEM;
> > > > +
> > > > + memset(engine_activity->eag, 0, num_activity_group * sizeof(struct engine_activity_group));
> > > > + engine_activity->num_activity_group = num_activity_group;
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int allocate_engine_activity_buffers(struct xe_guc *guc,
> > > > + struct engine_activity_buffer *buffer)
> > > > +{
> > > > + u32 metadata_size = sizeof(struct guc_engine_activity_metadata);
> > > > + u32 size = sizeof(struct guc_engine_activity_data);
> > > > + struct xe_gt *gt = guc_to_gt(guc);
> > > > + struct xe_tile *tile = gt_to_tile(gt);
> > > > + struct xe_bo *bo, *metadata_bo;
> > > > +
> > > > + metadata_bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(metadata_size),
> > > > + XE_BO_FLAG_SYSTEM |
> > > > + XE_BO_FLAG_GGTT |
> > > > + XE_BO_FLAG_GGTT_INVALIDATE);
> > > > + if (IS_ERR(metadata_bo))
> > > > + return PTR_ERR(metadata_bo);
> > > > +
> > > > + bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(size),
> > > > + XE_BO_FLAG_VRAM_IF_DGFX(tile) |
> > > > + XE_BO_FLAG_GGTT |
> > > > + XE_BO_FLAG_GGTT_INVALIDATE);
> > > > +
> > > > + if (IS_ERR(bo)) {
> > > > + xe_bo_unpin_map_no_vm(metadata_bo);
> > > > + return PTR_ERR(bo);
> > > > + }
> > > > +
> > > > + buffer->metadata_bo = metadata_bo;
> > > > + buffer->activity_bo = bo;
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine *hwe)
> > > > +{
> > > > + struct xe_guc *guc = &hwe->gt->uc.guc;
> > > > + struct engine_activity_group *eag = &guc->engine_activity.eag[0];
> > > > + u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
> > > > +
> > > > + return &eag->engine[guc_class][hwe->logical_instance];
> > > > +}
> > > > +
> > > > +static u64 cpu_ns_to_guc_tsc_tick(ktime_t ns, u32 freq)
> > > > +{
> > > > + return mul_u64_u32_div(ns, freq, NSEC_PER_SEC);
> > > > +}
> > > > +
> > > > +#define read_engine_activity_record(xe_, map_, field_) \
> > > > + xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity, field_)
> > > > +
> > > > +#define read_metadata_record(xe_, map_, field_) \
> > > > + xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity_metadata, field_)
> > > > +
> > > > +static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
> > > > +{
> > > > + struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
> > > > + struct guc_engine_activity *cached_activity = &ea->activity;
> > > > + struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
> > > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
> > > > + struct iosys_map activity_map, metadata_map;
> > > > + struct xe_device *xe = guc_to_xe(guc);
> > > > + struct xe_gt *gt = guc_to_gt(guc);
> > > > + u32 last_update_tick, global_change_num;
> > > > + u64 active_ticks, gpm_ts;
> > > > + u16 change_num;
> > > > +
> > > > + activity_map = engine_activity_map(guc, hwe);
> > > > + metadata_map = engine_metadata_map(guc);
> > > > + global_change_num = read_metadata_record(xe, &metadata_map, global_change_num);
> > > > +
> > > > + /* GuC has not initialized activity data yet, return 0 */
> > > > + if (!global_change_num)
> > > > + goto update;
> > > > +
> > > > + if (global_change_num == cached_metadata->global_change_num)
> > > > + goto update;
> > > > + else
> > > > + cached_metadata->global_change_num = global_change_num;
> > > > +
> > > > + change_num = read_engine_activity_record(xe, &activity_map, change_num);
> > > > +
> > > > + if (!change_num || change_num == cached_activity->change_num)
> > > > + goto update;
> > > > +
> > > > + /* read engine activity values */
> > > > + last_update_tick = read_engine_activity_record(xe, &activity_map, last_update_tick);
> > > > + active_ticks = read_engine_activity_record(xe, &activity_map, active_ticks);
> > > > +
> > > > + /* activity calculations */
> > > > + ea->running = !!last_update_tick;
> > > > + ea->total += active_ticks - cached_activity->active_ticks;
> > > > + ea->active = 0;
> > > > +
> > > > + /* cache the counter */
> > > > + cached_activity->change_num = change_num;
> > > > + cached_activity->last_update_tick = last_update_tick;
> > > > + cached_activity->active_ticks = active_ticks;
> > > > +
> > > > +update:
> > > > + if (ea->running) {
> > > > + gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
> > > > + engine_activity->gpm_timestamp_shift;
> > > > + ea->active = lower_32_bits(gpm_ts) - cached_activity->last_update_tick;
> > > > + }
> > > > +
> > > > + return ea->total + ea->active;
> > > > +}
> > > > +
> > > > +static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
> > > > +{
> > > > + struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
> > > > + struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
> > > > + struct guc_engine_activity *cached_activity = &ea->activity;
> > > > + struct iosys_map activity_map, metadata_map;
> > > > + struct xe_device *xe = guc_to_xe(guc);
> > > > + ktime_t now, cpu_delta;
> > > > + u64 numerator;
> > > > + u16 quanta_ratio;
> > > > +
> > > > + activity_map = engine_activity_map(guc, hwe);
> > > > + metadata_map = engine_metadata_map(guc);
> > > > +
> > > > + if (!cached_metadata->guc_tsc_frequency_hz)
> > > > + cached_metadata->guc_tsc_frequency_hz = read_metadata_record(xe, &metadata_map,
> > > > + guc_tsc_frequency_hz);
> > > > +
> > > > + quanta_ratio = read_engine_activity_record(xe, &activity_map, quanta_ratio);
> > > > + cached_activity->quanta_ratio = quanta_ratio;
> > > > +
> > > > + /* Total ticks calculations */
> > > > + now = ktime_get();
> > > > + cpu_delta = now - ea->last_cpu_ts;
> > > > + ea->last_cpu_ts = now;
> > > > + numerator = (ea->quanta_remainder_ns + cpu_delta) * cached_activity->quanta_ratio;
> > > > + ea->quanta_ns += numerator / TOTAL_QUANTA;
> > > > + ea->quanta_remainder_ns = numerator % TOTAL_QUANTA;
> > > > + ea->quanta = cpu_ns_to_guc_tsc_tick(ea->quanta_ns, cached_metadata->guc_tsc_frequency_hz);
> > > > +
> > > > + return ea->quanta;
> > > > +}
> > > > +
> > > > +static int enable_engine_activity_stats(struct xe_guc *guc)
> > > > +{
> > > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
> > > > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
> > > > + u32 metadata_ggtt_addr = xe_bo_ggtt_addr(buffer->metadata_bo);
> > > > + u32 ggtt_addr = xe_bo_ggtt_addr(buffer->activity_bo);
> > > > + int len = 0;
> > > > + u32 action[5];
> > > > +
> > > > + action[len++] = XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER;
> > > > + action[len++] = metadata_ggtt_addr;
> > > > + action[len++] = 0;
> > > > + action[len++] = ggtt_addr;
> > > > + action[len++] = 0;
> > > > +
> > > > + /* Blocking here to ensure the buffers are ready before reading them */
> > > > + return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
> > > > +}
> > > > +
> > > > +static void engine_activity_set_cpu_ts(struct xe_guc *guc)
> > > > +{
> > > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
> > > > + struct engine_activity_group *eag = &engine_activity->eag[0];
> > > > + int i, j;
> > > > +
> > > > + for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)
> > > > + for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; j++)
> > > > + eag->engine[i][j].last_cpu_ts = ktime_get();
> > > > +}
> > > > +
> > > > +static u32 gpm_timestamp_shift(struct xe_gt *gt)
> > > > +{
> > > > + u32 reg;
> > > > +
> > > > + reg = xe_mmio_read32(>->mmio, RPM_CONFIG0);
> > > > +
> > > > + return 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
> > > > +}
> > > > +
> > > > +/**
> > > > + * xe_guc_engine_activity_active_ticks - Get engine active ticks
> > > > + * @hwe: The hw_engine object
> > > > + *
> > > > + * Return: accumulated ticks @hwe was active since engine activity stats were enabled.
> > > > + */
> > > > +u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe)
> > > > +{
> > > > + struct xe_guc *guc = &hwe->gt->uc.guc;
> > > > +
> > > > + return get_engine_active_ticks(guc, hwe);
> > > > +}
> > > > +
> > > > +/**
> > > > + * xe_guc_engine_activity_total_ticks - Get engine total ticks
> > > > + * @hwe: The hw_engine object
> > > > + *
> > > > + * Return: accumulated quanta of ticks allocated for the engine
> > > > + */
> > > > +u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe)
> > > > +{
> > > > + struct xe_guc *guc = &hwe->gt->uc.guc;
> > > > +
> > > > + return get_engine_total_ticks(guc, hwe);
> > > > +}
> > > > +
> > > > +/**
> > > > + * xe_guc_engine_activity_enable_stats - Enable engine activity stats
> > > > + * @guc: The GuC object
> > > > + *
> > > > + * Enable engine activity stats and set initial timestamps
> > > > + */
> > > > +void xe_guc_engine_activity_enable_stats(struct xe_guc *guc)
> > > > +{
> > > > + int ret;
> > > > +
> > > > + ret = enable_engine_activity_stats(guc);
> > > > + if (ret)
> > > > + xe_gt_err(guc_to_gt(guc), "failed to enable activity stats%d\n", ret);
> > > > + else
> > > > + engine_activity_set_cpu_ts(guc);
> > > > +}
> > > > +
> > > > +static void engine_activity_fini(void *arg)
> > > > +{
> > > > + struct xe_guc_engine_activity *engine_activity = arg;
> > > > +
> > > > + kfree(engine_activity->eag);
> > > > +}
> > > > +
> > > > +/**
> > > > + * xe_guc_engine_activity_init - Initialize the engine activity data
> > > > + * @guc: The GuC object
> > > > + *
> > > > + * Return: 0 on success, negative error code otherwise.
> > > > + */
> > > > +int xe_guc_engine_activity_init(struct xe_guc *guc)
> > > > +{
> > > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
> > > > + struct xe_gt *gt = guc_to_gt(guc);
> > > > + int ret;
> > > > +
> > > > + ret = allocate_engine_activity_group(guc);
> > > > + if (ret) {
> > > > + xe_gt_err(gt, "failed to allocate activity group %d\n", ret);
> > > > + return ret;
> > > > + }
> > > > +
> > > > + ret = allocate_engine_activity_buffers(guc, &engine_activity->device_buffer);
> > > > + if (ret) {
> > > > + xe_gt_err(gt, "failed to allocate activity buffers%d\n", ret);
> > > > + kfree(engine_activity->eag);
> > > > + return ret;
> > > > + }
> > > > +
> > > > + engine_activity->gpm_timestamp_shift = gpm_timestamp_shift(gt);
> > > > +
> > > > + return devm_add_action_or_reset(gt_to_xe(gt)->drm.dev, engine_activity_fini,
> > > > + engine_activity);
> > > > +}
> > > > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.h b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
> > > > new file mode 100644
> > > > index 000000000000..c00f3da5513d
> > > > --- /dev/null
> > > > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
> > > > @@ -0,0 +1,18 @@
> > > > +/* SPDX-License-Identifier: MIT */
> > > > +/*
> > > > + * Copyright © 2025 Intel Corporation
> > > > + */
> > > > +
> > > > +#ifndef _XE_GUC_ENGINE_ACTIVITY_H_
> > > > +#define _XE_GUC_ENGINE_ACTIVITY_H_
> > > > +
> > > > +#include <linux/types.h>
> > > > +
> > > > +struct xe_hw_engine;
> > > > +struct xe_guc;
> > > > +
> > > > +int xe_guc_engine_activity_init(struct xe_guc *guc);
> > > > +void xe_guc_engine_activity_enable_stats(struct xe_guc *guc);
> > > > +u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe);
> > > > +u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe);
> > > > +#endif
> > > > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
> > > > new file mode 100644
> > > > index 000000000000..a2ab327d3eec
> > > > --- /dev/null
> > > > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
> > > > @@ -0,0 +1,89 @@
> > > > +/* SPDX-License-Identifier: MIT */
> > > > +/*
> > > > + * Copyright © 2025 Intel Corporation
> > > > + */
> > > > +
> > > > +#ifndef _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
> > > > +#define _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
> > > > +
> > > > +#include <linux/types.h>
> > > > +
> > > > +#include "xe_guc_fwif.h"
> > > > +/**
> > > > + * struct engine_activity - Engine specific activity data
> > > > + *
> > > > + * Contains engine specific activity data and snapshot of the
> > > > + * structures from GuC
> > > > + */
> > > > +struct engine_activity {
> > > > + /** @active: current activity */
> > > > + u64 active;
> > > > +
> > > > + /** @last_cpu_ts: cpu timestamp in nsec of previous sample */
> > > > + u64 last_cpu_ts;
> > > > +
> > > > + /** @quanta: total quanta used on HW */
> > > > + u64 quanta;
> > > > +
> > > > + /** @quanta_ns: total quanta_ns used on HW */
> > > > + u64 quanta_ns;
> > > > +
> > > > + /**
> > > > + * @quanta_remainder_ns: remainder when the CPU time is scaled as
> > > > + * per the quanta_ratio. This remainder is used in subsequent
> > > > + * quanta calculations.
> > > > + */
> > > > + u64 quanta_remainder_ns;
> > > > +
> > > > + /** @total: total engine activity */
> > > > + u64 total;
> > > > +
> > > > + /** @running: true if engine is running some work */
> > > > + bool running;
> > > > +
> > > > + /** @metadata: snapshot of engine activity metadata */
> > > > + struct guc_engine_activity_metadata metadata;
> > > > +
> > > > + /** @activity: snapshot of engine activity counter */
> > > > + struct guc_engine_activity activity;
> > > > +};
> > > > +
> > > > +/**
> > > > + * struct engine_activity_group - Activity data for all engines
> > > > + */
> > > > +struct engine_activity_group {
> > > > + /** @engine: engine specific activity data */
> > > > + struct engine_activity engine[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
> > > > +};
> > > > +
> > > > +/**
> > > > + * struct engine_activity_buffer - engine activity buffers
> > > > + *
> > > > + * This contains the buffers allocated for metadata and activity data
> > > > + */
> > > > +struct engine_activity_buffer {
> > > > + /** @activity_bo: object allocated to hold activity data */
> > > > + struct xe_bo *activity_bo;
> > > > +
> > > > + /** @metadata_bo: object allocated to hold activity metadata */
> > > > + struct xe_bo *metadata_bo;
> > > > +};
> > > > +
> > > > +/**
> > > > + * struct xe_guc_engine_activity - Data used by engine activity implementation
> > > > + */
> > > > +struct xe_guc_engine_activity {
> > > > + /** @gpm_timestamp_shift: Right shift value for the gpm timestamp */
> > > > + u32 gpm_timestamp_shift;
> > > > +
> > > > + /** @num_activity_group: number of activity groups */
> > > > + u32 num_activity_group;
> > > > +
> > > > + /** @eag: holds the device level engine activity data */
> > > > + struct engine_activity_group *eag;
> > > > +
> > > > + /** @device_buffer: buffer object for global engine activity */
> > > > + struct engine_activity_buffer device_buffer;
> > > > +};
> > > > +#endif
> > > > +
> > > > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > index 057153f89b30..6f57578b07cb 100644
> > > > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> > > > @@ -208,6 +208,25 @@ struct guc_engine_usage {
> > > > struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
> > > > } __packed;
> > > >
> > > > +/* Engine Activity stats */
> > > > +struct guc_engine_activity {
> > > > + u16 change_num;
> > > > + u16 quanta_ratio;
> > > > + u32 last_update_tick;
> > > > + u64 active_ticks;
> > > > +} __packed;
> > > > +
> > > > +struct guc_engine_activity_data {
> > > > + struct guc_engine_activity engine_activity[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
> > > > +} __packed;
> > > > +
> > > > +struct guc_engine_activity_metadata {
> > > > + u32 guc_tsc_frequency_hz;
> > > > + u32 lag_latency_usec;
> > > > + u32 global_change_num;
> > > > + u32 reserved;
> > > > +} __packed;
> > > > +
> > > > /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
> > > > enum xe_guc_recv_message {
> > > > XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
> > > > diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h
> > > > index 573aa6308380..63bac64429a5 100644
> > > > --- a/drivers/gpu/drm/xe/xe_guc_types.h
> > > > +++ b/drivers/gpu/drm/xe/xe_guc_types.h
> > > > @@ -13,6 +13,7 @@
> > > > #include "xe_guc_ads_types.h"
> > > > #include "xe_guc_buf_types.h"
> > > > #include "xe_guc_ct_types.h"
> > > > +#include "xe_guc_engine_activity_types.h"
> > > > #include "xe_guc_fwif.h"
> > > > #include "xe_guc_log_types.h"
> > > > #include "xe_guc_pc_types.h"
> > > > @@ -103,6 +104,9 @@ struct xe_guc {
> > > > /** @relay: GuC Relay Communication used in SR-IOV */
> > > > struct xe_guc_relay relay;
> > > >
> > > > + /** @engine_activity: Device specific engine activity */
> > > > + struct xe_guc_engine_activity engine_activity;
> > > > +
> > > > /**
> > > > * @notify_reg: Register which is written to notify GuC of H2G messages
> > > > */
> > > > --
> > > > 2.47.1
> > > >
>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 1/8] drm/xe: Add per-engine-class activity support
2025-01-30 22:36 ` Rodrigo Vivi
@ 2025-01-30 23:56 ` Lucas De Marchi
2025-01-31 17:13 ` Umesh Nerlige Ramappa
0 siblings, 1 reply; 45+ messages in thread
From: Lucas De Marchi @ 2025-01-30 23:56 UTC (permalink / raw)
To: Rodrigo Vivi
Cc: Riana Tauro, Umesh Nerlige Ramappa, intel-xe, anshuman.gupta,
vinay.belgaumkar, soham.purkait, Himal Prasad Ghimiray
On Thu, Jan 30, 2025 at 05:36:03PM -0500, Rodrigo Vivi wrote:
>On Thu, Jan 30, 2025 at 10:19:24AM +0530, Riana Tauro wrote:
>> Hi Umesh/Rodrigo
>>
>> On 1/30/2025 8:05 AM, Rodrigo Vivi wrote:
>> > On Wed, Jan 29, 2025 at 04:28:36PM -0800, Umesh Nerlige Ramappa wrote:
>> > > On Wed, Jan 29, 2025 at 03:46:44PM +0530, Riana Tauro wrote:
>> > > > GuC provides support to read engine counters to calculate the
>> > > > engine activity. KMD exposes two counters via the PMU interface to
>> > > > calculate engine activity
>> > > >
>> > > > Engine Active Ticks(engine-active-ticks) - number of active ticks for engine
>> > > > Engine Total Ticks (engine-total-ticks) - total ticks of engine
>> > > >
>> > > > Engine activity percentage can be calculated as below
>> > > > Engine activity % = (engine active ticks/engine total ticks) * 100.
>> > > >
>> > > > v2: fix cosmetic review comments
>> > > > add forcewake for gpm_ts (Umesh)
>> > > >
>> > > > v3: fix CI hooks error
>> > > > change function parameters and unpin bo on error
>> > > > of allocate_activity_buffers
>> > > > fix kernel-doc (Umesh)
>> > > > use engine activity (Umesh, Lucas)
>> > > > rename xe_engine_activity to xe_guc_engine_*
>> > > > fix commit message to use per-engine class(Lucas)
>> > > >
>> > > > v4: remove forcewake as engine is already running
>> > > > when reading gpm timestamp
>> > >
>> > > + Rodrigo
>> > >
>> > > Sorry, I think I mentioned offline that the runtime pm get is sufficient for
>> > > reading this register, but it's not. It does need a forcewake of the GT
>> > > domain. At the same time, we cannot use the xe_force_wake_get because of
>> > > the lockdep issue you mentioned and also I assume that xe_force_wake_get may
>> > > sleep and the event may be read from irq context.
>> The lockdep issue is due to perf holding a raw_spinlock and forcewake having
>> a spinlock. In 6.13 due to config PROVE_RAW_LOCK_NESTING being enabled was
>> seeing this issue. Latest patch has disabled this due to issues with i915.
>>
>> [ 465.359017] =============================
>> [ 465.363050] [ BUG: Invalid wait context ]
>> [ 465.367063] 6.13.0-rc5-xe #11 Tainted: G U
>> [ 465.372544] -----------------------------
>> [ 465.376555] swapper/0/0 is trying to lock:
>> [ 465.380652] ffff88810d5b8098 (&fw->lock){....}-{3:3}, at:
>> xe_force_wake_get+0x1f9/0x8c0 [xe]
>> [ 465.389168] other info that might help us debug this:
>> [ 465.394221] context-{5:5}
>> [ 465.396847] 1 lock held by swapper/0/0:
>> [ 465.400682] #0: ffff88885f031fb8 (&cpuctx_lock){....}-{2:2}, at:
>> __perf_event_read+0x60/0x230
>> [ 465.409295] stack backtrace:
>
>
>hmmm I had forgotten about this...
>
>Lucas, since you were the last one that looked into it,
>would be feasible to switch at least the xe_force_wake towards
>raw_spinlock?
no, I don't think so. We hold the spinlock and then call
xe_mmio_wait32(... XE_FORCE_WAKE_ACK_TIMEOUT_MS). Yeah.. it's only upper
bound, but we should look at other solutions.
1) move the read to the hrtimer, like is done for e.g. rapl. We can then
continue using spinlock for the hw interaction.
2) introduce a raw_spinlock that will protect only domain->ref
that would allow us to implement an _if_active variant. But I
don't know how that would help here since we need to read the
register. What do we do when the fw is not taken?
on gt-c6 that idea was dropped on the floor since it was
not working well and overcomplicating it.
3) ... something else?
Lucas De Marchi
>
>
>>
>>
>> Since in this case we are checking mmio only when engine is running
>> and gt will be active. i thought we could remove it.
>>
>> >>> + if (ea->running) {
>> >>> + gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
>> >>> + engine_activity->gpm_timestamp_shift;
>> >>> + ea->active = lower_32_bits(gpm_ts) -
>> cached_activity->last_update_tick;
>> >>> + }
>>
>> But yeah, gt might enter c6 just after reading ea->running. To avoid this,as
>> lucas suggested have to use hr timer.
>>
>> I thought if needed, will add it as part of a separate series.
>> I can add the forcewake back as the config is removed and add hr timer in
>> another series.
>>
>> Thanks
>> Riana
>> >
>> > I don't understand this statement entirely. force wake get cannot sleep.
>> > It is based on spin locks. It should not be issuing any lockdep here.
>> > It is quite simple flow with minimal or none interdependency. Remember
>> > that in i915 for instance it exists and lives in the middle of every
>> > mmio read and write call...
>> >
>> > >
>> > > I would check if we can add a helper xe_force_wake_get_if_active() and just
>> > > use that to bump up the wakeref.
>> >
>> > I would prefer to not complicate things...
>> >
>> > >
>> > > @Rodrigo, @Vinay Any thoughts on this ^ ?
>> >
>> > Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>> >
>> > >
>> > > Thanks,
>> > > Umesh
>> > >
>> > > >
>> > > > Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> > > > Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> > > > ---
>> > > > drivers/gpu/drm/xe/Makefile | 1 +
>> > > > drivers/gpu/drm/xe/abi/guc_actions_abi.h | 1 +
>> > > > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
>> > > > drivers/gpu/drm/xe/xe_guc_engine_activity.c | 317 ++++++++++++++++++
>> > > > drivers/gpu/drm/xe/xe_guc_engine_activity.h | 18 +
>> > > > .../gpu/drm/xe/xe_guc_engine_activity_types.h | 89 +++++
>> > > > drivers/gpu/drm/xe/xe_guc_fwif.h | 19 ++
>> > > > drivers/gpu/drm/xe/xe_guc_types.h | 4 +
>> > > > 8 files changed, 451 insertions(+)
>> > > > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.c
>> > > > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.h
>> > > > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>> > > >
>> > > > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> > > > index 328aff36831b..7e93461c60bd 100644
>> > > > --- a/drivers/gpu/drm/xe/Makefile
>> > > > +++ b/drivers/gpu/drm/xe/Makefile
>> > > > @@ -33,6 +33,7 @@ xe-y += xe_bb.o \
>> > > > xe_device_sysfs.o \
>> > > > xe_dma_buf.o \
>> > > > xe_drm_client.o \
>> > > > + xe_guc_engine_activity.o \
>> > > > xe_exec.o \
>> > > > xe_execlist.o \
>> > > > xe_exec_queue.o \
>> > > > diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>> > > > index fee385532fb0..ec516e838ee8 100644
>> > > > --- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>> > > > +++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>> > > > @@ -140,6 +140,7 @@ enum xe_guc_action {
>> > > > XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
>> > > > XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
>> > > > XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
>> > > > + XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
>> > > > XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
>> > > > XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
>> > > > XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,
>> > > > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > > > index 096859072396..124cc398798e 100644
>> > > > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > > > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > > > @@ -358,6 +358,8 @@
>> > > > #define RENDER_AWAKE_STATUS REG_BIT(1)
>> > > > #define MEDIA_SLICE0_AWAKE_STATUS REG_BIT(0)
>> > > >
>> > > > +#define MISC_STATUS_0 XE_REG(0xa500)
>> > > > +
>> > > > #define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4)
>> > > > #define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4)
>> > > > #define FORCEWAKE_GSC XE_REG(0xa618)
>> > > > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>> > > > new file mode 100644
>> > > > index 000000000000..088209b9c228
>> > > > --- /dev/null
>> > > > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>> > > > @@ -0,0 +1,317 @@
>> > > > +// SPDX-License-Identifier: MIT
>> > > > +/*
>> > > > + * Copyright © 2025 Intel Corporation
>> > > > + */
>> > > > +#include "xe_guc_engine_activity.h"
>> > > > +
>> > > > +#include "abi/guc_actions_abi.h"
>> > > > +#include "regs/xe_gt_regs.h"
>> > > > +
>> > > > +#include "xe_bo.h"
>> > > > +#include "xe_force_wake.h"
>> > > > +#include "xe_gt_printk.h"
>> > > > +#include "xe_guc.h"
>> > > > +#include "xe_guc_ct.h"
>> > > > +#include "xe_hw_engine.h"
>> > > > +#include "xe_map.h"
>> > > > +#include "xe_mmio.h"
>> > > > +
>> > > > +#define TOTAL_QUANTA 0x8000
>> > > > +
>> > > > +static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_engine *hwe)
>> > > > +{
>> > > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > > > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>> > > > + u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>> > > > + size_t offset = 0;
>> > > > +
>> > > > + offset = offsetof(struct guc_engine_activity_data,
>> > > > + engine_activity[guc_class][hwe->logical_instance]);
>> > > > +
>> > > > + return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap, offset);
>> > > > +}
>> > > > +
>> > > > +static struct iosys_map engine_metadata_map(struct xe_guc *guc)
>> > > > +{
>> > > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > > > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>> > > > +
>> > > > + return buffer->metadata_bo->vmap;
>> > > > +}
>> > > > +
>> > > > +static int allocate_engine_activity_group(struct xe_guc *guc)
>> > > > +{
>> > > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > > > + u32 num_activity_group = 1;
>> > > > +
>> > > > + engine_activity->eag = kmalloc_array(num_activity_group,
>> > > > + sizeof(struct engine_activity_group),
>> > > > + GFP_KERNEL);
>> > > > +
>> > > > + if (!engine_activity->eag)
>> > > > + return -ENOMEM;
>> > > > +
>> > > > + memset(engine_activity->eag, 0, num_activity_group * sizeof(struct engine_activity_group));
>> > > > + engine_activity->num_activity_group = num_activity_group;
>> > > > +
>> > > > + return 0;
>> > > > +}
>> > > > +
>> > > > +static int allocate_engine_activity_buffers(struct xe_guc *guc,
>> > > > + struct engine_activity_buffer *buffer)
>> > > > +{
>> > > > + u32 metadata_size = sizeof(struct guc_engine_activity_metadata);
>> > > > + u32 size = sizeof(struct guc_engine_activity_data);
>> > > > + struct xe_gt *gt = guc_to_gt(guc);
>> > > > + struct xe_tile *tile = gt_to_tile(gt);
>> > > > + struct xe_bo *bo, *metadata_bo;
>> > > > +
>> > > > + metadata_bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(metadata_size),
>> > > > + XE_BO_FLAG_SYSTEM |
>> > > > + XE_BO_FLAG_GGTT |
>> > > > + XE_BO_FLAG_GGTT_INVALIDATE);
>> > > > + if (IS_ERR(metadata_bo))
>> > > > + return PTR_ERR(metadata_bo);
>> > > > +
>> > > > + bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(size),
>> > > > + XE_BO_FLAG_VRAM_IF_DGFX(tile) |
>> > > > + XE_BO_FLAG_GGTT |
>> > > > + XE_BO_FLAG_GGTT_INVALIDATE);
>> > > > +
>> > > > + if (IS_ERR(bo)) {
>> > > > + xe_bo_unpin_map_no_vm(metadata_bo);
>> > > > + return PTR_ERR(bo);
>> > > > + }
>> > > > +
>> > > > + buffer->metadata_bo = metadata_bo;
>> > > > + buffer->activity_bo = bo;
>> > > > + return 0;
>> > > > +}
>> > > > +
>> > > > +static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine *hwe)
>> > > > +{
>> > > > + struct xe_guc *guc = &hwe->gt->uc.guc;
>> > > > + struct engine_activity_group *eag = &guc->engine_activity.eag[0];
>> > > > + u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>> > > > +
>> > > > + return &eag->engine[guc_class][hwe->logical_instance];
>> > > > +}
>> > > > +
>> > > > +static u64 cpu_ns_to_guc_tsc_tick(ktime_t ns, u32 freq)
>> > > > +{
>> > > > + return mul_u64_u32_div(ns, freq, NSEC_PER_SEC);
>> > > > +}
>> > > > +
>> > > > +#define read_engine_activity_record(xe_, map_, field_) \
>> > > > + xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity, field_)
>> > > > +
>> > > > +#define read_metadata_record(xe_, map_, field_) \
>> > > > + xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity_metadata, field_)
>> > > > +
>> > > > +static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>> > > > +{
>> > > > + struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>> > > > + struct guc_engine_activity *cached_activity = &ea->activity;
>> > > > + struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>> > > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > > > + struct iosys_map activity_map, metadata_map;
>> > > > + struct xe_device *xe = guc_to_xe(guc);
>> > > > + struct xe_gt *gt = guc_to_gt(guc);
>> > > > + u32 last_update_tick, global_change_num;
>> > > > + u64 active_ticks, gpm_ts;
>> > > > + u16 change_num;
>> > > > +
>> > > > + activity_map = engine_activity_map(guc, hwe);
>> > > > + metadata_map = engine_metadata_map(guc);
>> > > > + global_change_num = read_metadata_record(xe, &metadata_map, global_change_num);
>> > > > +
>> > > > + /* GuC has not initialized activity data yet, return 0 */
>> > > > + if (!global_change_num)
>> > > > + goto update;
>> > > > +
>> > > > + if (global_change_num == cached_metadata->global_change_num)
>> > > > + goto update;
>> > > > + else
>> > > > + cached_metadata->global_change_num = global_change_num;
>> > > > +
>> > > > + change_num = read_engine_activity_record(xe, &activity_map, change_num);
>> > > > +
>> > > > + if (!change_num || change_num == cached_activity->change_num)
>> > > > + goto update;
>> > > > +
>> > > > + /* read engine activity values */
>> > > > + last_update_tick = read_engine_activity_record(xe, &activity_map, last_update_tick);
>> > > > + active_ticks = read_engine_activity_record(xe, &activity_map, active_ticks);
>> > > > +
>> > > > + /* activity calculations */
>> > > > + ea->running = !!last_update_tick;
>> > > > + ea->total += active_ticks - cached_activity->active_ticks;
>> > > > + ea->active = 0;
>> > > > +
>> > > > + /* cache the counter */
>> > > > + cached_activity->change_num = change_num;
>> > > > + cached_activity->last_update_tick = last_update_tick;
>> > > > + cached_activity->active_ticks = active_ticks;
>> > > > +
>> > > > +update:
>> > > > + if (ea->running) {
>> > > > + gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
>> > > > + engine_activity->gpm_timestamp_shift;
>> > > > + ea->active = lower_32_bits(gpm_ts) - cached_activity->last_update_tick;
>> > > > + }
>> > > > +
>> > > > + return ea->total + ea->active;
>> > > > +}
>> > > > +
>> > > > +static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>> > > > +{
>> > > > + struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>> > > > + struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>> > > > + struct guc_engine_activity *cached_activity = &ea->activity;
>> > > > + struct iosys_map activity_map, metadata_map;
>> > > > + struct xe_device *xe = guc_to_xe(guc);
>> > > > + ktime_t now, cpu_delta;
>> > > > + u64 numerator;
>> > > > + u16 quanta_ratio;
>> > > > +
>> > > > + activity_map = engine_activity_map(guc, hwe);
>> > > > + metadata_map = engine_metadata_map(guc);
>> > > > +
>> > > > + if (!cached_metadata->guc_tsc_frequency_hz)
>> > > > + cached_metadata->guc_tsc_frequency_hz = read_metadata_record(xe, &metadata_map,
>> > > > + guc_tsc_frequency_hz);
>> > > > +
>> > > > + quanta_ratio = read_engine_activity_record(xe, &activity_map, quanta_ratio);
>> > > > + cached_activity->quanta_ratio = quanta_ratio;
>> > > > +
>> > > > + /* Total ticks calculations */
>> > > > + now = ktime_get();
>> > > > + cpu_delta = now - ea->last_cpu_ts;
>> > > > + ea->last_cpu_ts = now;
>> > > > + numerator = (ea->quanta_remainder_ns + cpu_delta) * cached_activity->quanta_ratio;
>> > > > + ea->quanta_ns += numerator / TOTAL_QUANTA;
>> > > > + ea->quanta_remainder_ns = numerator % TOTAL_QUANTA;
>> > > > + ea->quanta = cpu_ns_to_guc_tsc_tick(ea->quanta_ns, cached_metadata->guc_tsc_frequency_hz);
>> > > > +
>> > > > + return ea->quanta;
>> > > > +}
>> > > > +
>> > > > +static int enable_engine_activity_stats(struct xe_guc *guc)
>> > > > +{
>> > > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > > > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>> > > > + u32 metadata_ggtt_addr = xe_bo_ggtt_addr(buffer->metadata_bo);
>> > > > + u32 ggtt_addr = xe_bo_ggtt_addr(buffer->activity_bo);
>> > > > + int len = 0;
>> > > > + u32 action[5];
>> > > > +
>> > > > + action[len++] = XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER;
>> > > > + action[len++] = metadata_ggtt_addr;
>> > > > + action[len++] = 0;
>> > > > + action[len++] = ggtt_addr;
>> > > > + action[len++] = 0;
>> > > > +
>> > > > + /* Blocking here to ensure the buffers are ready before reading them */
>> > > > + return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
>> > > > +}
>> > > > +
>> > > > +static void engine_activity_set_cpu_ts(struct xe_guc *guc)
>> > > > +{
>> > > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > > > + struct engine_activity_group *eag = &engine_activity->eag[0];
>> > > > + int i, j;
>> > > > +
>> > > > + for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)
>> > > > + for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; j++)
>> > > > + eag->engine[i][j].last_cpu_ts = ktime_get();
>> > > > +}
>> > > > +
>> > > > +static u32 gpm_timestamp_shift(struct xe_gt *gt)
>> > > > +{
>> > > > + u32 reg;
>> > > > +
>> > > > + reg = xe_mmio_read32(>->mmio, RPM_CONFIG0);
>> > > > +
>> > > > + return 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
>> > > > +}
>> > > > +
>> > > > +/**
>> > > > + * xe_guc_engine_activity_active_ticks - Get engine active ticks
>> > > > + * @hwe: The hw_engine object
>> > > > + *
>> > > > + * Return: accumulated ticks @hwe was active since engine activity stats were enabled.
>> > > > + */
>> > > > +u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe)
>> > > > +{
>> > > > + struct xe_guc *guc = &hwe->gt->uc.guc;
>> > > > +
>> > > > + return get_engine_active_ticks(guc, hwe);
>> > > > +}
>> > > > +
>> > > > +/**
>> > > > + * xe_guc_engine_activity_total_ticks - Get engine total ticks
>> > > > + * @hwe: The hw_engine object
>> > > > + *
>> > > > + * Return: accumulated quanta of ticks allocated for the engine
>> > > > + */
>> > > > +u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe)
>> > > > +{
>> > > > + struct xe_guc *guc = &hwe->gt->uc.guc;
>> > > > +
>> > > > + return get_engine_total_ticks(guc, hwe);
>> > > > +}
>> > > > +
>> > > > +/**
>> > > > + * xe_guc_engine_activity_enable_stats - Enable engine activity stats
>> > > > + * @guc: The GuC object
>> > > > + *
>> > > > + * Enable engine activity stats and set initial timestamps
>> > > > + */
>> > > > +void xe_guc_engine_activity_enable_stats(struct xe_guc *guc)
>> > > > +{
>> > > > + int ret;
>> > > > +
>> > > > + ret = enable_engine_activity_stats(guc);
>> > > > + if (ret)
>> > > > + xe_gt_err(guc_to_gt(guc), "failed to enable activity stats%d\n", ret);
>> > > > + else
>> > > > + engine_activity_set_cpu_ts(guc);
>> > > > +}
>> > > > +
>> > > > +static void engine_activity_fini(void *arg)
>> > > > +{
>> > > > + struct xe_guc_engine_activity *engine_activity = arg;
>> > > > +
>> > > > + kfree(engine_activity->eag);
>> > > > +}
>> > > > +
>> > > > +/**
>> > > > + * xe_guc_engine_activity_init - Initialize the engine activity data
>> > > > + * @guc: The GuC object
>> > > > + *
>> > > > + * Return: 0 on success, negative error code otherwise.
>> > > > + */
>> > > > +int xe_guc_engine_activity_init(struct xe_guc *guc)
>> > > > +{
>> > > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > > > + struct xe_gt *gt = guc_to_gt(guc);
>> > > > + int ret;
>> > > > +
>> > > > + ret = allocate_engine_activity_group(guc);
>> > > > + if (ret) {
>> > > > + xe_gt_err(gt, "failed to allocate activity group %d\n", ret);
>> > > > + return ret;
>> > > > + }
>> > > > +
>> > > > + ret = allocate_engine_activity_buffers(guc, &engine_activity->device_buffer);
>> > > > + if (ret) {
>> > > > + xe_gt_err(gt, "failed to allocate activity buffers%d\n", ret);
>> > > > + kfree(engine_activity->eag);
>> > > > + return ret;
>> > > > + }
>> > > > +
>> > > > + engine_activity->gpm_timestamp_shift = gpm_timestamp_shift(gt);
>> > > > +
>> > > > + return devm_add_action_or_reset(gt_to_xe(gt)->drm.dev, engine_activity_fini,
>> > > > + engine_activity);
>> > > > +}
>> > > > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.h b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>> > > > new file mode 100644
>> > > > index 000000000000..c00f3da5513d
>> > > > --- /dev/null
>> > > > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>> > > > @@ -0,0 +1,18 @@
>> > > > +/* SPDX-License-Identifier: MIT */
>> > > > +/*
>> > > > + * Copyright © 2025 Intel Corporation
>> > > > + */
>> > > > +
>> > > > +#ifndef _XE_GUC_ENGINE_ACTIVITY_H_
>> > > > +#define _XE_GUC_ENGINE_ACTIVITY_H_
>> > > > +
>> > > > +#include <linux/types.h>
>> > > > +
>> > > > +struct xe_hw_engine;
>> > > > +struct xe_guc;
>> > > > +
>> > > > +int xe_guc_engine_activity_init(struct xe_guc *guc);
>> > > > +void xe_guc_engine_activity_enable_stats(struct xe_guc *guc);
>> > > > +u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe);
>> > > > +u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe);
>> > > > +#endif
>> > > > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>> > > > new file mode 100644
>> > > > index 000000000000..a2ab327d3eec
>> > > > --- /dev/null
>> > > > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>> > > > @@ -0,0 +1,89 @@
>> > > > +/* SPDX-License-Identifier: MIT */
>> > > > +/*
>> > > > + * Copyright © 2025 Intel Corporation
>> > > > + */
>> > > > +
>> > > > +#ifndef _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>> > > > +#define _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>> > > > +
>> > > > +#include <linux/types.h>
>> > > > +
>> > > > +#include "xe_guc_fwif.h"
>> > > > +/**
>> > > > + * struct engine_activity - Engine specific activity data
>> > > > + *
>> > > > + * Contains engine specific activity data and snapshot of the
>> > > > + * structures from GuC
>> > > > + */
>> > > > +struct engine_activity {
>> > > > + /** @active: current activity */
>> > > > + u64 active;
>> > > > +
>> > > > + /** @last_cpu_ts: cpu timestamp in nsec of previous sample */
>> > > > + u64 last_cpu_ts;
>> > > > +
>> > > > + /** @quanta: total quanta used on HW */
>> > > > + u64 quanta;
>> > > > +
>> > > > + /** @quanta_ns: total quanta_ns used on HW */
>> > > > + u64 quanta_ns;
>> > > > +
>> > > > + /**
>> > > > + * @quanta_remainder_ns: remainder when the CPU time is scaled as
>> > > > + * per the quanta_ratio. This remainder is used in subsequent
>> > > > + * quanta calculations.
>> > > > + */
>> > > > + u64 quanta_remainder_ns;
>> > > > +
>> > > > + /** @total: total engine activity */
>> > > > + u64 total;
>> > > > +
>> > > > + /** @running: true if engine is running some work */
>> > > > + bool running;
>> > > > +
>> > > > + /** @metadata: snapshot of engine activity metadata */
>> > > > + struct guc_engine_activity_metadata metadata;
>> > > > +
>> > > > + /** @activity: snapshot of engine activity counter */
>> > > > + struct guc_engine_activity activity;
>> > > > +};
>> > > > +
>> > > > +/**
>> > > > + * struct engine_activity_group - Activity data for all engines
>> > > > + */
>> > > > +struct engine_activity_group {
>> > > > + /** @engine: engine specific activity data */
>> > > > + struct engine_activity engine[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>> > > > +};
>> > > > +
>> > > > +/**
>> > > > + * struct engine_activity_buffer - engine activity buffers
>> > > > + *
>> > > > + * This contains the buffers allocated for metadata and activity data
>> > > > + */
>> > > > +struct engine_activity_buffer {
>> > > > + /** @activity_bo: object allocated to hold activity data */
>> > > > + struct xe_bo *activity_bo;
>> > > > +
>> > > > + /** @metadata_bo: object allocated to hold activity metadata */
>> > > > + struct xe_bo *metadata_bo;
>> > > > +};
>> > > > +
>> > > > +/**
>> > > > + * struct xe_guc_engine_activity - Data used by engine activity implementation
>> > > > + */
>> > > > +struct xe_guc_engine_activity {
>> > > > + /** @gpm_timestamp_shift: Right shift value for the gpm timestamp */
>> > > > + u32 gpm_timestamp_shift;
>> > > > +
>> > > > + /** @num_activity_group: number of activity groups */
>> > > > + u32 num_activity_group;
>> > > > +
>> > > > + /** @eag: holds the device level engine activity data */
>> > > > + struct engine_activity_group *eag;
>> > > > +
>> > > > + /** @device_buffer: buffer object for global engine activity */
>> > > > + struct engine_activity_buffer device_buffer;
>> > > > +};
>> > > > +#endif
>> > > > +
>> > > > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
>> > > > index 057153f89b30..6f57578b07cb 100644
>> > > > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
>> > > > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
>> > > > @@ -208,6 +208,25 @@ struct guc_engine_usage {
>> > > > struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>> > > > } __packed;
>> > > >
>> > > > +/* Engine Activity stats */
>> > > > +struct guc_engine_activity {
>> > > > + u16 change_num;
>> > > > + u16 quanta_ratio;
>> > > > + u32 last_update_tick;
>> > > > + u64 active_ticks;
>> > > > +} __packed;
>> > > > +
>> > > > +struct guc_engine_activity_data {
>> > > > + struct guc_engine_activity engine_activity[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>> > > > +} __packed;
>> > > > +
>> > > > +struct guc_engine_activity_metadata {
>> > > > + u32 guc_tsc_frequency_hz;
>> > > > + u32 lag_latency_usec;
>> > > > + u32 global_change_num;
>> > > > + u32 reserved;
>> > > > +} __packed;
>> > > > +
>> > > > /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
>> > > > enum xe_guc_recv_message {
>> > > > XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
>> > > > diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h
>> > > > index 573aa6308380..63bac64429a5 100644
>> > > > --- a/drivers/gpu/drm/xe/xe_guc_types.h
>> > > > +++ b/drivers/gpu/drm/xe/xe_guc_types.h
>> > > > @@ -13,6 +13,7 @@
>> > > > #include "xe_guc_ads_types.h"
>> > > > #include "xe_guc_buf_types.h"
>> > > > #include "xe_guc_ct_types.h"
>> > > > +#include "xe_guc_engine_activity_types.h"
>> > > > #include "xe_guc_fwif.h"
>> > > > #include "xe_guc_log_types.h"
>> > > > #include "xe_guc_pc_types.h"
>> > > > @@ -103,6 +104,9 @@ struct xe_guc {
>> > > > /** @relay: GuC Relay Communication used in SR-IOV */
>> > > > struct xe_guc_relay relay;
>> > > >
>> > > > + /** @engine_activity: Device specific engine activity */
>> > > > + struct xe_guc_engine_activity engine_activity;
>> > > > +
>> > > > /**
>> > > > * @notify_reg: Register which is written to notify GuC of H2G messages
>> > > > */
>> > > > --
>> > > > 2.47.1
>> > > >
>>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 1/8] drm/xe: Add per-engine-class activity support
2025-01-30 23:56 ` Lucas De Marchi
@ 2025-01-31 17:13 ` Umesh Nerlige Ramappa
2025-02-03 5:15 ` Riana Tauro
0 siblings, 1 reply; 45+ messages in thread
From: Umesh Nerlige Ramappa @ 2025-01-31 17:13 UTC (permalink / raw)
To: Lucas De Marchi
Cc: Rodrigo Vivi, Riana Tauro, intel-xe, anshuman.gupta,
vinay.belgaumkar, soham.purkait, Himal Prasad Ghimiray
On Thu, Jan 30, 2025 at 05:56:05PM -0600, Lucas De Marchi wrote:
>On Thu, Jan 30, 2025 at 05:36:03PM -0500, Rodrigo Vivi wrote:
>>On Thu, Jan 30, 2025 at 10:19:24AM +0530, Riana Tauro wrote:
>>>Hi Umesh/Rodrigo
>>>
>>>On 1/30/2025 8:05 AM, Rodrigo Vivi wrote:
>>>> On Wed, Jan 29, 2025 at 04:28:36PM -0800, Umesh Nerlige Ramappa wrote:
>>>> > On Wed, Jan 29, 2025 at 03:46:44PM +0530, Riana Tauro wrote:
>>>> > > GuC provides support to read engine counters to calculate the
>>>> > > engine activity. KMD exposes two counters via the PMU interface to
>>>> > > calculate engine activity
>>>> > >
>>>> > > Engine Active Ticks(engine-active-ticks) - number of active ticks for engine
>>>> > > Engine Total Ticks (engine-total-ticks) - total ticks of engine
>>>> > >
>>>> > > Engine activity percentage can be calculated as below
>>>> > > Engine activity % = (engine active ticks/engine total ticks) * 100.
>>>> > >
>>>> > > v2: fix cosmetic review comments
>>>> > > add forcewake for gpm_ts (Umesh)
>>>> > >
>>>> > > v3: fix CI hooks error
>>>> > > change function parameters and unpin bo on error
>>>> > > of allocate_activity_buffers
>>>> > > fix kernel-doc (Umesh)
>>>> > > use engine activity (Umesh, Lucas)
>>>> > > rename xe_engine_activity to xe_guc_engine_*
>>>> > > fix commit message to use per-engine class(Lucas)
>>>> > >
>>>> > > v4: remove forcewake as engine is already running
>>>> > > when reading gpm timestamp
>>>> >
>>>> > + Rodrigo
>>>> >
>>>> > Sorry, I think I mentioned offline that the runtime pm get is sufficient for
>>>> > reading this register, but it's not. It does need a forcewake of the GT
>>>> > domain. At the same time, we cannot use the xe_force_wake_get because of
>>>> > the lockdep issue you mentioned and also I assume that xe_force_wake_get may
>>>> > sleep and the event may be read from irq context.
>>>The lockdep issue is due to perf holding a raw_spinlock and forcewake having
>>>a spinlock. In 6.13 due to config PROVE_RAW_LOCK_NESTING being enabled was
>>>seeing this issue. Latest patch has disabled this due to issues with i915.
>>>
>>>[ 465.359017] =============================
>>>[ 465.363050] [ BUG: Invalid wait context ]
>>>[ 465.367063] 6.13.0-rc5-xe #11 Tainted: G U
>>>[ 465.372544] -----------------------------
>>>[ 465.376555] swapper/0/0 is trying to lock:
>>>[ 465.380652] ffff88810d5b8098 (&fw->lock){....}-{3:3}, at:
>>>xe_force_wake_get+0x1f9/0x8c0 [xe]
>>>[ 465.389168] other info that might help us debug this:
>>>[ 465.394221] context-{5:5}
>>>[ 465.396847] 1 lock held by swapper/0/0:
>>>[ 465.400682] #0: ffff88885f031fb8 (&cpuctx_lock){....}-{2:2}, at:
>>>__perf_event_read+0x60/0x230
>>>[ 465.409295] stack backtrace:
>>
>>
>>hmmm I had forgotten about this...
>>
>>Lucas, since you were the last one that looked into it,
>>would be feasible to switch at least the xe_force_wake towards
>>raw_spinlock?
>
>no, I don't think so. We hold the spinlock and then call
>xe_mmio_wait32(... XE_FORCE_WAKE_ACK_TIMEOUT_MS). Yeah.. it's only upper
>bound, but we should look at other solutions.
>
>1) move the read to the hrtimer, like is done for e.g. rapl. We can then
> continue using spinlock for the hw interaction.
My concern with (1) is that counter resolution will depend on the timer
periodicity and I am slightly hesitant to do that in the KMD. If
possible, KMD should not be the limiting factor. In the past I recall
i915 pmu had a 200hz timer running for sampling some events, but that
was deemed to be CPU intensive at some point.
Also if the GPU timestamp is being populated in memory at hrtimer
intervals, and the engine activity is populated in memory by GuC on a
different timeline, we may end up having to sync those two in KMD to
reduce the error margin (since eventually engine activity is a ratio of
these two counters).
>
>2) introduce a raw_spinlock that will protect only domain->ref
> that would allow us to implement an _if_active variant. But I
> don't know how that would help here since we need to read the
> register. What do we do when the fw is not taken?
_if_active was a bad suggestion for force_wake. I was confusing it with
runtime_pm. In this case, we want to get the force_wake and read the
register.
>
> on gt-c6 that idea was dropped on the floor since it was
> not working well and overcomplicating it.
>
>3) ... something else?
Maybe along with raw_spinlock in the force_wake_get, have a fastpath for
force_wake_get (essentially lower timeout). If that fails, we just
return the previous engine_activity/gpu_timestamp.
4) Would it make sense to acquire a FORCEWAKE_ALL (or a subset if we
know the specific domains of interest) at event_init and then release it
on event_destroy?
I would prefer (4) though if that's not a big power impact. Although I
don't know how it will affect the rc6_residency counter itself.
Regards,
Umesh
>
>Lucas De Marchi
>
>>
>>
>>>
>>>
>>>Since in this case we are checking mmio only when engine is running
>>>and gt will be active. i thought we could remove it.
>>>
>>>>>> + if (ea->running) {
>>>>>> + gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
>>>>>> + engine_activity->gpm_timestamp_shift;
>>>>>> + ea->active = lower_32_bits(gpm_ts) -
>>>cached_activity->last_update_tick;
>>>>>> + }
>>>
>>>But yeah, gt might enter c6 just after reading ea->running. To avoid this,as
>>>lucas suggested have to use hr timer.
>>>
>>>I thought if needed, will add it as part of a separate series.
>>>I can add the forcewake back as the config is removed and add hr timer in
>>>another series.
>>>
>>>Thanks
>>>Riana
>>>>
>>>> I don't understand this statement entirely. force wake get cannot sleep.
>>>> It is based on spin locks. It should not be issuing any lockdep here.
>>>> It is quite simple flow with minimal or none interdependency. Remember
>>>> that in i915 for instance it exists and lives in the middle of every
>>>> mmio read and write call...
>>>>
>>>> >
>>>> > I would check if we can add a helper xe_force_wake_get_if_active() and just
>>>> > use that to bump up the wakeref.
>>>>
>>>> I would prefer to not complicate things...
>>>>
>>>> >
>>>> > @Rodrigo, @Vinay Any thoughts on this ^ ?
>>>>
>>>> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>>>>
>>>> >
>>>> > Thanks,
>>>> > Umesh
>>>> >
>>>> > >
>>>> > > Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>>>> > > Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>>> > > ---
>>>> > > drivers/gpu/drm/xe/Makefile | 1 +
>>>> > > drivers/gpu/drm/xe/abi/guc_actions_abi.h | 1 +
>>>> > > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
>>>> > > drivers/gpu/drm/xe/xe_guc_engine_activity.c | 317 ++++++++++++++++++
>>>> > > drivers/gpu/drm/xe/xe_guc_engine_activity.h | 18 +
>>>> > > .../gpu/drm/xe/xe_guc_engine_activity_types.h | 89 +++++
>>>> > > drivers/gpu/drm/xe/xe_guc_fwif.h | 19 ++
>>>> > > drivers/gpu/drm/xe/xe_guc_types.h | 4 +
>>>> > > 8 files changed, 451 insertions(+)
>>>> > > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>>> > > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.h
>>>> > > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>>>> > >
>>>> > > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>>>> > > index 328aff36831b..7e93461c60bd 100644
>>>> > > --- a/drivers/gpu/drm/xe/Makefile
>>>> > > +++ b/drivers/gpu/drm/xe/Makefile
>>>> > > @@ -33,6 +33,7 @@ xe-y += xe_bb.o \
>>>> > > xe_device_sysfs.o \
>>>> > > xe_dma_buf.o \
>>>> > > xe_drm_client.o \
>>>> > > + xe_guc_engine_activity.o \
>>>> > > xe_exec.o \
>>>> > > xe_execlist.o \
>>>> > > xe_exec_queue.o \
>>>> > > diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>>> > > index fee385532fb0..ec516e838ee8 100644
>>>> > > --- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>>> > > +++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>>> > > @@ -140,6 +140,7 @@ enum xe_guc_action {
>>>> > > XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
>>>> > > XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
>>>> > > XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
>>>> > > + XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
>>>> > > XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
>>>> > > XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
>>>> > > XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,
>>>> > > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>>> > > index 096859072396..124cc398798e 100644
>>>> > > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>>> > > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>>> > > @@ -358,6 +358,8 @@
>>>> > > #define RENDER_AWAKE_STATUS REG_BIT(1)
>>>> > > #define MEDIA_SLICE0_AWAKE_STATUS REG_BIT(0)
>>>> > >
>>>> > > +#define MISC_STATUS_0 XE_REG(0xa500)
>>>> > > +
>>>> > > #define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4)
>>>> > > #define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4)
>>>> > > #define FORCEWAKE_GSC XE_REG(0xa618)
>>>> > > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>>> > > new file mode 100644
>>>> > > index 000000000000..088209b9c228
>>>> > > --- /dev/null
>>>> > > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>>> > > @@ -0,0 +1,317 @@
>>>> > > +// SPDX-License-Identifier: MIT
>>>> > > +/*
>>>> > > + * Copyright © 2025 Intel Corporation
>>>> > > + */
>>>> > > +#include "xe_guc_engine_activity.h"
>>>> > > +
>>>> > > +#include "abi/guc_actions_abi.h"
>>>> > > +#include "regs/xe_gt_regs.h"
>>>> > > +
>>>> > > +#include "xe_bo.h"
>>>> > > +#include "xe_force_wake.h"
>>>> > > +#include "xe_gt_printk.h"
>>>> > > +#include "xe_guc.h"
>>>> > > +#include "xe_guc_ct.h"
>>>> > > +#include "xe_hw_engine.h"
>>>> > > +#include "xe_map.h"
>>>> > > +#include "xe_mmio.h"
>>>> > > +
>>>> > > +#define TOTAL_QUANTA 0x8000
>>>> > > +
>>>> > > +static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_engine *hwe)
>>>> > > +{
>>>> > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>>> > > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>>>> > > + u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>>>> > > + size_t offset = 0;
>>>> > > +
>>>> > > + offset = offsetof(struct guc_engine_activity_data,
>>>> > > + engine_activity[guc_class][hwe->logical_instance]);
>>>> > > +
>>>> > > + return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap, offset);
>>>> > > +}
>>>> > > +
>>>> > > +static struct iosys_map engine_metadata_map(struct xe_guc *guc)
>>>> > > +{
>>>> > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>>> > > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>>>> > > +
>>>> > > + return buffer->metadata_bo->vmap;
>>>> > > +}
>>>> > > +
>>>> > > +static int allocate_engine_activity_group(struct xe_guc *guc)
>>>> > > +{
>>>> > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>>> > > + u32 num_activity_group = 1;
>>>> > > +
>>>> > > + engine_activity->eag = kmalloc_array(num_activity_group,
>>>> > > + sizeof(struct engine_activity_group),
>>>> > > + GFP_KERNEL);
>>>> > > +
>>>> > > + if (!engine_activity->eag)
>>>> > > + return -ENOMEM;
>>>> > > +
>>>> > > + memset(engine_activity->eag, 0, num_activity_group * sizeof(struct engine_activity_group));
>>>> > > + engine_activity->num_activity_group = num_activity_group;
>>>> > > +
>>>> > > + return 0;
>>>> > > +}
>>>> > > +
>>>> > > +static int allocate_engine_activity_buffers(struct xe_guc *guc,
>>>> > > + struct engine_activity_buffer *buffer)
>>>> > > +{
>>>> > > + u32 metadata_size = sizeof(struct guc_engine_activity_metadata);
>>>> > > + u32 size = sizeof(struct guc_engine_activity_data);
>>>> > > + struct xe_gt *gt = guc_to_gt(guc);
>>>> > > + struct xe_tile *tile = gt_to_tile(gt);
>>>> > > + struct xe_bo *bo, *metadata_bo;
>>>> > > +
>>>> > > + metadata_bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(metadata_size),
>>>> > > + XE_BO_FLAG_SYSTEM |
>>>> > > + XE_BO_FLAG_GGTT |
>>>> > > + XE_BO_FLAG_GGTT_INVALIDATE);
>>>> > > + if (IS_ERR(metadata_bo))
>>>> > > + return PTR_ERR(metadata_bo);
>>>> > > +
>>>> > > + bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(size),
>>>> > > + XE_BO_FLAG_VRAM_IF_DGFX(tile) |
>>>> > > + XE_BO_FLAG_GGTT |
>>>> > > + XE_BO_FLAG_GGTT_INVALIDATE);
>>>> > > +
>>>> > > + if (IS_ERR(bo)) {
>>>> > > + xe_bo_unpin_map_no_vm(metadata_bo);
>>>> > > + return PTR_ERR(bo);
>>>> > > + }
>>>> > > +
>>>> > > + buffer->metadata_bo = metadata_bo;
>>>> > > + buffer->activity_bo = bo;
>>>> > > + return 0;
>>>> > > +}
>>>> > > +
>>>> > > +static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine *hwe)
>>>> > > +{
>>>> > > + struct xe_guc *guc = &hwe->gt->uc.guc;
>>>> > > + struct engine_activity_group *eag = &guc->engine_activity.eag[0];
>>>> > > + u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>>>> > > +
>>>> > > + return &eag->engine[guc_class][hwe->logical_instance];
>>>> > > +}
>>>> > > +
>>>> > > +static u64 cpu_ns_to_guc_tsc_tick(ktime_t ns, u32 freq)
>>>> > > +{
>>>> > > + return mul_u64_u32_div(ns, freq, NSEC_PER_SEC);
>>>> > > +}
>>>> > > +
>>>> > > +#define read_engine_activity_record(xe_, map_, field_) \
>>>> > > + xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity, field_)
>>>> > > +
>>>> > > +#define read_metadata_record(xe_, map_, field_) \
>>>> > > + xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity_metadata, field_)
>>>> > > +
>>>> > > +static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>>>> > > +{
>>>> > > + struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>>>> > > + struct guc_engine_activity *cached_activity = &ea->activity;
>>>> > > + struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>>>> > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>>> > > + struct iosys_map activity_map, metadata_map;
>>>> > > + struct xe_device *xe = guc_to_xe(guc);
>>>> > > + struct xe_gt *gt = guc_to_gt(guc);
>>>> > > + u32 last_update_tick, global_change_num;
>>>> > > + u64 active_ticks, gpm_ts;
>>>> > > + u16 change_num;
>>>> > > +
>>>> > > + activity_map = engine_activity_map(guc, hwe);
>>>> > > + metadata_map = engine_metadata_map(guc);
>>>> > > + global_change_num = read_metadata_record(xe, &metadata_map, global_change_num);
>>>> > > +
>>>> > > + /* GuC has not initialized activity data yet, return 0 */
>>>> > > + if (!global_change_num)
>>>> > > + goto update;
>>>> > > +
>>>> > > + if (global_change_num == cached_metadata->global_change_num)
>>>> > > + goto update;
>>>> > > + else
>>>> > > + cached_metadata->global_change_num = global_change_num;
>>>> > > +
>>>> > > + change_num = read_engine_activity_record(xe, &activity_map, change_num);
>>>> > > +
>>>> > > + if (!change_num || change_num == cached_activity->change_num)
>>>> > > + goto update;
>>>> > > +
>>>> > > + /* read engine activity values */
>>>> > > + last_update_tick = read_engine_activity_record(xe, &activity_map, last_update_tick);
>>>> > > + active_ticks = read_engine_activity_record(xe, &activity_map, active_ticks);
>>>> > > +
>>>> > > + /* activity calculations */
>>>> > > + ea->running = !!last_update_tick;
>>>> > > + ea->total += active_ticks - cached_activity->active_ticks;
>>>> > > + ea->active = 0;
>>>> > > +
>>>> > > + /* cache the counter */
>>>> > > + cached_activity->change_num = change_num;
>>>> > > + cached_activity->last_update_tick = last_update_tick;
>>>> > > + cached_activity->active_ticks = active_ticks;
>>>> > > +
>>>> > > +update:
>>>> > > + if (ea->running) {
>>>> > > + gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
>>>> > > + engine_activity->gpm_timestamp_shift;
>>>> > > + ea->active = lower_32_bits(gpm_ts) - cached_activity->last_update_tick;
>>>> > > + }
>>>> > > +
>>>> > > + return ea->total + ea->active;
>>>> > > +}
>>>> > > +
>>>> > > +static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>>>> > > +{
>>>> > > + struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>>>> > > + struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>>>> > > + struct guc_engine_activity *cached_activity = &ea->activity;
>>>> > > + struct iosys_map activity_map, metadata_map;
>>>> > > + struct xe_device *xe = guc_to_xe(guc);
>>>> > > + ktime_t now, cpu_delta;
>>>> > > + u64 numerator;
>>>> > > + u16 quanta_ratio;
>>>> > > +
>>>> > > + activity_map = engine_activity_map(guc, hwe);
>>>> > > + metadata_map = engine_metadata_map(guc);
>>>> > > +
>>>> > > + if (!cached_metadata->guc_tsc_frequency_hz)
>>>> > > + cached_metadata->guc_tsc_frequency_hz = read_metadata_record(xe, &metadata_map,
>>>> > > + guc_tsc_frequency_hz);
>>>> > > +
>>>> > > + quanta_ratio = read_engine_activity_record(xe, &activity_map, quanta_ratio);
>>>> > > + cached_activity->quanta_ratio = quanta_ratio;
>>>> > > +
>>>> > > + /* Total ticks calculations */
>>>> > > + now = ktime_get();
>>>> > > + cpu_delta = now - ea->last_cpu_ts;
>>>> > > + ea->last_cpu_ts = now;
>>>> > > + numerator = (ea->quanta_remainder_ns + cpu_delta) * cached_activity->quanta_ratio;
>>>> > > + ea->quanta_ns += numerator / TOTAL_QUANTA;
>>>> > > + ea->quanta_remainder_ns = numerator % TOTAL_QUANTA;
>>>> > > + ea->quanta = cpu_ns_to_guc_tsc_tick(ea->quanta_ns, cached_metadata->guc_tsc_frequency_hz);
>>>> > > +
>>>> > > + return ea->quanta;
>>>> > > +}
>>>> > > +
>>>> > > +static int enable_engine_activity_stats(struct xe_guc *guc)
>>>> > > +{
>>>> > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>>> > > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>>>> > > + u32 metadata_ggtt_addr = xe_bo_ggtt_addr(buffer->metadata_bo);
>>>> > > + u32 ggtt_addr = xe_bo_ggtt_addr(buffer->activity_bo);
>>>> > > + int len = 0;
>>>> > > + u32 action[5];
>>>> > > +
>>>> > > + action[len++] = XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER;
>>>> > > + action[len++] = metadata_ggtt_addr;
>>>> > > + action[len++] = 0;
>>>> > > + action[len++] = ggtt_addr;
>>>> > > + action[len++] = 0;
>>>> > > +
>>>> > > + /* Blocking here to ensure the buffers are ready before reading them */
>>>> > > + return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
>>>> > > +}
>>>> > > +
>>>> > > +static void engine_activity_set_cpu_ts(struct xe_guc *guc)
>>>> > > +{
>>>> > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>>> > > + struct engine_activity_group *eag = &engine_activity->eag[0];
>>>> > > + int i, j;
>>>> > > +
>>>> > > + for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)
>>>> > > + for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; j++)
>>>> > > + eag->engine[i][j].last_cpu_ts = ktime_get();
>>>> > > +}
>>>> > > +
>>>> > > +static u32 gpm_timestamp_shift(struct xe_gt *gt)
>>>> > > +{
>>>> > > + u32 reg;
>>>> > > +
>>>> > > + reg = xe_mmio_read32(>->mmio, RPM_CONFIG0);
>>>> > > +
>>>> > > + return 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
>>>> > > +}
>>>> > > +
>>>> > > +/**
>>>> > > + * xe_guc_engine_activity_active_ticks - Get engine active ticks
>>>> > > + * @hwe: The hw_engine object
>>>> > > + *
>>>> > > + * Return: accumulated ticks @hwe was active since engine activity stats were enabled.
>>>> > > + */
>>>> > > +u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe)
>>>> > > +{
>>>> > > + struct xe_guc *guc = &hwe->gt->uc.guc;
>>>> > > +
>>>> > > + return get_engine_active_ticks(guc, hwe);
>>>> > > +}
>>>> > > +
>>>> > > +/**
>>>> > > + * xe_guc_engine_activity_total_ticks - Get engine total ticks
>>>> > > + * @hwe: The hw_engine object
>>>> > > + *
>>>> > > + * Return: accumulated quanta of ticks allocated for the engine
>>>> > > + */
>>>> > > +u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe)
>>>> > > +{
>>>> > > + struct xe_guc *guc = &hwe->gt->uc.guc;
>>>> > > +
>>>> > > + return get_engine_total_ticks(guc, hwe);
>>>> > > +}
>>>> > > +
>>>> > > +/**
>>>> > > + * xe_guc_engine_activity_enable_stats - Enable engine activity stats
>>>> > > + * @guc: The GuC object
>>>> > > + *
>>>> > > + * Enable engine activity stats and set initial timestamps
>>>> > > + */
>>>> > > +void xe_guc_engine_activity_enable_stats(struct xe_guc *guc)
>>>> > > +{
>>>> > > + int ret;
>>>> > > +
>>>> > > + ret = enable_engine_activity_stats(guc);
>>>> > > + if (ret)
>>>> > > + xe_gt_err(guc_to_gt(guc), "failed to enable activity stats%d\n", ret);
>>>> > > + else
>>>> > > + engine_activity_set_cpu_ts(guc);
>>>> > > +}
>>>> > > +
>>>> > > +static void engine_activity_fini(void *arg)
>>>> > > +{
>>>> > > + struct xe_guc_engine_activity *engine_activity = arg;
>>>> > > +
>>>> > > + kfree(engine_activity->eag);
>>>> > > +}
>>>> > > +
>>>> > > +/**
>>>> > > + * xe_guc_engine_activity_init - Initialize the engine activity data
>>>> > > + * @guc: The GuC object
>>>> > > + *
>>>> > > + * Return: 0 on success, negative error code otherwise.
>>>> > > + */
>>>> > > +int xe_guc_engine_activity_init(struct xe_guc *guc)
>>>> > > +{
>>>> > > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>>> > > + struct xe_gt *gt = guc_to_gt(guc);
>>>> > > + int ret;
>>>> > > +
>>>> > > + ret = allocate_engine_activity_group(guc);
>>>> > > + if (ret) {
>>>> > > + xe_gt_err(gt, "failed to allocate activity group %d\n", ret);
>>>> > > + return ret;
>>>> > > + }
>>>> > > +
>>>> > > + ret = allocate_engine_activity_buffers(guc, &engine_activity->device_buffer);
>>>> > > + if (ret) {
>>>> > > + xe_gt_err(gt, "failed to allocate activity buffers%d\n", ret);
>>>> > > + kfree(engine_activity->eag);
>>>> > > + return ret;
>>>> > > + }
>>>> > > +
>>>> > > + engine_activity->gpm_timestamp_shift = gpm_timestamp_shift(gt);
>>>> > > +
>>>> > > + return devm_add_action_or_reset(gt_to_xe(gt)->drm.dev, engine_activity_fini,
>>>> > > + engine_activity);
>>>> > > +}
>>>> > > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.h b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>>>> > > new file mode 100644
>>>> > > index 000000000000..c00f3da5513d
>>>> > > --- /dev/null
>>>> > > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>>>> > > @@ -0,0 +1,18 @@
>>>> > > +/* SPDX-License-Identifier: MIT */
>>>> > > +/*
>>>> > > + * Copyright © 2025 Intel Corporation
>>>> > > + */
>>>> > > +
>>>> > > +#ifndef _XE_GUC_ENGINE_ACTIVITY_H_
>>>> > > +#define _XE_GUC_ENGINE_ACTIVITY_H_
>>>> > > +
>>>> > > +#include <linux/types.h>
>>>> > > +
>>>> > > +struct xe_hw_engine;
>>>> > > +struct xe_guc;
>>>> > > +
>>>> > > +int xe_guc_engine_activity_init(struct xe_guc *guc);
>>>> > > +void xe_guc_engine_activity_enable_stats(struct xe_guc *guc);
>>>> > > +u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe);
>>>> > > +u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe);
>>>> > > +#endif
>>>> > > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>>>> > > new file mode 100644
>>>> > > index 000000000000..a2ab327d3eec
>>>> > > --- /dev/null
>>>> > > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>>>> > > @@ -0,0 +1,89 @@
>>>> > > +/* SPDX-License-Identifier: MIT */
>>>> > > +/*
>>>> > > + * Copyright © 2025 Intel Corporation
>>>> > > + */
>>>> > > +
>>>> > > +#ifndef _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>>>> > > +#define _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>>>> > > +
>>>> > > +#include <linux/types.h>
>>>> > > +
>>>> > > +#include "xe_guc_fwif.h"
>>>> > > +/**
>>>> > > + * struct engine_activity - Engine specific activity data
>>>> > > + *
>>>> > > + * Contains engine specific activity data and snapshot of the
>>>> > > + * structures from GuC
>>>> > > + */
>>>> > > +struct engine_activity {
>>>> > > + /** @active: current activity */
>>>> > > + u64 active;
>>>> > > +
>>>> > > + /** @last_cpu_ts: cpu timestamp in nsec of previous sample */
>>>> > > + u64 last_cpu_ts;
>>>> > > +
>>>> > > + /** @quanta: total quanta used on HW */
>>>> > > + u64 quanta;
>>>> > > +
>>>> > > + /** @quanta_ns: total quanta_ns used on HW */
>>>> > > + u64 quanta_ns;
>>>> > > +
>>>> > > + /**
>>>> > > + * @quanta_remainder_ns: remainder when the CPU time is scaled as
>>>> > > + * per the quanta_ratio. This remainder is used in subsequent
>>>> > > + * quanta calculations.
>>>> > > + */
>>>> > > + u64 quanta_remainder_ns;
>>>> > > +
>>>> > > + /** @total: total engine activity */
>>>> > > + u64 total;
>>>> > > +
>>>> > > + /** @running: true if engine is running some work */
>>>> > > + bool running;
>>>> > > +
>>>> > > + /** @metadata: snapshot of engine activity metadata */
>>>> > > + struct guc_engine_activity_metadata metadata;
>>>> > > +
>>>> > > + /** @activity: snapshot of engine activity counter */
>>>> > > + struct guc_engine_activity activity;
>>>> > > +};
>>>> > > +
>>>> > > +/**
>>>> > > + * struct engine_activity_group - Activity data for all engines
>>>> > > + */
>>>> > > +struct engine_activity_group {
>>>> > > + /** @engine: engine specific activity data */
>>>> > > + struct engine_activity engine[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>>>> > > +};
>>>> > > +
>>>> > > +/**
>>>> > > + * struct engine_activity_buffer - engine activity buffers
>>>> > > + *
>>>> > > + * This contains the buffers allocated for metadata and activity data
>>>> > > + */
>>>> > > +struct engine_activity_buffer {
>>>> > > + /** @activity_bo: object allocated to hold activity data */
>>>> > > + struct xe_bo *activity_bo;
>>>> > > +
>>>> > > + /** @metadata_bo: object allocated to hold activity metadata */
>>>> > > + struct xe_bo *metadata_bo;
>>>> > > +};
>>>> > > +
>>>> > > +/**
>>>> > > + * struct xe_guc_engine_activity - Data used by engine activity implementation
>>>> > > + */
>>>> > > +struct xe_guc_engine_activity {
>>>> > > + /** @gpm_timestamp_shift: Right shift value for the gpm timestamp */
>>>> > > + u32 gpm_timestamp_shift;
>>>> > > +
>>>> > > + /** @num_activity_group: number of activity groups */
>>>> > > + u32 num_activity_group;
>>>> > > +
>>>> > > + /** @eag: holds the device level engine activity data */
>>>> > > + struct engine_activity_group *eag;
>>>> > > +
>>>> > > + /** @device_buffer: buffer object for global engine activity */
>>>> > > + struct engine_activity_buffer device_buffer;
>>>> > > +};
>>>> > > +#endif
>>>> > > +
>>>> > > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
>>>> > > index 057153f89b30..6f57578b07cb 100644
>>>> > > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
>>>> > > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
>>>> > > @@ -208,6 +208,25 @@ struct guc_engine_usage {
>>>> > > struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>>>> > > } __packed;
>>>> > >
>>>> > > +/* Engine Activity stats */
>>>> > > +struct guc_engine_activity {
>>>> > > + u16 change_num;
>>>> > > + u16 quanta_ratio;
>>>> > > + u32 last_update_tick;
>>>> > > + u64 active_ticks;
>>>> > > +} __packed;
>>>> > > +
>>>> > > +struct guc_engine_activity_data {
>>>> > > + struct guc_engine_activity engine_activity[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>>>> > > +} __packed;
>>>> > > +
>>>> > > +struct guc_engine_activity_metadata {
>>>> > > + u32 guc_tsc_frequency_hz;
>>>> > > + u32 lag_latency_usec;
>>>> > > + u32 global_change_num;
>>>> > > + u32 reserved;
>>>> > > +} __packed;
>>>> > > +
>>>> > > /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
>>>> > > enum xe_guc_recv_message {
>>>> > > XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
>>>> > > diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h
>>>> > > index 573aa6308380..63bac64429a5 100644
>>>> > > --- a/drivers/gpu/drm/xe/xe_guc_types.h
>>>> > > +++ b/drivers/gpu/drm/xe/xe_guc_types.h
>>>> > > @@ -13,6 +13,7 @@
>>>> > > #include "xe_guc_ads_types.h"
>>>> > > #include "xe_guc_buf_types.h"
>>>> > > #include "xe_guc_ct_types.h"
>>>> > > +#include "xe_guc_engine_activity_types.h"
>>>> > > #include "xe_guc_fwif.h"
>>>> > > #include "xe_guc_log_types.h"
>>>> > > #include "xe_guc_pc_types.h"
>>>> > > @@ -103,6 +104,9 @@ struct xe_guc {
>>>> > > /** @relay: GuC Relay Communication used in SR-IOV */
>>>> > > struct xe_guc_relay relay;
>>>> > >
>>>> > > + /** @engine_activity: Device specific engine activity */
>>>> > > + struct xe_guc_engine_activity engine_activity;
>>>> > > +
>>>> > > /**
>>>> > > * @notify_reg: Register which is written to notify GuC of H2G messages
>>>> > > */
>>>> > > --
>>>> > > 2.47.1
>>>> > >
>>>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 1/8] drm/xe: Add per-engine-class activity support
2025-01-31 17:13 ` Umesh Nerlige Ramappa
@ 2025-02-03 5:15 ` Riana Tauro
0 siblings, 0 replies; 45+ messages in thread
From: Riana Tauro @ 2025-02-03 5:15 UTC (permalink / raw)
To: Umesh Nerlige Ramappa, Lucas De Marchi
Cc: Rodrigo Vivi, intel-xe, anshuman.gupta, vinay.belgaumkar,
soham.purkait, Himal Prasad Ghimiray
Hi Umesh
On 1/31/2025 10:43 PM, Umesh Nerlige Ramappa wrote:
> On Thu, Jan 30, 2025 at 05:56:05PM -0600, Lucas De Marchi wrote:
>> On Thu, Jan 30, 2025 at 05:36:03PM -0500, Rodrigo Vivi wrote:
>>> On Thu, Jan 30, 2025 at 10:19:24AM +0530, Riana Tauro wrote:
>>>> Hi Umesh/Rodrigo
>>>>
>>>> On 1/30/2025 8:05 AM, Rodrigo Vivi wrote:
>>>>> On Wed, Jan 29, 2025 at 04:28:36PM -0800, Umesh Nerlige Ramappa wrote:
>>>>> > On Wed, Jan 29, 2025 at 03:46:44PM +0530, Riana Tauro wrote:
>>>>> > > GuC provides support to read engine counters to calculate the
>>>>> > > engine activity. KMD exposes two counters via the PMU interface to
>>>>> > > calculate engine activity
>>>>> > >
>>>>> > > Engine Active Ticks(engine-active-ticks) - number of active
>>>>> ticks for engine
>>>>> > > Engine Total Ticks (engine-total-ticks) - total ticks of engine
>>>>> > >
>>>>> > > Engine activity percentage can be calculated as below
>>>>> > > Engine activity % = (engine active ticks/engine total ticks) *
>>>>> 100.
>>>>> > >
>>>>> > > v2: fix cosmetic review comments
>>>>> > > add forcewake for gpm_ts (Umesh)
>>>>> > >
>>>>> > > v3: fix CI hooks error
>>>>> > > change function parameters and unpin bo on error
>>>>> > > of allocate_activity_buffers
>>>>> > > fix kernel-doc (Umesh)
>>>>> > > use engine activity (Umesh, Lucas)
>>>>> > > rename xe_engine_activity to xe_guc_engine_*
>>>>> > > fix commit message to use per-engine class(Lucas)
>>>>> > >
>>>>> > > v4: remove forcewake as engine is already running
>>>>> > > when reading gpm timestamp
>>>>> >
>>>>> > + Rodrigo
>>>>> >
>>>>> > Sorry, I think I mentioned offline that the runtime pm get is
>>>>> sufficient for
>>>>> > reading this register, but it's not. It does need a forcewake of
>>>>> the GT
>>>>> > domain. At the same time, we cannot use the xe_force_wake_get
>>>>> because of
>>>>> > the lockdep issue you mentioned and also I assume that
>>>>> xe_force_wake_get may
>>>>> > sleep and the event may be read from irq context.
>>>> The lockdep issue is due to perf holding a raw_spinlock and
>>>> forcewake having
>>>> a spinlock. In 6.13 due to config PROVE_RAW_LOCK_NESTING being
>>>> enabled was
>>>> seeing this issue. Latest patch has disabled this due to issues with
>>>> i915.
>>>>
>>>> [ 465.359017] =============================
>>>> [ 465.363050] [ BUG: Invalid wait context ]
>>>> [ 465.367063] 6.13.0-rc5-xe #11 Tainted: G U
>>>> [ 465.372544] -----------------------------
>>>> [ 465.376555] swapper/0/0 is trying to lock:
>>>> [ 465.380652] ffff88810d5b8098 (&fw->lock){....}-{3:3}, at:
>>>> xe_force_wake_get+0x1f9/0x8c0 [xe]
>>>> [ 465.389168] other info that might help us debug this:
>>>> [ 465.394221] context-{5:5}
>>>> [ 465.396847] 1 lock held by swapper/0/0:
>>>> [ 465.400682] #0: ffff88885f031fb8 (&cpuctx_lock){....}-{2:2}, at:
>>>> __perf_event_read+0x60/0x230
>>>> [ 465.409295] stack backtrace:
>>>
>>>
>>> hmmm I had forgotten about this...
>>>
>>> Lucas, since you were the last one that looked into it,
>>> would be feasible to switch at least the xe_force_wake towards
>>> raw_spinlock?
>>
>> no, I don't think so. We hold the spinlock and then call
>> xe_mmio_wait32(... XE_FORCE_WAKE_ACK_TIMEOUT_MS). Yeah.. it's only upper
>> bound, but we should look at other solutions.
>>
>> 1) move the read to the hrtimer, like is done for e.g. rapl. We can then
>> continue using spinlock for the hw interaction.
>
> My concern with (1) is that counter resolution will depend on the timer
> periodicity and I am slightly hesitant to do that in the KMD. If
> possible, KMD should not be the limiting factor. In the past I recall
> i915 pmu had a 200hz timer running for sampling some events, but that
> was deemed to be CPU intensive at some point.
yeah had the same question here. What should be sampling frequency.
Should it be same as frequency events or how to handle this?
>
> Also if the GPU timestamp is being populated in memory at hrtimer
> intervals, and the engine activity is populated in memory by GuC on a
> different timeline, we may end up having to sync those two in KMD to
> reduce the error margin (since eventually engine activity is a ratio of
> these two counters).
>
>>
>> 2) introduce a raw_spinlock that will protect only domain->ref
>> that would allow us to implement an _if_active variant. But I
>> don't know how that would help here since we need to read the
>> register. What do we do when the fw is not taken?
>
> _if_active was a bad suggestion for force_wake. I was confusing it with
> runtime_pm. In this case, we want to get the force_wake and read the
> register.
>>
>> on gt-c6 that idea was dropped on the floor since it was
>> not working well and overcomplicating it.
>>
>> 3) ... something else?
>
> Maybe along with raw_spinlock in the force_wake_get, have a fastpath for
> force_wake_get (essentially lower timeout). If that fails, we just
> return the previous engine_activity/gpu_timestamp.
There was disagreement to converting force_wake lock to raw_spinlock.
Can there be another api for force_wake with raw_spinlock ?
>
> 4) Would it make sense to acquire a FORCEWAKE_ALL (or a subset if we
> know the specific domains of interest) at event_init and then release it
> on event_destroy?
We could do it only for engine events since gt-c6 events are present too
in pmu and it would always report 0 residency if done for all.
Thanks
Riana
>
> I would prefer (4) though if that's not a big power impact. Although I
> don't know how it will affect the rc6_residency counter itself.
>
> Regards,
> Umesh
>
>>
>> Lucas De Marchi
>>
>>>
>>>
>>>>
>>>>
>>>> Since in this case we are checking mmio only when engine is running
>>>> and gt will be active. i thought we could remove it.
>>>>
>>>>>>> + if (ea->running) {
>>>>>>> + gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
>>>>>>> + engine_activity->gpm_timestamp_shift;
>>>>>>> + ea->active = lower_32_bits(gpm_ts) -
>>>> cached_activity->last_update_tick;
>>>>>>> + }
>>>>
>>>> But yeah, gt might enter c6 just after reading ea->running. To avoid
>>>> this,as
>>>> lucas suggested have to use hr timer.
>>>>
>>>> I thought if needed, will add it as part of a separate series.
>>>> I can add the forcewake back as the config is removed and add hr
>>>> timer in
>>>> another series.
>>>>
>>>> Thanks
>>>> Riana
>>>>>
>>>>> I don't understand this statement entirely. force wake get cannot
>>>>> sleep.
>>>>> It is based on spin locks. It should not be issuing any lockdep here.
>>>>> It is quite simple flow with minimal or none interdependency. Remember
>>>>> that in i915 for instance it exists and lives in the middle of every
>>>>> mmio read and write call...
>>>>>
>>>>> >
>>>>> > I would check if we can add a helper
>>>>> xe_force_wake_get_if_active() and just
>>>>> > use that to bump up the wakeref.
>>>>>
>>>>> I would prefer to not complicate things...
>>>>>
>>>>> >
>>>>> > @Rodrigo, @Vinay Any thoughts on this ^ ?
>>>>>
>>>>> Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>>>>>
>>>>> >
>>>>> > Thanks,
>>>>> > Umesh
>>>>> >
>>>>> > >
>>>>> > > Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>>>>> > > Reviewed-by: Umesh Nerlige Ramappa
>>>>> <umesh.nerlige.ramappa@intel.com>
>>>>> > > ---
>>>>> > > drivers/gpu/drm/xe/Makefile | 1 +
>>>>> > > drivers/gpu/drm/xe/abi/guc_actions_abi.h | 1 +
>>>>> > > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
>>>>> > > drivers/gpu/drm/xe/xe_guc_engine_activity.c | 317 +++++++++++
>>>>> +++++++
>>>>> > > drivers/gpu/drm/xe/xe_guc_engine_activity.h | 18 +
>>>>> > > .../gpu/drm/xe/xe_guc_engine_activity_types.h | 89 +++++
>>>>> > > drivers/gpu/drm/xe/xe_guc_fwif.h | 19 ++
>>>>> > > drivers/gpu/drm/xe/xe_guc_types.h | 4 +
>>>>> > > 8 files changed, 451 insertions(+)
>>>>> > > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>>>> > > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.h
>>>>> > > create mode 100644 drivers/gpu/drm/xe/
>>>>> xe_guc_engine_activity_types.h
>>>>> > >
>>>>> > > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/
>>>>> Makefile
>>>>> > > index 328aff36831b..7e93461c60bd 100644
>>>>> > > --- a/drivers/gpu/drm/xe/Makefile
>>>>> > > +++ b/drivers/gpu/drm/xe/Makefile
>>>>> > > @@ -33,6 +33,7 @@ xe-y += xe_bb.o \
>>>>> > > xe_device_sysfs.o \
>>>>> > > xe_dma_buf.o \
>>>>> > > xe_drm_client.o \
>>>>> > > + xe_guc_engine_activity.o \
>>>>> > > xe_exec.o \
>>>>> > > xe_execlist.o \
>>>>> > > xe_exec_queue.o \
>>>>> > > diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/
>>>>> drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>>>> > > index fee385532fb0..ec516e838ee8 100644
>>>>> > > --- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>>>> > > +++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>>>> > > @@ -140,6 +140,7 @@ enum xe_guc_action {
>>>>> > > XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
>>>>> > > XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
>>>>> > > XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
>>>>> > > + XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
>>>>> > > XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
>>>>> > > XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
>>>>> > > XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,
>>>>> > > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/
>>>>> gpu/drm/xe/regs/xe_gt_regs.h
>>>>> > > index 096859072396..124cc398798e 100644
>>>>> > > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>>>> > > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>>>> > > @@ -358,6 +358,8 @@
>>>>> > > #define RENDER_AWAKE_STATUS REG_BIT(1)
>>>>> > > #define MEDIA_SLICE0_AWAKE_STATUS REG_BIT(0)
>>>>> > >
>>>>> > > +#define MISC_STATUS_0 XE_REG(0xa500)
>>>>> > > +
>>>>> > > #define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4)
>>>>> > > #define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4)
>>>>> > > #define FORCEWAKE_GSC XE_REG(0xa618)
>>>>> > > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/
>>>>> drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>>>> > > new file mode 100644
>>>>> > > index 000000000000..088209b9c228
>>>>> > > --- /dev/null
>>>>> > > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>>>> > > @@ -0,0 +1,317 @@
>>>>> > > +// SPDX-License-Identifier: MIT
>>>>> > > +/*
>>>>> > > + * Copyright © 2025 Intel Corporation
>>>>> > > + */
>>>>> > > +#include "xe_guc_engine_activity.h"
>>>>> > > +
>>>>> > > +#include "abi/guc_actions_abi.h"
>>>>> > > +#include "regs/xe_gt_regs.h"
>>>>> > > +
>>>>> > > +#include "xe_bo.h"
>>>>> > > +#include "xe_force_wake.h"
>>>>> > > +#include "xe_gt_printk.h"
>>>>> > > +#include "xe_guc.h"
>>>>> > > +#include "xe_guc_ct.h"
>>>>> > > +#include "xe_hw_engine.h"
>>>>> > > +#include "xe_map.h"
>>>>> > > +#include "xe_mmio.h"
>>>>> > > +
>>>>> > > +#define TOTAL_QUANTA 0x8000
>>>>> > > +
>>>>> > > +static struct iosys_map engine_activity_map(struct xe_guc
>>>>> *guc, struct xe_hw_engine *hwe)
>>>>> > > +{
>>>>> > > + struct xe_guc_engine_activity *engine_activity = &guc-
>>>>> >engine_activity;
>>>>> > > + struct engine_activity_buffer *buffer = &engine_activity-
>>>>> >device_buffer;
>>>>> > > + u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>>>>> > > + size_t offset = 0;
>>>>> > > +
>>>>> > > + offset = offsetof(struct guc_engine_activity_data,
>>>>> > > + engine_activity[guc_class][hwe->logical_instance]);
>>>>> > > +
>>>>> > > + return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap,
>>>>> offset);
>>>>> > > +}
>>>>> > > +
>>>>> > > +static struct iosys_map engine_metadata_map(struct xe_guc *guc)
>>>>> > > +{
>>>>> > > + struct xe_guc_engine_activity *engine_activity = &guc-
>>>>> >engine_activity;
>>>>> > > + struct engine_activity_buffer *buffer = &engine_activity-
>>>>> >device_buffer;
>>>>> > > +
>>>>> > > + return buffer->metadata_bo->vmap;
>>>>> > > +}
>>>>> > > +
>>>>> > > +static int allocate_engine_activity_group(struct xe_guc *guc)
>>>>> > > +{
>>>>> > > + struct xe_guc_engine_activity *engine_activity = &guc-
>>>>> >engine_activity;
>>>>> > > + u32 num_activity_group = 1;
>>>>> > > +
>>>>> > > + engine_activity->eag = kmalloc_array(num_activity_group,
>>>>> > > + sizeof(struct engine_activity_group),
>>>>> > > + GFP_KERNEL);
>>>>> > > +
>>>>> > > + if (!engine_activity->eag)
>>>>> > > + return -ENOMEM;
>>>>> > > +
>>>>> > > + memset(engine_activity->eag, 0, num_activity_group *
>>>>> sizeof(struct engine_activity_group));
>>>>> > > + engine_activity->num_activity_group = num_activity_group;
>>>>> > > +
>>>>> > > + return 0;
>>>>> > > +}
>>>>> > > +
>>>>> > > +static int allocate_engine_activity_buffers(struct xe_guc *guc,
>>>>> > > + struct engine_activity_buffer *buffer)
>>>>> > > +{
>>>>> > > + u32 metadata_size = sizeof(struct
>>>>> guc_engine_activity_metadata);
>>>>> > > + u32 size = sizeof(struct guc_engine_activity_data);
>>>>> > > + struct xe_gt *gt = guc_to_gt(guc);
>>>>> > > + struct xe_tile *tile = gt_to_tile(gt);
>>>>> > > + struct xe_bo *bo, *metadata_bo;
>>>>> > > +
>>>>> > > + metadata_bo = xe_managed_bo_create_pin_map(gt_to_xe(gt),
>>>>> tile, PAGE_ALIGN(metadata_size),
>>>>> > > + XE_BO_FLAG_SYSTEM |
>>>>> > > + XE_BO_FLAG_GGTT |
>>>>> > > + XE_BO_FLAG_GGTT_INVALIDATE);
>>>>> > > + if (IS_ERR(metadata_bo))
>>>>> > > + return PTR_ERR(metadata_bo);
>>>>> > > +
>>>>> > > + bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile,
>>>>> PAGE_ALIGN(size),
>>>>> > > + XE_BO_FLAG_VRAM_IF_DGFX(tile) |
>>>>> > > + XE_BO_FLAG_GGTT |
>>>>> > > + XE_BO_FLAG_GGTT_INVALIDATE);
>>>>> > > +
>>>>> > > + if (IS_ERR(bo)) {
>>>>> > > + xe_bo_unpin_map_no_vm(metadata_bo);
>>>>> > > + return PTR_ERR(bo);
>>>>> > > + }
>>>>> > > +
>>>>> > > + buffer->metadata_bo = metadata_bo;
>>>>> > > + buffer->activity_bo = bo;
>>>>> > > + return 0;
>>>>> > > +}
>>>>> > > +
>>>>> > > +static struct engine_activity
>>>>> *hw_engine_to_engine_activity(struct xe_hw_engine *hwe)
>>>>> > > +{
>>>>> > > + struct xe_guc *guc = &hwe->gt->uc.guc;
>>>>> > > + struct engine_activity_group *eag = &guc-
>>>>> >engine_activity.eag[0];
>>>>> > > + u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>>>>> > > +
>>>>> > > + return &eag->engine[guc_class][hwe->logical_instance];
>>>>> > > +}
>>>>> > > +
>>>>> > > +static u64 cpu_ns_to_guc_tsc_tick(ktime_t ns, u32 freq)
>>>>> > > +{
>>>>> > > + return mul_u64_u32_div(ns, freq, NSEC_PER_SEC);
>>>>> > > +}
>>>>> > > +
>>>>> > > +#define read_engine_activity_record(xe_, map_, field_) \
>>>>> > > + xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity,
>>>>> field_)
>>>>> > > +
>>>>> > > +#define read_metadata_record(xe_, map_, field_) \
>>>>> > > + xe_map_rd_field(xe_, map_, 0, struct
>>>>> guc_engine_activity_metadata, field_)
>>>>> > > +
>>>>> > > +static u64 get_engine_active_ticks(struct xe_guc *guc, struct
>>>>> xe_hw_engine *hwe)
>>>>> > > +{
>>>>> > > + struct engine_activity *ea =
>>>>> hw_engine_to_engine_activity(hwe);
>>>>> > > + struct guc_engine_activity *cached_activity = &ea->activity;
>>>>> > > + struct guc_engine_activity_metadata *cached_metadata =
>>>>> &ea->metadata;
>>>>> > > + struct xe_guc_engine_activity *engine_activity = &guc-
>>>>> >engine_activity;
>>>>> > > + struct iosys_map activity_map, metadata_map;
>>>>> > > + struct xe_device *xe = guc_to_xe(guc);
>>>>> > > + struct xe_gt *gt = guc_to_gt(guc);
>>>>> > > + u32 last_update_tick, global_change_num;
>>>>> > > + u64 active_ticks, gpm_ts;
>>>>> > > + u16 change_num;
>>>>> > > +
>>>>> > > + activity_map = engine_activity_map(guc, hwe);
>>>>> > > + metadata_map = engine_metadata_map(guc);
>>>>> > > + global_change_num = read_metadata_record(xe,
>>>>> &metadata_map, global_change_num);
>>>>> > > +
>>>>> > > + /* GuC has not initialized activity data yet, return 0 */
>>>>> > > + if (!global_change_num)
>>>>> > > + goto update;
>>>>> > > +
>>>>> > > + if (global_change_num == cached_metadata->global_change_num)
>>>>> > > + goto update;
>>>>> > > + else
>>>>> > > + cached_metadata->global_change_num = global_change_num;
>>>>> > > +
>>>>> > > + change_num = read_engine_activity_record(xe,
>>>>> &activity_map, change_num);
>>>>> > > +
>>>>> > > + if (!change_num || change_num == cached_activity->change_num)
>>>>> > > + goto update;
>>>>> > > +
>>>>> > > + /* read engine activity values */
>>>>> > > + last_update_tick = read_engine_activity_record(xe,
>>>>> &activity_map, last_update_tick);
>>>>> > > + active_ticks = read_engine_activity_record(xe,
>>>>> &activity_map, active_ticks);
>>>>> > > +
>>>>> > > + /* activity calculations */
>>>>> > > + ea->running = !!last_update_tick;
>>>>> > > + ea->total += active_ticks - cached_activity->active_ticks;
>>>>> > > + ea->active = 0;
>>>>> > > +
>>>>> > > + /* cache the counter */
>>>>> > > + cached_activity->change_num = change_num;
>>>>> > > + cached_activity->last_update_tick = last_update_tick;
>>>>> > > + cached_activity->active_ticks = active_ticks;
>>>>> > > +
>>>>> > > +update:
>>>>> > > + if (ea->running) {
>>>>> > > + gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
>>>>> > > + engine_activity->gpm_timestamp_shift;
>>>>> > > + ea->active = lower_32_bits(gpm_ts) - cached_activity-
>>>>> >last_update_tick;
>>>>> > > + }
>>>>> > > +
>>>>> > > + return ea->total + ea->active;
>>>>> > > +}
>>>>> > > +
>>>>> > > +static u64 get_engine_total_ticks(struct xe_guc *guc, struct
>>>>> xe_hw_engine *hwe)
>>>>> > > +{
>>>>> > > + struct engine_activity *ea =
>>>>> hw_engine_to_engine_activity(hwe);
>>>>> > > + struct guc_engine_activity_metadata *cached_metadata =
>>>>> &ea->metadata;
>>>>> > > + struct guc_engine_activity *cached_activity = &ea->activity;
>>>>> > > + struct iosys_map activity_map, metadata_map;
>>>>> > > + struct xe_device *xe = guc_to_xe(guc);
>>>>> > > + ktime_t now, cpu_delta;
>>>>> > > + u64 numerator;
>>>>> > > + u16 quanta_ratio;
>>>>> > > +
>>>>> > > + activity_map = engine_activity_map(guc, hwe);
>>>>> > > + metadata_map = engine_metadata_map(guc);
>>>>> > > +
>>>>> > > + if (!cached_metadata->guc_tsc_frequency_hz)
>>>>> > > + cached_metadata->guc_tsc_frequency_hz =
>>>>> read_metadata_record(xe, &metadata_map,
>>>>> > > + guc_tsc_frequency_hz);
>>>>> > > +
>>>>> > > + quanta_ratio = read_engine_activity_record(xe,
>>>>> &activity_map, quanta_ratio);
>>>>> > > + cached_activity->quanta_ratio = quanta_ratio;
>>>>> > > +
>>>>> > > + /* Total ticks calculations */
>>>>> > > + now = ktime_get();
>>>>> > > + cpu_delta = now - ea->last_cpu_ts;
>>>>> > > + ea->last_cpu_ts = now;
>>>>> > > + numerator = (ea->quanta_remainder_ns + cpu_delta) *
>>>>> cached_activity->quanta_ratio;
>>>>> > > + ea->quanta_ns += numerator / TOTAL_QUANTA;
>>>>> > > + ea->quanta_remainder_ns = numerator % TOTAL_QUANTA;
>>>>> > > + ea->quanta = cpu_ns_to_guc_tsc_tick(ea->quanta_ns,
>>>>> cached_metadata->guc_tsc_frequency_hz);
>>>>> > > +
>>>>> > > + return ea->quanta;
>>>>> > > +}
>>>>> > > +
>>>>> > > +static int enable_engine_activity_stats(struct xe_guc *guc)
>>>>> > > +{
>>>>> > > + struct xe_guc_engine_activity *engine_activity = &guc-
>>>>> >engine_activity;
>>>>> > > + struct engine_activity_buffer *buffer = &engine_activity-
>>>>> >device_buffer;
>>>>> > > + u32 metadata_ggtt_addr = xe_bo_ggtt_addr(buffer-
>>>>> >metadata_bo);
>>>>> > > + u32 ggtt_addr = xe_bo_ggtt_addr(buffer->activity_bo);
>>>>> > > + int len = 0;
>>>>> > > + u32 action[5];
>>>>> > > +
>>>>> > > + action[len++] =
>>>>> XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER;
>>>>> > > + action[len++] = metadata_ggtt_addr;
>>>>> > > + action[len++] = 0;
>>>>> > > + action[len++] = ggtt_addr;
>>>>> > > + action[len++] = 0;
>>>>> > > +
>>>>> > > + /* Blocking here to ensure the buffers are ready before
>>>>> reading them */
>>>>> > > + return xe_guc_ct_send_block(&guc->ct, action,
>>>>> ARRAY_SIZE(action));
>>>>> > > +}
>>>>> > > +
>>>>> > > +static void engine_activity_set_cpu_ts(struct xe_guc *guc)
>>>>> > > +{
>>>>> > > + struct xe_guc_engine_activity *engine_activity = &guc-
>>>>> >engine_activity;
>>>>> > > + struct engine_activity_group *eag = &engine_activity->eag[0];
>>>>> > > + int i, j;
>>>>> > > +
>>>>> > > + for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)
>>>>> > > + for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; j++)
>>>>> > > + eag->engine[i][j].last_cpu_ts = ktime_get();
>>>>> > > +}
>>>>> > > +
>>>>> > > +static u32 gpm_timestamp_shift(struct xe_gt *gt)
>>>>> > > +{
>>>>> > > + u32 reg;
>>>>> > > +
>>>>> > > + reg = xe_mmio_read32(>->mmio, RPM_CONFIG0);
>>>>> > > +
>>>>> > > + return 3 -
>>>>> REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
>>>>> > > +}
>>>>> > > +
>>>>> > > +/**
>>>>> > > + * xe_guc_engine_activity_active_ticks - Get engine active ticks
>>>>> > > + * @hwe: The hw_engine object
>>>>> > > + *
>>>>> > > + * Return: accumulated ticks @hwe was active since engine
>>>>> activity stats were enabled.
>>>>> > > + */
>>>>> > > +u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe)
>>>>> > > +{
>>>>> > > + struct xe_guc *guc = &hwe->gt->uc.guc;
>>>>> > > +
>>>>> > > + return get_engine_active_ticks(guc, hwe);
>>>>> > > +}
>>>>> > > +
>>>>> > > +/**
>>>>> > > + * xe_guc_engine_activity_total_ticks - Get engine total ticks
>>>>> > > + * @hwe: The hw_engine object
>>>>> > > + *
>>>>> > > + * Return: accumulated quanta of ticks allocated for the engine
>>>>> > > + */
>>>>> > > +u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe)
>>>>> > > +{
>>>>> > > + struct xe_guc *guc = &hwe->gt->uc.guc;
>>>>> > > +
>>>>> > > + return get_engine_total_ticks(guc, hwe);
>>>>> > > +}
>>>>> > > +
>>>>> > > +/**
>>>>> > > + * xe_guc_engine_activity_enable_stats - Enable engine
>>>>> activity stats
>>>>> > > + * @guc: The GuC object
>>>>> > > + *
>>>>> > > + * Enable engine activity stats and set initial timestamps
>>>>> > > + */
>>>>> > > +void xe_guc_engine_activity_enable_stats(struct xe_guc *guc)
>>>>> > > +{
>>>>> > > + int ret;
>>>>> > > +
>>>>> > > + ret = enable_engine_activity_stats(guc);
>>>>> > > + if (ret)
>>>>> > > + xe_gt_err(guc_to_gt(guc), "failed to enable activity
>>>>> stats%d\n", ret);
>>>>> > > + else
>>>>> > > + engine_activity_set_cpu_ts(guc);
>>>>> > > +}
>>>>> > > +
>>>>> > > +static void engine_activity_fini(void *arg)
>>>>> > > +{
>>>>> > > + struct xe_guc_engine_activity *engine_activity = arg;
>>>>> > > +
>>>>> > > + kfree(engine_activity->eag);
>>>>> > > +}
>>>>> > > +
>>>>> > > +/**
>>>>> > > + * xe_guc_engine_activity_init - Initialize the engine
>>>>> activity data
>>>>> > > + * @guc: The GuC object
>>>>> > > + *
>>>>> > > + * Return: 0 on success, negative error code otherwise.
>>>>> > > + */
>>>>> > > +int xe_guc_engine_activity_init(struct xe_guc *guc)
>>>>> > > +{
>>>>> > > + struct xe_guc_engine_activity *engine_activity = &guc-
>>>>> >engine_activity;
>>>>> > > + struct xe_gt *gt = guc_to_gt(guc);
>>>>> > > + int ret;
>>>>> > > +
>>>>> > > + ret = allocate_engine_activity_group(guc);
>>>>> > > + if (ret) {
>>>>> > > + xe_gt_err(gt, "failed to allocate activity group
>>>>> %d\n", ret);
>>>>> > > + return ret;
>>>>> > > + }
>>>>> > > +
>>>>> > > + ret = allocate_engine_activity_buffers(guc,
>>>>> &engine_activity->device_buffer);
>>>>> > > + if (ret) {
>>>>> > > + xe_gt_err(gt, "failed to allocate activity
>>>>> buffers%d\n", ret);
>>>>> > > + kfree(engine_activity->eag);
>>>>> > > + return ret;
>>>>> > > + }
>>>>> > > +
>>>>> > > + engine_activity->gpm_timestamp_shift =
>>>>> gpm_timestamp_shift(gt);
>>>>> > > +
>>>>> > > + return devm_add_action_or_reset(gt_to_xe(gt)->drm.dev,
>>>>> engine_activity_fini,
>>>>> > > + engine_activity);
>>>>> > > +}
>>>>> > > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.h b/
>>>>> drivers/gpu/drm/xe/xe_guc_engine_activity.h
>>>>> > > new file mode 100644
>>>>> > > index 000000000000..c00f3da5513d
>>>>> > > --- /dev/null
>>>>> > > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>>>>> > > @@ -0,0 +1,18 @@
>>>>> > > +/* SPDX-License-Identifier: MIT */
>>>>> > > +/*
>>>>> > > + * Copyright © 2025 Intel Corporation
>>>>> > > + */
>>>>> > > +
>>>>> > > +#ifndef _XE_GUC_ENGINE_ACTIVITY_H_
>>>>> > > +#define _XE_GUC_ENGINE_ACTIVITY_H_
>>>>> > > +
>>>>> > > +#include <linux/types.h>
>>>>> > > +
>>>>> > > +struct xe_hw_engine;
>>>>> > > +struct xe_guc;
>>>>> > > +
>>>>> > > +int xe_guc_engine_activity_init(struct xe_guc *guc);
>>>>> > > +void xe_guc_engine_activity_enable_stats(struct xe_guc *guc);
>>>>> > > +u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine
>>>>> *hwe);
>>>>> > > +u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe);
>>>>> > > +#endif
>>>>> > > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>>>>> b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>>>>> > > new file mode 100644
>>>>> > > index 000000000000..a2ab327d3eec
>>>>> > > --- /dev/null
>>>>> > > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>>>>> > > @@ -0,0 +1,89 @@
>>>>> > > +/* SPDX-License-Identifier: MIT */
>>>>> > > +/*
>>>>> > > + * Copyright © 2025 Intel Corporation
>>>>> > > + */
>>>>> > > +
>>>>> > > +#ifndef _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>>>>> > > +#define _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>>>>> > > +
>>>>> > > +#include <linux/types.h>
>>>>> > > +
>>>>> > > +#include "xe_guc_fwif.h"
>>>>> > > +/**
>>>>> > > + * struct engine_activity - Engine specific activity data
>>>>> > > + *
>>>>> > > + * Contains engine specific activity data and snapshot of the
>>>>> > > + * structures from GuC
>>>>> > > + */
>>>>> > > +struct engine_activity {
>>>>> > > + /** @active: current activity */
>>>>> > > + u64 active;
>>>>> > > +
>>>>> > > + /** @last_cpu_ts: cpu timestamp in nsec of previous sample */
>>>>> > > + u64 last_cpu_ts;
>>>>> > > +
>>>>> > > + /** @quanta: total quanta used on HW */
>>>>> > > + u64 quanta;
>>>>> > > +
>>>>> > > + /** @quanta_ns: total quanta_ns used on HW */
>>>>> > > + u64 quanta_ns;
>>>>> > > +
>>>>> > > + /**
>>>>> > > + * @quanta_remainder_ns: remainder when the CPU time is
>>>>> scaled as
>>>>> > > + * per the quanta_ratio. This remainder is used in subsequent
>>>>> > > + * quanta calculations.
>>>>> > > + */
>>>>> > > + u64 quanta_remainder_ns;
>>>>> > > +
>>>>> > > + /** @total: total engine activity */
>>>>> > > + u64 total;
>>>>> > > +
>>>>> > > + /** @running: true if engine is running some work */
>>>>> > > + bool running;
>>>>> > > +
>>>>> > > + /** @metadata: snapshot of engine activity metadata */
>>>>> > > + struct guc_engine_activity_metadata metadata;
>>>>> > > +
>>>>> > > + /** @activity: snapshot of engine activity counter */
>>>>> > > + struct guc_engine_activity activity;
>>>>> > > +};
>>>>> > > +
>>>>> > > +/**
>>>>> > > + * struct engine_activity_group - Activity data for all engines
>>>>> > > + */
>>>>> > > +struct engine_activity_group {
>>>>> > > + /** @engine: engine specific activity data */
>>>>> > > + struct engine_activity engine[GUC_MAX_ENGINE_CLASSES]
>>>>> [GUC_MAX_INSTANCES_PER_CLASS];
>>>>> > > +};
>>>>> > > +
>>>>> > > +/**
>>>>> > > + * struct engine_activity_buffer - engine activity buffers
>>>>> > > + *
>>>>> > > + * This contains the buffers allocated for metadata and
>>>>> activity data
>>>>> > > + */
>>>>> > > +struct engine_activity_buffer {
>>>>> > > + /** @activity_bo: object allocated to hold activity data */
>>>>> > > + struct xe_bo *activity_bo;
>>>>> > > +
>>>>> > > + /** @metadata_bo: object allocated to hold activity
>>>>> metadata */
>>>>> > > + struct xe_bo *metadata_bo;
>>>>> > > +};
>>>>> > > +
>>>>> > > +/**
>>>>> > > + * struct xe_guc_engine_activity - Data used by engine
>>>>> activity implementation
>>>>> > > + */
>>>>> > > +struct xe_guc_engine_activity {
>>>>> > > + /** @gpm_timestamp_shift: Right shift value for the gpm
>>>>> timestamp */
>>>>> > > + u32 gpm_timestamp_shift;
>>>>> > > +
>>>>> > > + /** @num_activity_group: number of activity groups */
>>>>> > > + u32 num_activity_group;
>>>>> > > +
>>>>> > > + /** @eag: holds the device level engine activity data */
>>>>> > > + struct engine_activity_group *eag;
>>>>> > > +
>>>>> > > + /** @device_buffer: buffer object for global engine
>>>>> activity */
>>>>> > > + struct engine_activity_buffer device_buffer;
>>>>> > > +};
>>>>> > > +#endif
>>>>> > > +
>>>>> > > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/
>>>>> drm/xe/xe_guc_fwif.h
>>>>> > > index 057153f89b30..6f57578b07cb 100644
>>>>> > > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
>>>>> > > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
>>>>> > > @@ -208,6 +208,25 @@ struct guc_engine_usage {
>>>>> > > struct guc_engine_usage_record
>>>>> engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>>>>> > > } __packed;
>>>>> > >
>>>>> > > +/* Engine Activity stats */
>>>>> > > +struct guc_engine_activity {
>>>>> > > + u16 change_num;
>>>>> > > + u16 quanta_ratio;
>>>>> > > + u32 last_update_tick;
>>>>> > > + u64 active_ticks;
>>>>> > > +} __packed;
>>>>> > > +
>>>>> > > +struct guc_engine_activity_data {
>>>>> > > + struct guc_engine_activity
>>>>> engine_activity[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>>>>> > > +} __packed;
>>>>> > > +
>>>>> > > +struct guc_engine_activity_metadata {
>>>>> > > + u32 guc_tsc_frequency_hz;
>>>>> > > + u32 lag_latency_usec;
>>>>> > > + u32 global_change_num;
>>>>> > > + u32 reserved;
>>>>> > > +} __packed;
>>>>> > > +
>>>>> > > /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
>>>>> > > enum xe_guc_recv_message {
>>>>> > > XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
>>>>> > > diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/
>>>>> drm/xe/xe_guc_types.h
>>>>> > > index 573aa6308380..63bac64429a5 100644
>>>>> > > --- a/drivers/gpu/drm/xe/xe_guc_types.h
>>>>> > > +++ b/drivers/gpu/drm/xe/xe_guc_types.h
>>>>> > > @@ -13,6 +13,7 @@
>>>>> > > #include "xe_guc_ads_types.h"
>>>>> > > #include "xe_guc_buf_types.h"
>>>>> > > #include "xe_guc_ct_types.h"
>>>>> > > +#include "xe_guc_engine_activity_types.h"
>>>>> > > #include "xe_guc_fwif.h"
>>>>> > > #include "xe_guc_log_types.h"
>>>>> > > #include "xe_guc_pc_types.h"
>>>>> > > @@ -103,6 +104,9 @@ struct xe_guc {
>>>>> > > /** @relay: GuC Relay Communication used in SR-IOV */
>>>>> > > struct xe_guc_relay relay;
>>>>> > >
>>>>> > > + /** @engine_activity: Device specific engine activity */
>>>>> > > + struct xe_guc_engine_activity engine_activity;
>>>>> > > +
>>>>> > > /**
>>>>> > > * @notify_reg: Register which is written to notify GuC of
>>>>> H2G messages
>>>>> > > */
>>>>> > > --
>>>>> > > 2.47.1
>>>>> > >
>>>>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v4 1/8] drm/xe: Add per-engine-class activity support
2025-01-30 4:49 ` Riana Tauro
2025-01-30 22:36 ` Rodrigo Vivi
@ 2025-01-30 23:00 ` Lucas De Marchi
1 sibling, 0 replies; 45+ messages in thread
From: Lucas De Marchi @ 2025-01-30 23:00 UTC (permalink / raw)
To: Riana Tauro
Cc: Rodrigo Vivi, Umesh Nerlige Ramappa, intel-xe, anshuman.gupta,
vinay.belgaumkar, soham.purkait, Himal Prasad Ghimiray
On Thu, Jan 30, 2025 at 10:19:24AM +0530, Riana Tauro wrote:
>Hi Umesh/Rodrigo
>
>On 1/30/2025 8:05 AM, Rodrigo Vivi wrote:
>>On Wed, Jan 29, 2025 at 04:28:36PM -0800, Umesh Nerlige Ramappa wrote:
>>>On Wed, Jan 29, 2025 at 03:46:44PM +0530, Riana Tauro wrote:
>>>>GuC provides support to read engine counters to calculate the
>>>>engine activity. KMD exposes two counters via the PMU interface to
>>>>calculate engine activity
>>>>
>>>>Engine Active Ticks(engine-active-ticks) - number of active ticks for engine
>>>>Engine Total Ticks (engine-total-ticks) - total ticks of engine
>>>>
>>>>Engine activity percentage can be calculated as below
>>>>Engine activity % = (engine active ticks/engine total ticks) * 100.
>>>>
>>>>v2: fix cosmetic review comments
>>>> add forcewake for gpm_ts (Umesh)
>>>>
>>>>v3: fix CI hooks error
>>>> change function parameters and unpin bo on error
>>>> of allocate_activity_buffers
>>>> fix kernel-doc (Umesh)
>>>> use engine activity (Umesh, Lucas)
>>>> rename xe_engine_activity to xe_guc_engine_*
>>>> fix commit message to use per-engine class(Lucas)
>>>>
>>>>v4: remove forcewake as engine is already running
>>>> when reading gpm timestamp
>>>
>>>+ Rodrigo
>>>
>>>Sorry, I think I mentioned offline that the runtime pm get is sufficient for
>>>reading this register, but it's not. It does need a forcewake of the GT
>>>domain. At the same time, we cannot use the xe_force_wake_get because of
>>>the lockdep issue you mentioned and also I assume that xe_force_wake_get may
>>>sleep and the event may be read from irq context.
>The lockdep issue is due to perf holding a raw_spinlock and forcewake
>having a spinlock. In 6.13 due to config PROVE_RAW_LOCK_NESTING being
>enabled was seeing this issue. Latest patch has disabled this due to
>issues with i915.
>
>[ 465.359017] =============================
>[ 465.363050] [ BUG: Invalid wait context ]
>[ 465.367063] 6.13.0-rc5-xe #11 Tainted: G U
>[ 465.372544] -----------------------------
>[ 465.376555] swapper/0/0 is trying to lock:
>[ 465.380652] ffff88810d5b8098 (&fw->lock){....}-{3:3}, at:
>xe_force_wake_get+0x1f9/0x8c0 [xe]
>[ 465.389168] other info that might help us debug this:
>[ 465.394221] context-{5:5}
>[ 465.396847] 1 lock held by swapper/0/0:
>[ 465.400682] #0: ffff88885f031fb8 (&cpuctx_lock){....}-{2:2}, at:
>__perf_event_read+0x60/0x230
>[ 465.409295] stack backtrace:
>
>
>Since in this case we are checking mmio only when engine is running
>and gt will be active. i thought we could remove it.
>
>>>> + if (ea->running) {
>>>> + gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
>>>> + engine_activity->gpm_timestamp_shift;
>>>> + ea->active = lower_32_bits(gpm_ts) -
>cached_activity->last_update_tick;
>>>> + }
>
>But yeah, gt might enter c6 just after reading ea->running. To avoid
>this,as lucas suggested have to use hr timer.
>
>I thought if needed, will add it as part of a separate series.
>I can add the forcewake back as the config is removed and add hr timer
no, we are only papering over CI exploding in order to buy time to get
it fixed. But I think I will remove the patch from topic/core-for-CI
since it has the potential to cause more harm.
Lucas De Marchi
>in another series.
>
>Thanks
>Riana
>>
>>I don't understand this statement entirely. force wake get cannot sleep.
>>It is based on spin locks. It should not be issuing any lockdep here.
>>It is quite simple flow with minimal or none interdependency. Remember
>>that in i915 for instance it exists and lives in the middle of every
>>mmio read and write call...
>>
>>>
>>>I would check if we can add a helper xe_force_wake_get_if_active() and just
>>>use that to bump up the wakeref.
>>
>>I would prefer to not complicate things...
>>
>>>
>>>@Rodrigo, @Vinay Any thoughts on this ^ ?
>>
>>Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>>
>>>
>>>Thanks,
>>>Umesh
>>>
>>>>
>>>>Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>>>>Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>>>---
>>>>drivers/gpu/drm/xe/Makefile | 1 +
>>>>drivers/gpu/drm/xe/abi/guc_actions_abi.h | 1 +
>>>>drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
>>>>drivers/gpu/drm/xe/xe_guc_engine_activity.c | 317 ++++++++++++++++++
>>>>drivers/gpu/drm/xe/xe_guc_engine_activity.h | 18 +
>>>>.../gpu/drm/xe/xe_guc_engine_activity_types.h | 89 +++++
>>>>drivers/gpu/drm/xe/xe_guc_fwif.h | 19 ++
>>>>drivers/gpu/drm/xe/xe_guc_types.h | 4 +
>>>>8 files changed, 451 insertions(+)
>>>>create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>>>create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.h
>>>>create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>>>>
>>>>diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>>>>index 328aff36831b..7e93461c60bd 100644
>>>>--- a/drivers/gpu/drm/xe/Makefile
>>>>+++ b/drivers/gpu/drm/xe/Makefile
>>>>@@ -33,6 +33,7 @@ xe-y += xe_bb.o \
>>>> xe_device_sysfs.o \
>>>> xe_dma_buf.o \
>>>> xe_drm_client.o \
>>>>+ xe_guc_engine_activity.o \
>>>> xe_exec.o \
>>>> xe_execlist.o \
>>>> xe_exec_queue.o \
>>>>diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>>>index fee385532fb0..ec516e838ee8 100644
>>>>--- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>>>+++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>>>@@ -140,6 +140,7 @@ enum xe_guc_action {
>>>> XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
>>>> XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
>>>> XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
>>>>+ XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
>>>> XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
>>>> XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
>>>> XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,
>>>>diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>>>index 096859072396..124cc398798e 100644
>>>>--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>>>+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>>>@@ -358,6 +358,8 @@
>>>>#define RENDER_AWAKE_STATUS REG_BIT(1)
>>>>#define MEDIA_SLICE0_AWAKE_STATUS REG_BIT(0)
>>>>
>>>>+#define MISC_STATUS_0 XE_REG(0xa500)
>>>>+
>>>>#define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4)
>>>>#define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4)
>>>>#define FORCEWAKE_GSC XE_REG(0xa618)
>>>>diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>>>new file mode 100644
>>>>index 000000000000..088209b9c228
>>>>--- /dev/null
>>>>+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>>>@@ -0,0 +1,317 @@
>>>>+// SPDX-License-Identifier: MIT
>>>>+/*
>>>>+ * Copyright © 2025 Intel Corporation
>>>>+ */
>>>>+#include "xe_guc_engine_activity.h"
>>>>+
>>>>+#include "abi/guc_actions_abi.h"
>>>>+#include "regs/xe_gt_regs.h"
>>>>+
>>>>+#include "xe_bo.h"
>>>>+#include "xe_force_wake.h"
>>>>+#include "xe_gt_printk.h"
>>>>+#include "xe_guc.h"
>>>>+#include "xe_guc_ct.h"
>>>>+#include "xe_hw_engine.h"
>>>>+#include "xe_map.h"
>>>>+#include "xe_mmio.h"
>>>>+
>>>>+#define TOTAL_QUANTA 0x8000
>>>>+
>>>>+static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_engine *hwe)
>>>>+{
>>>>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>>>+ struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>>>>+ u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>>>>+ size_t offset = 0;
>>>>+
>>>>+ offset = offsetof(struct guc_engine_activity_data,
>>>>+ engine_activity[guc_class][hwe->logical_instance]);
>>>>+
>>>>+ return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap, offset);
>>>>+}
>>>>+
>>>>+static struct iosys_map engine_metadata_map(struct xe_guc *guc)
>>>>+{
>>>>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>>>+ struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>>>>+
>>>>+ return buffer->metadata_bo->vmap;
>>>>+}
>>>>+
>>>>+static int allocate_engine_activity_group(struct xe_guc *guc)
>>>>+{
>>>>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>>>+ u32 num_activity_group = 1;
>>>>+
>>>>+ engine_activity->eag = kmalloc_array(num_activity_group,
>>>>+ sizeof(struct engine_activity_group),
>>>>+ GFP_KERNEL);
>>>>+
>>>>+ if (!engine_activity->eag)
>>>>+ return -ENOMEM;
>>>>+
>>>>+ memset(engine_activity->eag, 0, num_activity_group * sizeof(struct engine_activity_group));
>>>>+ engine_activity->num_activity_group = num_activity_group;
>>>>+
>>>>+ return 0;
>>>>+}
>>>>+
>>>>+static int allocate_engine_activity_buffers(struct xe_guc *guc,
>>>>+ struct engine_activity_buffer *buffer)
>>>>+{
>>>>+ u32 metadata_size = sizeof(struct guc_engine_activity_metadata);
>>>>+ u32 size = sizeof(struct guc_engine_activity_data);
>>>>+ struct xe_gt *gt = guc_to_gt(guc);
>>>>+ struct xe_tile *tile = gt_to_tile(gt);
>>>>+ struct xe_bo *bo, *metadata_bo;
>>>>+
>>>>+ metadata_bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(metadata_size),
>>>>+ XE_BO_FLAG_SYSTEM |
>>>>+ XE_BO_FLAG_GGTT |
>>>>+ XE_BO_FLAG_GGTT_INVALIDATE);
>>>>+ if (IS_ERR(metadata_bo))
>>>>+ return PTR_ERR(metadata_bo);
>>>>+
>>>>+ bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(size),
>>>>+ XE_BO_FLAG_VRAM_IF_DGFX(tile) |
>>>>+ XE_BO_FLAG_GGTT |
>>>>+ XE_BO_FLAG_GGTT_INVALIDATE);
>>>>+
>>>>+ if (IS_ERR(bo)) {
>>>>+ xe_bo_unpin_map_no_vm(metadata_bo);
>>>>+ return PTR_ERR(bo);
>>>>+ }
>>>>+
>>>>+ buffer->metadata_bo = metadata_bo;
>>>>+ buffer->activity_bo = bo;
>>>>+ return 0;
>>>>+}
>>>>+
>>>>+static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine *hwe)
>>>>+{
>>>>+ struct xe_guc *guc = &hwe->gt->uc.guc;
>>>>+ struct engine_activity_group *eag = &guc->engine_activity.eag[0];
>>>>+ u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>>>>+
>>>>+ return &eag->engine[guc_class][hwe->logical_instance];
>>>>+}
>>>>+
>>>>+static u64 cpu_ns_to_guc_tsc_tick(ktime_t ns, u32 freq)
>>>>+{
>>>>+ return mul_u64_u32_div(ns, freq, NSEC_PER_SEC);
>>>>+}
>>>>+
>>>>+#define read_engine_activity_record(xe_, map_, field_) \
>>>>+ xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity, field_)
>>>>+
>>>>+#define read_metadata_record(xe_, map_, field_) \
>>>>+ xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity_metadata, field_)
>>>>+
>>>>+static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>>>>+{
>>>>+ struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>>>>+ struct guc_engine_activity *cached_activity = &ea->activity;
>>>>+ struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>>>>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>>>+ struct iosys_map activity_map, metadata_map;
>>>>+ struct xe_device *xe = guc_to_xe(guc);
>>>>+ struct xe_gt *gt = guc_to_gt(guc);
>>>>+ u32 last_update_tick, global_change_num;
>>>>+ u64 active_ticks, gpm_ts;
>>>>+ u16 change_num;
>>>>+
>>>>+ activity_map = engine_activity_map(guc, hwe);
>>>>+ metadata_map = engine_metadata_map(guc);
>>>>+ global_change_num = read_metadata_record(xe, &metadata_map, global_change_num);
>>>>+
>>>>+ /* GuC has not initialized activity data yet, return 0 */
>>>>+ if (!global_change_num)
>>>>+ goto update;
>>>>+
>>>>+ if (global_change_num == cached_metadata->global_change_num)
>>>>+ goto update;
>>>>+ else
>>>>+ cached_metadata->global_change_num = global_change_num;
>>>>+
>>>>+ change_num = read_engine_activity_record(xe, &activity_map, change_num);
>>>>+
>>>>+ if (!change_num || change_num == cached_activity->change_num)
>>>>+ goto update;
>>>>+
>>>>+ /* read engine activity values */
>>>>+ last_update_tick = read_engine_activity_record(xe, &activity_map, last_update_tick);
>>>>+ active_ticks = read_engine_activity_record(xe, &activity_map, active_ticks);
>>>>+
>>>>+ /* activity calculations */
>>>>+ ea->running = !!last_update_tick;
>>>>+ ea->total += active_ticks - cached_activity->active_ticks;
>>>>+ ea->active = 0;
>>>>+
>>>>+ /* cache the counter */
>>>>+ cached_activity->change_num = change_num;
>>>>+ cached_activity->last_update_tick = last_update_tick;
>>>>+ cached_activity->active_ticks = active_ticks;
>>>>+
>>>>+update:
>>>>+ if (ea->running) {
>>>>+ gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
>>>>+ engine_activity->gpm_timestamp_shift;
>>>>+ ea->active = lower_32_bits(gpm_ts) - cached_activity->last_update_tick;
>>>>+ }
>>>>+
>>>>+ return ea->total + ea->active;
>>>>+}
>>>>+
>>>>+static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>>>>+{
>>>>+ struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>>>>+ struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>>>>+ struct guc_engine_activity *cached_activity = &ea->activity;
>>>>+ struct iosys_map activity_map, metadata_map;
>>>>+ struct xe_device *xe = guc_to_xe(guc);
>>>>+ ktime_t now, cpu_delta;
>>>>+ u64 numerator;
>>>>+ u16 quanta_ratio;
>>>>+
>>>>+ activity_map = engine_activity_map(guc, hwe);
>>>>+ metadata_map = engine_metadata_map(guc);
>>>>+
>>>>+ if (!cached_metadata->guc_tsc_frequency_hz)
>>>>+ cached_metadata->guc_tsc_frequency_hz = read_metadata_record(xe, &metadata_map,
>>>>+ guc_tsc_frequency_hz);
>>>>+
>>>>+ quanta_ratio = read_engine_activity_record(xe, &activity_map, quanta_ratio);
>>>>+ cached_activity->quanta_ratio = quanta_ratio;
>>>>+
>>>>+ /* Total ticks calculations */
>>>>+ now = ktime_get();
>>>>+ cpu_delta = now - ea->last_cpu_ts;
>>>>+ ea->last_cpu_ts = now;
>>>>+ numerator = (ea->quanta_remainder_ns + cpu_delta) * cached_activity->quanta_ratio;
>>>>+ ea->quanta_ns += numerator / TOTAL_QUANTA;
>>>>+ ea->quanta_remainder_ns = numerator % TOTAL_QUANTA;
>>>>+ ea->quanta = cpu_ns_to_guc_tsc_tick(ea->quanta_ns, cached_metadata->guc_tsc_frequency_hz);
>>>>+
>>>>+ return ea->quanta;
>>>>+}
>>>>+
>>>>+static int enable_engine_activity_stats(struct xe_guc *guc)
>>>>+{
>>>>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>>>+ struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>>>>+ u32 metadata_ggtt_addr = xe_bo_ggtt_addr(buffer->metadata_bo);
>>>>+ u32 ggtt_addr = xe_bo_ggtt_addr(buffer->activity_bo);
>>>>+ int len = 0;
>>>>+ u32 action[5];
>>>>+
>>>>+ action[len++] = XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER;
>>>>+ action[len++] = metadata_ggtt_addr;
>>>>+ action[len++] = 0;
>>>>+ action[len++] = ggtt_addr;
>>>>+ action[len++] = 0;
>>>>+
>>>>+ /* Blocking here to ensure the buffers are ready before reading them */
>>>>+ return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
>>>>+}
>>>>+
>>>>+static void engine_activity_set_cpu_ts(struct xe_guc *guc)
>>>>+{
>>>>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>>>+ struct engine_activity_group *eag = &engine_activity->eag[0];
>>>>+ int i, j;
>>>>+
>>>>+ for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)
>>>>+ for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; j++)
>>>>+ eag->engine[i][j].last_cpu_ts = ktime_get();
>>>>+}
>>>>+
>>>>+static u32 gpm_timestamp_shift(struct xe_gt *gt)
>>>>+{
>>>>+ u32 reg;
>>>>+
>>>>+ reg = xe_mmio_read32(>->mmio, RPM_CONFIG0);
>>>>+
>>>>+ return 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
>>>>+}
>>>>+
>>>>+/**
>>>>+ * xe_guc_engine_activity_active_ticks - Get engine active ticks
>>>>+ * @hwe: The hw_engine object
>>>>+ *
>>>>+ * Return: accumulated ticks @hwe was active since engine activity stats were enabled.
>>>>+ */
>>>>+u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe)
>>>>+{
>>>>+ struct xe_guc *guc = &hwe->gt->uc.guc;
>>>>+
>>>>+ return get_engine_active_ticks(guc, hwe);
>>>>+}
>>>>+
>>>>+/**
>>>>+ * xe_guc_engine_activity_total_ticks - Get engine total ticks
>>>>+ * @hwe: The hw_engine object
>>>>+ *
>>>>+ * Return: accumulated quanta of ticks allocated for the engine
>>>>+ */
>>>>+u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe)
>>>>+{
>>>>+ struct xe_guc *guc = &hwe->gt->uc.guc;
>>>>+
>>>>+ return get_engine_total_ticks(guc, hwe);
>>>>+}
>>>>+
>>>>+/**
>>>>+ * xe_guc_engine_activity_enable_stats - Enable engine activity stats
>>>>+ * @guc: The GuC object
>>>>+ *
>>>>+ * Enable engine activity stats and set initial timestamps
>>>>+ */
>>>>+void xe_guc_engine_activity_enable_stats(struct xe_guc *guc)
>>>>+{
>>>>+ int ret;
>>>>+
>>>>+ ret = enable_engine_activity_stats(guc);
>>>>+ if (ret)
>>>>+ xe_gt_err(guc_to_gt(guc), "failed to enable activity stats%d\n", ret);
>>>>+ else
>>>>+ engine_activity_set_cpu_ts(guc);
>>>>+}
>>>>+
>>>>+static void engine_activity_fini(void *arg)
>>>>+{
>>>>+ struct xe_guc_engine_activity *engine_activity = arg;
>>>>+
>>>>+ kfree(engine_activity->eag);
>>>>+}
>>>>+
>>>>+/**
>>>>+ * xe_guc_engine_activity_init - Initialize the engine activity data
>>>>+ * @guc: The GuC object
>>>>+ *
>>>>+ * Return: 0 on success, negative error code otherwise.
>>>>+ */
>>>>+int xe_guc_engine_activity_init(struct xe_guc *guc)
>>>>+{
>>>>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>>>+ struct xe_gt *gt = guc_to_gt(guc);
>>>>+ int ret;
>>>>+
>>>>+ ret = allocate_engine_activity_group(guc);
>>>>+ if (ret) {
>>>>+ xe_gt_err(gt, "failed to allocate activity group %d\n", ret);
>>>>+ return ret;
>>>>+ }
>>>>+
>>>>+ ret = allocate_engine_activity_buffers(guc, &engine_activity->device_buffer);
>>>>+ if (ret) {
>>>>+ xe_gt_err(gt, "failed to allocate activity buffers%d\n", ret);
>>>>+ kfree(engine_activity->eag);
>>>>+ return ret;
>>>>+ }
>>>>+
>>>>+ engine_activity->gpm_timestamp_shift = gpm_timestamp_shift(gt);
>>>>+
>>>>+ return devm_add_action_or_reset(gt_to_xe(gt)->drm.dev, engine_activity_fini,
>>>>+ engine_activity);
>>>>+}
>>>>diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.h b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>>>>new file mode 100644
>>>>index 000000000000..c00f3da5513d
>>>>--- /dev/null
>>>>+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>>>>@@ -0,0 +1,18 @@
>>>>+/* SPDX-License-Identifier: MIT */
>>>>+/*
>>>>+ * Copyright © 2025 Intel Corporation
>>>>+ */
>>>>+
>>>>+#ifndef _XE_GUC_ENGINE_ACTIVITY_H_
>>>>+#define _XE_GUC_ENGINE_ACTIVITY_H_
>>>>+
>>>>+#include <linux/types.h>
>>>>+
>>>>+struct xe_hw_engine;
>>>>+struct xe_guc;
>>>>+
>>>>+int xe_guc_engine_activity_init(struct xe_guc *guc);
>>>>+void xe_guc_engine_activity_enable_stats(struct xe_guc *guc);
>>>>+u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe);
>>>>+u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe);
>>>>+#endif
>>>>diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>>>>new file mode 100644
>>>>index 000000000000..a2ab327d3eec
>>>>--- /dev/null
>>>>+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>>>>@@ -0,0 +1,89 @@
>>>>+/* SPDX-License-Identifier: MIT */
>>>>+/*
>>>>+ * Copyright © 2025 Intel Corporation
>>>>+ */
>>>>+
>>>>+#ifndef _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>>>>+#define _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>>>>+
>>>>+#include <linux/types.h>
>>>>+
>>>>+#include "xe_guc_fwif.h"
>>>>+/**
>>>>+ * struct engine_activity - Engine specific activity data
>>>>+ *
>>>>+ * Contains engine specific activity data and snapshot of the
>>>>+ * structures from GuC
>>>>+ */
>>>>+struct engine_activity {
>>>>+ /** @active: current activity */
>>>>+ u64 active;
>>>>+
>>>>+ /** @last_cpu_ts: cpu timestamp in nsec of previous sample */
>>>>+ u64 last_cpu_ts;
>>>>+
>>>>+ /** @quanta: total quanta used on HW */
>>>>+ u64 quanta;
>>>>+
>>>>+ /** @quanta_ns: total quanta_ns used on HW */
>>>>+ u64 quanta_ns;
>>>>+
>>>>+ /**
>>>>+ * @quanta_remainder_ns: remainder when the CPU time is scaled as
>>>>+ * per the quanta_ratio. This remainder is used in subsequent
>>>>+ * quanta calculations.
>>>>+ */
>>>>+ u64 quanta_remainder_ns;
>>>>+
>>>>+ /** @total: total engine activity */
>>>>+ u64 total;
>>>>+
>>>>+ /** @running: true if engine is running some work */
>>>>+ bool running;
>>>>+
>>>>+ /** @metadata: snapshot of engine activity metadata */
>>>>+ struct guc_engine_activity_metadata metadata;
>>>>+
>>>>+ /** @activity: snapshot of engine activity counter */
>>>>+ struct guc_engine_activity activity;
>>>>+};
>>>>+
>>>>+/**
>>>>+ * struct engine_activity_group - Activity data for all engines
>>>>+ */
>>>>+struct engine_activity_group {
>>>>+ /** @engine: engine specific activity data */
>>>>+ struct engine_activity engine[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>>>>+};
>>>>+
>>>>+/**
>>>>+ * struct engine_activity_buffer - engine activity buffers
>>>>+ *
>>>>+ * This contains the buffers allocated for metadata and activity data
>>>>+ */
>>>>+struct engine_activity_buffer {
>>>>+ /** @activity_bo: object allocated to hold activity data */
>>>>+ struct xe_bo *activity_bo;
>>>>+
>>>>+ /** @metadata_bo: object allocated to hold activity metadata */
>>>>+ struct xe_bo *metadata_bo;
>>>>+};
>>>>+
>>>>+/**
>>>>+ * struct xe_guc_engine_activity - Data used by engine activity implementation
>>>>+ */
>>>>+struct xe_guc_engine_activity {
>>>>+ /** @gpm_timestamp_shift: Right shift value for the gpm timestamp */
>>>>+ u32 gpm_timestamp_shift;
>>>>+
>>>>+ /** @num_activity_group: number of activity groups */
>>>>+ u32 num_activity_group;
>>>>+
>>>>+ /** @eag: holds the device level engine activity data */
>>>>+ struct engine_activity_group *eag;
>>>>+
>>>>+ /** @device_buffer: buffer object for global engine activity */
>>>>+ struct engine_activity_buffer device_buffer;
>>>>+};
>>>>+#endif
>>>>+
>>>>diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
>>>>index 057153f89b30..6f57578b07cb 100644
>>>>--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
>>>>+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
>>>>@@ -208,6 +208,25 @@ struct guc_engine_usage {
>>>> struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>>>>} __packed;
>>>>
>>>>+/* Engine Activity stats */
>>>>+struct guc_engine_activity {
>>>>+ u16 change_num;
>>>>+ u16 quanta_ratio;
>>>>+ u32 last_update_tick;
>>>>+ u64 active_ticks;
>>>>+} __packed;
>>>>+
>>>>+struct guc_engine_activity_data {
>>>>+ struct guc_engine_activity engine_activity[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>>>>+} __packed;
>>>>+
>>>>+struct guc_engine_activity_metadata {
>>>>+ u32 guc_tsc_frequency_hz;
>>>>+ u32 lag_latency_usec;
>>>>+ u32 global_change_num;
>>>>+ u32 reserved;
>>>>+} __packed;
>>>>+
>>>>/* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
>>>>enum xe_guc_recv_message {
>>>> XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
>>>>diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h
>>>>index 573aa6308380..63bac64429a5 100644
>>>>--- a/drivers/gpu/drm/xe/xe_guc_types.h
>>>>+++ b/drivers/gpu/drm/xe/xe_guc_types.h
>>>>@@ -13,6 +13,7 @@
>>>>#include "xe_guc_ads_types.h"
>>>>#include "xe_guc_buf_types.h"
>>>>#include "xe_guc_ct_types.h"
>>>>+#include "xe_guc_engine_activity_types.h"
>>>>#include "xe_guc_fwif.h"
>>>>#include "xe_guc_log_types.h"
>>>>#include "xe_guc_pc_types.h"
>>>>@@ -103,6 +104,9 @@ struct xe_guc {
>>>> /** @relay: GuC Relay Communication used in SR-IOV */
>>>> struct xe_guc_relay relay;
>>>>
>>>>+ /** @engine_activity: Device specific engine activity */
>>>>+ struct xe_guc_engine_activity engine_activity;
>>>>+
>>>> /**
>>>> * @notify_reg: Register which is written to notify GuC of H2G messages
>>>> */
>>>>--
>>>>2.47.1
>>>>
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v4 1/8] drm/xe: Add per-engine-class activity support
2025-01-30 2:35 ` Rodrigo Vivi
2025-01-30 4:49 ` Riana Tauro
@ 2025-01-30 17:52 ` Umesh Nerlige Ramappa
2025-01-30 20:47 ` Lucas De Marchi
2 siblings, 0 replies; 45+ messages in thread
From: Umesh Nerlige Ramappa @ 2025-01-30 17:52 UTC (permalink / raw)
To: Rodrigo Vivi
Cc: Riana Tauro, intel-xe, anshuman.gupta, lucas.demarchi,
vinay.belgaumkar, soham.purkait, Himal Prasad Ghimiray
On Wed, Jan 29, 2025 at 09:35:45PM -0500, Rodrigo Vivi wrote:
>On Wed, Jan 29, 2025 at 04:28:36PM -0800, Umesh Nerlige Ramappa wrote:
>> On Wed, Jan 29, 2025 at 03:46:44PM +0530, Riana Tauro wrote:
>> > GuC provides support to read engine counters to calculate the
>> > engine activity. KMD exposes two counters via the PMU interface to
>> > calculate engine activity
>> >
>> > Engine Active Ticks(engine-active-ticks) - number of active ticks for engine
>> > Engine Total Ticks (engine-total-ticks) - total ticks of engine
>> >
>> > Engine activity percentage can be calculated as below
>> > Engine activity % = (engine active ticks/engine total ticks) * 100.
>> >
>> > v2: fix cosmetic review comments
>> > add forcewake for gpm_ts (Umesh)
>> >
>> > v3: fix CI hooks error
>> > change function parameters and unpin bo on error
>> > of allocate_activity_buffers
>> > fix kernel-doc (Umesh)
>> > use engine activity (Umesh, Lucas)
>> > rename xe_engine_activity to xe_guc_engine_*
>> > fix commit message to use per-engine class(Lucas)
>> >
>> > v4: remove forcewake as engine is already running
>> > when reading gpm timestamp
>>
>> + Rodrigo
>>
>> Sorry, I think I mentioned offline that the runtime pm get is sufficient for
>> reading this register, but it's not. It does need a forcewake of the GT
>> domain. At the same time, we cannot use the xe_force_wake_get because of
>> the lockdep issue you mentioned and also I assume that xe_force_wake_get may
>> sleep and the event may be read from irq context.
>
>I don't understand this statement entirely. force wake get cannot sleep.
>It is based on spin locks. It should not be issuing any lockdep here.
>It is quite simple flow with minimal or none interdependency. Remember
>that in i915 for instance it exists and lives in the middle of every
>mmio read and write call...
Ok, I think I am confusing with the runtime pm get in terms of sleeping.
I see that the forcewake is just using spinlocks.
Thanks for clarifying.
Umesh
>
>>
>> I would check if we can add a helper xe_force_wake_get_if_active() and just
>> use that to bump up the wakeref.
>
>I would prefer to not complicate things...
>
>>
>> @Rodrigo, @Vinay Any thoughts on this ^ ?
>
>Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>
>>
>> Thanks,
>> Umesh
>>
>> >
>> > Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> > Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> > ---
>> > drivers/gpu/drm/xe/Makefile | 1 +
>> > drivers/gpu/drm/xe/abi/guc_actions_abi.h | 1 +
>> > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
>> > drivers/gpu/drm/xe/xe_guc_engine_activity.c | 317 ++++++++++++++++++
>> > drivers/gpu/drm/xe/xe_guc_engine_activity.h | 18 +
>> > .../gpu/drm/xe/xe_guc_engine_activity_types.h | 89 +++++
>> > drivers/gpu/drm/xe/xe_guc_fwif.h | 19 ++
>> > drivers/gpu/drm/xe/xe_guc_types.h | 4 +
>> > 8 files changed, 451 insertions(+)
>> > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.c
>> > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.h
>> > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>> >
>> > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> > index 328aff36831b..7e93461c60bd 100644
>> > --- a/drivers/gpu/drm/xe/Makefile
>> > +++ b/drivers/gpu/drm/xe/Makefile
>> > @@ -33,6 +33,7 @@ xe-y += xe_bb.o \
>> > xe_device_sysfs.o \
>> > xe_dma_buf.o \
>> > xe_drm_client.o \
>> > + xe_guc_engine_activity.o \
>> > xe_exec.o \
>> > xe_execlist.o \
>> > xe_exec_queue.o \
>> > diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>> > index fee385532fb0..ec516e838ee8 100644
>> > --- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>> > +++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>> > @@ -140,6 +140,7 @@ enum xe_guc_action {
>> > XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
>> > XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
>> > XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
>> > + XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
>> > XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
>> > XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
>> > XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,
>> > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > index 096859072396..124cc398798e 100644
>> > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > @@ -358,6 +358,8 @@
>> > #define RENDER_AWAKE_STATUS REG_BIT(1)
>> > #define MEDIA_SLICE0_AWAKE_STATUS REG_BIT(0)
>> >
>> > +#define MISC_STATUS_0 XE_REG(0xa500)
>> > +
>> > #define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4)
>> > #define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4)
>> > #define FORCEWAKE_GSC XE_REG(0xa618)
>> > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>> > new file mode 100644
>> > index 000000000000..088209b9c228
>> > --- /dev/null
>> > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>> > @@ -0,0 +1,317 @@
>> > +// SPDX-License-Identifier: MIT
>> > +/*
>> > + * Copyright © 2025 Intel Corporation
>> > + */
>> > +#include "xe_guc_engine_activity.h"
>> > +
>> > +#include "abi/guc_actions_abi.h"
>> > +#include "regs/xe_gt_regs.h"
>> > +
>> > +#include "xe_bo.h"
>> > +#include "xe_force_wake.h"
>> > +#include "xe_gt_printk.h"
>> > +#include "xe_guc.h"
>> > +#include "xe_guc_ct.h"
>> > +#include "xe_hw_engine.h"
>> > +#include "xe_map.h"
>> > +#include "xe_mmio.h"
>> > +
>> > +#define TOTAL_QUANTA 0x8000
>> > +
>> > +static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_engine *hwe)
>> > +{
>> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>> > + u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>> > + size_t offset = 0;
>> > +
>> > + offset = offsetof(struct guc_engine_activity_data,
>> > + engine_activity[guc_class][hwe->logical_instance]);
>> > +
>> > + return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap, offset);
>> > +}
>> > +
>> > +static struct iosys_map engine_metadata_map(struct xe_guc *guc)
>> > +{
>> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>> > +
>> > + return buffer->metadata_bo->vmap;
>> > +}
>> > +
>> > +static int allocate_engine_activity_group(struct xe_guc *guc)
>> > +{
>> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > + u32 num_activity_group = 1;
>> > +
>> > + engine_activity->eag = kmalloc_array(num_activity_group,
>> > + sizeof(struct engine_activity_group),
>> > + GFP_KERNEL);
>> > +
>> > + if (!engine_activity->eag)
>> > + return -ENOMEM;
>> > +
>> > + memset(engine_activity->eag, 0, num_activity_group * sizeof(struct engine_activity_group));
>> > + engine_activity->num_activity_group = num_activity_group;
>> > +
>> > + return 0;
>> > +}
>> > +
>> > +static int allocate_engine_activity_buffers(struct xe_guc *guc,
>> > + struct engine_activity_buffer *buffer)
>> > +{
>> > + u32 metadata_size = sizeof(struct guc_engine_activity_metadata);
>> > + u32 size = sizeof(struct guc_engine_activity_data);
>> > + struct xe_gt *gt = guc_to_gt(guc);
>> > + struct xe_tile *tile = gt_to_tile(gt);
>> > + struct xe_bo *bo, *metadata_bo;
>> > +
>> > + metadata_bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(metadata_size),
>> > + XE_BO_FLAG_SYSTEM |
>> > + XE_BO_FLAG_GGTT |
>> > + XE_BO_FLAG_GGTT_INVALIDATE);
>> > + if (IS_ERR(metadata_bo))
>> > + return PTR_ERR(metadata_bo);
>> > +
>> > + bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(size),
>> > + XE_BO_FLAG_VRAM_IF_DGFX(tile) |
>> > + XE_BO_FLAG_GGTT |
>> > + XE_BO_FLAG_GGTT_INVALIDATE);
>> > +
>> > + if (IS_ERR(bo)) {
>> > + xe_bo_unpin_map_no_vm(metadata_bo);
>> > + return PTR_ERR(bo);
>> > + }
>> > +
>> > + buffer->metadata_bo = metadata_bo;
>> > + buffer->activity_bo = bo;
>> > + return 0;
>> > +}
>> > +
>> > +static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine *hwe)
>> > +{
>> > + struct xe_guc *guc = &hwe->gt->uc.guc;
>> > + struct engine_activity_group *eag = &guc->engine_activity.eag[0];
>> > + u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>> > +
>> > + return &eag->engine[guc_class][hwe->logical_instance];
>> > +}
>> > +
>> > +static u64 cpu_ns_to_guc_tsc_tick(ktime_t ns, u32 freq)
>> > +{
>> > + return mul_u64_u32_div(ns, freq, NSEC_PER_SEC);
>> > +}
>> > +
>> > +#define read_engine_activity_record(xe_, map_, field_) \
>> > + xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity, field_)
>> > +
>> > +#define read_metadata_record(xe_, map_, field_) \
>> > + xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity_metadata, field_)
>> > +
>> > +static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>> > +{
>> > + struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>> > + struct guc_engine_activity *cached_activity = &ea->activity;
>> > + struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > + struct iosys_map activity_map, metadata_map;
>> > + struct xe_device *xe = guc_to_xe(guc);
>> > + struct xe_gt *gt = guc_to_gt(guc);
>> > + u32 last_update_tick, global_change_num;
>> > + u64 active_ticks, gpm_ts;
>> > + u16 change_num;
>> > +
>> > + activity_map = engine_activity_map(guc, hwe);
>> > + metadata_map = engine_metadata_map(guc);
>> > + global_change_num = read_metadata_record(xe, &metadata_map, global_change_num);
>> > +
>> > + /* GuC has not initialized activity data yet, return 0 */
>> > + if (!global_change_num)
>> > + goto update;
>> > +
>> > + if (global_change_num == cached_metadata->global_change_num)
>> > + goto update;
>> > + else
>> > + cached_metadata->global_change_num = global_change_num;
>> > +
>> > + change_num = read_engine_activity_record(xe, &activity_map, change_num);
>> > +
>> > + if (!change_num || change_num == cached_activity->change_num)
>> > + goto update;
>> > +
>> > + /* read engine activity values */
>> > + last_update_tick = read_engine_activity_record(xe, &activity_map, last_update_tick);
>> > + active_ticks = read_engine_activity_record(xe, &activity_map, active_ticks);
>> > +
>> > + /* activity calculations */
>> > + ea->running = !!last_update_tick;
>> > + ea->total += active_ticks - cached_activity->active_ticks;
>> > + ea->active = 0;
>> > +
>> > + /* cache the counter */
>> > + cached_activity->change_num = change_num;
>> > + cached_activity->last_update_tick = last_update_tick;
>> > + cached_activity->active_ticks = active_ticks;
>> > +
>> > +update:
>> > + if (ea->running) {
>> > + gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
>> > + engine_activity->gpm_timestamp_shift;
>> > + ea->active = lower_32_bits(gpm_ts) - cached_activity->last_update_tick;
>> > + }
>> > +
>> > + return ea->total + ea->active;
>> > +}
>> > +
>> > +static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>> > +{
>> > + struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>> > + struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>> > + struct guc_engine_activity *cached_activity = &ea->activity;
>> > + struct iosys_map activity_map, metadata_map;
>> > + struct xe_device *xe = guc_to_xe(guc);
>> > + ktime_t now, cpu_delta;
>> > + u64 numerator;
>> > + u16 quanta_ratio;
>> > +
>> > + activity_map = engine_activity_map(guc, hwe);
>> > + metadata_map = engine_metadata_map(guc);
>> > +
>> > + if (!cached_metadata->guc_tsc_frequency_hz)
>> > + cached_metadata->guc_tsc_frequency_hz = read_metadata_record(xe, &metadata_map,
>> > + guc_tsc_frequency_hz);
>> > +
>> > + quanta_ratio = read_engine_activity_record(xe, &activity_map, quanta_ratio);
>> > + cached_activity->quanta_ratio = quanta_ratio;
>> > +
>> > + /* Total ticks calculations */
>> > + now = ktime_get();
>> > + cpu_delta = now - ea->last_cpu_ts;
>> > + ea->last_cpu_ts = now;
>> > + numerator = (ea->quanta_remainder_ns + cpu_delta) * cached_activity->quanta_ratio;
>> > + ea->quanta_ns += numerator / TOTAL_QUANTA;
>> > + ea->quanta_remainder_ns = numerator % TOTAL_QUANTA;
>> > + ea->quanta = cpu_ns_to_guc_tsc_tick(ea->quanta_ns, cached_metadata->guc_tsc_frequency_hz);
>> > +
>> > + return ea->quanta;
>> > +}
>> > +
>> > +static int enable_engine_activity_stats(struct xe_guc *guc)
>> > +{
>> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>> > + u32 metadata_ggtt_addr = xe_bo_ggtt_addr(buffer->metadata_bo);
>> > + u32 ggtt_addr = xe_bo_ggtt_addr(buffer->activity_bo);
>> > + int len = 0;
>> > + u32 action[5];
>> > +
>> > + action[len++] = XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER;
>> > + action[len++] = metadata_ggtt_addr;
>> > + action[len++] = 0;
>> > + action[len++] = ggtt_addr;
>> > + action[len++] = 0;
>> > +
>> > + /* Blocking here to ensure the buffers are ready before reading them */
>> > + return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
>> > +}
>> > +
>> > +static void engine_activity_set_cpu_ts(struct xe_guc *guc)
>> > +{
>> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > + struct engine_activity_group *eag = &engine_activity->eag[0];
>> > + int i, j;
>> > +
>> > + for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)
>> > + for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; j++)
>> > + eag->engine[i][j].last_cpu_ts = ktime_get();
>> > +}
>> > +
>> > +static u32 gpm_timestamp_shift(struct xe_gt *gt)
>> > +{
>> > + u32 reg;
>> > +
>> > + reg = xe_mmio_read32(>->mmio, RPM_CONFIG0);
>> > +
>> > + return 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
>> > +}
>> > +
>> > +/**
>> > + * xe_guc_engine_activity_active_ticks - Get engine active ticks
>> > + * @hwe: The hw_engine object
>> > + *
>> > + * Return: accumulated ticks @hwe was active since engine activity stats were enabled.
>> > + */
>> > +u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe)
>> > +{
>> > + struct xe_guc *guc = &hwe->gt->uc.guc;
>> > +
>> > + return get_engine_active_ticks(guc, hwe);
>> > +}
>> > +
>> > +/**
>> > + * xe_guc_engine_activity_total_ticks - Get engine total ticks
>> > + * @hwe: The hw_engine object
>> > + *
>> > + * Return: accumulated quanta of ticks allocated for the engine
>> > + */
>> > +u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe)
>> > +{
>> > + struct xe_guc *guc = &hwe->gt->uc.guc;
>> > +
>> > + return get_engine_total_ticks(guc, hwe);
>> > +}
>> > +
>> > +/**
>> > + * xe_guc_engine_activity_enable_stats - Enable engine activity stats
>> > + * @guc: The GuC object
>> > + *
>> > + * Enable engine activity stats and set initial timestamps
>> > + */
>> > +void xe_guc_engine_activity_enable_stats(struct xe_guc *guc)
>> > +{
>> > + int ret;
>> > +
>> > + ret = enable_engine_activity_stats(guc);
>> > + if (ret)
>> > + xe_gt_err(guc_to_gt(guc), "failed to enable activity stats%d\n", ret);
>> > + else
>> > + engine_activity_set_cpu_ts(guc);
>> > +}
>> > +
>> > +static void engine_activity_fini(void *arg)
>> > +{
>> > + struct xe_guc_engine_activity *engine_activity = arg;
>> > +
>> > + kfree(engine_activity->eag);
>> > +}
>> > +
>> > +/**
>> > + * xe_guc_engine_activity_init - Initialize the engine activity data
>> > + * @guc: The GuC object
>> > + *
>> > + * Return: 0 on success, negative error code otherwise.
>> > + */
>> > +int xe_guc_engine_activity_init(struct xe_guc *guc)
>> > +{
>> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > + struct xe_gt *gt = guc_to_gt(guc);
>> > + int ret;
>> > +
>> > + ret = allocate_engine_activity_group(guc);
>> > + if (ret) {
>> > + xe_gt_err(gt, "failed to allocate activity group %d\n", ret);
>> > + return ret;
>> > + }
>> > +
>> > + ret = allocate_engine_activity_buffers(guc, &engine_activity->device_buffer);
>> > + if (ret) {
>> > + xe_gt_err(gt, "failed to allocate activity buffers%d\n", ret);
>> > + kfree(engine_activity->eag);
>> > + return ret;
>> > + }
>> > +
>> > + engine_activity->gpm_timestamp_shift = gpm_timestamp_shift(gt);
>> > +
>> > + return devm_add_action_or_reset(gt_to_xe(gt)->drm.dev, engine_activity_fini,
>> > + engine_activity);
>> > +}
>> > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.h b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>> > new file mode 100644
>> > index 000000000000..c00f3da5513d
>> > --- /dev/null
>> > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>> > @@ -0,0 +1,18 @@
>> > +/* SPDX-License-Identifier: MIT */
>> > +/*
>> > + * Copyright © 2025 Intel Corporation
>> > + */
>> > +
>> > +#ifndef _XE_GUC_ENGINE_ACTIVITY_H_
>> > +#define _XE_GUC_ENGINE_ACTIVITY_H_
>> > +
>> > +#include <linux/types.h>
>> > +
>> > +struct xe_hw_engine;
>> > +struct xe_guc;
>> > +
>> > +int xe_guc_engine_activity_init(struct xe_guc *guc);
>> > +void xe_guc_engine_activity_enable_stats(struct xe_guc *guc);
>> > +u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe);
>> > +u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe);
>> > +#endif
>> > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>> > new file mode 100644
>> > index 000000000000..a2ab327d3eec
>> > --- /dev/null
>> > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>> > @@ -0,0 +1,89 @@
>> > +/* SPDX-License-Identifier: MIT */
>> > +/*
>> > + * Copyright © 2025 Intel Corporation
>> > + */
>> > +
>> > +#ifndef _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>> > +#define _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>> > +
>> > +#include <linux/types.h>
>> > +
>> > +#include "xe_guc_fwif.h"
>> > +/**
>> > + * struct engine_activity - Engine specific activity data
>> > + *
>> > + * Contains engine specific activity data and snapshot of the
>> > + * structures from GuC
>> > + */
>> > +struct engine_activity {
>> > + /** @active: current activity */
>> > + u64 active;
>> > +
>> > + /** @last_cpu_ts: cpu timestamp in nsec of previous sample */
>> > + u64 last_cpu_ts;
>> > +
>> > + /** @quanta: total quanta used on HW */
>> > + u64 quanta;
>> > +
>> > + /** @quanta_ns: total quanta_ns used on HW */
>> > + u64 quanta_ns;
>> > +
>> > + /**
>> > + * @quanta_remainder_ns: remainder when the CPU time is scaled as
>> > + * per the quanta_ratio. This remainder is used in subsequent
>> > + * quanta calculations.
>> > + */
>> > + u64 quanta_remainder_ns;
>> > +
>> > + /** @total: total engine activity */
>> > + u64 total;
>> > +
>> > + /** @running: true if engine is running some work */
>> > + bool running;
>> > +
>> > + /** @metadata: snapshot of engine activity metadata */
>> > + struct guc_engine_activity_metadata metadata;
>> > +
>> > + /** @activity: snapshot of engine activity counter */
>> > + struct guc_engine_activity activity;
>> > +};
>> > +
>> > +/**
>> > + * struct engine_activity_group - Activity data for all engines
>> > + */
>> > +struct engine_activity_group {
>> > + /** @engine: engine specific activity data */
>> > + struct engine_activity engine[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>> > +};
>> > +
>> > +/**
>> > + * struct engine_activity_buffer - engine activity buffers
>> > + *
>> > + * This contains the buffers allocated for metadata and activity data
>> > + */
>> > +struct engine_activity_buffer {
>> > + /** @activity_bo: object allocated to hold activity data */
>> > + struct xe_bo *activity_bo;
>> > +
>> > + /** @metadata_bo: object allocated to hold activity metadata */
>> > + struct xe_bo *metadata_bo;
>> > +};
>> > +
>> > +/**
>> > + * struct xe_guc_engine_activity - Data used by engine activity implementation
>> > + */
>> > +struct xe_guc_engine_activity {
>> > + /** @gpm_timestamp_shift: Right shift value for the gpm timestamp */
>> > + u32 gpm_timestamp_shift;
>> > +
>> > + /** @num_activity_group: number of activity groups */
>> > + u32 num_activity_group;
>> > +
>> > + /** @eag: holds the device level engine activity data */
>> > + struct engine_activity_group *eag;
>> > +
>> > + /** @device_buffer: buffer object for global engine activity */
>> > + struct engine_activity_buffer device_buffer;
>> > +};
>> > +#endif
>> > +
>> > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
>> > index 057153f89b30..6f57578b07cb 100644
>> > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
>> > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
>> > @@ -208,6 +208,25 @@ struct guc_engine_usage {
>> > struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>> > } __packed;
>> >
>> > +/* Engine Activity stats */
>> > +struct guc_engine_activity {
>> > + u16 change_num;
>> > + u16 quanta_ratio;
>> > + u32 last_update_tick;
>> > + u64 active_ticks;
>> > +} __packed;
>> > +
>> > +struct guc_engine_activity_data {
>> > + struct guc_engine_activity engine_activity[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>> > +} __packed;
>> > +
>> > +struct guc_engine_activity_metadata {
>> > + u32 guc_tsc_frequency_hz;
>> > + u32 lag_latency_usec;
>> > + u32 global_change_num;
>> > + u32 reserved;
>> > +} __packed;
>> > +
>> > /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
>> > enum xe_guc_recv_message {
>> > XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
>> > diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h
>> > index 573aa6308380..63bac64429a5 100644
>> > --- a/drivers/gpu/drm/xe/xe_guc_types.h
>> > +++ b/drivers/gpu/drm/xe/xe_guc_types.h
>> > @@ -13,6 +13,7 @@
>> > #include "xe_guc_ads_types.h"
>> > #include "xe_guc_buf_types.h"
>> > #include "xe_guc_ct_types.h"
>> > +#include "xe_guc_engine_activity_types.h"
>> > #include "xe_guc_fwif.h"
>> > #include "xe_guc_log_types.h"
>> > #include "xe_guc_pc_types.h"
>> > @@ -103,6 +104,9 @@ struct xe_guc {
>> > /** @relay: GuC Relay Communication used in SR-IOV */
>> > struct xe_guc_relay relay;
>> >
>> > + /** @engine_activity: Device specific engine activity */
>> > + struct xe_guc_engine_activity engine_activity;
>> > +
>> > /**
>> > * @notify_reg: Register which is written to notify GuC of H2G messages
>> > */
>> > --
>> > 2.47.1
>> >
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 1/8] drm/xe: Add per-engine-class activity support
2025-01-30 2:35 ` Rodrigo Vivi
2025-01-30 4:49 ` Riana Tauro
2025-01-30 17:52 ` Umesh Nerlige Ramappa
@ 2025-01-30 20:47 ` Lucas De Marchi
2 siblings, 0 replies; 45+ messages in thread
From: Lucas De Marchi @ 2025-01-30 20:47 UTC (permalink / raw)
To: Rodrigo Vivi
Cc: Umesh Nerlige Ramappa, Riana Tauro, intel-xe, anshuman.gupta,
vinay.belgaumkar, soham.purkait, Himal Prasad Ghimiray
On Wed, Jan 29, 2025 at 09:35:45PM -0500, Rodrigo Vivi wrote:
>On Wed, Jan 29, 2025 at 04:28:36PM -0800, Umesh Nerlige Ramappa wrote:
>> On Wed, Jan 29, 2025 at 03:46:44PM +0530, Riana Tauro wrote:
>> > GuC provides support to read engine counters to calculate the
>> > engine activity. KMD exposes two counters via the PMU interface to
>> > calculate engine activity
>> >
>> > Engine Active Ticks(engine-active-ticks) - number of active ticks for engine
>> > Engine Total Ticks (engine-total-ticks) - total ticks of engine
>> >
>> > Engine activity percentage can be calculated as below
>> > Engine activity % = (engine active ticks/engine total ticks) * 100.
>> >
>> > v2: fix cosmetic review comments
>> > add forcewake for gpm_ts (Umesh)
>> >
>> > v3: fix CI hooks error
>> > change function parameters and unpin bo on error
>> > of allocate_activity_buffers
>> > fix kernel-doc (Umesh)
>> > use engine activity (Umesh, Lucas)
>> > rename xe_engine_activity to xe_guc_engine_*
>> > fix commit message to use per-engine class(Lucas)
>> >
>> > v4: remove forcewake as engine is already running
>> > when reading gpm timestamp
>>
>> + Rodrigo
>>
>> Sorry, I think I mentioned offline that the runtime pm get is sufficient for
>> reading this register, but it's not. It does need a forcewake of the GT
>> domain. At the same time, we cannot use the xe_force_wake_get because of
>> the lockdep issue you mentioned and also I assume that xe_force_wake_get may
>> sleep and the event may be read from irq context.
>
>I don't understand this statement entirely. force wake get cannot sleep.
>It is based on spin locks. It should not be issuing any lockdep here.
in the read call, perf is holding a raw_spinlock. You can't take a spinlock
when you hold a raw_spinlock, so you can't even check if you need a force wake.
In a RT kernel, spinlock may sleep, raw_spinlock may not.
We are only not getting splats on drm-tip because the pmu in i915 got
the locks wrong and the temporary solution starting from 6.13 was to
shoot the messenger:
177ab7c0296b ("Revert "lockdep: Enable PROVE_RAW_LOCK_NESTING with PROVE_LOCKING."")
I'm starting to think it's better to remove that patch and disabling
perf_pmu CI for i915. Becauses we almost did the same mistake in xe
since CI is not covering that. I started to fix i915 a few weeks ago,
but then got side tracked with other things... I may return to that
soon.
>It is quite simple flow with minimal or none interdependency. Remember
>that in i915 for instance it exists and lives in the middle of every
>mmio read and write call...
and it's wrong
>
>>
>> I would check if we can add a helper xe_force_wake_get_if_active() and just
>> use that to bump up the wakeref.
>
>I would prefer to not complicate things...
also see my other reply to Umesh: _if_active() wouldn't work neither.
As it stands in the perf core, we either convert the lock needed to be a
raw_spinlock, or we need to move the actual hw read to another context
as I suggested.
Lucas De Marchi
>
>>
>> @Rodrigo, @Vinay Any thoughts on this ^ ?
>
>Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>
>>
>> Thanks,
>> Umesh
>>
>> >
>> > Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> > Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> > ---
>> > drivers/gpu/drm/xe/Makefile | 1 +
>> > drivers/gpu/drm/xe/abi/guc_actions_abi.h | 1 +
>> > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
>> > drivers/gpu/drm/xe/xe_guc_engine_activity.c | 317 ++++++++++++++++++
>> > drivers/gpu/drm/xe/xe_guc_engine_activity.h | 18 +
>> > .../gpu/drm/xe/xe_guc_engine_activity_types.h | 89 +++++
>> > drivers/gpu/drm/xe/xe_guc_fwif.h | 19 ++
>> > drivers/gpu/drm/xe/xe_guc_types.h | 4 +
>> > 8 files changed, 451 insertions(+)
>> > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.c
>> > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.h
>> > create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>> >
>> > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> > index 328aff36831b..7e93461c60bd 100644
>> > --- a/drivers/gpu/drm/xe/Makefile
>> > +++ b/drivers/gpu/drm/xe/Makefile
>> > @@ -33,6 +33,7 @@ xe-y += xe_bb.o \
>> > xe_device_sysfs.o \
>> > xe_dma_buf.o \
>> > xe_drm_client.o \
>> > + xe_guc_engine_activity.o \
>> > xe_exec.o \
>> > xe_execlist.o \
>> > xe_exec_queue.o \
>> > diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>> > index fee385532fb0..ec516e838ee8 100644
>> > --- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>> > +++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>> > @@ -140,6 +140,7 @@ enum xe_guc_action {
>> > XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
>> > XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
>> > XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
>> > + XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
>> > XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
>> > XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
>> > XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,
>> > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > index 096859072396..124cc398798e 100644
>> > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > @@ -358,6 +358,8 @@
>> > #define RENDER_AWAKE_STATUS REG_BIT(1)
>> > #define MEDIA_SLICE0_AWAKE_STATUS REG_BIT(0)
>> >
>> > +#define MISC_STATUS_0 XE_REG(0xa500)
>> > +
>> > #define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4)
>> > #define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4)
>> > #define FORCEWAKE_GSC XE_REG(0xa618)
>> > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>> > new file mode 100644
>> > index 000000000000..088209b9c228
>> > --- /dev/null
>> > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>> > @@ -0,0 +1,317 @@
>> > +// SPDX-License-Identifier: MIT
>> > +/*
>> > + * Copyright © 2025 Intel Corporation
>> > + */
>> > +#include "xe_guc_engine_activity.h"
>> > +
>> > +#include "abi/guc_actions_abi.h"
>> > +#include "regs/xe_gt_regs.h"
>> > +
>> > +#include "xe_bo.h"
>> > +#include "xe_force_wake.h"
>> > +#include "xe_gt_printk.h"
>> > +#include "xe_guc.h"
>> > +#include "xe_guc_ct.h"
>> > +#include "xe_hw_engine.h"
>> > +#include "xe_map.h"
>> > +#include "xe_mmio.h"
>> > +
>> > +#define TOTAL_QUANTA 0x8000
>> > +
>> > +static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_engine *hwe)
>> > +{
>> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>> > + u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>> > + size_t offset = 0;
>> > +
>> > + offset = offsetof(struct guc_engine_activity_data,
>> > + engine_activity[guc_class][hwe->logical_instance]);
>> > +
>> > + return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap, offset);
>> > +}
>> > +
>> > +static struct iosys_map engine_metadata_map(struct xe_guc *guc)
>> > +{
>> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>> > +
>> > + return buffer->metadata_bo->vmap;
>> > +}
>> > +
>> > +static int allocate_engine_activity_group(struct xe_guc *guc)
>> > +{
>> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > + u32 num_activity_group = 1;
>> > +
>> > + engine_activity->eag = kmalloc_array(num_activity_group,
>> > + sizeof(struct engine_activity_group),
>> > + GFP_KERNEL);
>> > +
>> > + if (!engine_activity->eag)
>> > + return -ENOMEM;
>> > +
>> > + memset(engine_activity->eag, 0, num_activity_group * sizeof(struct engine_activity_group));
>> > + engine_activity->num_activity_group = num_activity_group;
>> > +
>> > + return 0;
>> > +}
>> > +
>> > +static int allocate_engine_activity_buffers(struct xe_guc *guc,
>> > + struct engine_activity_buffer *buffer)
>> > +{
>> > + u32 metadata_size = sizeof(struct guc_engine_activity_metadata);
>> > + u32 size = sizeof(struct guc_engine_activity_data);
>> > + struct xe_gt *gt = guc_to_gt(guc);
>> > + struct xe_tile *tile = gt_to_tile(gt);
>> > + struct xe_bo *bo, *metadata_bo;
>> > +
>> > + metadata_bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(metadata_size),
>> > + XE_BO_FLAG_SYSTEM |
>> > + XE_BO_FLAG_GGTT |
>> > + XE_BO_FLAG_GGTT_INVALIDATE);
>> > + if (IS_ERR(metadata_bo))
>> > + return PTR_ERR(metadata_bo);
>> > +
>> > + bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(size),
>> > + XE_BO_FLAG_VRAM_IF_DGFX(tile) |
>> > + XE_BO_FLAG_GGTT |
>> > + XE_BO_FLAG_GGTT_INVALIDATE);
>> > +
>> > + if (IS_ERR(bo)) {
>> > + xe_bo_unpin_map_no_vm(metadata_bo);
>> > + return PTR_ERR(bo);
>> > + }
>> > +
>> > + buffer->metadata_bo = metadata_bo;
>> > + buffer->activity_bo = bo;
>> > + return 0;
>> > +}
>> > +
>> > +static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine *hwe)
>> > +{
>> > + struct xe_guc *guc = &hwe->gt->uc.guc;
>> > + struct engine_activity_group *eag = &guc->engine_activity.eag[0];
>> > + u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>> > +
>> > + return &eag->engine[guc_class][hwe->logical_instance];
>> > +}
>> > +
>> > +static u64 cpu_ns_to_guc_tsc_tick(ktime_t ns, u32 freq)
>> > +{
>> > + return mul_u64_u32_div(ns, freq, NSEC_PER_SEC);
>> > +}
>> > +
>> > +#define read_engine_activity_record(xe_, map_, field_) \
>> > + xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity, field_)
>> > +
>> > +#define read_metadata_record(xe_, map_, field_) \
>> > + xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity_metadata, field_)
>> > +
>> > +static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>> > +{
>> > + struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>> > + struct guc_engine_activity *cached_activity = &ea->activity;
>> > + struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > + struct iosys_map activity_map, metadata_map;
>> > + struct xe_device *xe = guc_to_xe(guc);
>> > + struct xe_gt *gt = guc_to_gt(guc);
>> > + u32 last_update_tick, global_change_num;
>> > + u64 active_ticks, gpm_ts;
>> > + u16 change_num;
>> > +
>> > + activity_map = engine_activity_map(guc, hwe);
>> > + metadata_map = engine_metadata_map(guc);
>> > + global_change_num = read_metadata_record(xe, &metadata_map, global_change_num);
>> > +
>> > + /* GuC has not initialized activity data yet, return 0 */
>> > + if (!global_change_num)
>> > + goto update;
>> > +
>> > + if (global_change_num == cached_metadata->global_change_num)
>> > + goto update;
>> > + else
>> > + cached_metadata->global_change_num = global_change_num;
>> > +
>> > + change_num = read_engine_activity_record(xe, &activity_map, change_num);
>> > +
>> > + if (!change_num || change_num == cached_activity->change_num)
>> > + goto update;
>> > +
>> > + /* read engine activity values */
>> > + last_update_tick = read_engine_activity_record(xe, &activity_map, last_update_tick);
>> > + active_ticks = read_engine_activity_record(xe, &activity_map, active_ticks);
>> > +
>> > + /* activity calculations */
>> > + ea->running = !!last_update_tick;
>> > + ea->total += active_ticks - cached_activity->active_ticks;
>> > + ea->active = 0;
>> > +
>> > + /* cache the counter */
>> > + cached_activity->change_num = change_num;
>> > + cached_activity->last_update_tick = last_update_tick;
>> > + cached_activity->active_ticks = active_ticks;
>> > +
>> > +update:
>> > + if (ea->running) {
>> > + gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
>> > + engine_activity->gpm_timestamp_shift;
>> > + ea->active = lower_32_bits(gpm_ts) - cached_activity->last_update_tick;
>> > + }
>> > +
>> > + return ea->total + ea->active;
>> > +}
>> > +
>> > +static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>> > +{
>> > + struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>> > + struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>> > + struct guc_engine_activity *cached_activity = &ea->activity;
>> > + struct iosys_map activity_map, metadata_map;
>> > + struct xe_device *xe = guc_to_xe(guc);
>> > + ktime_t now, cpu_delta;
>> > + u64 numerator;
>> > + u16 quanta_ratio;
>> > +
>> > + activity_map = engine_activity_map(guc, hwe);
>> > + metadata_map = engine_metadata_map(guc);
>> > +
>> > + if (!cached_metadata->guc_tsc_frequency_hz)
>> > + cached_metadata->guc_tsc_frequency_hz = read_metadata_record(xe, &metadata_map,
>> > + guc_tsc_frequency_hz);
>> > +
>> > + quanta_ratio = read_engine_activity_record(xe, &activity_map, quanta_ratio);
>> > + cached_activity->quanta_ratio = quanta_ratio;
>> > +
>> > + /* Total ticks calculations */
>> > + now = ktime_get();
>> > + cpu_delta = now - ea->last_cpu_ts;
>> > + ea->last_cpu_ts = now;
>> > + numerator = (ea->quanta_remainder_ns + cpu_delta) * cached_activity->quanta_ratio;
>> > + ea->quanta_ns += numerator / TOTAL_QUANTA;
>> > + ea->quanta_remainder_ns = numerator % TOTAL_QUANTA;
>> > + ea->quanta = cpu_ns_to_guc_tsc_tick(ea->quanta_ns, cached_metadata->guc_tsc_frequency_hz);
>> > +
>> > + return ea->quanta;
>> > +}
>> > +
>> > +static int enable_engine_activity_stats(struct xe_guc *guc)
>> > +{
>> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > + struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>> > + u32 metadata_ggtt_addr = xe_bo_ggtt_addr(buffer->metadata_bo);
>> > + u32 ggtt_addr = xe_bo_ggtt_addr(buffer->activity_bo);
>> > + int len = 0;
>> > + u32 action[5];
>> > +
>> > + action[len++] = XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER;
>> > + action[len++] = metadata_ggtt_addr;
>> > + action[len++] = 0;
>> > + action[len++] = ggtt_addr;
>> > + action[len++] = 0;
>> > +
>> > + /* Blocking here to ensure the buffers are ready before reading them */
>> > + return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
>> > +}
>> > +
>> > +static void engine_activity_set_cpu_ts(struct xe_guc *guc)
>> > +{
>> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > + struct engine_activity_group *eag = &engine_activity->eag[0];
>> > + int i, j;
>> > +
>> > + for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)
>> > + for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; j++)
>> > + eag->engine[i][j].last_cpu_ts = ktime_get();
>> > +}
>> > +
>> > +static u32 gpm_timestamp_shift(struct xe_gt *gt)
>> > +{
>> > + u32 reg;
>> > +
>> > + reg = xe_mmio_read32(>->mmio, RPM_CONFIG0);
>> > +
>> > + return 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
>> > +}
>> > +
>> > +/**
>> > + * xe_guc_engine_activity_active_ticks - Get engine active ticks
>> > + * @hwe: The hw_engine object
>> > + *
>> > + * Return: accumulated ticks @hwe was active since engine activity stats were enabled.
>> > + */
>> > +u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe)
>> > +{
>> > + struct xe_guc *guc = &hwe->gt->uc.guc;
>> > +
>> > + return get_engine_active_ticks(guc, hwe);
>> > +}
>> > +
>> > +/**
>> > + * xe_guc_engine_activity_total_ticks - Get engine total ticks
>> > + * @hwe: The hw_engine object
>> > + *
>> > + * Return: accumulated quanta of ticks allocated for the engine
>> > + */
>> > +u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe)
>> > +{
>> > + struct xe_guc *guc = &hwe->gt->uc.guc;
>> > +
>> > + return get_engine_total_ticks(guc, hwe);
>> > +}
>> > +
>> > +/**
>> > + * xe_guc_engine_activity_enable_stats - Enable engine activity stats
>> > + * @guc: The GuC object
>> > + *
>> > + * Enable engine activity stats and set initial timestamps
>> > + */
>> > +void xe_guc_engine_activity_enable_stats(struct xe_guc *guc)
>> > +{
>> > + int ret;
>> > +
>> > + ret = enable_engine_activity_stats(guc);
>> > + if (ret)
>> > + xe_gt_err(guc_to_gt(guc), "failed to enable activity stats%d\n", ret);
>> > + else
>> > + engine_activity_set_cpu_ts(guc);
>> > +}
>> > +
>> > +static void engine_activity_fini(void *arg)
>> > +{
>> > + struct xe_guc_engine_activity *engine_activity = arg;
>> > +
>> > + kfree(engine_activity->eag);
>> > +}
>> > +
>> > +/**
>> > + * xe_guc_engine_activity_init - Initialize the engine activity data
>> > + * @guc: The GuC object
>> > + *
>> > + * Return: 0 on success, negative error code otherwise.
>> > + */
>> > +int xe_guc_engine_activity_init(struct xe_guc *guc)
>> > +{
>> > + struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>> > + struct xe_gt *gt = guc_to_gt(guc);
>> > + int ret;
>> > +
>> > + ret = allocate_engine_activity_group(guc);
>> > + if (ret) {
>> > + xe_gt_err(gt, "failed to allocate activity group %d\n", ret);
>> > + return ret;
>> > + }
>> > +
>> > + ret = allocate_engine_activity_buffers(guc, &engine_activity->device_buffer);
>> > + if (ret) {
>> > + xe_gt_err(gt, "failed to allocate activity buffers%d\n", ret);
>> > + kfree(engine_activity->eag);
>> > + return ret;
>> > + }
>> > +
>> > + engine_activity->gpm_timestamp_shift = gpm_timestamp_shift(gt);
>> > +
>> > + return devm_add_action_or_reset(gt_to_xe(gt)->drm.dev, engine_activity_fini,
>> > + engine_activity);
>> > +}
>> > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.h b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>> > new file mode 100644
>> > index 000000000000..c00f3da5513d
>> > --- /dev/null
>> > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>> > @@ -0,0 +1,18 @@
>> > +/* SPDX-License-Identifier: MIT */
>> > +/*
>> > + * Copyright © 2025 Intel Corporation
>> > + */
>> > +
>> > +#ifndef _XE_GUC_ENGINE_ACTIVITY_H_
>> > +#define _XE_GUC_ENGINE_ACTIVITY_H_
>> > +
>> > +#include <linux/types.h>
>> > +
>> > +struct xe_hw_engine;
>> > +struct xe_guc;
>> > +
>> > +int xe_guc_engine_activity_init(struct xe_guc *guc);
>> > +void xe_guc_engine_activity_enable_stats(struct xe_guc *guc);
>> > +u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe);
>> > +u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe);
>> > +#endif
>> > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>> > new file mode 100644
>> > index 000000000000..a2ab327d3eec
>> > --- /dev/null
>> > +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>> > @@ -0,0 +1,89 @@
>> > +/* SPDX-License-Identifier: MIT */
>> > +/*
>> > + * Copyright © 2025 Intel Corporation
>> > + */
>> > +
>> > +#ifndef _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>> > +#define _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>> > +
>> > +#include <linux/types.h>
>> > +
>> > +#include "xe_guc_fwif.h"
>> > +/**
>> > + * struct engine_activity - Engine specific activity data
>> > + *
>> > + * Contains engine specific activity data and snapshot of the
>> > + * structures from GuC
>> > + */
>> > +struct engine_activity {
>> > + /** @active: current activity */
>> > + u64 active;
>> > +
>> > + /** @last_cpu_ts: cpu timestamp in nsec of previous sample */
>> > + u64 last_cpu_ts;
>> > +
>> > + /** @quanta: total quanta used on HW */
>> > + u64 quanta;
>> > +
>> > + /** @quanta_ns: total quanta_ns used on HW */
>> > + u64 quanta_ns;
>> > +
>> > + /**
>> > + * @quanta_remainder_ns: remainder when the CPU time is scaled as
>> > + * per the quanta_ratio. This remainder is used in subsequent
>> > + * quanta calculations.
>> > + */
>> > + u64 quanta_remainder_ns;
>> > +
>> > + /** @total: total engine activity */
>> > + u64 total;
>> > +
>> > + /** @running: true if engine is running some work */
>> > + bool running;
>> > +
>> > + /** @metadata: snapshot of engine activity metadata */
>> > + struct guc_engine_activity_metadata metadata;
>> > +
>> > + /** @activity: snapshot of engine activity counter */
>> > + struct guc_engine_activity activity;
>> > +};
>> > +
>> > +/**
>> > + * struct engine_activity_group - Activity data for all engines
>> > + */
>> > +struct engine_activity_group {
>> > + /** @engine: engine specific activity data */
>> > + struct engine_activity engine[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>> > +};
>> > +
>> > +/**
>> > + * struct engine_activity_buffer - engine activity buffers
>> > + *
>> > + * This contains the buffers allocated for metadata and activity data
>> > + */
>> > +struct engine_activity_buffer {
>> > + /** @activity_bo: object allocated to hold activity data */
>> > + struct xe_bo *activity_bo;
>> > +
>> > + /** @metadata_bo: object allocated to hold activity metadata */
>> > + struct xe_bo *metadata_bo;
>> > +};
>> > +
>> > +/**
>> > + * struct xe_guc_engine_activity - Data used by engine activity implementation
>> > + */
>> > +struct xe_guc_engine_activity {
>> > + /** @gpm_timestamp_shift: Right shift value for the gpm timestamp */
>> > + u32 gpm_timestamp_shift;
>> > +
>> > + /** @num_activity_group: number of activity groups */
>> > + u32 num_activity_group;
>> > +
>> > + /** @eag: holds the device level engine activity data */
>> > + struct engine_activity_group *eag;
>> > +
>> > + /** @device_buffer: buffer object for global engine activity */
>> > + struct engine_activity_buffer device_buffer;
>> > +};
>> > +#endif
>> > +
>> > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
>> > index 057153f89b30..6f57578b07cb 100644
>> > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
>> > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
>> > @@ -208,6 +208,25 @@ struct guc_engine_usage {
>> > struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>> > } __packed;
>> >
>> > +/* Engine Activity stats */
>> > +struct guc_engine_activity {
>> > + u16 change_num;
>> > + u16 quanta_ratio;
>> > + u32 last_update_tick;
>> > + u64 active_ticks;
>> > +} __packed;
>> > +
>> > +struct guc_engine_activity_data {
>> > + struct guc_engine_activity engine_activity[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>> > +} __packed;
>> > +
>> > +struct guc_engine_activity_metadata {
>> > + u32 guc_tsc_frequency_hz;
>> > + u32 lag_latency_usec;
>> > + u32 global_change_num;
>> > + u32 reserved;
>> > +} __packed;
>> > +
>> > /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
>> > enum xe_guc_recv_message {
>> > XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
>> > diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h
>> > index 573aa6308380..63bac64429a5 100644
>> > --- a/drivers/gpu/drm/xe/xe_guc_types.h
>> > +++ b/drivers/gpu/drm/xe/xe_guc_types.h
>> > @@ -13,6 +13,7 @@
>> > #include "xe_guc_ads_types.h"
>> > #include "xe_guc_buf_types.h"
>> > #include "xe_guc_ct_types.h"
>> > +#include "xe_guc_engine_activity_types.h"
>> > #include "xe_guc_fwif.h"
>> > #include "xe_guc_log_types.h"
>> > #include "xe_guc_pc_types.h"
>> > @@ -103,6 +104,9 @@ struct xe_guc {
>> > /** @relay: GuC Relay Communication used in SR-IOV */
>> > struct xe_guc_relay relay;
>> >
>> > + /** @engine_activity: Device specific engine activity */
>> > + struct xe_guc_engine_activity engine_activity;
>> > +
>> > /**
>> > * @notify_reg: Register which is written to notify GuC of H2G messages
>> > */
>> > --
>> > 2.47.1
>> >
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v4 1/8] drm/xe: Add per-engine-class activity support
2025-01-30 0:28 ` Umesh Nerlige Ramappa
2025-01-30 2:35 ` Rodrigo Vivi
@ 2025-01-30 20:38 ` Lucas De Marchi
1 sibling, 0 replies; 45+ messages in thread
From: Lucas De Marchi @ 2025-01-30 20:38 UTC (permalink / raw)
To: Umesh Nerlige Ramappa
Cc: Riana Tauro, intel-xe, anshuman.gupta, vinay.belgaumkar,
soham.purkait, rodrigo.vivi
On Wed, Jan 29, 2025 at 04:28:36PM -0800, Umesh Nerlige Ramappa wrote:
>On Wed, Jan 29, 2025 at 03:46:44PM +0530, Riana Tauro wrote:
>>GuC provides support to read engine counters to calculate the
>>engine activity. KMD exposes two counters via the PMU interface to
>>calculate engine activity
>>
>>Engine Active Ticks(engine-active-ticks) - number of active ticks for engine
>>Engine Total Ticks (engine-total-ticks) - total ticks of engine
>>
>>Engine activity percentage can be calculated as below
>>Engine activity % = (engine active ticks/engine total ticks) * 100.
>>
>>v2: fix cosmetic review comments
>> add forcewake for gpm_ts (Umesh)
>>
>>v3: fix CI hooks error
>> change function parameters and unpin bo on error
>> of allocate_activity_buffers
>> fix kernel-doc (Umesh)
>> use engine activity (Umesh, Lucas)
>> rename xe_engine_activity to xe_guc_engine_*
>> fix commit message to use per-engine class(Lucas)
>>
>>v4: remove forcewake as engine is already running
>> when reading gpm timestamp
>
>+ Rodrigo
>
>Sorry, I think I mentioned offline that the runtime pm get is
>sufficient for reading this register, but it's not. It does need a
>forcewake of the GT domain. At the same time, we cannot use the
>xe_force_wake_get because of the lockdep issue you mentioned and also
>I assume that xe_force_wake_get may sleep and the event may be read
>from irq context.
>
>I would check if we can add a helper xe_force_wake_get_if_active() and
>just use that to bump up the wakeref.
See my previous series for gt-c6. I tried that, but it doesn't work.
It's not that you can't wait for it to wake, you can't even take the
lock to see if you need to wake it up.
Alternative that I mentioned earlier (didn't check what's being done
here) is to separate the hw read from the perf read. Use a timer like is
done for rapl and let the perf read only have a raw_spinlock around
reading the value in memory that the timer saved. It'd also good to do
some more investigation about what other pmu drivers are doing.
Lucas De Marchi
>
>@Rodrigo, @Vinay Any thoughts on this ^ ?
>
>Thanks,
>Umesh
>
>>
>>Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>>Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>---
>>drivers/gpu/drm/xe/Makefile | 1 +
>>drivers/gpu/drm/xe/abi/guc_actions_abi.h | 1 +
>>drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
>>drivers/gpu/drm/xe/xe_guc_engine_activity.c | 317 ++++++++++++++++++
>>drivers/gpu/drm/xe/xe_guc_engine_activity.h | 18 +
>>.../gpu/drm/xe/xe_guc_engine_activity_types.h | 89 +++++
>>drivers/gpu/drm/xe/xe_guc_fwif.h | 19 ++
>>drivers/gpu/drm/xe/xe_guc_types.h | 4 +
>>8 files changed, 451 insertions(+)
>>create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.h
>>create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>>
>>diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>>index 328aff36831b..7e93461c60bd 100644
>>--- a/drivers/gpu/drm/xe/Makefile
>>+++ b/drivers/gpu/drm/xe/Makefile
>>@@ -33,6 +33,7 @@ xe-y += xe_bb.o \
>> xe_device_sysfs.o \
>> xe_dma_buf.o \
>> xe_drm_client.o \
>>+ xe_guc_engine_activity.o \
>> xe_exec.o \
>> xe_execlist.o \
>> xe_exec_queue.o \
>>diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>index fee385532fb0..ec516e838ee8 100644
>>--- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>+++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>@@ -140,6 +140,7 @@ enum xe_guc_action {
>> XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC = 0x4601,
>> XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
>> XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
>>+ XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
>> XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
>> XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
>> XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,
>>diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>index 096859072396..124cc398798e 100644
>>--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>>@@ -358,6 +358,8 @@
>>#define RENDER_AWAKE_STATUS REG_BIT(1)
>>#define MEDIA_SLICE0_AWAKE_STATUS REG_BIT(0)
>>
>>+#define MISC_STATUS_0 XE_REG(0xa500)
>>+
>>#define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4)
>>#define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4)
>>#define FORCEWAKE_GSC XE_REG(0xa618)
>>diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>new file mode 100644
>>index 000000000000..088209b9c228
>>--- /dev/null
>>+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>@@ -0,0 +1,317 @@
>>+// SPDX-License-Identifier: MIT
>>+/*
>>+ * Copyright © 2025 Intel Corporation
>>+ */
>>+#include "xe_guc_engine_activity.h"
>>+
>>+#include "abi/guc_actions_abi.h"
>>+#include "regs/xe_gt_regs.h"
>>+
>>+#include "xe_bo.h"
>>+#include "xe_force_wake.h"
>>+#include "xe_gt_printk.h"
>>+#include "xe_guc.h"
>>+#include "xe_guc_ct.h"
>>+#include "xe_hw_engine.h"
>>+#include "xe_map.h"
>>+#include "xe_mmio.h"
>>+
>>+#define TOTAL_QUANTA 0x8000
>>+
>>+static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_engine *hwe)
>>+{
>>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>+ struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>>+ u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>>+ size_t offset = 0;
>>+
>>+ offset = offsetof(struct guc_engine_activity_data,
>>+ engine_activity[guc_class][hwe->logical_instance]);
>>+
>>+ return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap, offset);
>>+}
>>+
>>+static struct iosys_map engine_metadata_map(struct xe_guc *guc)
>>+{
>>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>+ struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>>+
>>+ return buffer->metadata_bo->vmap;
>>+}
>>+
>>+static int allocate_engine_activity_group(struct xe_guc *guc)
>>+{
>>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>+ u32 num_activity_group = 1;
>>+
>>+ engine_activity->eag = kmalloc_array(num_activity_group,
>>+ sizeof(struct engine_activity_group),
>>+ GFP_KERNEL);
>>+
>>+ if (!engine_activity->eag)
>>+ return -ENOMEM;
>>+
>>+ memset(engine_activity->eag, 0, num_activity_group * sizeof(struct engine_activity_group));
>>+ engine_activity->num_activity_group = num_activity_group;
>>+
>>+ return 0;
>>+}
>>+
>>+static int allocate_engine_activity_buffers(struct xe_guc *guc,
>>+ struct engine_activity_buffer *buffer)
>>+{
>>+ u32 metadata_size = sizeof(struct guc_engine_activity_metadata);
>>+ u32 size = sizeof(struct guc_engine_activity_data);
>>+ struct xe_gt *gt = guc_to_gt(guc);
>>+ struct xe_tile *tile = gt_to_tile(gt);
>>+ struct xe_bo *bo, *metadata_bo;
>>+
>>+ metadata_bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(metadata_size),
>>+ XE_BO_FLAG_SYSTEM |
>>+ XE_BO_FLAG_GGTT |
>>+ XE_BO_FLAG_GGTT_INVALIDATE);
>>+ if (IS_ERR(metadata_bo))
>>+ return PTR_ERR(metadata_bo);
>>+
>>+ bo = xe_managed_bo_create_pin_map(gt_to_xe(gt), tile, PAGE_ALIGN(size),
>>+ XE_BO_FLAG_VRAM_IF_DGFX(tile) |
>>+ XE_BO_FLAG_GGTT |
>>+ XE_BO_FLAG_GGTT_INVALIDATE);
>>+
>>+ if (IS_ERR(bo)) {
>>+ xe_bo_unpin_map_no_vm(metadata_bo);
>>+ return PTR_ERR(bo);
>>+ }
>>+
>>+ buffer->metadata_bo = metadata_bo;
>>+ buffer->activity_bo = bo;
>>+ return 0;
>>+}
>>+
>>+static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine *hwe)
>>+{
>>+ struct xe_guc *guc = &hwe->gt->uc.guc;
>>+ struct engine_activity_group *eag = &guc->engine_activity.eag[0];
>>+ u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>>+
>>+ return &eag->engine[guc_class][hwe->logical_instance];
>>+}
>>+
>>+static u64 cpu_ns_to_guc_tsc_tick(ktime_t ns, u32 freq)
>>+{
>>+ return mul_u64_u32_div(ns, freq, NSEC_PER_SEC);
>>+}
>>+
>>+#define read_engine_activity_record(xe_, map_, field_) \
>>+ xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity, field_)
>>+
>>+#define read_metadata_record(xe_, map_, field_) \
>>+ xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity_metadata, field_)
>>+
>>+static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>>+{
>>+ struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>>+ struct guc_engine_activity *cached_activity = &ea->activity;
>>+ struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>+ struct iosys_map activity_map, metadata_map;
>>+ struct xe_device *xe = guc_to_xe(guc);
>>+ struct xe_gt *gt = guc_to_gt(guc);
>>+ u32 last_update_tick, global_change_num;
>>+ u64 active_ticks, gpm_ts;
>>+ u16 change_num;
>>+
>>+ activity_map = engine_activity_map(guc, hwe);
>>+ metadata_map = engine_metadata_map(guc);
>>+ global_change_num = read_metadata_record(xe, &metadata_map, global_change_num);
>>+
>>+ /* GuC has not initialized activity data yet, return 0 */
>>+ if (!global_change_num)
>>+ goto update;
>>+
>>+ if (global_change_num == cached_metadata->global_change_num)
>>+ goto update;
>>+ else
>>+ cached_metadata->global_change_num = global_change_num;
>>+
>>+ change_num = read_engine_activity_record(xe, &activity_map, change_num);
>>+
>>+ if (!change_num || change_num == cached_activity->change_num)
>>+ goto update;
>>+
>>+ /* read engine activity values */
>>+ last_update_tick = read_engine_activity_record(xe, &activity_map, last_update_tick);
>>+ active_ticks = read_engine_activity_record(xe, &activity_map, active_ticks);
>>+
>>+ /* activity calculations */
>>+ ea->running = !!last_update_tick;
>>+ ea->total += active_ticks - cached_activity->active_ticks;
>>+ ea->active = 0;
>>+
>>+ /* cache the counter */
>>+ cached_activity->change_num = change_num;
>>+ cached_activity->last_update_tick = last_update_tick;
>>+ cached_activity->active_ticks = active_ticks;
>>+
>>+update:
>>+ if (ea->running) {
>>+ gpm_ts = xe_mmio_read64_2x32(>->mmio, MISC_STATUS_0) >>
>>+ engine_activity->gpm_timestamp_shift;
>>+ ea->active = lower_32_bits(gpm_ts) - cached_activity->last_update_tick;
>>+ }
>>+
>>+ return ea->total + ea->active;
>>+}
>>+
>>+static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>>+{
>>+ struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>>+ struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>>+ struct guc_engine_activity *cached_activity = &ea->activity;
>>+ struct iosys_map activity_map, metadata_map;
>>+ struct xe_device *xe = guc_to_xe(guc);
>>+ ktime_t now, cpu_delta;
>>+ u64 numerator;
>>+ u16 quanta_ratio;
>>+
>>+ activity_map = engine_activity_map(guc, hwe);
>>+ metadata_map = engine_metadata_map(guc);
>>+
>>+ if (!cached_metadata->guc_tsc_frequency_hz)
>>+ cached_metadata->guc_tsc_frequency_hz = read_metadata_record(xe, &metadata_map,
>>+ guc_tsc_frequency_hz);
>>+
>>+ quanta_ratio = read_engine_activity_record(xe, &activity_map, quanta_ratio);
>>+ cached_activity->quanta_ratio = quanta_ratio;
>>+
>>+ /* Total ticks calculations */
>>+ now = ktime_get();
>>+ cpu_delta = now - ea->last_cpu_ts;
>>+ ea->last_cpu_ts = now;
>>+ numerator = (ea->quanta_remainder_ns + cpu_delta) * cached_activity->quanta_ratio;
>>+ ea->quanta_ns += numerator / TOTAL_QUANTA;
>>+ ea->quanta_remainder_ns = numerator % TOTAL_QUANTA;
>>+ ea->quanta = cpu_ns_to_guc_tsc_tick(ea->quanta_ns, cached_metadata->guc_tsc_frequency_hz);
>>+
>>+ return ea->quanta;
>>+}
>>+
>>+static int enable_engine_activity_stats(struct xe_guc *guc)
>>+{
>>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>+ struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>>+ u32 metadata_ggtt_addr = xe_bo_ggtt_addr(buffer->metadata_bo);
>>+ u32 ggtt_addr = xe_bo_ggtt_addr(buffer->activity_bo);
>>+ int len = 0;
>>+ u32 action[5];
>>+
>>+ action[len++] = XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER;
>>+ action[len++] = metadata_ggtt_addr;
>>+ action[len++] = 0;
>>+ action[len++] = ggtt_addr;
>>+ action[len++] = 0;
>>+
>>+ /* Blocking here to ensure the buffers are ready before reading them */
>>+ return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
>>+}
>>+
>>+static void engine_activity_set_cpu_ts(struct xe_guc *guc)
>>+{
>>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>+ struct engine_activity_group *eag = &engine_activity->eag[0];
>>+ int i, j;
>>+
>>+ for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)
>>+ for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; j++)
>>+ eag->engine[i][j].last_cpu_ts = ktime_get();
>>+}
>>+
>>+static u32 gpm_timestamp_shift(struct xe_gt *gt)
>>+{
>>+ u32 reg;
>>+
>>+ reg = xe_mmio_read32(>->mmio, RPM_CONFIG0);
>>+
>>+ return 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
>>+}
>>+
>>+/**
>>+ * xe_guc_engine_activity_active_ticks - Get engine active ticks
>>+ * @hwe: The hw_engine object
>>+ *
>>+ * Return: accumulated ticks @hwe was active since engine activity stats were enabled.
>>+ */
>>+u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe)
>>+{
>>+ struct xe_guc *guc = &hwe->gt->uc.guc;
>>+
>>+ return get_engine_active_ticks(guc, hwe);
>>+}
>>+
>>+/**
>>+ * xe_guc_engine_activity_total_ticks - Get engine total ticks
>>+ * @hwe: The hw_engine object
>>+ *
>>+ * Return: accumulated quanta of ticks allocated for the engine
>>+ */
>>+u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe)
>>+{
>>+ struct xe_guc *guc = &hwe->gt->uc.guc;
>>+
>>+ return get_engine_total_ticks(guc, hwe);
>>+}
>>+
>>+/**
>>+ * xe_guc_engine_activity_enable_stats - Enable engine activity stats
>>+ * @guc: The GuC object
>>+ *
>>+ * Enable engine activity stats and set initial timestamps
>>+ */
>>+void xe_guc_engine_activity_enable_stats(struct xe_guc *guc)
>>+{
>>+ int ret;
>>+
>>+ ret = enable_engine_activity_stats(guc);
>>+ if (ret)
>>+ xe_gt_err(guc_to_gt(guc), "failed to enable activity stats%d\n", ret);
>>+ else
>>+ engine_activity_set_cpu_ts(guc);
>>+}
>>+
>>+static void engine_activity_fini(void *arg)
>>+{
>>+ struct xe_guc_engine_activity *engine_activity = arg;
>>+
>>+ kfree(engine_activity->eag);
>>+}
>>+
>>+/**
>>+ * xe_guc_engine_activity_init - Initialize the engine activity data
>>+ * @guc: The GuC object
>>+ *
>>+ * Return: 0 on success, negative error code otherwise.
>>+ */
>>+int xe_guc_engine_activity_init(struct xe_guc *guc)
>>+{
>>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>>+ struct xe_gt *gt = guc_to_gt(guc);
>>+ int ret;
>>+
>>+ ret = allocate_engine_activity_group(guc);
>>+ if (ret) {
>>+ xe_gt_err(gt, "failed to allocate activity group %d\n", ret);
>>+ return ret;
>>+ }
>>+
>>+ ret = allocate_engine_activity_buffers(guc, &engine_activity->device_buffer);
>>+ if (ret) {
>>+ xe_gt_err(gt, "failed to allocate activity buffers%d\n", ret);
>>+ kfree(engine_activity->eag);
>>+ return ret;
>>+ }
>>+
>>+ engine_activity->gpm_timestamp_shift = gpm_timestamp_shift(gt);
>>+
>>+ return devm_add_action_or_reset(gt_to_xe(gt)->drm.dev, engine_activity_fini,
>>+ engine_activity);
>>+}
>>diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.h b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>>new file mode 100644
>>index 000000000000..c00f3da5513d
>>--- /dev/null
>>+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>>@@ -0,0 +1,18 @@
>>+/* SPDX-License-Identifier: MIT */
>>+/*
>>+ * Copyright © 2025 Intel Corporation
>>+ */
>>+
>>+#ifndef _XE_GUC_ENGINE_ACTIVITY_H_
>>+#define _XE_GUC_ENGINE_ACTIVITY_H_
>>+
>>+#include <linux/types.h>
>>+
>>+struct xe_hw_engine;
>>+struct xe_guc;
>>+
>>+int xe_guc_engine_activity_init(struct xe_guc *guc);
>>+void xe_guc_engine_activity_enable_stats(struct xe_guc *guc);
>>+u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe);
>>+u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe);
>>+#endif
>>diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>>new file mode 100644
>>index 000000000000..a2ab327d3eec
>>--- /dev/null
>>+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>>@@ -0,0 +1,89 @@
>>+/* SPDX-License-Identifier: MIT */
>>+/*
>>+ * Copyright © 2025 Intel Corporation
>>+ */
>>+
>>+#ifndef _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>>+#define _XE_GUC_ENGINE_ACTIVITY_TYPES_H_
>>+
>>+#include <linux/types.h>
>>+
>>+#include "xe_guc_fwif.h"
>>+/**
>>+ * struct engine_activity - Engine specific activity data
>>+ *
>>+ * Contains engine specific activity data and snapshot of the
>>+ * structures from GuC
>>+ */
>>+struct engine_activity {
>>+ /** @active: current activity */
>>+ u64 active;
>>+
>>+ /** @last_cpu_ts: cpu timestamp in nsec of previous sample */
>>+ u64 last_cpu_ts;
>>+
>>+ /** @quanta: total quanta used on HW */
>>+ u64 quanta;
>>+
>>+ /** @quanta_ns: total quanta_ns used on HW */
>>+ u64 quanta_ns;
>>+
>>+ /**
>>+ * @quanta_remainder_ns: remainder when the CPU time is scaled as
>>+ * per the quanta_ratio. This remainder is used in subsequent
>>+ * quanta calculations.
>>+ */
>>+ u64 quanta_remainder_ns;
>>+
>>+ /** @total: total engine activity */
>>+ u64 total;
>>+
>>+ /** @running: true if engine is running some work */
>>+ bool running;
>>+
>>+ /** @metadata: snapshot of engine activity metadata */
>>+ struct guc_engine_activity_metadata metadata;
>>+
>>+ /** @activity: snapshot of engine activity counter */
>>+ struct guc_engine_activity activity;
>>+};
>>+
>>+/**
>>+ * struct engine_activity_group - Activity data for all engines
>>+ */
>>+struct engine_activity_group {
>>+ /** @engine: engine specific activity data */
>>+ struct engine_activity engine[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>>+};
>>+
>>+/**
>>+ * struct engine_activity_buffer - engine activity buffers
>>+ *
>>+ * This contains the buffers allocated for metadata and activity data
>>+ */
>>+struct engine_activity_buffer {
>>+ /** @activity_bo: object allocated to hold activity data */
>>+ struct xe_bo *activity_bo;
>>+
>>+ /** @metadata_bo: object allocated to hold activity metadata */
>>+ struct xe_bo *metadata_bo;
>>+};
>>+
>>+/**
>>+ * struct xe_guc_engine_activity - Data used by engine activity implementation
>>+ */
>>+struct xe_guc_engine_activity {
>>+ /** @gpm_timestamp_shift: Right shift value for the gpm timestamp */
>>+ u32 gpm_timestamp_shift;
>>+
>>+ /** @num_activity_group: number of activity groups */
>>+ u32 num_activity_group;
>>+
>>+ /** @eag: holds the device level engine activity data */
>>+ struct engine_activity_group *eag;
>>+
>>+ /** @device_buffer: buffer object for global engine activity */
>>+ struct engine_activity_buffer device_buffer;
>>+};
>>+#endif
>>+
>>diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
>>index 057153f89b30..6f57578b07cb 100644
>>--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
>>+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
>>@@ -208,6 +208,25 @@ struct guc_engine_usage {
>> struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>>} __packed;
>>
>>+/* Engine Activity stats */
>>+struct guc_engine_activity {
>>+ u16 change_num;
>>+ u16 quanta_ratio;
>>+ u32 last_update_tick;
>>+ u64 active_ticks;
>>+} __packed;
>>+
>>+struct guc_engine_activity_data {
>>+ struct guc_engine_activity engine_activity[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
>>+} __packed;
>>+
>>+struct guc_engine_activity_metadata {
>>+ u32 guc_tsc_frequency_hz;
>>+ u32 lag_latency_usec;
>>+ u32 global_change_num;
>>+ u32 reserved;
>>+} __packed;
>>+
>>/* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
>>enum xe_guc_recv_message {
>> XE_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
>>diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h
>>index 573aa6308380..63bac64429a5 100644
>>--- a/drivers/gpu/drm/xe/xe_guc_types.h
>>+++ b/drivers/gpu/drm/xe/xe_guc_types.h
>>@@ -13,6 +13,7 @@
>>#include "xe_guc_ads_types.h"
>>#include "xe_guc_buf_types.h"
>>#include "xe_guc_ct_types.h"
>>+#include "xe_guc_engine_activity_types.h"
>>#include "xe_guc_fwif.h"
>>#include "xe_guc_log_types.h"
>>#include "xe_guc_pc_types.h"
>>@@ -103,6 +104,9 @@ struct xe_guc {
>> /** @relay: GuC Relay Communication used in SR-IOV */
>> struct xe_guc_relay relay;
>>
>>+ /** @engine_activity: Device specific engine activity */
>>+ struct xe_guc_engine_activity engine_activity;
>>+
>> /**
>> * @notify_reg: Register which is written to notify GuC of H2G messages
>> */
>>--
>>2.47.1
>>
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH v4 2/8] drm/xe/trace: Add trace for engine activity
2025-01-29 10:16 [PATCH v4 0/8] PMU Support for per-engine-class activity Riana Tauro
2025-01-29 10:16 ` [PATCH v4 1/8] drm/xe: Add per-engine-class activity support Riana Tauro
@ 2025-01-29 10:16 ` Riana Tauro
2025-01-29 10:16 ` [PATCH v4 3/8] drm/xe/guc: Expose engine activity only for supported GuC version Riana Tauro
` (14 subsequent siblings)
16 siblings, 0 replies; 45+ messages in thread
From: Riana Tauro @ 2025-01-29 10:16 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, umesh.nerlige.ramappa,
lucas.demarchi, vinay.belgaumkar, soham.purkait
Add engine activity related information to trace events for
better debuggability
v2: add trace for engine activity (Umesh)
v3: use hex for quanta_ratio
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
drivers/gpu/drm/xe/xe_guc_engine_activity.c | 5 +++
drivers/gpu/drm/xe/xe_trace_guc.h | 49 +++++++++++++++++++++
2 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
index 088209b9c228..9c08af273397 100644
--- a/drivers/gpu/drm/xe/xe_guc_engine_activity.c
+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
@@ -15,6 +15,7 @@
#include "xe_hw_engine.h"
#include "xe_map.h"
#include "xe_mmio.h"
+#include "xe_trace_guc.h"
#define TOTAL_QUANTA 0x8000
@@ -160,6 +161,8 @@ static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
ea->active = lower_32_bits(gpm_ts) - cached_activity->last_update_tick;
}
+ trace_xe_guc_engine_activity(xe, ea, hwe->name, hwe->instance);
+
return ea->total + ea->active;
}
@@ -193,6 +196,8 @@ static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
ea->quanta_remainder_ns = numerator % TOTAL_QUANTA;
ea->quanta = cpu_ns_to_guc_tsc_tick(ea->quanta_ns, cached_metadata->guc_tsc_frequency_hz);
+ trace_xe_guc_engine_activity(xe, ea, hwe->name, hwe->instance);
+
return ea->quanta;
}
diff --git a/drivers/gpu/drm/xe/xe_trace_guc.h b/drivers/gpu/drm/xe/xe_trace_guc.h
index 23abdd55dc62..78949db9cfce 100644
--- a/drivers/gpu/drm/xe/xe_trace_guc.h
+++ b/drivers/gpu/drm/xe/xe_trace_guc.h
@@ -14,6 +14,7 @@
#include "xe_device_types.h"
#include "xe_guc_exec_queue_types.h"
+#include "xe_guc_engine_activity_types.h"
#define __dev_name_xe(xe) dev_name((xe)->drm.dev)
@@ -100,6 +101,54 @@ DEFINE_EVENT_PRINT(xe_guc_ctb, xe_guc_ctb_g2h,
);
+TRACE_EVENT(xe_guc_engine_activity,
+ TP_PROTO(struct xe_device *xe, struct engine_activity *ea, const char *name,
+ u16 instance),
+ TP_ARGS(xe, ea, name, instance),
+
+ TP_STRUCT__entry(
+ __string(dev, __dev_name_xe(xe))
+ __string(name, name)
+ __field(u32, global_change_num)
+ __field(u32, guc_tsc_frequency_hz)
+ __field(u32, lag_latency_usec)
+ __field(u16, instance)
+ __field(u16, change_num)
+ __field(u16, quanta_ratio)
+ __field(u32, last_update_tick)
+ __field(u64, active_ticks)
+ __field(u64, active)
+ __field(u64, total)
+ __field(u64, quanta)
+ __field(u64, last_cpu_ts)
+ ),
+
+ TP_fast_assign(
+ __assign_str(dev);
+ __assign_str(name);
+ __entry->global_change_num = ea->metadata.global_change_num;
+ __entry->guc_tsc_frequency_hz = ea->metadata.guc_tsc_frequency_hz;
+ __entry->lag_latency_usec = ea->metadata.lag_latency_usec;
+ __entry->instance = instance;
+ __entry->change_num = ea->activity.change_num;
+ __entry->quanta_ratio = ea->activity.quanta_ratio;
+ __entry->last_update_tick = ea->activity.last_update_tick;
+ __entry->active_ticks = ea->activity.active_ticks;
+ __entry->active = ea->active;
+ __entry->total = ea->total;
+ __entry->quanta = ea->quanta;
+ __entry->last_cpu_ts = ea->last_cpu_ts;
+ ),
+
+ TP_printk("dev=%s engine %s:%d Active=%llu, quanta=%llu, last_cpu_ts=%llu\n"
+ "Activity metadata: global_change_num=%u, guc_tsc_frequency_hz=%u lag_latency_usec=%u\n"
+ "Activity data: change_num=%u, quanta_ratio=0x%x, last_update_tick=%u, active_ticks=%llu\n",
+ __get_str(dev), __get_str(name), __entry->instance,
+ (__entry->active + __entry->total), __entry->quanta, __entry->last_cpu_ts,
+ __entry->global_change_num, __entry->guc_tsc_frequency_hz,
+ __entry->lag_latency_usec, __entry->change_num, __entry->quanta_ratio,
+ __entry->last_update_tick, __entry->active_ticks)
+);
#endif
/* This part must be outside protection */
--
2.47.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* [PATCH v4 3/8] drm/xe/guc: Expose engine activity only for supported GuC version
2025-01-29 10:16 [PATCH v4 0/8] PMU Support for per-engine-class activity Riana Tauro
2025-01-29 10:16 ` [PATCH v4 1/8] drm/xe: Add per-engine-class activity support Riana Tauro
2025-01-29 10:16 ` [PATCH v4 2/8] drm/xe/trace: Add trace for engine activity Riana Tauro
@ 2025-01-29 10:16 ` Riana Tauro
2025-01-29 20:18 ` Michal Wajdeczko
2025-01-29 10:16 ` [PATCH v4 4/8] drm/xe/xe_pmu: Add PMU support for per-engine-class activity Riana Tauro
` (13 subsequent siblings)
16 siblings, 1 reply; 45+ messages in thread
From: Riana Tauro @ 2025-01-29 10:16 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, umesh.nerlige.ramappa,
lucas.demarchi, vinay.belgaumkar, soham.purkait
Engine activity is supported only on GuC submission version >= 1.14.1
Allow enabling/reading engine activity only on supported
GuC versions. Warn once if not supported.
v2: use guc submission version (John)
v3: use drm_warn_once to avoid stacktrace (Umesh)
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/xe_guc_engine_activity.c | 32 +++++++++++++++++++++
drivers/gpu/drm/xe/xe_guc_engine_activity.h | 1 +
2 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
index 9c08af273397..4d720afd12ac 100644
--- a/drivers/gpu/drm/xe/xe_guc_engine_activity.c
+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
@@ -250,6 +250,9 @@ u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe)
{
struct xe_guc *guc = &hwe->gt->uc.guc;
+ if (!xe_guc_engine_activity_supported(guc))
+ return 0;
+
return get_engine_active_ticks(guc, hwe);
}
@@ -263,9 +266,32 @@ u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe)
{
struct xe_guc *guc = &hwe->gt->uc.guc;
+ if (!xe_guc_engine_activity_supported(guc))
+ return 0;
+
return get_engine_total_ticks(guc, hwe);
}
+/**
+ * xe_guc_engine_activity_supported - Check support for Engine activity stats
+ * @guc: The GuC object
+ *
+ * Engine activity stats is supported from GuC submission version
+ * (1.14.1)
+ *
+ * Return: true if engine activity stats supported, false otherwise
+ */
+bool xe_guc_engine_activity_supported(struct xe_guc *guc)
+{
+ if (GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 14, 1))
+ return true;
+
+ drm_warn_once(&guc_to_xe(guc)->drm,
+ "per-engine-class activity not supported for this GuC version\n");
+
+ return false;
+}
+
/**
* xe_guc_engine_activity_enable_stats - Enable engine activity stats
* @guc: The GuC object
@@ -276,6 +302,9 @@ void xe_guc_engine_activity_enable_stats(struct xe_guc *guc)
{
int ret;
+ if (!xe_guc_engine_activity_supported(guc))
+ return;
+
ret = enable_engine_activity_stats(guc);
if (ret)
xe_gt_err(guc_to_gt(guc), "failed to enable activity stats%d\n", ret);
@@ -302,6 +331,9 @@ int xe_guc_engine_activity_init(struct xe_guc *guc)
struct xe_gt *gt = guc_to_gt(guc);
int ret;
+ if (!xe_guc_engine_activity_supported(guc))
+ return 0;
+
ret = allocate_engine_activity_group(guc);
if (ret) {
xe_gt_err(gt, "failed to allocate activity group %d\n", ret);
diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.h b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
index c00f3da5513d..9d3ea3f67b6a 100644
--- a/drivers/gpu/drm/xe/xe_guc_engine_activity.h
+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
@@ -12,6 +12,7 @@ struct xe_hw_engine;
struct xe_guc;
int xe_guc_engine_activity_init(struct xe_guc *guc);
+bool xe_guc_engine_activity_supported(struct xe_guc *guc);
void xe_guc_engine_activity_enable_stats(struct xe_guc *guc);
u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe);
u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe);
--
2.47.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [PATCH v4 3/8] drm/xe/guc: Expose engine activity only for supported GuC version
2025-01-29 10:16 ` [PATCH v4 3/8] drm/xe/guc: Expose engine activity only for supported GuC version Riana Tauro
@ 2025-01-29 20:18 ` Michal Wajdeczko
2025-01-30 5:20 ` Riana Tauro
0 siblings, 1 reply; 45+ messages in thread
From: Michal Wajdeczko @ 2025-01-29 20:18 UTC (permalink / raw)
To: Riana Tauro, intel-xe
Cc: anshuman.gupta, umesh.nerlige.ramappa, lucas.demarchi,
vinay.belgaumkar, soham.purkait
On 29.01.2025 11:16, Riana Tauro wrote:
> Engine activity is supported only on GuC submission version >= 1.14.1
> Allow enabling/reading engine activity only on supported
> GuC versions. Warn once if not supported.
>
> v2: use guc submission version (John)
> v3: use drm_warn_once to avoid stacktrace (Umesh)
>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc_engine_activity.c | 32 +++++++++++++++++++++
> drivers/gpu/drm/xe/xe_guc_engine_activity.h | 1 +
> 2 files changed, 33 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
> index 9c08af273397..4d720afd12ac 100644
> --- a/drivers/gpu/drm/xe/xe_guc_engine_activity.c
> +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
> @@ -250,6 +250,9 @@ u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe)
> {
> struct xe_guc *guc = &hwe->gt->uc.guc;
>
> + if (!xe_guc_engine_activity_supported(guc))
> + return 0;
> +
> return get_engine_active_ticks(guc, hwe);
> }
>
> @@ -263,9 +266,32 @@ u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe)
> {
> struct xe_guc *guc = &hwe->gt->uc.guc;
>
> + if (!xe_guc_engine_activity_supported(guc))
> + return 0;
> +
> return get_engine_total_ticks(guc, hwe);
> }
>
> +/**
> + * xe_guc_engine_activity_supported - Check support for Engine activity stats
> + * @guc: The GuC object
> + *
> + * Engine activity stats is supported from GuC submission version
> + * (1.14.1)
> + *
> + * Return: true if engine activity stats supported, false otherwise
> + */
> +bool xe_guc_engine_activity_supported(struct xe_guc *guc)
> +{
> + if (GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 14, 1))
> + return true;
this patch seems to be redundant as patch:
[PATCH v4 5/8] drm/xe/guc: Bump minimum required GuC version to v70.36.0
now requires at least submit version 1.17.1
> +
> + drm_warn_once(&guc_to_xe(guc)->drm,
btw, for GuC related logs we prefer xe_gt_info() logs
and _once() variant is n/a here as it will hide any other messages from
drivers running on other devices that might be present on the system
better option seems to be check/log once in the init() and then just set
a flag that could be used later
> + "per-engine-class activity not supported for this GuC version\n");
and maybe we should be more friendly and instead "this" also print
actual version used to save the user looking for it elsewhere
> +
> + return false;
> +}
> +
> /**
> * xe_guc_engine_activity_enable_stats - Enable engine activity stats
> * @guc: The GuC object
> @@ -276,6 +302,9 @@ void xe_guc_engine_activity_enable_stats(struct xe_guc *guc)
> {
> int ret;
>
> + if (!xe_guc_engine_activity_supported(guc))
> + return;
> +
> ret = enable_engine_activity_stats(guc);
> if (ret)
> xe_gt_err(guc_to_gt(guc), "failed to enable activity stats%d\n", ret);
> @@ -302,6 +331,9 @@ int xe_guc_engine_activity_init(struct xe_guc *guc)
> struct xe_gt *gt = guc_to_gt(guc);
> int ret;
>
> + if (!xe_guc_engine_activity_supported(guc))
> + return 0;
> +
> ret = allocate_engine_activity_group(guc);
> if (ret) {
> xe_gt_err(gt, "failed to allocate activity group %d\n", ret);
> diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.h b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
> index c00f3da5513d..9d3ea3f67b6a 100644
> --- a/drivers/gpu/drm/xe/xe_guc_engine_activity.h
> +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
> @@ -12,6 +12,7 @@ struct xe_hw_engine;
> struct xe_guc;
>
> int xe_guc_engine_activity_init(struct xe_guc *guc);
> +bool xe_guc_engine_activity_supported(struct xe_guc *guc);
> void xe_guc_engine_activity_enable_stats(struct xe_guc *guc);
> u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe);
> u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe);
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 3/8] drm/xe/guc: Expose engine activity only for supported GuC version
2025-01-29 20:18 ` Michal Wajdeczko
@ 2025-01-30 5:20 ` Riana Tauro
0 siblings, 0 replies; 45+ messages in thread
From: Riana Tauro @ 2025-01-30 5:20 UTC (permalink / raw)
To: Michal Wajdeczko, intel-xe
Cc: anshuman.gupta, umesh.nerlige.ramappa, lucas.demarchi,
vinay.belgaumkar, soham.purkait
Hi Michal
On 1/30/2025 1:48 AM, Michal Wajdeczko wrote:
>
>
> On 29.01.2025 11:16, Riana Tauro wrote:
>> Engine activity is supported only on GuC submission version >= 1.14.1
>> Allow enabling/reading engine activity only on supported
>> GuC versions. Warn once if not supported.
>>
>> v2: use guc submission version (John)
>> v3: use drm_warn_once to avoid stacktrace (Umesh)
>>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_guc_engine_activity.c | 32 +++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_guc_engine_activity.h | 1 +
>> 2 files changed, 33 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>> index 9c08af273397..4d720afd12ac 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>> @@ -250,6 +250,9 @@ u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe)
>> {
>> struct xe_guc *guc = &hwe->gt->uc.guc;
>>
>> + if (!xe_guc_engine_activity_supported(guc))
>> + return 0;
>> +
>> return get_engine_active_ticks(guc, hwe);
>> }
>>
>> @@ -263,9 +266,32 @@ u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe)
>> {
>> struct xe_guc *guc = &hwe->gt->uc.guc;
>>
>> + if (!xe_guc_engine_activity_supported(guc))
>> + return 0;
>> +
>> return get_engine_total_ticks(guc, hwe);
>> }
>>
>> +/**
>> + * xe_guc_engine_activity_supported - Check support for Engine activity stats
>> + * @guc: The GuC object
>> + *
>> + * Engine activity stats is supported from GuC submission version
>> + * (1.14.1)
>> + *
>> + * Return: true if engine activity stats supported, false otherwise
>> + */
>> +bool xe_guc_engine_activity_supported(struct xe_guc *guc)
>> +{
>> + if (GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 14, 1))
>> + return true;
>
> this patch seems to be redundant as patch:
>
> [PATCH v4 5/8] drm/xe/guc: Bump minimum required GuC version to v70.36.0
>
> now requires at least submit version 1.17.1
This feature support was added in 1.14.1 hence the version.
[PATCH v4 5/8] drm/xe/guc: Bump minimum required GuC version to v70.36.0
Upstream firmware latest above 70.33 is 36.0
>
>> +
>> + drm_warn_once(&guc_to_xe(guc)->drm,
>
> btw, for GuC related logs we prefer xe_gt_info() logs
will replace in the series with gt versions
>
> and _once() variant is n/a here as it will hide any other messages from
> drivers running on other devices that might be present on the system
I thought _once would be per-device. Will re-check
But removing _once would log the message after every suspend/resume or
reset. If that's okay will remove once
>
> better option seems to be check/log once in the init() and then just set
> a flag that could be used later
This sounds good. Will add this in the next rev
>
>> + "per-engine-class activity not supported for this GuC version\n");
>
> and maybe we should be more friendly and instead "this" also print
> actual version used to save the user looking for it elsewhere
Sure, will add this
Thanks
Riana
>
>> +
>> + return false;
>> +}
>> +
>> /**
>> * xe_guc_engine_activity_enable_stats - Enable engine activity stats
>> * @guc: The GuC object
>> @@ -276,6 +302,9 @@ void xe_guc_engine_activity_enable_stats(struct xe_guc *guc)
>> {
>> int ret;
>>
>> + if (!xe_guc_engine_activity_supported(guc))
>> + return;
>> +
>> ret = enable_engine_activity_stats(guc);
>> if (ret)
>> xe_gt_err(guc_to_gt(guc), "failed to enable activity stats%d\n", ret);
>> @@ -302,6 +331,9 @@ int xe_guc_engine_activity_init(struct xe_guc *guc)
>> struct xe_gt *gt = guc_to_gt(guc);
>> int ret;
>>
>> + if (!xe_guc_engine_activity_supported(guc))
>> + return 0;
>> +
>> ret = allocate_engine_activity_group(guc);
>> if (ret) {
>> xe_gt_err(gt, "failed to allocate activity group %d\n", ret);
>> diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.h b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>> index c00f3da5513d..9d3ea3f67b6a 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>> +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
>> @@ -12,6 +12,7 @@ struct xe_hw_engine;
>> struct xe_guc;
>>
>> int xe_guc_engine_activity_init(struct xe_guc *guc);
>> +bool xe_guc_engine_activity_supported(struct xe_guc *guc);
>> void xe_guc_engine_activity_enable_stats(struct xe_guc *guc);
>> u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe);
>> u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe);
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH v4 4/8] drm/xe/xe_pmu: Add PMU support for per-engine-class activity
2025-01-29 10:16 [PATCH v4 0/8] PMU Support for per-engine-class activity Riana Tauro
` (2 preceding siblings ...)
2025-01-29 10:16 ` [PATCH v4 3/8] drm/xe/guc: Expose engine activity only for supported GuC version Riana Tauro
@ 2025-01-29 10:16 ` Riana Tauro
2025-01-31 23:11 ` Umesh Nerlige Ramappa
2025-01-29 10:16 ` [PATCH v4 5/8] drm/xe/guc: Bump minimum required GuC version to v70.36.0 Riana Tauro
` (12 subsequent siblings)
16 siblings, 1 reply; 45+ messages in thread
From: Riana Tauro @ 2025-01-29 10:16 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, umesh.nerlige.ramappa,
lucas.demarchi, vinay.belgaumkar, soham.purkait
PMU provides two counters (engine-active-ticks, engine-total-ticks)
to calculate engine activity. When querying engine activity,
user must group these 2 counters using the perf_event
group mechanism to ensure both counters are sampled together.
To list the events
./perf list
xe_0000_03_00.0/engine-active-ticks/ [Kernel PMU event]
xe_0000_03_00.0/engine-total-ticks/ [Kernel PMU event]
The formats to be used with the above are
engine_instance - config:12-19
engine_class - config:20-27
gt - config:60-63
The events can then be read using perf tool
./perf stat -e xe_0000_03_00.0/engine-active-ticks,gt=0,
engine_class=0,engine_instance=0/,
xe_0000_03_00.0/engine-total-ticks,gt=0,
engine_class=0,engine_instance=0/ -I 1000
Engine activity can then be calculated as below
engine activity % = (engine active ticks/engine total ticks) * 100
v2: validate gt
rename total-ticks to engine-total-ticks
add helper to get hwe (Umesh)
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/xe_guc.c | 5 ++
drivers/gpu/drm/xe/xe_pmu.c | 129 +++++++++++++++++++++++++++++++++---
drivers/gpu/drm/xe/xe_uc.c | 3 +
3 files changed, 128 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 1619c0a52db9..bc1ff0a4e1e7 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -27,6 +27,7 @@
#include "xe_guc_capture.h"
#include "xe_guc_ct.h"
#include "xe_guc_db_mgr.h"
+#include "xe_guc_engine_activity.h"
#include "xe_guc_hwconfig.h"
#include "xe_guc_log.h"
#include "xe_guc_pc.h"
@@ -744,6 +745,10 @@ int xe_guc_init_post_hwconfig(struct xe_guc *guc)
if (ret)
return ret;
+ ret = xe_guc_engine_activity_init(guc);
+ if (ret)
+ return ret;
+
ret = xe_guc_buf_cache_init(&guc->buf);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
index 3910a82328ee..8ea78d8f7e2e 100644
--- a/drivers/gpu/drm/xe/xe_pmu.c
+++ b/drivers/gpu/drm/xe/xe_pmu.c
@@ -8,15 +8,16 @@
#include "xe_device.h"
#include "xe_gt_idle.h"
+#include "xe_guc_engine_activity.h"
+#include "xe_hw_engine.h"
#include "xe_pm.h"
#include "xe_pmu.h"
/**
* DOC: Xe PMU (Performance Monitoring Unit)
*
- * Expose events/counters like GT-C6 residency and GT frequency to user land via
- * the perf interface. Events are per device. The GT can be selected with an
- * extra config sub-field (bits 60-63).
+ * Expose events/counters like GT-C6 residency, GT frequency and per-class-engine
+ * activity to user land via the perf interface. Events are per device.
*
* All events are listed in sysfs:
*
@@ -24,7 +25,19 @@
* $ ls /sys/bus/event_source/devices/xe_0000_00_02.0/events/
* $ ls /sys/bus/event_source/devices/xe_0000_00_02.0/format/
*
- * The format directory has info regarding the configs that can be used.
+ * format directory configs:
+ *
+ * 60 56 52 48 44 40 36 32
+ * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
+ * [ gt ]
+ *
+ * 28 24 20 16 12 8 4 0
+ * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
+ * [ engine_class ] [ engine_instance ] [ event ]
+ *
+ * engine_class and engine_instance bits will be applicable for
+ * per-engine-class activity events (engine-active-ticks, engine-total-ticks)
+ *
* The standard perf tool can be used to grep for a certain event as well.
* Example:
*
@@ -35,20 +48,34 @@
* $ perf stat -e <event_name,gt=> -I <interval>
*/
-#define XE_PMU_EVENT_GT_MASK GENMASK_ULL(63, 60)
-#define XE_PMU_EVENT_ID_MASK GENMASK_ULL(11, 0)
+#define XE_PMU_EVENT_GT_MASK GENMASK_ULL(63, 60)
+#define XE_PMU_EVENT_ENGINE_CLASS_MASK GENMASK_ULL(27, 20)
+#define XE_PMU_EVENT_ENGINE_INSTANCE_MASK GENMASK_ULL(19, 12)
+#define XE_PMU_EVENT_ID_MASK GENMASK_ULL(11, 0)
static unsigned int config_to_event_id(u64 config)
{
return FIELD_GET(XE_PMU_EVENT_ID_MASK, config);
}
+static unsigned int config_to_engine_class(u64 config)
+{
+ return FIELD_GET(XE_PMU_EVENT_ENGINE_CLASS_MASK, config);
+}
+
+static unsigned int config_to_engine_instance(u64 config)
+{
+ return FIELD_GET(XE_PMU_EVENT_ENGINE_INSTANCE_MASK, config);
+}
+
static unsigned int config_to_gt_id(u64 config)
{
return FIELD_GET(XE_PMU_EVENT_GT_MASK, config);
}
-#define XE_PMU_EVENT_GT_C6_RESIDENCY 0x01
+#define XE_PMU_EVENT_GT_C6_RESIDENCY 0x01
+#define XE_PMU_EVENT_ENGINE_ACTIVE_TICKS 0x02
+#define XE_PMU_EVENT_ENGINE_TOTAL_TICKS 0x03
static struct xe_gt *event_to_gt(struct perf_event *event)
{
@@ -58,6 +85,24 @@ static struct xe_gt *event_to_gt(struct perf_event *event)
return xe_device_get_gt(xe, gt);
}
+static struct xe_hw_engine *event_to_hwe(struct perf_event *event)
+{
+ struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base);
+ struct drm_xe_engine_class_instance eci;
+ u64 config = event->attr.config;
+ struct xe_hw_engine *hwe;
+
+ eci.engine_class = config_to_engine_class(config);
+ eci.engine_instance = config_to_engine_instance(config);
+ eci.gt_id = config_to_gt_id(config);
+
+ hwe = xe_hw_engine_lookup(xe, eci);
+ if (!hwe || xe_hw_engine_is_reserved(hwe))
+ return NULL;
+
+ return hwe;
+}
+
static bool event_supported(struct xe_pmu *pmu, unsigned int gt,
unsigned int id)
{
@@ -68,6 +113,35 @@ static bool event_supported(struct xe_pmu *pmu, unsigned int gt,
pmu->supported_events & BIT_ULL(id);
}
+static bool event_param_valid(struct perf_event *event)
+{
+ struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base);
+ unsigned int engine_class, engine_instance;
+ u64 config = event->attr.config;
+ struct xe_gt *gt;
+
+ gt = xe_device_get_gt(xe, config_to_gt_id(config));
+ if (!gt)
+ return false;
+
+ engine_class = config_to_engine_class(config);
+ engine_instance = config_to_engine_instance(config);
+
+ switch (config_to_event_id(config)) {
+ case XE_PMU_EVENT_GT_C6_RESIDENCY:
+ if (engine_class || engine_instance)
+ return false;
+ break;
+ case XE_PMU_EVENT_ENGINE_ACTIVE_TICKS:
+ case XE_PMU_EVENT_ENGINE_TOTAL_TICKS:
+ if (!event_to_hwe(event))
+ return false;
+ break;
+ }
+
+ return true;
+}
+
static void xe_pmu_event_destroy(struct perf_event *event)
{
struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base);
@@ -101,6 +175,9 @@ static int xe_pmu_event_init(struct perf_event *event)
if (!event_supported(pmu, gt, id))
return -ENOENT;
+ if (!event_param_valid(event))
+ return -ENOENT;
+
if (has_branch_stack(event))
return -EOPNOTSUPP;
@@ -113,6 +190,23 @@ static int xe_pmu_event_init(struct perf_event *event)
return 0;
}
+static u64 read_engine_events(struct perf_event *event)
+{
+ struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base);
+ struct xe_hw_engine *hwe;
+ u64 val = 0;
+
+ hwe = event_to_hwe(event);
+ if (!hwe)
+ drm_warn(&xe->drm, "unknown pmu engine\n");
+ else if (config_to_event_id(event->attr.config) == XE_PMU_EVENT_ENGINE_ACTIVE_TICKS)
+ val = xe_guc_engine_activity_active_ticks(hwe);
+ else
+ val = xe_guc_engine_activity_total_ticks(hwe);
+
+ return val;
+}
+
static u64 __xe_pmu_event_read(struct perf_event *event)
{
struct xe_gt *gt = event_to_gt(event);
@@ -123,6 +217,9 @@ static u64 __xe_pmu_event_read(struct perf_event *event)
switch (config_to_event_id(event->attr.config)) {
case XE_PMU_EVENT_GT_C6_RESIDENCY:
return xe_gt_idle_residency_msec(>->gtidle);
+ case XE_PMU_EVENT_ENGINE_ACTIVE_TICKS:
+ case XE_PMU_EVENT_ENGINE_TOTAL_TICKS:
+ return read_engine_events(event);
}
return 0;
@@ -207,11 +304,15 @@ static void xe_pmu_event_del(struct perf_event *event, int flags)
xe_pmu_event_stop(event, PERF_EF_UPDATE);
}
-PMU_FORMAT_ATTR(gt, "config:60-63");
-PMU_FORMAT_ATTR(event, "config:0-11");
+PMU_FORMAT_ATTR(gt, "config:60-63");
+PMU_FORMAT_ATTR(engine_class, "config:20-27");
+PMU_FORMAT_ATTR(engine_instance, "config:12-19");
+PMU_FORMAT_ATTR(event, "config:0-11");
static struct attribute *pmu_format_attrs[] = {
&format_attr_event.attr,
+ &format_attr_engine_class.attr,
+ &format_attr_engine_instance.attr,
&format_attr_gt.attr,
NULL,
};
@@ -270,6 +371,8 @@ static ssize_t event_attr_show(struct device *dev,
XE_EVENT_ATTR_GROUP(v_, id_, &pmu_event_ ##v_.attr.attr)
XE_EVENT_ATTR_SIMPLE(gt-c6-residency, gt_c6_residency, XE_PMU_EVENT_GT_C6_RESIDENCY, "ms");
+XE_EVENT_ATTR_NOUNIT(engine-active-ticks, engine_active_ticks, XE_PMU_EVENT_ENGINE_ACTIVE_TICKS);
+XE_EVENT_ATTR_NOUNIT(engine-total-ticks, engine_total_ticks, XE_PMU_EVENT_ENGINE_TOTAL_TICKS);
static struct attribute *pmu_empty_event_attrs[] = {
/* Empty - all events are added as groups with .attr_update() */
@@ -283,15 +386,23 @@ static const struct attribute_group pmu_events_attr_group = {
static const struct attribute_group *pmu_events_attr_update[] = {
&pmu_group_gt_c6_residency,
+ &pmu_group_engine_active_ticks,
+ &pmu_group_engine_total_ticks,
NULL,
};
static void set_supported_events(struct xe_pmu *pmu)
{
struct xe_device *xe = container_of(pmu, typeof(*xe), pmu);
+ struct xe_gt *gt = xe_device_get_gt(xe, 0);
if (!xe->info.skip_guc_pc)
pmu->supported_events |= BIT_ULL(XE_PMU_EVENT_GT_C6_RESIDENCY);
+
+ if (xe_guc_engine_activity_supported(>->uc.guc)) {
+ pmu->supported_events |= BIT_ULL(XE_PMU_EVENT_ENGINE_ACTIVE_TICKS);
+ pmu->supported_events |= BIT_ULL(XE_PMU_EVENT_ENGINE_TOTAL_TICKS);
+ }
}
/**
diff --git a/drivers/gpu/drm/xe/xe_uc.c b/drivers/gpu/drm/xe/xe_uc.c
index 0d073a9987c2..769905036b35 100644
--- a/drivers/gpu/drm/xe/xe_uc.c
+++ b/drivers/gpu/drm/xe/xe_uc.c
@@ -14,6 +14,7 @@
#include "xe_gt_sriov_vf.h"
#include "xe_guc.h"
#include "xe_guc_pc.h"
+#include "xe_guc_engine_activity.h"
#include "xe_huc.h"
#include "xe_sriov.h"
#include "xe_uc_fw.h"
@@ -210,6 +211,8 @@ int xe_uc_init_hw(struct xe_uc *uc)
if (ret)
return ret;
+ xe_guc_engine_activity_enable_stats(&uc->guc);
+
/* We don't fail the driver load if HuC fails to auth, but let's warn */
ret = xe_huc_auth(&uc->huc, XE_HUC_AUTH_VIA_GUC);
xe_gt_assert(uc_to_gt(uc), !ret);
--
2.47.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [PATCH v4 4/8] drm/xe/xe_pmu: Add PMU support for per-engine-class activity
2025-01-29 10:16 ` [PATCH v4 4/8] drm/xe/xe_pmu: Add PMU support for per-engine-class activity Riana Tauro
@ 2025-01-31 23:11 ` Umesh Nerlige Ramappa
2025-02-03 14:14 ` Riana Tauro
0 siblings, 1 reply; 45+ messages in thread
From: Umesh Nerlige Ramappa @ 2025-01-31 23:11 UTC (permalink / raw)
To: Riana Tauro
Cc: intel-xe, anshuman.gupta, lucas.demarchi, vinay.belgaumkar,
soham.purkait
On Wed, Jan 29, 2025 at 03:46:47PM +0530, Riana Tauro wrote:
>PMU provides two counters (engine-active-ticks, engine-total-ticks)
>to calculate engine activity. When querying engine activity,
>user must group these 2 counters using the perf_event
>group mechanism to ensure both counters are sampled together.
>
>To list the events
>
> ./perf list
> xe_0000_03_00.0/engine-active-ticks/ [Kernel PMU event]
> xe_0000_03_00.0/engine-total-ticks/ [Kernel PMU event]
checkpatch complains that the line is > 75 columns here. Maybe drop the
'[Kernel PMU event]' and move it to left:
./perf list
xe_0000_03_00.0/engine-active-ticks/
xe_0000_03_00.0/engine-total-ticks/
>
>The formats to be used with the above are
>
> engine_instance - config:12-19
> engine_class - config:20-27
> gt - config:60-63
>
>The events can then be read using perf tool
>
>./perf stat -e xe_0000_03_00.0/engine-active-ticks,gt=0,
> engine_class=0,engine_instance=0/,
> xe_0000_03_00.0/engine-total-ticks,gt=0,
> engine_class=0,engine_instance=0/ -I 1000
>
>Engine activity can then be calculated as below
>engine activity % = (engine active ticks/engine total ticks) * 100
>
>v2: validate gt
> rename total-ticks to engine-total-ticks
> add helper to get hwe (Umesh)
>
>Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>---
> drivers/gpu/drm/xe/xe_guc.c | 5 ++
> drivers/gpu/drm/xe/xe_pmu.c | 129 +++++++++++++++++++++++++++++++++---
> drivers/gpu/drm/xe/xe_uc.c | 3 +
> 3 files changed, 128 insertions(+), 9 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>index 1619c0a52db9..bc1ff0a4e1e7 100644
>--- a/drivers/gpu/drm/xe/xe_guc.c
>+++ b/drivers/gpu/drm/xe/xe_guc.c
>@@ -27,6 +27,7 @@
> #include "xe_guc_capture.h"
> #include "xe_guc_ct.h"
> #include "xe_guc_db_mgr.h"
>+#include "xe_guc_engine_activity.h"
> #include "xe_guc_hwconfig.h"
> #include "xe_guc_log.h"
> #include "xe_guc_pc.h"
>@@ -744,6 +745,10 @@ int xe_guc_init_post_hwconfig(struct xe_guc *guc)
> if (ret)
> return ret;
>
>+ ret = xe_guc_engine_activity_init(guc);
>+ if (ret)
>+ return ret;
>+
> ret = xe_guc_buf_cache_init(&guc->buf);
> if (ret)
> return ret;
>diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
>index 3910a82328ee..8ea78d8f7e2e 100644
>--- a/drivers/gpu/drm/xe/xe_pmu.c
>+++ b/drivers/gpu/drm/xe/xe_pmu.c
>@@ -8,15 +8,16 @@
>
> #include "xe_device.h"
> #include "xe_gt_idle.h"
>+#include "xe_guc_engine_activity.h"
>+#include "xe_hw_engine.h"
> #include "xe_pm.h"
> #include "xe_pmu.h"
>
> /**
> * DOC: Xe PMU (Performance Monitoring Unit)
> *
>- * Expose events/counters like GT-C6 residency and GT frequency to user land via
>- * the perf interface. Events are per device. The GT can be selected with an
>- * extra config sub-field (bits 60-63).
>+ * Expose events/counters like GT-C6 residency, GT frequency and per-class-engine
>+ * activity to user land via the perf interface. Events are per device.
> *
> * All events are listed in sysfs:
> *
>@@ -24,7 +25,19 @@
> * $ ls /sys/bus/event_source/devices/xe_0000_00_02.0/events/
> * $ ls /sys/bus/event_source/devices/xe_0000_00_02.0/format/
> *
>- * The format directory has info regarding the configs that can be used.
>+ * format directory configs:
>+ *
>+ * 60 56 52 48 44 40 36 32
>+ * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
>+ * [ gt ]
>+ *
>+ * 28 24 20 16 12 8 4 0
>+ * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
>+ * [ engine_class ] [ engine_instance ] [ event ]
>+ *
>+ * engine_class and engine_instance bits will be applicable for
>+ * per-engine-class activity events (engine-active-ticks, engine-total-ticks)
Please also mention that gt is applicable to the engine events as well.
Also a line saying "engine_class and engine_instance are not applicable
to gt events (like c6 and frequency)".
Ideally it would be good if there is an intuitive way for the user to
determine this association, maybe something like:
gt-<event>
/* gt should be passed in format for events like c6, freq etc. */
gt-engine-<event>
/* gt and engine* should be passed in format for active/total ticks */
but I am afraid that could just result in very long event names in
future, so I am okay with what it is now with the required documentation.
@Lucas, any thoughts here ^ ?
>+ *
> * The standard perf tool can be used to grep for a certain event as well.
> * Example:
> *
>@@ -35,20 +48,34 @@
> * $ perf stat -e <event_name,gt=> -I <interval>
> */
>
>-#define XE_PMU_EVENT_GT_MASK GENMASK_ULL(63, 60)
>-#define XE_PMU_EVENT_ID_MASK GENMASK_ULL(11, 0)
>+#define XE_PMU_EVENT_GT_MASK GENMASK_ULL(63, 60)
>+#define XE_PMU_EVENT_ENGINE_CLASS_MASK GENMASK_ULL(27, 20)
>+#define XE_PMU_EVENT_ENGINE_INSTANCE_MASK GENMASK_ULL(19, 12)
>+#define XE_PMU_EVENT_ID_MASK GENMASK_ULL(11, 0)
>
> static unsigned int config_to_event_id(u64 config)
> {
> return FIELD_GET(XE_PMU_EVENT_ID_MASK, config);
> }
>
>+static unsigned int config_to_engine_class(u64 config)
>+{
>+ return FIELD_GET(XE_PMU_EVENT_ENGINE_CLASS_MASK, config);
>+}
>+
>+static unsigned int config_to_engine_instance(u64 config)
>+{
>+ return FIELD_GET(XE_PMU_EVENT_ENGINE_INSTANCE_MASK, config);
>+}
>+
> static unsigned int config_to_gt_id(u64 config)
> {
> return FIELD_GET(XE_PMU_EVENT_GT_MASK, config);
> }
>
>-#define XE_PMU_EVENT_GT_C6_RESIDENCY 0x01
>+#define XE_PMU_EVENT_GT_C6_RESIDENCY 0x01
>+#define XE_PMU_EVENT_ENGINE_ACTIVE_TICKS 0x02
>+#define XE_PMU_EVENT_ENGINE_TOTAL_TICKS 0x03
checkpatch warning here ^ (space before tab)
Thanks,
Umesh
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 4/8] drm/xe/xe_pmu: Add PMU support for per-engine-class activity
2025-01-31 23:11 ` Umesh Nerlige Ramappa
@ 2025-02-03 14:14 ` Riana Tauro
2025-02-05 1:28 ` Umesh Nerlige Ramappa
0 siblings, 1 reply; 45+ messages in thread
From: Riana Tauro @ 2025-02-03 14:14 UTC (permalink / raw)
To: Umesh Nerlige Ramappa, lucas.demarchi
Cc: intel-xe, anshuman.gupta, vinay.belgaumkar, soham.purkait
Hi Umesh
On 2/1/2025 4:41 AM, Umesh Nerlige Ramappa wrote:
> On Wed, Jan 29, 2025 at 03:46:47PM +0530, Riana Tauro wrote:
>> PMU provides two counters (engine-active-ticks, engine-total-ticks)
>> to calculate engine activity. When querying engine activity,
>> user must group these 2 counters using the perf_event
>> group mechanism to ensure both counters are sampled together.
>>
>> To list the events
>>
>> ./perf list
>> xe_0000_03_00.0/engine-active-ticks/ [Kernel PMU event]
>> xe_0000_03_00.0/engine-total-ticks/ [Kernel PMU event]
>
> checkpatch complains that the line is > 75 columns here. Maybe drop the
> '[Kernel PMU event]' and move it to left:
>
> ./perf list
> xe_0000_03_00.0/engine-active-ticks/
> xe_0000_03_00.0/engine-total-ticks/
CI doesn't show this. Its below 75
>
>>
>> The formats to be used with the above are
>>
>> engine_instance - config:12-19
>> engine_class - config:20-27
>> gt - config:60-63
>>
>> The events can then be read using perf tool
>>
>> ./perf stat -e xe_0000_03_00.0/engine-active-ticks,gt=0,
>> engine_class=0,engine_instance=0/,
>> xe_0000_03_00.0/engine-total-ticks,gt=0,
>> engine_class=0,engine_instance=0/ -I 1000
>>
>> Engine activity can then be calculated as below
>> engine activity % = (engine active ticks/engine total ticks) * 100
>>
>> v2: validate gt
>> rename total-ticks to engine-total-ticks
>> add helper to get hwe (Umesh)
>>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_guc.c | 5 ++
>> drivers/gpu/drm/xe/xe_pmu.c | 129 +++++++++++++++++++++++++++++++++---
>> drivers/gpu/drm/xe/xe_uc.c | 3 +
>> 3 files changed, 128 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>> index 1619c0a52db9..bc1ff0a4e1e7 100644
>> --- a/drivers/gpu/drm/xe/xe_guc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>> @@ -27,6 +27,7 @@
>> #include "xe_guc_capture.h"
>> #include "xe_guc_ct.h"
>> #include "xe_guc_db_mgr.h"
>> +#include "xe_guc_engine_activity.h"
>> #include "xe_guc_hwconfig.h"
>> #include "xe_guc_log.h"
>> #include "xe_guc_pc.h"
>> @@ -744,6 +745,10 @@ int xe_guc_init_post_hwconfig(struct xe_guc *guc)
>> if (ret)
>> return ret;
>>
>> + ret = xe_guc_engine_activity_init(guc);
>> + if (ret)
>> + return ret;
>> +
>> ret = xe_guc_buf_cache_init(&guc->buf);
>> if (ret)
>> return ret;
>> diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
>> index 3910a82328ee..8ea78d8f7e2e 100644
>> --- a/drivers/gpu/drm/xe/xe_pmu.c
>> +++ b/drivers/gpu/drm/xe/xe_pmu.c
>> @@ -8,15 +8,16 @@
>>
>> #include "xe_device.h"
>> #include "xe_gt_idle.h"
>> +#include "xe_guc_engine_activity.h"
>> +#include "xe_hw_engine.h"
>> #include "xe_pm.h"
>> #include "xe_pmu.h"
>>
>> /**
>> * DOC: Xe PMU (Performance Monitoring Unit)
>> *
>> - * Expose events/counters like GT-C6 residency and GT frequency to
>> user land via
>> - * the perf interface. Events are per device. The GT can be selected
>> with an
>> - * extra config sub-field (bits 60-63).
>> + * Expose events/counters like GT-C6 residency, GT frequency and per-
>> class-engine
>> + * activity to user land via the perf interface. Events are per device.
>> *
>> * All events are listed in sysfs:
>> *
>> @@ -24,7 +25,19 @@
>> * $ ls /sys/bus/event_source/devices/xe_0000_00_02.0/events/
>> * $ ls /sys/bus/event_source/devices/xe_0000_00_02.0/format/
>> *
>> - * The format directory has info regarding the configs that can be used.
>> + * format directory configs:
>> + *
>> + * 60 56 52 48 44 40
>> 36 32
>> + * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - -
>> - - | - - - - |
>> + * [ gt ]
>> + *
>> + * 28 24 20 16 12
>> 8 4 0
>> + * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - -
>> - - | - - - - |
>> + * [ engine_class ] [ engine_instance ] [
>> event ]
>> + *
>> + * engine_class and engine_instance bits will be applicable for
>> + * per-engine-class activity events (engine-active-ticks, engine-
>> total-ticks)
>
> Please also mention that gt is applicable to the engine events as well.
>
> Also a line saying "engine_class and engine_instance are not applicable
> to gt events (like c6 and frequency)".
Is the below description okay ?
"if event[0:11] == (0x02 | 0x03) (engine-* events)
use engine_class[20:27], engine_instance[12:19] and gt[60:63] to select
the required engine of the gt
For the rest of the events use gt[60:63] to select gt. Rest of
the formats are not applicable"
>
> Ideally it would be good if there is an intuitive way for the user to
> determine this association, maybe something like:
>
> gt-<event>
> /* gt should be passed in format for events like c6, freq etc. */
>
> gt-engine-<event>
> /* gt and engine* should be passed in format for active/total ticks */
would be intuitive to find formats.
>
> but I am afraid that could just result in very long event names in
> future, so I am okay with what it is now with the required documentation.
>
> @Lucas, any thoughts here ^ ?
>
>> + *
>> * The standard perf tool can be used to grep for a certain event as
>> well.
>> * Example:
>> *
>> @@ -35,20 +48,34 @@
>> * $ perf stat -e <event_name,gt=> -I <interval>
>> */
>>
>> -#define XE_PMU_EVENT_GT_MASK GENMASK_ULL(63, 60)
>> -#define XE_PMU_EVENT_ID_MASK GENMASK_ULL(11, 0)
>> +#define XE_PMU_EVENT_GT_MASK GENMASK_ULL(63, 60)
>> +#define XE_PMU_EVENT_ENGINE_CLASS_MASK GENMASK_ULL(27, 20)
>> +#define XE_PMU_EVENT_ENGINE_INSTANCE_MASK GENMASK_ULL(19, 12)
>> +#define XE_PMU_EVENT_ID_MASK GENMASK_ULL(11, 0)
>>
>> static unsigned int config_to_event_id(u64 config)
>> {
>> return FIELD_GET(XE_PMU_EVENT_ID_MASK, config);
>> }
>>
>> +static unsigned int config_to_engine_class(u64 config)
>> +{
>> + return FIELD_GET(XE_PMU_EVENT_ENGINE_CLASS_MASK, config);
>> +}
>> +
>> +static unsigned int config_to_engine_instance(u64 config)
>> +{
>> + return FIELD_GET(XE_PMU_EVENT_ENGINE_INSTANCE_MASK, config);
>> +}
>> +
>> static unsigned int config_to_gt_id(u64 config)
>> {
>> return FIELD_GET(XE_PMU_EVENT_GT_MASK, config);
>> }
>>
>> -#define XE_PMU_EVENT_GT_C6_RESIDENCY 0x01
>> +#define XE_PMU_EVENT_GT_C6_RESIDENCY 0x01
>> +#define XE_PMU_EVENT_ENGINE_ACTIVE_TICKS 0x02
>> +#define XE_PMU_EVENT_ENGINE_TOTAL_TICKS 0x03
>
> checkpatch warning here ^ (space before tab)
Will fix this
Thanks
Riana Tauro
>
> Thanks,
> Umesh
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 4/8] drm/xe/xe_pmu: Add PMU support for per-engine-class activity
2025-02-03 14:14 ` Riana Tauro
@ 2025-02-05 1:28 ` Umesh Nerlige Ramappa
0 siblings, 0 replies; 45+ messages in thread
From: Umesh Nerlige Ramappa @ 2025-02-05 1:28 UTC (permalink / raw)
To: Riana Tauro
Cc: lucas.demarchi, intel-xe, anshuman.gupta, vinay.belgaumkar,
soham.purkait
On Mon, Feb 03, 2025 at 07:44:27PM +0530, Riana Tauro wrote:
>Hi Umesh
>
>On 2/1/2025 4:41 AM, Umesh Nerlige Ramappa wrote:
>>On Wed, Jan 29, 2025 at 03:46:47PM +0530, Riana Tauro wrote:
>>>PMU provides two counters (engine-active-ticks, engine-total-ticks)
>>>to calculate engine activity. When querying engine activity,
>>>user must group these 2 counters using the perf_event
>>>group mechanism to ensure both counters are sampled together.
>>>
>>>To list the events
>>>
>>> ./perf list
>>> xe_0000_03_00.0/engine-active-ticks/ [Kernel PMU event]
>>> xe_0000_03_00.0/engine-total-ticks/ [Kernel PMU event]
>>
>>checkpatch complains that the line is > 75 columns here. Maybe drop the
>>'[Kernel PMU event]' and move it to left:
>>
>>./perf list
>> xe_0000_03_00.0/engine-active-ticks/
>> xe_0000_03_00.0/engine-total-ticks/
>CI doesn't show this. Its below 75
oh, my bad
>>
>>>
>>>The formats to be used with the above are
>>>
>>> engine_instance - config:12-19
>>> engine_class - config:20-27
>>> gt - config:60-63
>>>
>>>The events can then be read using perf tool
>>>
>>>./perf stat -e xe_0000_03_00.0/engine-active-ticks,gt=0,
>>> engine_class=0,engine_instance=0/,
>>> xe_0000_03_00.0/engine-total-ticks,gt=0,
>>> engine_class=0,engine_instance=0/ -I 1000
>>>
>>>Engine activity can then be calculated as below
>>>engine activity % = (engine active ticks/engine total ticks) * 100
>>>
>>>v2: validate gt
>>> rename total-ticks to engine-total-ticks
>>> add helper to get hwe (Umesh)
>>>
>>>Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>>>---
>>>drivers/gpu/drm/xe/xe_guc.c | 5 ++
>>>drivers/gpu/drm/xe/xe_pmu.c | 129 +++++++++++++++++++++++++++++++++---
>>>drivers/gpu/drm/xe/xe_uc.c | 3 +
>>>3 files changed, 128 insertions(+), 9 deletions(-)
>>>
>>>diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>>>index 1619c0a52db9..bc1ff0a4e1e7 100644
>>>--- a/drivers/gpu/drm/xe/xe_guc.c
>>>+++ b/drivers/gpu/drm/xe/xe_guc.c
>>>@@ -27,6 +27,7 @@
>>>#include "xe_guc_capture.h"
>>>#include "xe_guc_ct.h"
>>>#include "xe_guc_db_mgr.h"
>>>+#include "xe_guc_engine_activity.h"
>>>#include "xe_guc_hwconfig.h"
>>>#include "xe_guc_log.h"
>>>#include "xe_guc_pc.h"
>>>@@ -744,6 +745,10 @@ int xe_guc_init_post_hwconfig(struct xe_guc *guc)
>>> if (ret)
>>> return ret;
>>>
>>>+ ret = xe_guc_engine_activity_init(guc);
>>>+ if (ret)
>>>+ return ret;
>>>+
>>> ret = xe_guc_buf_cache_init(&guc->buf);
>>> if (ret)
>>> return ret;
>>>diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
>>>index 3910a82328ee..8ea78d8f7e2e 100644
>>>--- a/drivers/gpu/drm/xe/xe_pmu.c
>>>+++ b/drivers/gpu/drm/xe/xe_pmu.c
>>>@@ -8,15 +8,16 @@
>>>
>>>#include "xe_device.h"
>>>#include "xe_gt_idle.h"
>>>+#include "xe_guc_engine_activity.h"
>>>+#include "xe_hw_engine.h"
>>>#include "xe_pm.h"
>>>#include "xe_pmu.h"
>>>
>>>/**
>>> * DOC: Xe PMU (Performance Monitoring Unit)
>>> *
>>>- * Expose events/counters like GT-C6 residency and GT frequency
>>>to user land via
>>>- * the perf interface. Events are per device. The GT can be
>>>selected with an
>>>- * extra config sub-field (bits 60-63).
>>>+ * Expose events/counters like GT-C6 residency, GT frequency and
>>>per- class-engine
>>>+ * activity to user land via the perf interface. Events are per device.
>>> *
>>> * All events are listed in sysfs:
>>> *
>>>@@ -24,7 +25,19 @@
>>> * $ ls /sys/bus/event_source/devices/xe_0000_00_02.0/events/
>>> * $ ls /sys/bus/event_source/devices/xe_0000_00_02.0/format/
>>> *
>>>- * The format directory has info regarding the configs that can be used.
>>>+ * format directory configs:
>>>+ *
>>>+ * 60 56 52 48 44 40
>>>36 32
>>>+ * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
>>>- - - - | - - - - |
>>>+ * [ gt ]
>>>+ *
>>>+ * 28 24 20 16 12
>>>8 4 0
>>>+ * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
>>>- - - - | - - - - |
>>>+ * [ engine_class ] [ engine_instance ] [
>>>event ]
>>>+ *
>>>+ * engine_class and engine_instance bits will be applicable for
>>>+ * per-engine-class activity events (engine-active-ticks, engine-
>>>total-ticks)
>>
>>Please also mention that gt is applicable to the engine events as well.
>>
>>Also a line saying "engine_class and engine_instance are not
>>applicable to gt events (like c6 and frequency)".
>
>Is the below description okay ?
>
>"if event[0:11] == (0x02 | 0x03) (engine-* events)
>use engine_class[20:27], engine_instance[12:19] and gt[60:63] to select
>the required engine of the gt
>
>For the rest of the events use gt[60:63] to select gt. Rest of
>the formats are not applicable"
Note that I would only mention events known to us today. If more are
added in future, doc needs to be updated.
Something like this:
The following format parameters are available to read events, but only
some are valid with each event:
gt[60:63] Selects gt for the event
engine_class[20:27] Selects engine-class for event
engine_instance[12:19] Selects the engine-instance for the event
vf_id/function[x:y] Selects the function of the event
For engine specific events (engine-*), gt, engine_class and
engine_instance parameters must be passed/set as populated by the
DRM_XE_DEVICE_QUERY_ENGINES.
For gt specific events (gt-*) gt parameter must be passed. All other
parameters must be set to 0.
Thanks,
Umesh
>>
>>Ideally it would be good if there is an intuitive way for the user to
>>determine this association, maybe something like:
>>
>>gt-<event>
>>/* gt should be passed in format for events like c6, freq etc. */
>>
>>gt-engine-<event>
>>/* gt and engine* should be passed in format for active/total ticks */
>would be intuitive to find formats.
>>
>>but I am afraid that could just result in very long event names in
>>future, so I am okay with what it is now with the required
>>documentation.
>>
>>@Lucas, any thoughts here ^ ?
>>
>>>+ *
>>> * The standard perf tool can be used to grep for a certain event
>>>as well.
>>> * Example:
>>> *
>>>@@ -35,20 +48,34 @@
>>> * $ perf stat -e <event_name,gt=> -I <interval>
>>> */
>>>
>>>-#define XE_PMU_EVENT_GT_MASK GENMASK_ULL(63, 60)
>>>-#define XE_PMU_EVENT_ID_MASK GENMASK_ULL(11, 0)
>>>+#define XE_PMU_EVENT_GT_MASK GENMASK_ULL(63, 60)
>>>+#define XE_PMU_EVENT_ENGINE_CLASS_MASK GENMASK_ULL(27, 20)
>>>+#define XE_PMU_EVENT_ENGINE_INSTANCE_MASK GENMASK_ULL(19, 12)
>>>+#define XE_PMU_EVENT_ID_MASK GENMASK_ULL(11, 0)
>>>
>>>static unsigned int config_to_event_id(u64 config)
>>>{
>>> return FIELD_GET(XE_PMU_EVENT_ID_MASK, config);
>>>}
>>>
>>>+static unsigned int config_to_engine_class(u64 config)
>>>+{
>>>+ return FIELD_GET(XE_PMU_EVENT_ENGINE_CLASS_MASK, config);
>>>+}
>>>+
>>>+static unsigned int config_to_engine_instance(u64 config)
>>>+{
>>>+ return FIELD_GET(XE_PMU_EVENT_ENGINE_INSTANCE_MASK, config);
>>>+}
>>>+
>>>static unsigned int config_to_gt_id(u64 config)
>>>{
>>> return FIELD_GET(XE_PMU_EVENT_GT_MASK, config);
>>>}
>>>
>>>-#define XE_PMU_EVENT_GT_C6_RESIDENCY 0x01
>>>+#define XE_PMU_EVENT_GT_C6_RESIDENCY 0x01
>>>+#define XE_PMU_EVENT_ENGINE_ACTIVE_TICKS 0x02
>>>+#define XE_PMU_EVENT_ENGINE_TOTAL_TICKS 0x03
>>
>>checkpatch warning here ^ (space before tab)
>Will fix this
>
>Thanks
>Riana Tauro
>>
>>Thanks,
>>Umesh
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH v4 5/8] drm/xe/guc: Bump minimum required GuC version to v70.36.0
2025-01-29 10:16 [PATCH v4 0/8] PMU Support for per-engine-class activity Riana Tauro
` (3 preceding siblings ...)
2025-01-29 10:16 ` [PATCH v4 4/8] drm/xe/xe_pmu: Add PMU support for per-engine-class activity Riana Tauro
@ 2025-01-29 10:16 ` Riana Tauro
2025-01-30 17:40 ` Umesh Nerlige Ramappa
2025-01-30 20:04 ` John Harrison
2025-01-29 10:16 ` [PATCH v4 6/8] drm/xe: Add support for per-function engine activity Riana Tauro
` (11 subsequent siblings)
16 siblings, 2 replies; 45+ messages in thread
From: Riana Tauro @ 2025-01-29 10:16 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, umesh.nerlige.ramappa,
lucas.demarchi, vinay.belgaumkar, soham.purkait
The VF API version for this release is 1.17.1
Bump the minimum required version to v70.36.0 to support
engine activity.
Suggested-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/xe_uc_fw.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index 18e06ee9e23f..d9ff285c5d1d 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -108,17 +108,17 @@ struct fw_blobs_by_type {
#define XE_GUC_FIRMWARE_DEFS(fw_def, mmp_ver, major_ver) \
fw_def(PANTHERLAKE, mmp_ver(xe, guc, ptl, 70, 38, 1)) \
- fw_def(BATTLEMAGE, major_ver(xe, guc, bmg, 70, 29, 2)) \
- fw_def(LUNARLAKE, major_ver(xe, guc, lnl, 70, 29, 2)) \
- fw_def(METEORLAKE, major_ver(i915, guc, mtl, 70, 29, 2)) \
- fw_def(PVC, mmp_ver(xe, guc, pvc, 70, 29, 2)) \
- fw_def(DG2, major_ver(i915, guc, dg2, 70, 29, 2)) \
- fw_def(DG1, major_ver(i915, guc, dg1, 70, 29, 2)) \
- fw_def(ALDERLAKE_N, major_ver(i915, guc, tgl, 70, 29, 2)) \
- fw_def(ALDERLAKE_P, major_ver(i915, guc, adlp, 70, 29, 2)) \
- fw_def(ALDERLAKE_S, major_ver(i915, guc, tgl, 70, 29, 2)) \
- fw_def(ROCKETLAKE, major_ver(i915, guc, tgl, 70, 29, 2)) \
- fw_def(TIGERLAKE, major_ver(i915, guc, tgl, 70, 29, 2))
+ fw_def(BATTLEMAGE, major_ver(xe, guc, bmg, 70, 36, 0)) \
+ fw_def(LUNARLAKE, major_ver(xe, guc, lnl, 70, 36, 0)) \
+ fw_def(METEORLAKE, major_ver(i915, guc, mtl, 70, 36, 0)) \
+ fw_def(PVC, mmp_ver(xe, guc, pvc, 70, 36, 0)) \
+ fw_def(DG2, major_ver(i915, guc, dg2, 70, 36, 0)) \
+ fw_def(DG1, major_ver(i915, guc, dg1, 70, 36, 0)) \
+ fw_def(ALDERLAKE_N, major_ver(i915, guc, tgl, 70, 36, 0)) \
+ fw_def(ALDERLAKE_P, major_ver(i915, guc, adlp, 70, 36, 0)) \
+ fw_def(ALDERLAKE_S, major_ver(i915, guc, tgl, 70, 36, 0)) \
+ fw_def(ROCKETLAKE, major_ver(i915, guc, tgl, 70, 36, 0)) \
+ fw_def(TIGERLAKE, major_ver(i915, guc, tgl, 70, 36, 0))
#define XE_HUC_FIRMWARE_DEFS(fw_def, mmp_ver, no_ver) \
fw_def(PANTHERLAKE, mmp_ver(xe, huc, ptl, 10, 2, 1)) \
@@ -320,9 +320,9 @@ static int guc_read_css_info(struct xe_uc_fw *uc_fw, struct uc_css_header *css)
xe_gt_assert(gt, uc_fw->type == XE_UC_FW_TYPE_GUC);
- /* We don't support GuC releases older than 70.29.2 */
- if (MAKE_GUC_VER_STRUCT(*release) < MAKE_GUC_VER(70, 29, 2)) {
- xe_gt_err(gt, "Unsupported GuC v%u.%u.%u! v70.29.2 or newer is required\n",
+ /* We don't support GuC releases older than 70.36.0 */
+ if (MAKE_GUC_VER_STRUCT(*release) < MAKE_GUC_VER(70, 36, 0)) {
+ xe_gt_err(gt, "Unsupported GuC v%u.%u.%u! v70.36.0 or newer is required\n",
release->major, release->minor, release->patch);
return -EINVAL;
}
--
2.47.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [PATCH v4 5/8] drm/xe/guc: Bump minimum required GuC version to v70.36.0
2025-01-29 10:16 ` [PATCH v4 5/8] drm/xe/guc: Bump minimum required GuC version to v70.36.0 Riana Tauro
@ 2025-01-30 17:40 ` Umesh Nerlige Ramappa
2025-01-30 20:04 ` John Harrison
1 sibling, 0 replies; 45+ messages in thread
From: Umesh Nerlige Ramappa @ 2025-01-30 17:40 UTC (permalink / raw)
To: Riana Tauro
Cc: intel-xe, anshuman.gupta, lucas.demarchi, vinay.belgaumkar,
soham.purkait, john.c.harrison
On Wed, Jan 29, 2025 at 03:46:48PM +0530, Riana Tauro wrote:
>The VF API version for this release is 1.17.1
>
>Bump the minimum required version to v70.36.0 to support
>engine activity.
+ John, since he mentioned offline that some platforms require a
specific version here.
Regards,
Umesh
>
>Suggested-by: John Harrison <John.C.Harrison@Intel.com>
>Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>---
> drivers/gpu/drm/xe/xe_uc_fw.c | 28 ++++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
>index 18e06ee9e23f..d9ff285c5d1d 100644
>--- a/drivers/gpu/drm/xe/xe_uc_fw.c
>+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
>@@ -108,17 +108,17 @@ struct fw_blobs_by_type {
>
> #define XE_GUC_FIRMWARE_DEFS(fw_def, mmp_ver, major_ver) \
> fw_def(PANTHERLAKE, mmp_ver(xe, guc, ptl, 70, 38, 1)) \
>- fw_def(BATTLEMAGE, major_ver(xe, guc, bmg, 70, 29, 2)) \
>- fw_def(LUNARLAKE, major_ver(xe, guc, lnl, 70, 29, 2)) \
>- fw_def(METEORLAKE, major_ver(i915, guc, mtl, 70, 29, 2)) \
>- fw_def(PVC, mmp_ver(xe, guc, pvc, 70, 29, 2)) \
>- fw_def(DG2, major_ver(i915, guc, dg2, 70, 29, 2)) \
>- fw_def(DG1, major_ver(i915, guc, dg1, 70, 29, 2)) \
>- fw_def(ALDERLAKE_N, major_ver(i915, guc, tgl, 70, 29, 2)) \
>- fw_def(ALDERLAKE_P, major_ver(i915, guc, adlp, 70, 29, 2)) \
>- fw_def(ALDERLAKE_S, major_ver(i915, guc, tgl, 70, 29, 2)) \
>- fw_def(ROCKETLAKE, major_ver(i915, guc, tgl, 70, 29, 2)) \
>- fw_def(TIGERLAKE, major_ver(i915, guc, tgl, 70, 29, 2))
>+ fw_def(BATTLEMAGE, major_ver(xe, guc, bmg, 70, 36, 0)) \
>+ fw_def(LUNARLAKE, major_ver(xe, guc, lnl, 70, 36, 0)) \
>+ fw_def(METEORLAKE, major_ver(i915, guc, mtl, 70, 36, 0)) \
>+ fw_def(PVC, mmp_ver(xe, guc, pvc, 70, 36, 0)) \
>+ fw_def(DG2, major_ver(i915, guc, dg2, 70, 36, 0)) \
>+ fw_def(DG1, major_ver(i915, guc, dg1, 70, 36, 0)) \
>+ fw_def(ALDERLAKE_N, major_ver(i915, guc, tgl, 70, 36, 0)) \
>+ fw_def(ALDERLAKE_P, major_ver(i915, guc, adlp, 70, 36, 0)) \
>+ fw_def(ALDERLAKE_S, major_ver(i915, guc, tgl, 70, 36, 0)) \
>+ fw_def(ROCKETLAKE, major_ver(i915, guc, tgl, 70, 36, 0)) \
>+ fw_def(TIGERLAKE, major_ver(i915, guc, tgl, 70, 36, 0))
>
> #define XE_HUC_FIRMWARE_DEFS(fw_def, mmp_ver, no_ver) \
> fw_def(PANTHERLAKE, mmp_ver(xe, huc, ptl, 10, 2, 1)) \
>@@ -320,9 +320,9 @@ static int guc_read_css_info(struct xe_uc_fw *uc_fw, struct uc_css_header *css)
>
> xe_gt_assert(gt, uc_fw->type == XE_UC_FW_TYPE_GUC);
>
>- /* We don't support GuC releases older than 70.29.2 */
>- if (MAKE_GUC_VER_STRUCT(*release) < MAKE_GUC_VER(70, 29, 2)) {
>- xe_gt_err(gt, "Unsupported GuC v%u.%u.%u! v70.29.2 or newer is required\n",
>+ /* We don't support GuC releases older than 70.36.0 */
>+ if (MAKE_GUC_VER_STRUCT(*release) < MAKE_GUC_VER(70, 36, 0)) {
>+ xe_gt_err(gt, "Unsupported GuC v%u.%u.%u! v70.36.0 or newer is required\n",
> release->major, release->minor, release->patch);
> return -EINVAL;
> }
>--
>2.47.1
>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 5/8] drm/xe/guc: Bump minimum required GuC version to v70.36.0
2025-01-29 10:16 ` [PATCH v4 5/8] drm/xe/guc: Bump minimum required GuC version to v70.36.0 Riana Tauro
2025-01-30 17:40 ` Umesh Nerlige Ramappa
@ 2025-01-30 20:04 ` John Harrison
2025-01-31 7:01 ` Riana Tauro
1 sibling, 1 reply; 45+ messages in thread
From: John Harrison @ 2025-01-30 20:04 UTC (permalink / raw)
To: Riana Tauro, intel-xe
Cc: anshuman.gupta, umesh.nerlige.ramappa, lucas.demarchi,
vinay.belgaumkar, soham.purkait
On 1/29/2025 02:16, Riana Tauro wrote:
> The VF API version for this release is 1.17.1
>
> Bump the minimum required version to v70.36.0 to support
> engine activity.
We can only bump the minimum recommended version, not the required version.
>
> Suggested-by: John Harrison <John.C.Harrison@Intel.com>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
> drivers/gpu/drm/xe/xe_uc_fw.c | 28 ++++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
> index 18e06ee9e23f..d9ff285c5d1d 100644
> --- a/drivers/gpu/drm/xe/xe_uc_fw.c
> +++ b/drivers/gpu/drm/xe/xe_uc_fw.c
> @@ -108,17 +108,17 @@ struct fw_blobs_by_type {
>
> #define XE_GUC_FIRMWARE_DEFS(fw_def, mmp_ver, major_ver) \
> fw_def(PANTHERLAKE, mmp_ver(xe, guc, ptl, 70, 38, 1)) \
> - fw_def(BATTLEMAGE, major_ver(xe, guc, bmg, 70, 29, 2)) \
> - fw_def(LUNARLAKE, major_ver(xe, guc, lnl, 70, 29, 2)) \
> - fw_def(METEORLAKE, major_ver(i915, guc, mtl, 70, 29, 2)) \
> - fw_def(PVC, mmp_ver(xe, guc, pvc, 70, 29, 2)) \
> - fw_def(DG2, major_ver(i915, guc, dg2, 70, 29, 2)) \
> - fw_def(DG1, major_ver(i915, guc, dg1, 70, 29, 2)) \
> - fw_def(ALDERLAKE_N, major_ver(i915, guc, tgl, 70, 29, 2)) \
> - fw_def(ALDERLAKE_P, major_ver(i915, guc, adlp, 70, 29, 2)) \
> - fw_def(ALDERLAKE_S, major_ver(i915, guc, tgl, 70, 29, 2)) \
> - fw_def(ROCKETLAKE, major_ver(i915, guc, tgl, 70, 29, 2)) \
> - fw_def(TIGERLAKE, major_ver(i915, guc, tgl, 70, 29, 2))
> + fw_def(BATTLEMAGE, major_ver(xe, guc, bmg, 70, 36, 0)) \
> + fw_def(LUNARLAKE, major_ver(xe, guc, lnl, 70, 36, 0)) \
> + fw_def(METEORLAKE, major_ver(i915, guc, mtl, 70, 36, 0)) \
> + fw_def(PVC, mmp_ver(xe, guc, pvc, 70, 36, 0)) \
> + fw_def(DG2, major_ver(i915, guc, dg2, 70, 36, 0)) \
> + fw_def(DG1, major_ver(i915, guc, dg1, 70, 36, 0)) \
> + fw_def(ALDERLAKE_N, major_ver(i915, guc, tgl, 70, 36, 0)) \
> + fw_def(ALDERLAKE_P, major_ver(i915, guc, adlp, 70, 36, 0)) \
> + fw_def(ALDERLAKE_S, major_ver(i915, guc, tgl, 70, 36, 0)) \
> + fw_def(ROCKETLAKE, major_ver(i915, guc, tgl, 70, 36, 0)) \
> + fw_def(TIGERLAKE, major_ver(i915, guc, tgl, 70, 36, 0))
This part is technically fine, but note that we have just discovered an
issue with recent GuC releases which means we need to wait for a bug fix
before updating.
Also note that the purpose of the minor/patch version numbers in this
table is just to provide a notice to the user that they should update.
So after the update to 70.36.0, if a user boots a LNL with 70.29.2, they
will get a line in dmesg saying "please update". But the driver will
still load and run with no negative effects.
>
> #define XE_HUC_FIRMWARE_DEFS(fw_def, mmp_ver, no_ver) \
> fw_def(PANTHERLAKE, mmp_ver(xe, huc, ptl, 10, 2, 1)) \
> @@ -320,9 +320,9 @@ static int guc_read_css_info(struct xe_uc_fw *uc_fw, struct uc_css_header *css)
>
> xe_gt_assert(gt, uc_fw->type == XE_UC_FW_TYPE_GUC);
>
> - /* We don't support GuC releases older than 70.29.2 */
> - if (MAKE_GUC_VER_STRUCT(*release) < MAKE_GUC_VER(70, 29, 2)) {
> - xe_gt_err(gt, "Unsupported GuC v%u.%u.%u! v70.29.2 or newer is required\n",
> + /* We don't support GuC releases older than 70.36.0 */
> + if (MAKE_GUC_VER_STRUCT(*release) < MAKE_GUC_VER(70, 36, 0)) {
> + xe_gt_err(gt, "Unsupported GuC v%u.%u.%u! v70.36.0 or newer is required\n",
This is definitely not allowed.
Once a GuC has been released for a given platform, it must be supported
forever on that platform. Which means that LNL and BMG must forever be
able to run on 70.29.2.
If we really need to, we can add a per platform variant of this check
for new platforms. E.g. PTL must be at least 70.39.42 or whatever. But
we can't ever change the Xe global base line version. And there isn't
much point in adding a new platform baseline because we just don't push
the firmware upstream for new platforms until we are ready to do an
official release. So there simply aren't any other versions available to
warrant a baseline version check.
Rather than bumping the baseline here, individual features must check
for a suitable GuC version. Which is what you have in patch #3 - the
check for GUC_VER(1.14.1). That ensures that the new feature will not
try to run if a new enough GuC is not available on the user's system.
John.
> release->major, release->minor, release->patch);
> return -EINVAL;
> }
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 5/8] drm/xe/guc: Bump minimum required GuC version to v70.36.0
2025-01-30 20:04 ` John Harrison
@ 2025-01-31 7:01 ` Riana Tauro
0 siblings, 0 replies; 45+ messages in thread
From: Riana Tauro @ 2025-01-31 7:01 UTC (permalink / raw)
To: John Harrison, intel-xe
Cc: anshuman.gupta, umesh.nerlige.ramappa, lucas.demarchi,
vinay.belgaumkar, soham.purkait
Hi John
On 1/31/2025 1:34 AM, John Harrison wrote:
> On 1/29/2025 02:16, Riana Tauro wrote:
>> The VF API version for this release is 1.17.1
>>
>> Bump the minimum required version to v70.36.0 to support
>> engine activity.
> We can only bump the minimum recommended version, not the required version.
I took the reference of 70.29.2 patch for this.
>
>>
>> Suggested-by: John Harrison <John.C.Harrison@Intel.com>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_uc_fw.c | 28 ++++++++++++++--------------
>> 1 file changed, 14 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/
>> xe_uc_fw.c
>> index 18e06ee9e23f..d9ff285c5d1d 100644
>> --- a/drivers/gpu/drm/xe/xe_uc_fw.c
>> +++ b/drivers/gpu/drm/xe/xe_uc_fw.c
>> @@ -108,17 +108,17 @@ struct fw_blobs_by_type {
>> #define XE_GUC_FIRMWARE_DEFS(fw_def, mmp_ver, major_ver) \
>> fw_def(PANTHERLAKE, mmp_ver(xe, guc, ptl, 70, 38,
>> 1)) \
>> - fw_def(BATTLEMAGE, major_ver(xe, guc, bmg, 70, 29,
>> 2)) \
>> - fw_def(LUNARLAKE, major_ver(xe, guc, lnl, 70, 29,
>> 2)) \
>> - fw_def(METEORLAKE, major_ver(i915, guc, mtl, 70, 29,
>> 2)) \
>> - fw_def(PVC, mmp_ver(xe, guc, pvc, 70, 29, 2)) \
>> - fw_def(DG2, major_ver(i915, guc, dg2, 70, 29,
>> 2)) \
>> - fw_def(DG1, major_ver(i915, guc, dg1, 70, 29,
>> 2)) \
>> - fw_def(ALDERLAKE_N, major_ver(i915, guc, tgl, 70, 29,
>> 2)) \
>> - fw_def(ALDERLAKE_P, major_ver(i915, guc, adlp, 70,
>> 29, 2)) \
>> - fw_def(ALDERLAKE_S, major_ver(i915, guc, tgl, 70, 29,
>> 2)) \
>> - fw_def(ROCKETLAKE, major_ver(i915, guc, tgl, 70, 29,
>> 2)) \
>> - fw_def(TIGERLAKE, major_ver(i915, guc, tgl, 70, 29, 2))
>> + fw_def(BATTLEMAGE, major_ver(xe, guc, bmg, 70, 36,
>> 0)) \
>> + fw_def(LUNARLAKE, major_ver(xe, guc, lnl, 70, 36,
>> 0)) \
>> + fw_def(METEORLAKE, major_ver(i915, guc, mtl, 70, 36,
>> 0)) \
>> + fw_def(PVC, mmp_ver(xe, guc, pvc, 70, 36, 0)) \
>> + fw_def(DG2, major_ver(i915, guc, dg2, 70, 36,
>> 0)) \
>> + fw_def(DG1, major_ver(i915, guc, dg1, 70, 36,
>> 0)) \
>> + fw_def(ALDERLAKE_N, major_ver(i915, guc, tgl, 70, 36,
>> 0)) \
>> + fw_def(ALDERLAKE_P, major_ver(i915, guc, adlp, 70,
>> 36, 0)) \
>> + fw_def(ALDERLAKE_S, major_ver(i915, guc, tgl, 70, 36,
>> 0)) \
>> + fw_def(ROCKETLAKE, major_ver(i915, guc, tgl, 70, 36,
>> 0)) \
>> + fw_def(TIGERLAKE, major_ver(i915, guc, tgl, 70, 36, 0))
> This part is technically fine, but note that we have just discovered an
> issue with recent GuC releases which means we need to wait for a bug fix
> before updating.
I added this as per your suggestion in the last rev. Should i drop this
from the series till the guc release with the bug fix comes in?
>
> Also note that the purpose of the minor/patch version numbers in this
> table is just to provide a notice to the user that they should update.
> So after the update to 70.36.0, if a user boots a LNL with 70.29.2, they
> will get a line in dmesg saying "please update". But the driver will
> still load and run with no negative effects.
>
>> #define XE_HUC_FIRMWARE_DEFS(fw_def, mmp_ver, no_ver) \
>> fw_def(PANTHERLAKE, mmp_ver(xe, huc, ptl, 10, 2,
>> 1)) \
>> @@ -320,9 +320,9 @@ static int guc_read_css_info(struct xe_uc_fw
>> *uc_fw, struct uc_css_header *css)
>> xe_gt_assert(gt, uc_fw->type == XE_UC_FW_TYPE_GUC);
>> - /* We don't support GuC releases older than 70.29.2 */
>> - if (MAKE_GUC_VER_STRUCT(*release) < MAKE_GUC_VER(70, 29, 2)) {
>> - xe_gt_err(gt, "Unsupported GuC v%u.%u.%u! v70.29.2 or newer
>> is required\n",
>> + /* We don't support GuC releases older than 70.36.0 */
>> + if (MAKE_GUC_VER_STRUCT(*release) < MAKE_GUC_VER(70, 36, 0)) {
>> + xe_gt_err(gt, "Unsupported GuC v%u.%u.%u! v70.36.0 or newer
>> is required\n",
> This is definitely not allowed.
>
> Once a GuC has been released for a given platform, it must be supported
> forever on that platform. Which means that LNL and BMG must forever be
> able to run on 70.29.2.
>
> If we really need to, we can add a per platform variant of this check
> for new platforms. E.g. PTL must be at least 70.39.42 or whatever. But
> we can't ever change the Xe global base line version. And there isn't
> much point in adding a new platform baseline because we just don't push
> the firmware upstream for new platforms until we are ready to do an
> official release. So there simply aren't any other versions available to
> warrant a baseline version check.
>
> Rather than bumping the baseline here, individual features must check
> for a suitable GuC version. Which is what you have in patch #3 - the
> check for GUC_VER(1.14.1). That ensures that the new feature will not
> try to run if a new enough GuC is not available on the user's system.
Sorry about that. I took the reference of the patch 70.29.2. Looks like
that was intended for baseline update.
I will drop the baseline update.
Thanks
Riana
>
> John.
>
>> release->major, release->minor, release->patch);
>> return -EINVAL;
>> }
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH v4 6/8] drm/xe: Add support for per-function engine activity
2025-01-29 10:16 [PATCH v4 0/8] PMU Support for per-engine-class activity Riana Tauro
` (4 preceding siblings ...)
2025-01-29 10:16 ` [PATCH v4 5/8] drm/xe/guc: Bump minimum required GuC version to v70.36.0 Riana Tauro
@ 2025-01-29 10:16 ` Riana Tauro
2025-01-31 23:52 ` Umesh Nerlige Ramappa
2025-01-29 10:16 ` [PATCH v4 7/8] drm/xe/xe_pmu: Add pmu support for per-function engine activity stats Riana Tauro
` (10 subsequent siblings)
16 siblings, 1 reply; 45+ messages in thread
From: Riana Tauro @ 2025-01-29 10:16 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, umesh.nerlige.ramappa,
lucas.demarchi, vinay.belgaumkar, soham.purkait
Add support for function level per-engine-class activity stats.
This is enabled when sriov_numvfs is set and disabled when vf's
are disabled.
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/abi/guc_actions_abi.h | 1 +
drivers/gpu/drm/xe/xe_guc_engine_activity.c | 200 +++++++++++++++---
drivers/gpu/drm/xe/xe_guc_engine_activity.h | 5 +-
.../gpu/drm/xe/xe_guc_engine_activity_types.h | 8 +-
drivers/gpu/drm/xe/xe_pmu.c | 4 +-
5 files changed, 186 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
index ec516e838ee8..448afb86e05c 100644
--- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
@@ -141,6 +141,7 @@ enum xe_guc_action {
XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
+ XE_GUC_ACTION_SET_FUNCTION_ENGINE_ACTIVITY_BUFFER = 0x550D,
XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,
diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
index 4d720afd12ac..0ab716a58d5c 100644
--- a/drivers/gpu/drm/xe/xe_guc_engine_activity.c
+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
@@ -15,35 +15,61 @@
#include "xe_hw_engine.h"
#include "xe_map.h"
#include "xe_mmio.h"
+#include "xe_sriov_pf_helpers.h"
#include "xe_trace_guc.h"
#define TOTAL_QUANTA 0x8000
-static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_engine *hwe)
+static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_engine *hwe,
+ unsigned int index)
{
struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
size_t offset = 0;
- offset = offsetof(struct guc_engine_activity_data,
+ if (index) {
+ buffer = &engine_activity->function_buffer;
+ offset = sizeof(struct guc_engine_activity_data) * (index - 1);
+ } else {
+ buffer = &engine_activity->device_buffer;
+ }
+
+ offset += offsetof(struct guc_engine_activity_data,
engine_activity[guc_class][hwe->logical_instance]);
return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap, offset);
}
-static struct iosys_map engine_metadata_map(struct xe_guc *guc)
+static struct iosys_map engine_metadata_map(struct xe_guc *guc,
+ unsigned int index)
{
struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
- struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
+ struct engine_activity_buffer *buffer;
+ size_t offset = 0;
+
+ if (index) {
+ buffer = &engine_activity->function_buffer;
+ offset = sizeof(struct guc_engine_activity_metadata) * (index - 1);
+ } else {
+ buffer = &engine_activity->device_buffer;
+ }
- return buffer->metadata_bo->vmap;
+ return IOSYS_MAP_INIT_OFFSET(&buffer->metadata_bo->vmap, offset);
}
static int allocate_engine_activity_group(struct xe_guc *guc)
{
struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
- u32 num_activity_group = 1;
+ struct xe_device *xe = guc_to_xe(guc);
+ u32 num_activity_group;
+
+ /*
+ * Two additional activity groups are allocated one for global
+ * and one for PF engine activity when SRIOV is enabled
+ */
+ num_activity_group = IS_SRIOV_PF(xe) ? xe_sriov_pf_get_totalvfs(xe) + 2 : 1;
+
engine_activity->eag = kmalloc_array(num_activity_group,
sizeof(struct engine_activity_group),
@@ -59,10 +85,11 @@ static int allocate_engine_activity_group(struct xe_guc *guc)
}
static int allocate_engine_activity_buffers(struct xe_guc *guc,
- struct engine_activity_buffer *buffer)
+ struct engine_activity_buffer *buffer,
+ int count)
{
- u32 metadata_size = sizeof(struct guc_engine_activity_metadata);
- u32 size = sizeof(struct guc_engine_activity_data);
+ u32 metadata_size = sizeof(struct guc_engine_activity_metadata) * count;
+ u32 size = sizeof(struct guc_engine_activity_data) * count;
struct xe_gt *gt = guc_to_gt(guc);
struct xe_tile *tile = gt_to_tile(gt);
struct xe_bo *bo, *metadata_bo;
@@ -89,10 +116,17 @@ static int allocate_engine_activity_buffers(struct xe_guc *guc,
return 0;
}
-static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine *hwe)
+static void free_engine_activity_buffers(struct engine_activity_buffer *buffer)
+{
+ xe_bo_unpin_map_no_vm(buffer->metadata_bo);
+ xe_bo_unpin_map_no_vm(buffer->activity_bo);
+}
+
+static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine *hwe,
+ unsigned int index)
{
struct xe_guc *guc = &hwe->gt->uc.guc;
- struct engine_activity_group *eag = &guc->engine_activity.eag[0];
+ struct engine_activity_group *eag = &guc->engine_activity.eag[index];
u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
return &eag->engine[guc_class][hwe->logical_instance];
@@ -109,9 +143,10 @@ static u64 cpu_ns_to_guc_tsc_tick(ktime_t ns, u32 freq)
#define read_metadata_record(xe_, map_, field_) \
xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity_metadata, field_)
-static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
+static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe,
+ unsigned int index)
{
- struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
+ struct engine_activity *ea = hw_engine_to_engine_activity(hwe, index);
struct guc_engine_activity *cached_activity = &ea->activity;
struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
@@ -122,8 +157,8 @@ static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
u64 active_ticks, gpm_ts;
u16 change_num;
- activity_map = engine_activity_map(guc, hwe);
- metadata_map = engine_metadata_map(guc);
+ activity_map = engine_activity_map(guc, hwe, index);
+ metadata_map = engine_metadata_map(guc, index);
global_change_num = read_metadata_record(xe, &metadata_map, global_change_num);
/* GuC has not initialized activity data yet, return 0 */
@@ -166,9 +201,9 @@ static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
return ea->total + ea->active;
}
-static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
+static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe, unsigned int index)
{
- struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
+ struct engine_activity *ea = hw_engine_to_engine_activity(hwe, index);
struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
struct guc_engine_activity *cached_activity = &ea->activity;
struct iosys_map activity_map, metadata_map;
@@ -177,8 +212,8 @@ static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
u64 numerator;
u16 quanta_ratio;
- activity_map = engine_activity_map(guc, hwe);
- metadata_map = engine_metadata_map(guc);
+ activity_map = engine_activity_map(guc, hwe, index);
+ metadata_map = engine_metadata_map(guc, index);
if (!cached_metadata->guc_tsc_frequency_hz)
cached_metadata->guc_tsc_frequency_hz = read_metadata_record(xe, &metadata_map,
@@ -220,10 +255,35 @@ static int enable_engine_activity_stats(struct xe_guc *guc)
return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
}
-static void engine_activity_set_cpu_ts(struct xe_guc *guc)
+static int enable_function_engine_activity_stats(struct xe_guc *guc, bool enable)
{
struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
- struct engine_activity_group *eag = &engine_activity->eag[0];
+ u32 metadata_ggtt_addr = 0, ggtt_addr = 0, num_functions = 0;
+ struct engine_activity_buffer *buffer = &engine_activity->function_buffer;
+ u32 action[6];
+ int len = 0;
+
+ if (enable) {
+ metadata_ggtt_addr = xe_bo_ggtt_addr(buffer->metadata_bo);
+ ggtt_addr = xe_bo_ggtt_addr(buffer->activity_bo);
+ num_functions = engine_activity->num_functions;
+ }
+
+ action[len++] = XE_GUC_ACTION_SET_FUNCTION_ENGINE_ACTIVITY_BUFFER;
+ action[len++] = num_functions;
+ action[len++] = metadata_ggtt_addr;
+ action[len++] = 0;
+ action[len++] = ggtt_addr;
+ action[len++] = 0;
+
+ /* Blocking here to ensure the buffers are ready before reading them */
+ return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
+}
+
+static void engine_activity_set_cpu_ts(struct xe_guc *guc, unsigned int index)
+{
+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
+ struct engine_activity_group *eag = &engine_activity->eag[index];
int i, j;
for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)
@@ -240,36 +300,103 @@ static u32 gpm_timestamp_shift(struct xe_gt *gt)
return 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
}
+static bool is_function_valid(struct xe_guc *guc, unsigned int fn_id)
+{
+ struct xe_device *xe = guc_to_xe(guc);
+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
+
+ if (!IS_SRIOV(xe) && fn_id)
+ return false;
+
+ if (fn_id > engine_activity->num_functions)
+ return false;
+
+ return true;
+}
+
+static int engine_activity_disable_function_stats(struct xe_guc *guc, bool enable)
+{
+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
+ struct engine_activity_buffer *buffer = &engine_activity->function_buffer;
+ int ret;
+
+ if (!engine_activity->num_functions)
+ return 0;
+
+ ret = enable_function_engine_activity_stats(guc, enable);
+ if (ret)
+ return ret;
+
+ free_engine_activity_buffers(buffer);
+ engine_activity->num_functions = 0;
+
+ return 0;
+}
+
+static int engine_activity_enable_function_stats(struct xe_guc *guc, int num_vfs, bool enable)
+{
+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
+ struct engine_activity_buffer *buffer = &engine_activity->function_buffer;
+ int ret, i;
+
+ /* This includes 1 PF and num_vfs */
+ engine_activity->num_functions = num_vfs + 1;
+
+ ret = allocate_engine_activity_buffers(guc, buffer, engine_activity->num_functions);
+ if (ret)
+ return ret;
+
+ ret = enable_function_engine_activity_stats(guc, enable);
+ if (ret) {
+ free_engine_activity_buffers(buffer);
+ engine_activity->num_functions = 0;
+ return ret;
+ }
+
+ for (i = 0; i < engine_activity->num_functions; i++)
+ engine_activity_set_cpu_ts(guc, i + 1);
+
+ return 0;
+}
+
/**
* xe_guc_engine_activity_active_ticks - Get engine active ticks
* @hwe: The hw_engine object
+ * @fn_id: function id to report on
*
* Return: accumulated ticks @hwe was active since engine activity stats were enabled.
*/
-u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe)
+u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe, unsigned int fn_id)
{
struct xe_guc *guc = &hwe->gt->uc.guc;
if (!xe_guc_engine_activity_supported(guc))
return 0;
- return get_engine_active_ticks(guc, hwe);
+ if (!is_function_valid(guc, fn_id))
+ return 0;
+
+ return get_engine_active_ticks(guc, hwe, fn_id);
}
/**
* xe_guc_engine_activity_total_ticks - Get engine total ticks
* @hwe: The hw_engine object
+ * @fn_id: function id to report on
*
* Return: accumulated quanta of ticks allocated for the engine
*/
-u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe)
+u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe, unsigned int fn_id)
{
struct xe_guc *guc = &hwe->gt->uc.guc;
if (!xe_guc_engine_activity_supported(guc))
return 0;
- return get_engine_total_ticks(guc, hwe);
+ if (!is_function_valid(guc, fn_id))
+ return 0;
+
+ return get_engine_total_ticks(guc, hwe, fn_id);
}
/**
@@ -292,6 +419,25 @@ bool xe_guc_engine_activity_supported(struct xe_guc *guc)
return false;
}
+/**
+ * xe_guc_engine_activity_function_stats - Enable/Disable per-function engine activity stats
+ * @guc: The GuC object
+ * @num_vfs: number of vfs
+ * @enable: true to enable, false otherwise
+ *
+ * Return: 0 on success, negative error code otherwise
+ */
+int xe_guc_engine_activity_function_stats(struct xe_guc *guc, int num_vfs, bool enable)
+{
+ if (!xe_guc_engine_activity_supported(guc))
+ return 0;
+
+ if (enable)
+ return engine_activity_enable_function_stats(guc, num_vfs, enable);
+
+ return engine_activity_disable_function_stats(guc, enable);
+}
+
/**
* xe_guc_engine_activity_enable_stats - Enable engine activity stats
* @guc: The GuC object
@@ -309,7 +455,7 @@ void xe_guc_engine_activity_enable_stats(struct xe_guc *guc)
if (ret)
xe_gt_err(guc_to_gt(guc), "failed to enable activity stats%d\n", ret);
else
- engine_activity_set_cpu_ts(guc);
+ engine_activity_set_cpu_ts(guc, 0);
}
static void engine_activity_fini(void *arg)
@@ -340,7 +486,7 @@ int xe_guc_engine_activity_init(struct xe_guc *guc)
return ret;
}
- ret = allocate_engine_activity_buffers(guc, &engine_activity->device_buffer);
+ ret = allocate_engine_activity_buffers(guc, &engine_activity->device_buffer, 1);
if (ret) {
xe_gt_err(gt, "failed to allocate activity buffers%d\n", ret);
kfree(engine_activity->eag);
diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.h b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
index 9d3ea3f67b6a..765397b959e0 100644
--- a/drivers/gpu/drm/xe/xe_guc_engine_activity.h
+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.h
@@ -14,6 +14,7 @@ struct xe_guc;
int xe_guc_engine_activity_init(struct xe_guc *guc);
bool xe_guc_engine_activity_supported(struct xe_guc *guc);
void xe_guc_engine_activity_enable_stats(struct xe_guc *guc);
-u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe);
-u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe);
+int xe_guc_engine_activity_function_stats(struct xe_guc *guc, int num_vfs, bool enable);
+u64 xe_guc_engine_activity_active_ticks(struct xe_hw_engine *hwe, unsigned int fn_id);
+u64 xe_guc_engine_activity_total_ticks(struct xe_hw_engine *hwe, unsigned int fn_id);
#endif
diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
index a2ab327d3eec..be7c1873c95f 100644
--- a/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
@@ -79,11 +79,17 @@ struct xe_guc_engine_activity {
/** @num_activity_group: number of activity groups */
u32 num_activity_group;
- /** @eag: holds the device level engine activity data */
+ /** @num_functions: number of functions */
+ u32 num_functions;
+
+ /** @eag: array with entries to hold engine activity stats of global, PF and VF's */
struct engine_activity_group *eag;
/** @device_buffer: buffer object for global engine activity */
struct engine_activity_buffer device_buffer;
+
+ /** @function_buffer: buffer object for per-function engine activity */
+ struct engine_activity_buffer function_buffer;
};
#endif
diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
index 8ea78d8f7e2e..15e9a57aa429 100644
--- a/drivers/gpu/drm/xe/xe_pmu.c
+++ b/drivers/gpu/drm/xe/xe_pmu.c
@@ -200,9 +200,9 @@ static u64 read_engine_events(struct perf_event *event)
if (!hwe)
drm_warn(&xe->drm, "unknown pmu engine\n");
else if (config_to_event_id(event->attr.config) == XE_PMU_EVENT_ENGINE_ACTIVE_TICKS)
- val = xe_guc_engine_activity_active_ticks(hwe);
+ val = xe_guc_engine_activity_active_ticks(hwe, 0);
else
- val = xe_guc_engine_activity_total_ticks(hwe);
+ val = xe_guc_engine_activity_total_ticks(hwe, 0);
return val;
}
--
2.47.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [PATCH v4 6/8] drm/xe: Add support for per-function engine activity
2025-01-29 10:16 ` [PATCH v4 6/8] drm/xe: Add support for per-function engine activity Riana Tauro
@ 2025-01-31 23:52 ` Umesh Nerlige Ramappa
2025-02-03 5:26 ` Riana Tauro
0 siblings, 1 reply; 45+ messages in thread
From: Umesh Nerlige Ramappa @ 2025-01-31 23:52 UTC (permalink / raw)
To: Riana Tauro
Cc: intel-xe, anshuman.gupta, lucas.demarchi, vinay.belgaumkar,
soham.purkait
On Wed, Jan 29, 2025 at 03:46:49PM +0530, Riana Tauro wrote:
>Add support for function level per-engine-class activity stats.
>This is enabled when sriov_numvfs is set and disabled when vf's
>are disabled.
>
>Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>---
> drivers/gpu/drm/xe/abi/guc_actions_abi.h | 1 +
> drivers/gpu/drm/xe/xe_guc_engine_activity.c | 200 +++++++++++++++---
> drivers/gpu/drm/xe/xe_guc_engine_activity.h | 5 +-
> .../gpu/drm/xe/xe_guc_engine_activity_types.h | 8 +-
> drivers/gpu/drm/xe/xe_pmu.c | 4 +-
> 5 files changed, 186 insertions(+), 32 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>index ec516e838ee8..448afb86e05c 100644
>--- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>+++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>@@ -141,6 +141,7 @@ enum xe_guc_action {
> XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
> XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
> XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
>+ XE_GUC_ACTION_SET_FUNCTION_ENGINE_ACTIVITY_BUFFER = 0x550D,
> XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
> XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
> XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,
>diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>index 4d720afd12ac..0ab716a58d5c 100644
>--- a/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>@@ -15,35 +15,61 @@
> #include "xe_hw_engine.h"
> #include "xe_map.h"
> #include "xe_mmio.h"
>+#include "xe_sriov_pf_helpers.h"
> #include "xe_trace_guc.h"
>
> #define TOTAL_QUANTA 0x8000
>
>-static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_engine *hwe)
>+static struct iosys_map engine_activity_map(struct xe_guc *guc, struct xe_hw_engine *hwe,
>+ unsigned int index)
> {
> struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
> struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
You can drop the initialization here since it is being set below.
> u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
> size_t offset = 0;
For readability, you could set offset = 0 in the else part instead of
here.
>
>- offset = offsetof(struct guc_engine_activity_data,
>+ if (index) {
>+ buffer = &engine_activity->function_buffer;
>+ offset = sizeof(struct guc_engine_activity_data) * (index - 1);
>+ } else {
>+ buffer = &engine_activity->device_buffer;
>+ }
>+
>+ offset += offsetof(struct guc_engine_activity_data,
> engine_activity[guc_class][hwe->logical_instance]);
>
> return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap, offset);
> }
>
>-static struct iosys_map engine_metadata_map(struct xe_guc *guc)
>+static struct iosys_map engine_metadata_map(struct xe_guc *guc,
>+ unsigned int index)
> {
> struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>- struct engine_activity_buffer *buffer = &engine_activity->device_buffer;
>+ struct engine_activity_buffer *buffer;
>+ size_t offset = 0;
Same here ^
>+
>+ if (index) {
>+ buffer = &engine_activity->function_buffer;
>+ offset = sizeof(struct guc_engine_activity_metadata) * (index - 1);
>+ } else {
>+ buffer = &engine_activity->device_buffer;
>+ }
>
>- return buffer->metadata_bo->vmap;
>+ return IOSYS_MAP_INIT_OFFSET(&buffer->metadata_bo->vmap, offset);
> }
>
> static int allocate_engine_activity_group(struct xe_guc *guc)
> {
> struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>- u32 num_activity_group = 1;
>+ struct xe_device *xe = guc_to_xe(guc);
>+ u32 num_activity_group;
>+
>+ /*
>+ * Two additional activity groups are allocated one for global
>+ * and one for PF engine activity when SRIOV is enabled
>+ */
>+ num_activity_group = IS_SRIOV_PF(xe) ? xe_sriov_pf_get_totalvfs(xe) + 2 : 1;
>+
>
> engine_activity->eag = kmalloc_array(num_activity_group,
> sizeof(struct engine_activity_group),
>@@ -59,10 +85,11 @@ static int allocate_engine_activity_group(struct xe_guc *guc)
> }
>
> static int allocate_engine_activity_buffers(struct xe_guc *guc,
>- struct engine_activity_buffer *buffer)
>+ struct engine_activity_buffer *buffer,
>+ int count)
> {
>- u32 metadata_size = sizeof(struct guc_engine_activity_metadata);
>- u32 size = sizeof(struct guc_engine_activity_data);
>+ u32 metadata_size = sizeof(struct guc_engine_activity_metadata) * count;
>+ u32 size = sizeof(struct guc_engine_activity_data) * count;
> struct xe_gt *gt = guc_to_gt(guc);
> struct xe_tile *tile = gt_to_tile(gt);
> struct xe_bo *bo, *metadata_bo;
>@@ -89,10 +116,17 @@ static int allocate_engine_activity_buffers(struct xe_guc *guc,
> return 0;
> }
>
>-static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine *hwe)
>+static void free_engine_activity_buffers(struct engine_activity_buffer *buffer)
>+{
>+ xe_bo_unpin_map_no_vm(buffer->metadata_bo);
+ xe_bo_unpin_map_no_vm(buffer->activity_bo);
>+}
>+
>+static struct engine_activity *hw_engine_to_engine_activity(struct xe_hw_engine *hwe,
>+ unsigned int index)
> {
> struct xe_guc *guc = &hwe->gt->uc.guc;
>- struct engine_activity_group *eag = &guc->engine_activity.eag[0];
>+ struct engine_activity_group *eag = &guc->engine_activity.eag[index];
> u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>
> return &eag->engine[guc_class][hwe->logical_instance];
>@@ -109,9 +143,10 @@ static u64 cpu_ns_to_guc_tsc_tick(ktime_t ns, u32 freq)
> #define read_metadata_record(xe_, map_, field_) \
> xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity_metadata, field_)
>
>-static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>+static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe,
>+ unsigned int index)
> {
>- struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>+ struct engine_activity *ea = hw_engine_to_engine_activity(hwe, index);
> struct guc_engine_activity *cached_activity = &ea->activity;
> struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
> struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>@@ -122,8 +157,8 @@ static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
> u64 active_ticks, gpm_ts;
> u16 change_num;
>
>- activity_map = engine_activity_map(guc, hwe);
>- metadata_map = engine_metadata_map(guc);
>+ activity_map = engine_activity_map(guc, hwe, index);
>+ metadata_map = engine_metadata_map(guc, index);
> global_change_num = read_metadata_record(xe, &metadata_map, global_change_num);
>
> /* GuC has not initialized activity data yet, return 0 */
>@@ -166,9 +201,9 @@ static u64 get_engine_active_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
> return ea->total + ea->active;
> }
>
>-static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
>+static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe, unsigned int index)
> {
>- struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>+ struct engine_activity *ea = hw_engine_to_engine_activity(hwe, index);
> struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
> struct guc_engine_activity *cached_activity = &ea->activity;
> struct iosys_map activity_map, metadata_map;
>@@ -177,8 +212,8 @@ static u64 get_engine_total_ticks(struct xe_guc *guc, struct xe_hw_engine *hwe)
> u64 numerator;
> u16 quanta_ratio;
>
>- activity_map = engine_activity_map(guc, hwe);
>- metadata_map = engine_metadata_map(guc);
>+ activity_map = engine_activity_map(guc, hwe, index);
>+ metadata_map = engine_metadata_map(guc, index);
>
> if (!cached_metadata->guc_tsc_frequency_hz)
> cached_metadata->guc_tsc_frequency_hz = read_metadata_record(xe, &metadata_map,
>@@ -220,10 +255,35 @@ static int enable_engine_activity_stats(struct xe_guc *guc)
> return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
> }
>
>-static void engine_activity_set_cpu_ts(struct xe_guc *guc)
>+static int enable_function_engine_activity_stats(struct xe_guc *guc, bool enable)
> {
> struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>- struct engine_activity_group *eag = &engine_activity->eag[0];
>+ u32 metadata_ggtt_addr = 0, ggtt_addr = 0, num_functions = 0;
>+ struct engine_activity_buffer *buffer = &engine_activity->function_buffer;
>+ u32 action[6];
>+ int len = 0;
>+
>+ if (enable) {
>+ metadata_ggtt_addr = xe_bo_ggtt_addr(buffer->metadata_bo);
>+ ggtt_addr = xe_bo_ggtt_addr(buffer->activity_bo);
>+ num_functions = engine_activity->num_functions;
>+ }
>+
>+ action[len++] = XE_GUC_ACTION_SET_FUNCTION_ENGINE_ACTIVITY_BUFFER;
>+ action[len++] = num_functions;
>+ action[len++] = metadata_ggtt_addr;
>+ action[len++] = 0;
>+ action[len++] = ggtt_addr;
>+ action[len++] = 0;
>+
>+ /* Blocking here to ensure the buffers are ready before reading them */
>+ return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
>+}
>+
>+static void engine_activity_set_cpu_ts(struct xe_guc *guc, unsigned int index)
>+{
>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>+ struct engine_activity_group *eag = &engine_activity->eag[index];
> int i, j;
>
> for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)
>@@ -240,36 +300,103 @@ static u32 gpm_timestamp_shift(struct xe_gt *gt)
> return 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
> }
>
>+static bool is_function_valid(struct xe_guc *guc, unsigned int fn_id)
>+{
>+ struct xe_device *xe = guc_to_xe(guc);
>+ struct xe_guc_engine_activity *engine_activity = &guc->engine_activity;
>+
>+ if (!IS_SRIOV(xe) && fn_id)
>+ return false;
>+
>+ if (fn_id > engine_activity->num_functions)
This ^ should be 'else if'. Consider the Native case where fn_id = 0. I
believe num_functions will be 0 for native, so the check would fail
always for native. Right?
>+ return false;
>+
>+ return true;
>+}
>+
Thanks,
Umesh
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 6/8] drm/xe: Add support for per-function engine activity
2025-01-31 23:52 ` Umesh Nerlige Ramappa
@ 2025-02-03 5:26 ` Riana Tauro
2025-02-05 1:30 ` Umesh Nerlige Ramappa
0 siblings, 1 reply; 45+ messages in thread
From: Riana Tauro @ 2025-02-03 5:26 UTC (permalink / raw)
To: Umesh Nerlige Ramappa
Cc: intel-xe, anshuman.gupta, lucas.demarchi, vinay.belgaumkar,
soham.purkait
Hi Umesh
Thank you for the review comments
On 2/1/2025 5:22 AM, Umesh Nerlige Ramappa wrote:
> On Wed, Jan 29, 2025 at 03:46:49PM +0530, Riana Tauro wrote:
>> Add support for function level per-engine-class activity stats.
>> This is enabled when sriov_numvfs is set and disabled when vf's
>> are disabled.
>>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>> drivers/gpu/drm/xe/abi/guc_actions_abi.h | 1 +
>> drivers/gpu/drm/xe/xe_guc_engine_activity.c | 200 +++++++++++++++---
>> drivers/gpu/drm/xe/xe_guc_engine_activity.h | 5 +-
>> .../gpu/drm/xe/xe_guc_engine_activity_types.h | 8 +-
>> drivers/gpu/drm/xe/xe_pmu.c | 4 +-
>> 5 files changed, 186 insertions(+), 32 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/
>> drm/xe/abi/guc_actions_abi.h
>> index ec516e838ee8..448afb86e05c 100644
>> --- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>> +++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>> @@ -141,6 +141,7 @@ enum xe_guc_action {
>> XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
>> XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
>> XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
>> + XE_GUC_ACTION_SET_FUNCTION_ENGINE_ACTIVITY_BUFFER = 0x550D,
>> XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
>> XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
>> XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,
>> diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c b/drivers/
>> gpu/drm/xe/xe_guc_engine_activity.c
>> index 4d720afd12ac..0ab716a58d5c 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>> @@ -15,35 +15,61 @@
>> #include "xe_hw_engine.h"
>> #include "xe_map.h"
>> #include "xe_mmio.h"
>> +#include "xe_sriov_pf_helpers.h"
>> #include "xe_trace_guc.h"
>>
>> #define TOTAL_QUANTA 0x8000
>>
>> -static struct iosys_map engine_activity_map(struct xe_guc *guc,
>> struct xe_hw_engine *hwe)
>> +static struct iosys_map engine_activity_map(struct xe_guc *guc,
>> struct xe_hw_engine *hwe,
>> + unsigned int index)
>> {
>> struct xe_guc_engine_activity *engine_activity = &guc-
>> >engine_activity;
>> struct engine_activity_buffer *buffer = &engine_activity-
>> >device_buffer;
> You can drop the initialization here since it is being set below.
yeah missed to do this. will fix it
>
>> u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>> size_t offset = 0;
> For readability, you could set offset = 0 in the else part instead of here.
okay will add it below
>>
>> - offset = offsetof(struct guc_engine_activity_data,
>> + if (index) {
>> + buffer = &engine_activity->function_buffer;
>> + offset = sizeof(struct guc_engine_activity_data) * (index - 1);
>> + } else {
>> + buffer = &engine_activity->device_buffer;
>> + }
>> +
>> + offset += offsetof(struct guc_engine_activity_data,
>> engine_activity[guc_class][hwe->logical_instance]);
>>
>> return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap, offset);
>> }
>>
>> -static struct iosys_map engine_metadata_map(struct xe_guc *guc)
>> +static struct iosys_map engine_metadata_map(struct xe_guc *guc,
>> + unsigned int index)
>> {
>> struct xe_guc_engine_activity *engine_activity = &guc-
>> >engine_activity;
>> - struct engine_activity_buffer *buffer = &engine_activity-
>> >device_buffer;
>> + struct engine_activity_buffer *buffer;
>> + size_t offset = 0;
> Same here ^
>
>> +
>> + if (index) {
>> + buffer = &engine_activity->function_buffer;
>> + offset = sizeof(struct guc_engine_activity_metadata) * (index
>> - 1);
>> + } else {
>> + buffer = &engine_activity->device_buffer;
>> + }
>>
>> - return buffer->metadata_bo->vmap;
>> + return IOSYS_MAP_INIT_OFFSET(&buffer->metadata_bo->vmap, offset);
>> }
>>
>> static int allocate_engine_activity_group(struct xe_guc *guc)
>> {
>> struct xe_guc_engine_activity *engine_activity = &guc-
>> >engine_activity;
>> - u32 num_activity_group = 1;
>> + struct xe_device *xe = guc_to_xe(guc);
>> + u32 num_activity_group;
>> +
>> + /*
>> + * Two additional activity groups are allocated one for global
>> + * and one for PF engine activity when SRIOV is enabled
>> + */
>> + num_activity_group = IS_SRIOV_PF(xe) ?
>> xe_sriov_pf_get_totalvfs(xe) + 2 : 1;
>> +
>>
>> engine_activity->eag = kmalloc_array(num_activity_group,
>> sizeof(struct engine_activity_group),
>> @@ -59,10 +85,11 @@ static int allocate_engine_activity_group(struct
>> xe_guc *guc)
>> }
>>
>> static int allocate_engine_activity_buffers(struct xe_guc *guc,
>> - struct engine_activity_buffer *buffer)
>> + struct engine_activity_buffer *buffer,
>> + int count)
>> {
>> - u32 metadata_size = sizeof(struct guc_engine_activity_metadata);
>> - u32 size = sizeof(struct guc_engine_activity_data);
>> + u32 metadata_size = sizeof(struct guc_engine_activity_metadata) *
>> count;
>> + u32 size = sizeof(struct guc_engine_activity_data) * count;
>> struct xe_gt *gt = guc_to_gt(guc);
>> struct xe_tile *tile = gt_to_tile(gt);
>> struct xe_bo *bo, *metadata_bo;
>> @@ -89,10 +116,17 @@ static int
>> allocate_engine_activity_buffers(struct xe_guc *guc,
>> return 0;
>> }
>>
>> -static struct engine_activity *hw_engine_to_engine_activity(struct
>> xe_hw_engine *hwe)
>> +static void free_engine_activity_buffers(struct
>> engine_activity_buffer *buffer)
>> +{
>> + xe_bo_unpin_map_no_vm(buffer->metadata_bo);
> + xe_bo_unpin_map_no_vm(buffer->activity_bo);
>> +}
>> +
>> +static struct engine_activity *hw_engine_to_engine_activity(struct
>> xe_hw_engine *hwe,
>> + unsigned int index)
>> {
>> struct xe_guc *guc = &hwe->gt->uc.guc;
>> - struct engine_activity_group *eag = &guc->engine_activity.eag[0];
>> + struct engine_activity_group *eag = &guc-
>> >engine_activity.eag[index];
>> u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>>
>> return &eag->engine[guc_class][hwe->logical_instance];
>> @@ -109,9 +143,10 @@ static u64 cpu_ns_to_guc_tsc_tick(ktime_t ns, u32
>> freq)
>> #define read_metadata_record(xe_, map_, field_) \
>> xe_map_rd_field(xe_, map_, 0, struct guc_engine_activity_metadata,
>> field_)
>>
>> -static u64 get_engine_active_ticks(struct xe_guc *guc, struct
>> xe_hw_engine *hwe)
>> +static u64 get_engine_active_ticks(struct xe_guc *guc, struct
>> xe_hw_engine *hwe,
>> + unsigned int index)
>> {
>> - struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>> + struct engine_activity *ea = hw_engine_to_engine_activity(hwe,
>> index);
>> struct guc_engine_activity *cached_activity = &ea->activity;
>> struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>> struct xe_guc_engine_activity *engine_activity = &guc-
>> >engine_activity;
>> @@ -122,8 +157,8 @@ static u64 get_engine_active_ticks(struct xe_guc
>> *guc, struct xe_hw_engine *hwe)
>> u64 active_ticks, gpm_ts;
>> u16 change_num;
>>
>> - activity_map = engine_activity_map(guc, hwe);
>> - metadata_map = engine_metadata_map(guc);
>> + activity_map = engine_activity_map(guc, hwe, index);
>> + metadata_map = engine_metadata_map(guc, index);
>> global_change_num = read_metadata_record(xe, &metadata_map,
>> global_change_num);
>>
>> /* GuC has not initialized activity data yet, return 0 */
>> @@ -166,9 +201,9 @@ static u64 get_engine_active_ticks(struct xe_guc
>> *guc, struct xe_hw_engine *hwe)
>> return ea->total + ea->active;
>> }
>>
>> -static u64 get_engine_total_ticks(struct xe_guc *guc, struct
>> xe_hw_engine *hwe)
>> +static u64 get_engine_total_ticks(struct xe_guc *guc, struct
>> xe_hw_engine *hwe, unsigned int index)
>> {
>> - struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>> + struct engine_activity *ea = hw_engine_to_engine_activity(hwe,
>> index);
>> struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>> struct guc_engine_activity *cached_activity = &ea->activity;
>> struct iosys_map activity_map, metadata_map;
>> @@ -177,8 +212,8 @@ static u64 get_engine_total_ticks(struct xe_guc
>> *guc, struct xe_hw_engine *hwe)
>> u64 numerator;
>> u16 quanta_ratio;
>>
>> - activity_map = engine_activity_map(guc, hwe);
>> - metadata_map = engine_metadata_map(guc);
>> + activity_map = engine_activity_map(guc, hwe, index);
>> + metadata_map = engine_metadata_map(guc, index);
>>
>> if (!cached_metadata->guc_tsc_frequency_hz)
>> cached_metadata->guc_tsc_frequency_hz =
>> read_metadata_record(xe, &metadata_map,
>> @@ -220,10 +255,35 @@ static int enable_engine_activity_stats(struct
>> xe_guc *guc)
>> return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
>> }
>>
>> -static void engine_activity_set_cpu_ts(struct xe_guc *guc)
>> +static int enable_function_engine_activity_stats(struct xe_guc *guc,
>> bool enable)
>> {
>> struct xe_guc_engine_activity *engine_activity = &guc-
>> >engine_activity;
>> - struct engine_activity_group *eag = &engine_activity->eag[0];
>> + u32 metadata_ggtt_addr = 0, ggtt_addr = 0, num_functions = 0;
>> + struct engine_activity_buffer *buffer = &engine_activity-
>> >function_buffer;
>> + u32 action[6];
>> + int len = 0;
>> +
>> + if (enable) {
>> + metadata_ggtt_addr = xe_bo_ggtt_addr(buffer->metadata_bo);
>> + ggtt_addr = xe_bo_ggtt_addr(buffer->activity_bo);
>> + num_functions = engine_activity->num_functions;
>> + }
>> +
>> + action[len++] = XE_GUC_ACTION_SET_FUNCTION_ENGINE_ACTIVITY_BUFFER;
>> + action[len++] = num_functions;
>> + action[len++] = metadata_ggtt_addr;
>> + action[len++] = 0;
>> + action[len++] = ggtt_addr;
>> + action[len++] = 0;
>> +
>> + /* Blocking here to ensure the buffers are ready before reading
>> them */
>> + return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
>> +}
>> +
>> +static void engine_activity_set_cpu_ts(struct xe_guc *guc, unsigned
>> int index)
>> +{
>> + struct xe_guc_engine_activity *engine_activity = &guc-
>> >engine_activity;
>> + struct engine_activity_group *eag = &engine_activity->eag[index];
>> int i, j;
>>
>> for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)
>> @@ -240,36 +300,103 @@ static u32 gpm_timestamp_shift(struct xe_gt *gt)
>> return 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
>> }
>>
>> +static bool is_function_valid(struct xe_guc *guc, unsigned int fn_id)
>> +{
>> + struct xe_device *xe = guc_to_xe(guc);
>> + struct xe_guc_engine_activity *engine_activity = &guc-
>> >engine_activity;
>> +
>> + if (!IS_SRIOV(xe) && fn_id)
>> + return false;
>> +
>> + if (fn_id > engine_activity->num_functions)
>
> This ^ should be 'else if'. Consider the Native case where fn_id = 0. I
> believe num_functions will be 0 for native, so the check would fail
> always for native. Right?
Only if it's greater it would fail. So for native it will not.
In case of SRIOV too. It'll fail only if num_vfs is not set.
So there won't be two counters one global and one PF. Only global will
be present.
Thanks
Riana
>
>> + return false;
>> +
>> + return true;
>> +}
>> +
>
> Thanks,
> Umesh
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 6/8] drm/xe: Add support for per-function engine activity
2025-02-03 5:26 ` Riana Tauro
@ 2025-02-05 1:30 ` Umesh Nerlige Ramappa
0 siblings, 0 replies; 45+ messages in thread
From: Umesh Nerlige Ramappa @ 2025-02-05 1:30 UTC (permalink / raw)
To: Riana Tauro
Cc: intel-xe, anshuman.gupta, lucas.demarchi, vinay.belgaumkar,
soham.purkait
On Mon, Feb 03, 2025 at 10:56:03AM +0530, Riana Tauro wrote:
>Hi Umesh
>
>Thank you for the review comments
>
>On 2/1/2025 5:22 AM, Umesh Nerlige Ramappa wrote:
>>On Wed, Jan 29, 2025 at 03:46:49PM +0530, Riana Tauro wrote:
>>>Add support for function level per-engine-class activity stats.
>>>This is enabled when sriov_numvfs is set and disabled when vf's
>>>are disabled.
>>>
>>>Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>>>---
>>>drivers/gpu/drm/xe/abi/guc_actions_abi.h | 1 +
>>>drivers/gpu/drm/xe/xe_guc_engine_activity.c | 200 +++++++++++++++---
>>>drivers/gpu/drm/xe/xe_guc_engine_activity.h | 5 +-
>>>.../gpu/drm/xe/xe_guc_engine_activity_types.h | 8 +-
>>>drivers/gpu/drm/xe/xe_pmu.c | 4 +-
>>>5 files changed, 186 insertions(+), 32 deletions(-)
>>>
>>>diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>>b/drivers/gpu/ drm/xe/abi/guc_actions_abi.h
>>>index ec516e838ee8..448afb86e05c 100644
>>>--- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>>+++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
>>>@@ -141,6 +141,7 @@ enum xe_guc_action {
>>> XE_GUC_ACTION_CLIENT_SOFT_RESET = 0x5507,
>>> XE_GUC_ACTION_SET_ENG_UTIL_BUFF = 0x550A,
>>> XE_GUC_ACTION_SET_DEVICE_ENGINE_ACTIVITY_BUFFER = 0x550C,
>>>+ XE_GUC_ACTION_SET_FUNCTION_ENGINE_ACTIVITY_BUFFER = 0x550D,
>>> XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR = 0x6000,
>>> XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC = 0x6002,
>>> XE_GUC_ACTION_PAGE_FAULT_RES_DESC = 0x6003,
>>>diff --git a/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>>b/drivers/ gpu/drm/xe/xe_guc_engine_activity.c
>>>index 4d720afd12ac..0ab716a58d5c 100644
>>>--- a/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>>+++ b/drivers/gpu/drm/xe/xe_guc_engine_activity.c
>>>@@ -15,35 +15,61 @@
>>>#include "xe_hw_engine.h"
>>>#include "xe_map.h"
>>>#include "xe_mmio.h"
>>>+#include "xe_sriov_pf_helpers.h"
>>>#include "xe_trace_guc.h"
>>>
>>>#define TOTAL_QUANTA 0x8000
>>>
>>>-static struct iosys_map engine_activity_map(struct xe_guc *guc,
>>>struct xe_hw_engine *hwe)
>>>+static struct iosys_map engine_activity_map(struct xe_guc *guc,
>>>struct xe_hw_engine *hwe,
>>>+ unsigned int index)
>>>{
>>> struct xe_guc_engine_activity *engine_activity = &guc-
>>>>engine_activity;
>>> struct engine_activity_buffer *buffer = &engine_activity-
>>>>device_buffer;
>>You can drop the initialization here since it is being set below.
>yeah missed to do this. will fix it
>>
>>> u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>>> size_t offset = 0;
>>For readability, you could set offset = 0 in the else part instead of here.
>okay will add it below
>>>
>>>- offset = offsetof(struct guc_engine_activity_data,
>>>+ if (index) {
>>>+ buffer = &engine_activity->function_buffer;
>>>+ offset = sizeof(struct guc_engine_activity_data) * (index - 1);
>>>+ } else {
>>>+ buffer = &engine_activity->device_buffer;
>>>+ }
>>>+
>>>+ offset += offsetof(struct guc_engine_activity_data,
>>> engine_activity[guc_class][hwe->logical_instance]);
>>>
>>> return IOSYS_MAP_INIT_OFFSET(&buffer->activity_bo->vmap, offset);
>>>}
>>>
>>>-static struct iosys_map engine_metadata_map(struct xe_guc *guc)
>>>+static struct iosys_map engine_metadata_map(struct xe_guc *guc,
>>>+ unsigned int index)
>>>{
>>> struct xe_guc_engine_activity *engine_activity = &guc-
>>>>engine_activity;
>>>- struct engine_activity_buffer *buffer = &engine_activity-
>>>>device_buffer;
>>>+ struct engine_activity_buffer *buffer;
>>>+ size_t offset = 0;
>>Same here ^
>>
>>>+
>>>+ if (index) {
>>>+ buffer = &engine_activity->function_buffer;
>>>+ offset = sizeof(struct guc_engine_activity_metadata) *
>>>(index - 1);
>>>+ } else {
>>>+ buffer = &engine_activity->device_buffer;
>>>+ }
>>>
>>>- return buffer->metadata_bo->vmap;
>>>+ return IOSYS_MAP_INIT_OFFSET(&buffer->metadata_bo->vmap, offset);
>>>}
>>>
>>>static int allocate_engine_activity_group(struct xe_guc *guc)
>>>{
>>> struct xe_guc_engine_activity *engine_activity = &guc-
>>>>engine_activity;
>>>- u32 num_activity_group = 1;
>>>+ struct xe_device *xe = guc_to_xe(guc);
>>>+ u32 num_activity_group;
>>>+
>>>+ /*
>>>+ * Two additional activity groups are allocated one for global
>>>+ * and one for PF engine activity when SRIOV is enabled
>>>+ */
>>>+ num_activity_group = IS_SRIOV_PF(xe) ?
>>>xe_sriov_pf_get_totalvfs(xe) + 2 : 1;
>>>+
>>>
>>> engine_activity->eag = kmalloc_array(num_activity_group,
>>> sizeof(struct engine_activity_group),
>>>@@ -59,10 +85,11 @@ static int
>>>allocate_engine_activity_group(struct xe_guc *guc)
>>>}
>>>
>>>static int allocate_engine_activity_buffers(struct xe_guc *guc,
>>>- struct engine_activity_buffer *buffer)
>>>+ struct engine_activity_buffer *buffer,
>>>+ int count)
>>>{
>>>- u32 metadata_size = sizeof(struct guc_engine_activity_metadata);
>>>- u32 size = sizeof(struct guc_engine_activity_data);
>>>+ u32 metadata_size = sizeof(struct
>>>guc_engine_activity_metadata) * count;
>>>+ u32 size = sizeof(struct guc_engine_activity_data) * count;
>>> struct xe_gt *gt = guc_to_gt(guc);
>>> struct xe_tile *tile = gt_to_tile(gt);
>>> struct xe_bo *bo, *metadata_bo;
>>>@@ -89,10 +116,17 @@ static int
>>>allocate_engine_activity_buffers(struct xe_guc *guc,
>>> return 0;
>>>}
>>>
>>>-static struct engine_activity
>>>*hw_engine_to_engine_activity(struct xe_hw_engine *hwe)
>>>+static void free_engine_activity_buffers(struct
>>>engine_activity_buffer *buffer)
>>>+{
>>>+ xe_bo_unpin_map_no_vm(buffer->metadata_bo);
>>+ xe_bo_unpin_map_no_vm(buffer->activity_bo);
>>>+}
>>>+
>>>+static struct engine_activity
>>>*hw_engine_to_engine_activity(struct xe_hw_engine *hwe,
>>>+ unsigned int index)
>>>{
>>> struct xe_guc *guc = &hwe->gt->uc.guc;
>>>- struct engine_activity_group *eag = &guc->engine_activity.eag[0];
>>>+ struct engine_activity_group *eag = &guc-
>>>>engine_activity.eag[index];
>>> u16 guc_class = xe_engine_class_to_guc_class(hwe->class);
>>>
>>> return &eag->engine[guc_class][hwe->logical_instance];
>>>@@ -109,9 +143,10 @@ static u64 cpu_ns_to_guc_tsc_tick(ktime_t ns,
>>>u32 freq)
>>>#define read_metadata_record(xe_, map_, field_) \
>>> xe_map_rd_field(xe_, map_, 0, struct
>>>guc_engine_activity_metadata, field_)
>>>
>>>-static u64 get_engine_active_ticks(struct xe_guc *guc, struct
>>>xe_hw_engine *hwe)
>>>+static u64 get_engine_active_ticks(struct xe_guc *guc, struct
>>>xe_hw_engine *hwe,
>>>+ unsigned int index)
>>>{
>>>- struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>>>+ struct engine_activity *ea =
>>>hw_engine_to_engine_activity(hwe, index);
>>> struct guc_engine_activity *cached_activity = &ea->activity;
>>> struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>>> struct xe_guc_engine_activity *engine_activity = &guc-
>>>>engine_activity;
>>>@@ -122,8 +157,8 @@ static u64 get_engine_active_ticks(struct
>>>xe_guc *guc, struct xe_hw_engine *hwe)
>>> u64 active_ticks, gpm_ts;
>>> u16 change_num;
>>>
>>>- activity_map = engine_activity_map(guc, hwe);
>>>- metadata_map = engine_metadata_map(guc);
>>>+ activity_map = engine_activity_map(guc, hwe, index);
>>>+ metadata_map = engine_metadata_map(guc, index);
>>> global_change_num = read_metadata_record(xe, &metadata_map,
>>>global_change_num);
>>>
>>> /* GuC has not initialized activity data yet, return 0 */
>>>@@ -166,9 +201,9 @@ static u64 get_engine_active_ticks(struct
>>>xe_guc *guc, struct xe_hw_engine *hwe)
>>> return ea->total + ea->active;
>>>}
>>>
>>>-static u64 get_engine_total_ticks(struct xe_guc *guc, struct
>>>xe_hw_engine *hwe)
>>>+static u64 get_engine_total_ticks(struct xe_guc *guc, struct
>>>xe_hw_engine *hwe, unsigned int index)
>>>{
>>>- struct engine_activity *ea = hw_engine_to_engine_activity(hwe);
>>>+ struct engine_activity *ea =
>>>hw_engine_to_engine_activity(hwe, index);
>>> struct guc_engine_activity_metadata *cached_metadata = &ea->metadata;
>>> struct guc_engine_activity *cached_activity = &ea->activity;
>>> struct iosys_map activity_map, metadata_map;
>>>@@ -177,8 +212,8 @@ static u64 get_engine_total_ticks(struct
>>>xe_guc *guc, struct xe_hw_engine *hwe)
>>> u64 numerator;
>>> u16 quanta_ratio;
>>>
>>>- activity_map = engine_activity_map(guc, hwe);
>>>- metadata_map = engine_metadata_map(guc);
>>>+ activity_map = engine_activity_map(guc, hwe, index);
>>>+ metadata_map = engine_metadata_map(guc, index);
>>>
>>> if (!cached_metadata->guc_tsc_frequency_hz)
>>> cached_metadata->guc_tsc_frequency_hz =
>>>read_metadata_record(xe, &metadata_map,
>>>@@ -220,10 +255,35 @@ static int
>>>enable_engine_activity_stats(struct xe_guc *guc)
>>> return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
>>>}
>>>
>>>-static void engine_activity_set_cpu_ts(struct xe_guc *guc)
>>>+static int enable_function_engine_activity_stats(struct xe_guc
>>>*guc, bool enable)
>>>{
>>> struct xe_guc_engine_activity *engine_activity = &guc-
>>>>engine_activity;
>>>- struct engine_activity_group *eag = &engine_activity->eag[0];
>>>+ u32 metadata_ggtt_addr = 0, ggtt_addr = 0, num_functions = 0;
>>>+ struct engine_activity_buffer *buffer = &engine_activity-
>>>>function_buffer;
>>>+ u32 action[6];
>>>+ int len = 0;
>>>+
>>>+ if (enable) {
>>>+ metadata_ggtt_addr = xe_bo_ggtt_addr(buffer->metadata_bo);
>>>+ ggtt_addr = xe_bo_ggtt_addr(buffer->activity_bo);
>>>+ num_functions = engine_activity->num_functions;
>>>+ }
>>>+
>>>+ action[len++] = XE_GUC_ACTION_SET_FUNCTION_ENGINE_ACTIVITY_BUFFER;
>>>+ action[len++] = num_functions;
>>>+ action[len++] = metadata_ggtt_addr;
>>>+ action[len++] = 0;
>>>+ action[len++] = ggtt_addr;
>>>+ action[len++] = 0;
>>>+
>>>+ /* Blocking here to ensure the buffers are ready before
>>>reading them */
>>>+ return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action));
>>>+}
>>>+
>>>+static void engine_activity_set_cpu_ts(struct xe_guc *guc,
>>>unsigned int index)
>>>+{
>>>+ struct xe_guc_engine_activity *engine_activity = &guc-
>>>>engine_activity;
>>>+ struct engine_activity_group *eag = &engine_activity->eag[index];
>>> int i, j;
>>>
>>> for (i = 0; i < GUC_MAX_ENGINE_CLASSES; i++)
>>>@@ -240,36 +300,103 @@ static u32 gpm_timestamp_shift(struct xe_gt *gt)
>>> return 3 - REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
>>>}
>>>
>>>+static bool is_function_valid(struct xe_guc *guc, unsigned int fn_id)
>>>+{
>>>+ struct xe_device *xe = guc_to_xe(guc);
>>>+ struct xe_guc_engine_activity *engine_activity = &guc-
>>>>engine_activity;
>>>+
>>>+ if (!IS_SRIOV(xe) && fn_id)
>>>+ return false;
>>>+
>>>+ if (fn_id > engine_activity->num_functions)
>>
>>This ^ should be 'else if'. Consider the Native case where fn_id =
>>0. I believe num_functions will be 0 for native, so the check would
>>fail always for native. Right?
>Only if it's greater it would fail. So for native it will not.
ah, sorry my bad. Looks fine
Thanks,
Umesh
>
>In case of SRIOV too. It'll fail only if num_vfs is not set.
>So there won't be two counters one global and one PF. Only global will
>be present.
>
>Thanks
>Riana
>>
>>>+ return false;
>>>+
>>>+ return true;
>>>+}
>>>+
>>
>>Thanks,
>>Umesh
>
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH v4 7/8] drm/xe/xe_pmu: Add pmu support for per-function engine activity stats
2025-01-29 10:16 [PATCH v4 0/8] PMU Support for per-engine-class activity Riana Tauro
` (5 preceding siblings ...)
2025-01-29 10:16 ` [PATCH v4 6/8] drm/xe: Add support for per-function engine activity Riana Tauro
@ 2025-01-29 10:16 ` Riana Tauro
2025-02-01 0:00 ` Umesh Nerlige Ramappa
2025-02-01 0:23 ` Lucas De Marchi
2025-01-29 10:16 ` [PATCH v4 8/8] drm/xe/pf: Enable per-function per-engine-class " Riana Tauro
` (9 subsequent siblings)
16 siblings, 2 replies; 45+ messages in thread
From: Riana Tauro @ 2025-01-29 10:16 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, umesh.nerlige.ramappa,
lucas.demarchi, vinay.belgaumkar, soham.purkait
Add pmu support for per-function per-engine-class engine activity
stats.
per-function per-engine-class activity is enabled when num_vfs
are set. If num_vfs is set to 2, then the applicable function ids
are
0 - Global per-engine-class activity
1 - PF per-engine-class activity
2,3 - per-VF per-engine-class activity from PF
This can be read from perf tool as shown below
./perf stat -e xe_<bdf>/engine-active-ticks,gt=0,engine_class=0,
engine_instance=0,function=1/ -I 1000
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/xe_pmu.c | 45 ++++++++++++++++++++++++++++++-------
1 file changed, 37 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
index 15e9a57aa429..2968fc9a358c 100644
--- a/drivers/gpu/drm/xe/xe_pmu.c
+++ b/drivers/gpu/drm/xe/xe_pmu.c
@@ -12,6 +12,7 @@
#include "xe_hw_engine.h"
#include "xe_pm.h"
#include "xe_pmu.h"
+#include "xe_sriov_pf_helpers.h"
/**
* DOC: Xe PMU (Performance Monitoring Unit)
@@ -29,15 +30,21 @@
*
* 60 56 52 48 44 40 36 32
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
- * [ gt ]
+ * [ gt ] [ function ]
*
* 28 24 20 16 12 8 4 0
* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
* [ engine_class ] [ engine_instance ] [ event ]
*
- * engine_class and engine_instance bits will be applicable for
+ * function, engine_class and engine_instance bits will be applicable for
* per-engine-class activity events (engine-active-ticks, engine-total-ticks)
*
+ * Function id applicable for per-engine-class activity
+ *
+ * 0 - global per-engine-class activity
+ * 1 - PF per-engine-class activity
+ * 2 .. (num_vfs + 1) - per-VF per-engine-class activity from PF
+ *
* The standard perf tool can be used to grep for a certain event as well.
* Example:
*
@@ -49,6 +56,7 @@
*/
#define XE_PMU_EVENT_GT_MASK GENMASK_ULL(63, 60)
+#define XE_PMU_EVENT_FUNCTION_MASK GENMASK_ULL(59, 44)
#define XE_PMU_EVENT_ENGINE_CLASS_MASK GENMASK_ULL(27, 20)
#define XE_PMU_EVENT_ENGINE_INSTANCE_MASK GENMASK_ULL(19, 12)
#define XE_PMU_EVENT_ID_MASK GENMASK_ULL(11, 0)
@@ -58,6 +66,11 @@ static unsigned int config_to_event_id(u64 config)
return FIELD_GET(XE_PMU_EVENT_ID_MASK, config);
}
+static unsigned int config_to_function_id(u64 config)
+{
+ return FIELD_GET(XE_PMU_EVENT_FUNCTION_MASK, config);
+}
+
static unsigned int config_to_engine_class(u64 config)
{
return FIELD_GET(XE_PMU_EVENT_ENGINE_CLASS_MASK, config);
@@ -116,7 +129,7 @@ static bool event_supported(struct xe_pmu *pmu, unsigned int gt,
static bool event_param_valid(struct perf_event *event)
{
struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base);
- unsigned int engine_class, engine_instance;
+ unsigned int engine_class, engine_instance, function_id;
u64 config = event->attr.config;
struct xe_gt *gt;
@@ -124,18 +137,28 @@ static bool event_param_valid(struct perf_event *event)
if (!gt)
return false;
+ function_id = config_to_function_id(config);
+ if (function_id && !IS_SRIOV_PF(xe))
+ return false;
+
engine_class = config_to_engine_class(config);
engine_instance = config_to_engine_instance(config);
switch (config_to_event_id(config)) {
case XE_PMU_EVENT_GT_C6_RESIDENCY:
- if (engine_class || engine_instance)
+ if (engine_class || engine_instance || function_id)
return false;
break;
case XE_PMU_EVENT_ENGINE_ACTIVE_TICKS:
case XE_PMU_EVENT_ENGINE_TOTAL_TICKS:
if (!event_to_hwe(event))
return false;
+ /*
+ * Two additional functions are required for global(0)
+ * and PF(1) when SRIOV is enabled
+ */
+ if (function_id > xe_sriov_pf_get_totalvfs(xe) + 1)
+ return false;
break;
}
@@ -194,15 +217,19 @@ static u64 read_engine_events(struct perf_event *event)
{
struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base);
struct xe_hw_engine *hwe;
- u64 val = 0;
+ unsigned int function_id;
+ u64 val = 0, config;
+
+ config = event->attr.config;
+ function_id = config_to_function_id(config);
hwe = event_to_hwe(event);
if (!hwe)
drm_warn(&xe->drm, "unknown pmu engine\n");
- else if (config_to_event_id(event->attr.config) == XE_PMU_EVENT_ENGINE_ACTIVE_TICKS)
- val = xe_guc_engine_activity_active_ticks(hwe, 0);
+ else if (config_to_event_id(config) == XE_PMU_EVENT_ENGINE_ACTIVE_TICKS)
+ val = xe_guc_engine_activity_active_ticks(hwe, function_id);
else
- val = xe_guc_engine_activity_total_ticks(hwe, 0);
+ val = xe_guc_engine_activity_total_ticks(hwe, function_id);
return val;
}
@@ -305,6 +332,7 @@ static void xe_pmu_event_del(struct perf_event *event, int flags)
}
PMU_FORMAT_ATTR(gt, "config:60-63");
+PMU_FORMAT_ATTR(function, "config:44-59");
PMU_FORMAT_ATTR(engine_class, "config:20-27");
PMU_FORMAT_ATTR(engine_instance, "config:12-19");
PMU_FORMAT_ATTR(event, "config:0-11");
@@ -313,6 +341,7 @@ static struct attribute *pmu_format_attrs[] = {
&format_attr_event.attr,
&format_attr_engine_class.attr,
&format_attr_engine_instance.attr,
+ &format_attr_function.attr,
&format_attr_gt.attr,
NULL,
};
--
2.47.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* Re: [PATCH v4 7/8] drm/xe/xe_pmu: Add pmu support for per-function engine activity stats
2025-01-29 10:16 ` [PATCH v4 7/8] drm/xe/xe_pmu: Add pmu support for per-function engine activity stats Riana Tauro
@ 2025-02-01 0:00 ` Umesh Nerlige Ramappa
2025-02-01 0:23 ` Lucas De Marchi
1 sibling, 0 replies; 45+ messages in thread
From: Umesh Nerlige Ramappa @ 2025-02-01 0:00 UTC (permalink / raw)
To: Riana Tauro
Cc: intel-xe, anshuman.gupta, lucas.demarchi, vinay.belgaumkar,
soham.purkait
On Wed, Jan 29, 2025 at 03:46:50PM +0530, Riana Tauro wrote:
>Add pmu support for per-function per-engine-class engine activity
>stats.
>
>per-function per-engine-class activity is enabled when num_vfs
>are set. If num_vfs is set to 2, then the applicable function ids
>are
>
>0 - Global per-engine-class activity
>1 - PF per-engine-class activity
>2,3 - per-VF per-engine-class activity from PF
>
>This can be read from perf tool as shown below
>
>./perf stat -e xe_<bdf>/engine-active-ticks,gt=0,engine_class=0,
> engine_instance=0,function=1/ -I 1000
>
>Signed-off-by: Riana Tauro <riana.tauro@intel.com>
LGTM,
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Thanks,
Umesh
>---
> drivers/gpu/drm/xe/xe_pmu.c | 45 ++++++++++++++++++++++++++++++-------
> 1 file changed, 37 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
>index 15e9a57aa429..2968fc9a358c 100644
>--- a/drivers/gpu/drm/xe/xe_pmu.c
>+++ b/drivers/gpu/drm/xe/xe_pmu.c
>@@ -12,6 +12,7 @@
> #include "xe_hw_engine.h"
> #include "xe_pm.h"
> #include "xe_pmu.h"
>+#include "xe_sriov_pf_helpers.h"
>
> /**
> * DOC: Xe PMU (Performance Monitoring Unit)
>@@ -29,15 +30,21 @@
> *
> * 60 56 52 48 44 40 36 32
> * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
>- * [ gt ]
>+ * [ gt ] [ function ]
> *
> * 28 24 20 16 12 8 4 0
> * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
> * [ engine_class ] [ engine_instance ] [ event ]
> *
>- * engine_class and engine_instance bits will be applicable for
>+ * function, engine_class and engine_instance bits will be applicable for
> * per-engine-class activity events (engine-active-ticks, engine-total-ticks)
> *
>+ * Function id applicable for per-engine-class activity
>+ *
>+ * 0 - global per-engine-class activity
>+ * 1 - PF per-engine-class activity
>+ * 2 .. (num_vfs + 1) - per-VF per-engine-class activity from PF
>+ *
> * The standard perf tool can be used to grep for a certain event as well.
> * Example:
> *
>@@ -49,6 +56,7 @@
> */
>
> #define XE_PMU_EVENT_GT_MASK GENMASK_ULL(63, 60)
>+#define XE_PMU_EVENT_FUNCTION_MASK GENMASK_ULL(59, 44)
> #define XE_PMU_EVENT_ENGINE_CLASS_MASK GENMASK_ULL(27, 20)
> #define XE_PMU_EVENT_ENGINE_INSTANCE_MASK GENMASK_ULL(19, 12)
> #define XE_PMU_EVENT_ID_MASK GENMASK_ULL(11, 0)
>@@ -58,6 +66,11 @@ static unsigned int config_to_event_id(u64 config)
> return FIELD_GET(XE_PMU_EVENT_ID_MASK, config);
> }
>
>+static unsigned int config_to_function_id(u64 config)
>+{
>+ return FIELD_GET(XE_PMU_EVENT_FUNCTION_MASK, config);
>+}
>+
> static unsigned int config_to_engine_class(u64 config)
> {
> return FIELD_GET(XE_PMU_EVENT_ENGINE_CLASS_MASK, config);
>@@ -116,7 +129,7 @@ static bool event_supported(struct xe_pmu *pmu, unsigned int gt,
> static bool event_param_valid(struct perf_event *event)
> {
> struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base);
>- unsigned int engine_class, engine_instance;
>+ unsigned int engine_class, engine_instance, function_id;
> u64 config = event->attr.config;
> struct xe_gt *gt;
>
>@@ -124,18 +137,28 @@ static bool event_param_valid(struct perf_event *event)
> if (!gt)
> return false;
>
>+ function_id = config_to_function_id(config);
>+ if (function_id && !IS_SRIOV_PF(xe))
>+ return false;
>+
> engine_class = config_to_engine_class(config);
> engine_instance = config_to_engine_instance(config);
>
> switch (config_to_event_id(config)) {
> case XE_PMU_EVENT_GT_C6_RESIDENCY:
>- if (engine_class || engine_instance)
>+ if (engine_class || engine_instance || function_id)
> return false;
> break;
> case XE_PMU_EVENT_ENGINE_ACTIVE_TICKS:
> case XE_PMU_EVENT_ENGINE_TOTAL_TICKS:
> if (!event_to_hwe(event))
> return false;
>+ /*
>+ * Two additional functions are required for global(0)
>+ * and PF(1) when SRIOV is enabled
>+ */
>+ if (function_id > xe_sriov_pf_get_totalvfs(xe) + 1)
>+ return false;
> break;
> }
>
>@@ -194,15 +217,19 @@ static u64 read_engine_events(struct perf_event *event)
> {
> struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base);
> struct xe_hw_engine *hwe;
>- u64 val = 0;
>+ unsigned int function_id;
>+ u64 val = 0, config;
>+
>+ config = event->attr.config;
>+ function_id = config_to_function_id(config);
>
> hwe = event_to_hwe(event);
> if (!hwe)
> drm_warn(&xe->drm, "unknown pmu engine\n");
>- else if (config_to_event_id(event->attr.config) == XE_PMU_EVENT_ENGINE_ACTIVE_TICKS)
>- val = xe_guc_engine_activity_active_ticks(hwe, 0);
>+ else if (config_to_event_id(config) == XE_PMU_EVENT_ENGINE_ACTIVE_TICKS)
>+ val = xe_guc_engine_activity_active_ticks(hwe, function_id);
> else
>- val = xe_guc_engine_activity_total_ticks(hwe, 0);
>+ val = xe_guc_engine_activity_total_ticks(hwe, function_id);
>
> return val;
> }
>@@ -305,6 +332,7 @@ static void xe_pmu_event_del(struct perf_event *event, int flags)
> }
>
> PMU_FORMAT_ATTR(gt, "config:60-63");
>+PMU_FORMAT_ATTR(function, "config:44-59");
> PMU_FORMAT_ATTR(engine_class, "config:20-27");
> PMU_FORMAT_ATTR(engine_instance, "config:12-19");
> PMU_FORMAT_ATTR(event, "config:0-11");
>@@ -313,6 +341,7 @@ static struct attribute *pmu_format_attrs[] = {
> &format_attr_event.attr,
> &format_attr_engine_class.attr,
> &format_attr_engine_instance.attr,
>+ &format_attr_function.attr,
> &format_attr_gt.attr,
> NULL,
> };
>--
>2.47.1
>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 7/8] drm/xe/xe_pmu: Add pmu support for per-function engine activity stats
2025-01-29 10:16 ` [PATCH v4 7/8] drm/xe/xe_pmu: Add pmu support for per-function engine activity stats Riana Tauro
2025-02-01 0:00 ` Umesh Nerlige Ramappa
@ 2025-02-01 0:23 ` Lucas De Marchi
2025-02-01 1:21 ` Umesh Nerlige Ramappa
2025-02-03 9:59 ` Riana Tauro
1 sibling, 2 replies; 45+ messages in thread
From: Lucas De Marchi @ 2025-02-01 0:23 UTC (permalink / raw)
To: Riana Tauro
Cc: intel-xe, anshuman.gupta, umesh.nerlige.ramappa, vinay.belgaumkar,
soham.purkait
On Wed, Jan 29, 2025 at 03:46:50PM +0530, Riana Tauro wrote:
>Add pmu support for per-function per-engine-class engine activity
>stats.
>
>per-function per-engine-class activity is enabled when num_vfs
>are set. If num_vfs is set to 2, then the applicable function ids
>are
>
>0 - Global per-engine-class activity
>1 - PF per-engine-class activity
>2,3 - per-VF per-engine-class activity from PF
IMO that's super confusing. The pci function is already part of the
pmu name and hence event source:
/sys/bus/event_source/devices/xe_0000_00_02.0
function --^
in a pf/vf scenario, what's the point of the global one?
Also is it monitoring per-vf, all vfs or what? The interface looks
confusing.
>
>This can be read from perf tool as shown below
>
>./perf stat -e xe_<bdf>/engine-active-ticks,gt=0,engine_class=0,
> engine_instance=0,function=1/ -I 1000
>
>Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>---
> drivers/gpu/drm/xe/xe_pmu.c | 45 ++++++++++++++++++++++++++++++-------
> 1 file changed, 37 insertions(+), 8 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
>index 15e9a57aa429..2968fc9a358c 100644
>--- a/drivers/gpu/drm/xe/xe_pmu.c
>+++ b/drivers/gpu/drm/xe/xe_pmu.c
>@@ -12,6 +12,7 @@
> #include "xe_hw_engine.h"
> #include "xe_pm.h"
> #include "xe_pmu.h"
>+#include "xe_sriov_pf_helpers.h"
>
> /**
> * DOC: Xe PMU (Performance Monitoring Unit)
>@@ -29,15 +30,21 @@
> *
> * 60 56 52 48 44 40 36 32
> * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
>- * [ gt ]
>+ * [ gt ] [ function ]
> *
> * 28 24 20 16 12 8 4 0
> * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
> * [ engine_class ] [ engine_instance ] [ event ]
I usually like ascii art, but I'm not sure this buys us anything
compared to the GENMASKs below, particularly because they don't apply to
all events and they are **not** set in stone. Userspace is supposed to
read from sysfs what are the bits correspond to each parameter.
Lucas De Marchi
> *
>- * engine_class and engine_instance bits will be applicable for
>+ * function, engine_class and engine_instance bits will be applicable for
> * per-engine-class activity events (engine-active-ticks, engine-total-ticks)
> *
>+ * Function id applicable for per-engine-class activity
>+ *
>+ * 0 - global per-engine-class activity
>+ * 1 - PF per-engine-class activity
>+ * 2 .. (num_vfs + 1) - per-VF per-engine-class activity from PF
>+ *
> * The standard perf tool can be used to grep for a certain event as well.
> * Example:
> *
>@@ -49,6 +56,7 @@
> */
>
> #define XE_PMU_EVENT_GT_MASK GENMASK_ULL(63, 60)
>+#define XE_PMU_EVENT_FUNCTION_MASK GENMASK_ULL(59, 44)
> #define XE_PMU_EVENT_ENGINE_CLASS_MASK GENMASK_ULL(27, 20)
> #define XE_PMU_EVENT_ENGINE_INSTANCE_MASK GENMASK_ULL(19, 12)
> #define XE_PMU_EVENT_ID_MASK GENMASK_ULL(11, 0)
>@@ -58,6 +66,11 @@ static unsigned int config_to_event_id(u64 config)
> return FIELD_GET(XE_PMU_EVENT_ID_MASK, config);
> }
>
>+static unsigned int config_to_function_id(u64 config)
>+{
>+ return FIELD_GET(XE_PMU_EVENT_FUNCTION_MASK, config);
>+}
>+
> static unsigned int config_to_engine_class(u64 config)
> {
> return FIELD_GET(XE_PMU_EVENT_ENGINE_CLASS_MASK, config);
>@@ -116,7 +129,7 @@ static bool event_supported(struct xe_pmu *pmu, unsigned int gt,
> static bool event_param_valid(struct perf_event *event)
> {
> struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base);
>- unsigned int engine_class, engine_instance;
>+ unsigned int engine_class, engine_instance, function_id;
> u64 config = event->attr.config;
> struct xe_gt *gt;
>
>@@ -124,18 +137,28 @@ static bool event_param_valid(struct perf_event *event)
> if (!gt)
> return false;
>
>+ function_id = config_to_function_id(config);
>+ if (function_id && !IS_SRIOV_PF(xe))
>+ return false;
>+
> engine_class = config_to_engine_class(config);
> engine_instance = config_to_engine_instance(config);
>
> switch (config_to_event_id(config)) {
> case XE_PMU_EVENT_GT_C6_RESIDENCY:
>- if (engine_class || engine_instance)
>+ if (engine_class || engine_instance || function_id)
> return false;
> break;
> case XE_PMU_EVENT_ENGINE_ACTIVE_TICKS:
> case XE_PMU_EVENT_ENGINE_TOTAL_TICKS:
> if (!event_to_hwe(event))
> return false;
>+ /*
>+ * Two additional functions are required for global(0)
>+ * and PF(1) when SRIOV is enabled
>+ */
>+ if (function_id > xe_sriov_pf_get_totalvfs(xe) + 1)
>+ return false;
> break;
> }
>
>@@ -194,15 +217,19 @@ static u64 read_engine_events(struct perf_event *event)
> {
> struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base);
> struct xe_hw_engine *hwe;
>- u64 val = 0;
>+ unsigned int function_id;
>+ u64 val = 0, config;
>+
>+ config = event->attr.config;
>+ function_id = config_to_function_id(config);
>
> hwe = event_to_hwe(event);
> if (!hwe)
> drm_warn(&xe->drm, "unknown pmu engine\n");
>- else if (config_to_event_id(event->attr.config) == XE_PMU_EVENT_ENGINE_ACTIVE_TICKS)
>- val = xe_guc_engine_activity_active_ticks(hwe, 0);
>+ else if (config_to_event_id(config) == XE_PMU_EVENT_ENGINE_ACTIVE_TICKS)
>+ val = xe_guc_engine_activity_active_ticks(hwe, function_id);
> else
>- val = xe_guc_engine_activity_total_ticks(hwe, 0);
>+ val = xe_guc_engine_activity_total_ticks(hwe, function_id);
>
> return val;
> }
>@@ -305,6 +332,7 @@ static void xe_pmu_event_del(struct perf_event *event, int flags)
> }
>
> PMU_FORMAT_ATTR(gt, "config:60-63");
>+PMU_FORMAT_ATTR(function, "config:44-59");
> PMU_FORMAT_ATTR(engine_class, "config:20-27");
> PMU_FORMAT_ATTR(engine_instance, "config:12-19");
> PMU_FORMAT_ATTR(event, "config:0-11");
>@@ -313,6 +341,7 @@ static struct attribute *pmu_format_attrs[] = {
> &format_attr_event.attr,
> &format_attr_engine_class.attr,
> &format_attr_engine_instance.attr,
>+ &format_attr_function.attr,
> &format_attr_gt.attr,
> NULL,
> };
>--
>2.47.1
>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 7/8] drm/xe/xe_pmu: Add pmu support for per-function engine activity stats
2025-02-01 0:23 ` Lucas De Marchi
@ 2025-02-01 1:21 ` Umesh Nerlige Ramappa
2025-02-01 2:53 ` Lucas De Marchi
2025-02-03 9:59 ` Riana Tauro
1 sibling, 1 reply; 45+ messages in thread
From: Umesh Nerlige Ramappa @ 2025-02-01 1:21 UTC (permalink / raw)
To: Lucas De Marchi
Cc: Riana Tauro, intel-xe, anshuman.gupta, vinay.belgaumkar,
soham.purkait
On Fri, Jan 31, 2025 at 06:23:05PM -0600, Lucas De Marchi wrote:
>On Wed, Jan 29, 2025 at 03:46:50PM +0530, Riana Tauro wrote:
>>Add pmu support for per-function per-engine-class engine activity
>>stats.
>>
>>per-function per-engine-class activity is enabled when num_vfs
>>are set. If num_vfs is set to 2, then the applicable function ids
>>are
>>
>>0 - Global per-engine-class activity
>>1 - PF per-engine-class activity
>>2,3 - per-VF per-engine-class activity from PF
>
>IMO that's super confusing. The pci function is already part of the
>pmu name and hence event source:
>
> /sys/bus/event_source/devices/xe_0000_00_02.0
> function --^
>
>in a pf/vf scenario, what's the point of the global one?
From a use case perspective, it should be possible to add up the
utilizations across the pf/vf to get the global one. We are exposing the
global one because
1) We get that info from GuC anyways
2) Backwards compatible with tools that implement Native only support
I am open to dropping it though since I am not sure how tools will
consume this from Xe KMD.
>Also is it monitoring per-vf, all vfs or what? The interface looks
>confusing.
From a PF, KMD has the capability to monitor (1) Global = PF and all
VFs, (2) PF only and (3) specific VF.
w.r.t the interface:
I forget what was decided (if at all) on how to expose the individual PF
and VF values. Did we plan on going ahead and creating a separate PMU
event source (and PMU device) for each. In that case, this should be:
/sys/bus/event_source/devices/xe_0000_00_02.0 (Global) (should return
the same counts on Native as well as SRIOV)
/sys/bus/event_source/devices/xe_pf_0000_00_02.0 (PF monitoring PF)
/sys/bus/event_source/devices/xe_pf_0000_00_02.1 (PF monitoring VF1)
/sys/bus/event_source/devices/xe_pf_0000_00_02.2 (PF monitoring VF2)
If in future a VF will be able to monitor it's own activity, it should
be
/sys/bus/event_source/devices/xe_0000_00_02.1 (VF1 monitoring it's own
activity)
If we do that, then vf index parameter can be dropped. TBH, I like the
current interface where vf index is being passed in config, but open to
other ideas.
Thanks,
Umesh
>
>
>>
>>This can be read from perf tool as shown below
>>
>>./perf stat -e xe_<bdf>/engine-active-ticks,gt=0,engine_class=0,
>> engine_instance=0,function=1/ -I 1000
>>
>>Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>>---
>>drivers/gpu/drm/xe/xe_pmu.c | 45 ++++++++++++++++++++++++++++++-------
>>1 file changed, 37 insertions(+), 8 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
>>index 15e9a57aa429..2968fc9a358c 100644
>>--- a/drivers/gpu/drm/xe/xe_pmu.c
>>+++ b/drivers/gpu/drm/xe/xe_pmu.c
>>@@ -12,6 +12,7 @@
>>#include "xe_hw_engine.h"
>>#include "xe_pm.h"
>>#include "xe_pmu.h"
>>+#include "xe_sriov_pf_helpers.h"
>>
>>/**
>> * DOC: Xe PMU (Performance Monitoring Unit)
>>@@ -29,15 +30,21 @@
>> *
>> * 60 56 52 48 44 40 36 32
>> * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
>>- * [ gt ]
>>+ * [ gt ] [ function ]
>> *
>> * 28 24 20 16 12 8 4 0
>> * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
>> * [ engine_class ] [ engine_instance ] [ event ]
>
>I usually like ascii art, but I'm not sure this buys us anything
>compared to the GENMASKs below, particularly because they don't apply to
>all events and they are **not** set in stone. Userspace is supposed to
>read from sysfs what are the bits correspond to each parameter.
>
>Lucas De Marchi
>
>> *
>>- * engine_class and engine_instance bits will be applicable for
>>+ * function, engine_class and engine_instance bits will be applicable for
>> * per-engine-class activity events (engine-active-ticks, engine-total-ticks)
>> *
>>+ * Function id applicable for per-engine-class activity
>>+ *
>>+ * 0 - global per-engine-class activity
>>+ * 1 - PF per-engine-class activity
>>+ * 2 .. (num_vfs + 1) - per-VF per-engine-class activity from PF
>>+ *
>> * The standard perf tool can be used to grep for a certain event as well.
>> * Example:
>> *
>>@@ -49,6 +56,7 @@
>> */
>>
>>#define XE_PMU_EVENT_GT_MASK GENMASK_ULL(63, 60)
>>+#define XE_PMU_EVENT_FUNCTION_MASK GENMASK_ULL(59, 44)
>>#define XE_PMU_EVENT_ENGINE_CLASS_MASK GENMASK_ULL(27, 20)
>>#define XE_PMU_EVENT_ENGINE_INSTANCE_MASK GENMASK_ULL(19, 12)
>>#define XE_PMU_EVENT_ID_MASK GENMASK_ULL(11, 0)
>>@@ -58,6 +66,11 @@ static unsigned int config_to_event_id(u64 config)
>> return FIELD_GET(XE_PMU_EVENT_ID_MASK, config);
>>}
>>
>>+static unsigned int config_to_function_id(u64 config)
>>+{
>>+ return FIELD_GET(XE_PMU_EVENT_FUNCTION_MASK, config);
>>+}
>>+
>>static unsigned int config_to_engine_class(u64 config)
>>{
>> return FIELD_GET(XE_PMU_EVENT_ENGINE_CLASS_MASK, config);
>>@@ -116,7 +129,7 @@ static bool event_supported(struct xe_pmu *pmu, unsigned int gt,
>>static bool event_param_valid(struct perf_event *event)
>>{
>> struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base);
>>- unsigned int engine_class, engine_instance;
>>+ unsigned int engine_class, engine_instance, function_id;
>> u64 config = event->attr.config;
>> struct xe_gt *gt;
>>
>>@@ -124,18 +137,28 @@ static bool event_param_valid(struct perf_event *event)
>> if (!gt)
>> return false;
>>
>>+ function_id = config_to_function_id(config);
>>+ if (function_id && !IS_SRIOV_PF(xe))
>>+ return false;
>>+
>> engine_class = config_to_engine_class(config);
>> engine_instance = config_to_engine_instance(config);
>>
>> switch (config_to_event_id(config)) {
>> case XE_PMU_EVENT_GT_C6_RESIDENCY:
>>- if (engine_class || engine_instance)
>>+ if (engine_class || engine_instance || function_id)
>> return false;
>> break;
>> case XE_PMU_EVENT_ENGINE_ACTIVE_TICKS:
>> case XE_PMU_EVENT_ENGINE_TOTAL_TICKS:
>> if (!event_to_hwe(event))
>> return false;
>>+ /*
>>+ * Two additional functions are required for global(0)
>>+ * and PF(1) when SRIOV is enabled
>>+ */
>>+ if (function_id > xe_sriov_pf_get_totalvfs(xe) + 1)
>>+ return false;
>> break;
>> }
>>
>>@@ -194,15 +217,19 @@ static u64 read_engine_events(struct perf_event *event)
>>{
>> struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base);
>> struct xe_hw_engine *hwe;
>>- u64 val = 0;
>>+ unsigned int function_id;
>>+ u64 val = 0, config;
>>+
>>+ config = event->attr.config;
>>+ function_id = config_to_function_id(config);
>>
>> hwe = event_to_hwe(event);
>> if (!hwe)
>> drm_warn(&xe->drm, "unknown pmu engine\n");
>>- else if (config_to_event_id(event->attr.config) == XE_PMU_EVENT_ENGINE_ACTIVE_TICKS)
>>- val = xe_guc_engine_activity_active_ticks(hwe, 0);
>>+ else if (config_to_event_id(config) == XE_PMU_EVENT_ENGINE_ACTIVE_TICKS)
>>+ val = xe_guc_engine_activity_active_ticks(hwe, function_id);
>> else
>>- val = xe_guc_engine_activity_total_ticks(hwe, 0);
>>+ val = xe_guc_engine_activity_total_ticks(hwe, function_id);
>>
>> return val;
>>}
>>@@ -305,6 +332,7 @@ static void xe_pmu_event_del(struct perf_event *event, int flags)
>>}
>>
>>PMU_FORMAT_ATTR(gt, "config:60-63");
>>+PMU_FORMAT_ATTR(function, "config:44-59");
>>PMU_FORMAT_ATTR(engine_class, "config:20-27");
>>PMU_FORMAT_ATTR(engine_instance, "config:12-19");
>>PMU_FORMAT_ATTR(event, "config:0-11");
>>@@ -313,6 +341,7 @@ static struct attribute *pmu_format_attrs[] = {
>> &format_attr_event.attr,
>> &format_attr_engine_class.attr,
>> &format_attr_engine_instance.attr,
>>+ &format_attr_function.attr,
>> &format_attr_gt.attr,
>> NULL,
>>};
>>--
>>2.47.1
>>
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 7/8] drm/xe/xe_pmu: Add pmu support for per-function engine activity stats
2025-02-01 1:21 ` Umesh Nerlige Ramappa
@ 2025-02-01 2:53 ` Lucas De Marchi
0 siblings, 0 replies; 45+ messages in thread
From: Lucas De Marchi @ 2025-02-01 2:53 UTC (permalink / raw)
To: Umesh Nerlige Ramappa
Cc: Riana Tauro, intel-xe, anshuman.gupta, vinay.belgaumkar,
soham.purkait, Michal Wajdeczko
On Fri, Jan 31, 2025 at 05:21:47PM -0800, Umesh Nerlige Ramappa wrote:
>On Fri, Jan 31, 2025 at 06:23:05PM -0600, Lucas De Marchi wrote:
>>On Wed, Jan 29, 2025 at 03:46:50PM +0530, Riana Tauro wrote:
>>>Add pmu support for per-function per-engine-class engine activity
>>>stats.
>>>
>>>per-function per-engine-class activity is enabled when num_vfs
>>>are set. If num_vfs is set to 2, then the applicable function ids
>>>are
>>>
>>>0 - Global per-engine-class activity
>>>1 - PF per-engine-class activity
>>>2,3 - per-VF per-engine-class activity from PF
>>
>>IMO that's super confusing. The pci function is already part of the
>>pmu name and hence event source:
>>
>> /sys/bus/event_source/devices/xe_0000_00_02.0
>> function --^
>>
>>in a pf/vf scenario, what's the point of the global one?
>
>From a use case perspective, it should be possible to add up the
>utilizations across the pf/vf to get the global one. We are exposing
>the global one because
>
>1) We get that info from GuC anyways
>2) Backwards compatible with tools that implement Native only support
>
>I am open to dropping it though since I am not sure how tools will
>consume this from Xe KMD.
>
>>Also is it monitoring per-vf, all vfs or what? The interface looks
>>confusing.
>
>From a PF, KMD has the capability to monitor (1) Global = PF and all
>VFs, (2) PF only and (3) specific VF.
>
>w.r.t the interface:
>
>I forget what was decided (if at all) on how to expose the individual
>PF and VF values. Did we plan on going ahead and creating a separate
>PMU event source (and PMU device) for each. In that case, this should
>be:
not for the common case, which is the driver attached to the VF is
actually running inside a VM. Remeber that there's no driver for the
global one - there's only the PF driver and the VF drivers.
If the host needs to monitor the utilization by the VF, then maybe we
can use a bitmask to specify the functions, but I'm not sure.
>
>/sys/bus/event_source/devices/xe_0000_00_02.0 (Global) (should return
>the same counts on Native as well as SRIOV)
>
>/sys/bus/event_source/devices/xe_pf_0000_00_02.0 (PF monitoring PF)
>/sys/bus/event_source/devices/xe_pf_0000_00_02.1 (PF monitoring VF1)
>/sys/bus/event_source/devices/xe_pf_0000_00_02.2 (PF monitoring VF2)
that won't work... as per above, there's only one pmu driver, unless you
are attaching a vf driver on the same host, which is done only for test
purposes, not for a real case scenario.
>
>If in future a VF will be able to monitor it's own activity, it should
>be
>
>/sys/bus/event_source/devices/xe_0000_00_02.1 (VF1 monitoring it's own
>activity)
>
>If we do that, then vf index parameter can be dropped. TBH, I like the
>current interface where vf index is being passed in config, but open
>to other ideas.
maybe we only need to clarify the names and the global vs pf
distinction. Let's bring Michal to the discussion and clarify the
usages. I'd prefer to start these counters without the VF part, but in a
way that it can be extended for when we add it.
Lucas De Marchi
>
>Thanks,
>Umesh
>
>
>>
>>
>>>
>>>This can be read from perf tool as shown below
>>>
>>>./perf stat -e xe_<bdf>/engine-active-ticks,gt=0,engine_class=0,
>>> engine_instance=0,function=1/ -I 1000
>>>
>>>Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>>>---
>>>drivers/gpu/drm/xe/xe_pmu.c | 45 ++++++++++++++++++++++++++++++-------
>>>1 file changed, 37 insertions(+), 8 deletions(-)
>>>
>>>diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
>>>index 15e9a57aa429..2968fc9a358c 100644
>>>--- a/drivers/gpu/drm/xe/xe_pmu.c
>>>+++ b/drivers/gpu/drm/xe/xe_pmu.c
>>>@@ -12,6 +12,7 @@
>>>#include "xe_hw_engine.h"
>>>#include "xe_pm.h"
>>>#include "xe_pmu.h"
>>>+#include "xe_sriov_pf_helpers.h"
>>>
>>>/**
>>>* DOC: Xe PMU (Performance Monitoring Unit)
>>>@@ -29,15 +30,21 @@
>>>*
>>>* 60 56 52 48 44 40 36 32
>>>* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
>>>- * [ gt ]
>>>+ * [ gt ] [ function ]
>>>*
>>>* 28 24 20 16 12 8 4 0
>>>* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
>>>* [ engine_class ] [ engine_instance ] [ event ]
>>
>>I usually like ascii art, but I'm not sure this buys us anything
>>compared to the GENMASKs below, particularly because they don't apply to
>>all events and they are **not** set in stone. Userspace is supposed to
>>read from sysfs what are the bits correspond to each parameter.
>>
>>Lucas De Marchi
>>
>>>*
>>>- * engine_class and engine_instance bits will be applicable for
>>>+ * function, engine_class and engine_instance bits will be applicable for
>>>* per-engine-class activity events (engine-active-ticks, engine-total-ticks)
>>>*
>>>+ * Function id applicable for per-engine-class activity
>>>+ *
>>>+ * 0 - global per-engine-class activity
>>>+ * 1 - PF per-engine-class activity
>>>+ * 2 .. (num_vfs + 1) - per-VF per-engine-class activity from PF
>>>+ *
>>>* The standard perf tool can be used to grep for a certain event as well.
>>>* Example:
>>>*
>>>@@ -49,6 +56,7 @@
>>>*/
>>>
>>>#define XE_PMU_EVENT_GT_MASK GENMASK_ULL(63, 60)
>>>+#define XE_PMU_EVENT_FUNCTION_MASK GENMASK_ULL(59, 44)
>>>#define XE_PMU_EVENT_ENGINE_CLASS_MASK GENMASK_ULL(27, 20)
>>>#define XE_PMU_EVENT_ENGINE_INSTANCE_MASK GENMASK_ULL(19, 12)
>>>#define XE_PMU_EVENT_ID_MASK GENMASK_ULL(11, 0)
>>>@@ -58,6 +66,11 @@ static unsigned int config_to_event_id(u64 config)
>>> return FIELD_GET(XE_PMU_EVENT_ID_MASK, config);
>>>}
>>>
>>>+static unsigned int config_to_function_id(u64 config)
>>>+{
>>>+ return FIELD_GET(XE_PMU_EVENT_FUNCTION_MASK, config);
>>>+}
>>>+
>>>static unsigned int config_to_engine_class(u64 config)
>>>{
>>> return FIELD_GET(XE_PMU_EVENT_ENGINE_CLASS_MASK, config);
>>>@@ -116,7 +129,7 @@ static bool event_supported(struct xe_pmu *pmu, unsigned int gt,
>>>static bool event_param_valid(struct perf_event *event)
>>>{
>>> struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base);
>>>- unsigned int engine_class, engine_instance;
>>>+ unsigned int engine_class, engine_instance, function_id;
>>> u64 config = event->attr.config;
>>> struct xe_gt *gt;
>>>
>>>@@ -124,18 +137,28 @@ static bool event_param_valid(struct perf_event *event)
>>> if (!gt)
>>> return false;
>>>
>>>+ function_id = config_to_function_id(config);
>>>+ if (function_id && !IS_SRIOV_PF(xe))
>>>+ return false;
>>>+
>>> engine_class = config_to_engine_class(config);
>>> engine_instance = config_to_engine_instance(config);
>>>
>>> switch (config_to_event_id(config)) {
>>> case XE_PMU_EVENT_GT_C6_RESIDENCY:
>>>- if (engine_class || engine_instance)
>>>+ if (engine_class || engine_instance || function_id)
>>> return false;
>>> break;
>>> case XE_PMU_EVENT_ENGINE_ACTIVE_TICKS:
>>> case XE_PMU_EVENT_ENGINE_TOTAL_TICKS:
>>> if (!event_to_hwe(event))
>>> return false;
>>>+ /*
>>>+ * Two additional functions are required for global(0)
>>>+ * and PF(1) when SRIOV is enabled
>>>+ */
>>>+ if (function_id > xe_sriov_pf_get_totalvfs(xe) + 1)
>>>+ return false;
>>> break;
>>> }
>>>
>>>@@ -194,15 +217,19 @@ static u64 read_engine_events(struct perf_event *event)
>>>{
>>> struct xe_device *xe = container_of(event->pmu, typeof(*xe), pmu.base);
>>> struct xe_hw_engine *hwe;
>>>- u64 val = 0;
>>>+ unsigned int function_id;
>>>+ u64 val = 0, config;
>>>+
>>>+ config = event->attr.config;
>>>+ function_id = config_to_function_id(config);
>>>
>>> hwe = event_to_hwe(event);
>>> if (!hwe)
>>> drm_warn(&xe->drm, "unknown pmu engine\n");
>>>- else if (config_to_event_id(event->attr.config) == XE_PMU_EVENT_ENGINE_ACTIVE_TICKS)
>>>- val = xe_guc_engine_activity_active_ticks(hwe, 0);
>>>+ else if (config_to_event_id(config) == XE_PMU_EVENT_ENGINE_ACTIVE_TICKS)
>>>+ val = xe_guc_engine_activity_active_ticks(hwe, function_id);
>>> else
>>>- val = xe_guc_engine_activity_total_ticks(hwe, 0);
>>>+ val = xe_guc_engine_activity_total_ticks(hwe, function_id);
>>>
>>> return val;
>>>}
>>>@@ -305,6 +332,7 @@ static void xe_pmu_event_del(struct perf_event *event, int flags)
>>>}
>>>
>>>PMU_FORMAT_ATTR(gt, "config:60-63");
>>>+PMU_FORMAT_ATTR(function, "config:44-59");
>>>PMU_FORMAT_ATTR(engine_class, "config:20-27");
>>>PMU_FORMAT_ATTR(engine_instance, "config:12-19");
>>>PMU_FORMAT_ATTR(event, "config:0-11");
>>>@@ -313,6 +341,7 @@ static struct attribute *pmu_format_attrs[] = {
>>> &format_attr_event.attr,
>>> &format_attr_engine_class.attr,
>>> &format_attr_engine_instance.attr,
>>>+ &format_attr_function.attr,
>>> &format_attr_gt.attr,
>>> NULL,
>>>};
>>>--
>>>2.47.1
>>>
^ permalink raw reply [flat|nested] 45+ messages in thread
* Re: [PATCH v4 7/8] drm/xe/xe_pmu: Add pmu support for per-function engine activity stats
2025-02-01 0:23 ` Lucas De Marchi
2025-02-01 1:21 ` Umesh Nerlige Ramappa
@ 2025-02-03 9:59 ` Riana Tauro
1 sibling, 0 replies; 45+ messages in thread
From: Riana Tauro @ 2025-02-03 9:59 UTC (permalink / raw)
To: Lucas De Marchi
Cc: intel-xe, anshuman.gupta, umesh.nerlige.ramappa, vinay.belgaumkar,
soham.purkait
On 2/1/2025 5:53 AM, Lucas De Marchi wrote:
> On Wed, Jan 29, 2025 at 03:46:50PM +0530, Riana Tauro wrote:
>> Add pmu support for per-function per-engine-class engine activity
>> stats.
>>
>> per-function per-engine-class activity is enabled when num_vfs
>> are set. If num_vfs is set to 2, then the applicable function ids
>> are
>>
>> 0 - Global per-engine-class activity
>> 1 - PF per-engine-class activity
>> 2,3 - per-VF per-engine-class activity from PF
>
> IMO that's super confusing. The pci function is already part of the
> pmu name and hence event source:
>
> /sys/bus/event_source/devices/xe_0000_00_02.0
> function --^
>
> in a pf/vf scenario, what's the point of the global one?
> Also is it monitoring per-vf, all vfs or what? The interface looks
> confusing.
>
>
>>
>> This can be read from perf tool as shown below
>>
>> ./perf stat -e xe_<bdf>/engine-active-ticks,gt=0,engine_class=0,
>> engine_instance=0,function=1/ -I 1000
>>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_pmu.c | 45 ++++++++++++++++++++++++++++++-------
>> 1 file changed, 37 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c
>> index 15e9a57aa429..2968fc9a358c 100644
>> --- a/drivers/gpu/drm/xe/xe_pmu.c
>> +++ b/drivers/gpu/drm/xe/xe_pmu.c
>> @@ -12,6 +12,7 @@
>> #include "xe_hw_engine.h"
>> #include "xe_pm.h"
>> #include "xe_pmu.h"
>> +#include "xe_sriov_pf_helpers.h"
>>
>> /**
>> * DOC: Xe PMU (Performance Monitoring Unit)
>> @@ -29,15 +30,21 @@
>> *
>> * 60 56 52 48 44 40
>> 36 32
>> * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - -
>> - | - - - - |
>> - * [ gt ]
>> + * [ gt ] [ function ]
>> *
>> * 28 24 20 16 12 8
>> 4 0
>> * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - -
>> - | - - - - |
>> * [ engine_class ] [ engine_instance ] [
>> event ]
>
> I usually like ascii art, but I'm not sure this buys us anything
> compared to the GENMASKs below, particularly because they don't apply to
> all events and they are **not** set in stone.
Yeah but there were some pmus using similar format description in
documentation even if all the bits are not applicable to every event.
Thought adding format bits in description would be better than
going through code to find the bits. Will remove it if not required.
Will add the formats specific to engine events in description instead
Thanks
Riana
Userspace is supposed to
> read from sysfs what are the bits correspond to each parameter.
>
> Lucas De Marchi
>
>> *
>> - * engine_class and engine_instance bits will be applicable for
>> + * function, engine_class and engine_instance bits will be applicable
>> for
>> * per-engine-class activity events (engine-active-ticks, engine-
>> total-ticks)
>> *
>> + * Function id applicable for per-engine-class activity
>> + *
>> + * 0 - global per-engine-class activity
>> + * 1 - PF per-engine-class activity
>> + * 2 .. (num_vfs + 1) - per-VF per-engine-class activity from PF
>> + *
>> * The standard perf tool can be used to grep for a certain event as
>> well.
>> * Example:
>> *
>> @@ -49,6 +56,7 @@
>> */
>>
>> #define XE_PMU_EVENT_GT_MASK GENMASK_ULL(63, 60)
>> +#define XE_PMU_EVENT_FUNCTION_MASK GENMASK_ULL(59, 44)
>> #define XE_PMU_EVENT_ENGINE_CLASS_MASK GENMASK_ULL(27, 20)
>> #define XE_PMU_EVENT_ENGINE_INSTANCE_MASK GENMASK_ULL(19, 12)
>> #define XE_PMU_EVENT_ID_MASK GENMASK_ULL(11, 0)
>> @@ -58,6 +66,11 @@ static unsigned int config_to_event_id(u64 config)
>> return FIELD_GET(XE_PMU_EVENT_ID_MASK, config);
>> }
>>
>> +static unsigned int config_to_function_id(u64 config)
>> +{
>> + return FIELD_GET(XE_PMU_EVENT_FUNCTION_MASK, config);
>> +}
>> +
>> static unsigned int config_to_engine_class(u64 config)
>> {
>> return FIELD_GET(XE_PMU_EVENT_ENGINE_CLASS_MASK, config);
>> @@ -116,7 +129,7 @@ static bool event_supported(struct xe_pmu *pmu,
>> unsigned int gt,
>> static bool event_param_valid(struct perf_event *event)
>> {
>> struct xe_device *xe = container_of(event->pmu, typeof(*xe),
>> pmu.base);
>> - unsigned int engine_class, engine_instance;
>> + unsigned int engine_class, engine_instance, function_id;
>> u64 config = event->attr.config;
>> struct xe_gt *gt;
>>
>> @@ -124,18 +137,28 @@ static bool event_param_valid(struct perf_event
>> *event)
>> if (!gt)
>> return false;
>>
>> + function_id = config_to_function_id(config);
>> + if (function_id && !IS_SRIOV_PF(xe))
>> + return false;
>> +
>> engine_class = config_to_engine_class(config);
>> engine_instance = config_to_engine_instance(config);
>>
>> switch (config_to_event_id(config)) {
>> case XE_PMU_EVENT_GT_C6_RESIDENCY:
>> - if (engine_class || engine_instance)
>> + if (engine_class || engine_instance || function_id)
>> return false;
>> break;
>> case XE_PMU_EVENT_ENGINE_ACTIVE_TICKS:
>> case XE_PMU_EVENT_ENGINE_TOTAL_TICKS:
>> if (!event_to_hwe(event))
>> return false;
>> + /*
>> + * Two additional functions are required for global(0)
>> + * and PF(1) when SRIOV is enabled
>> + */
>> + if (function_id > xe_sriov_pf_get_totalvfs(xe) + 1)
>> + return false;
>> break;
>> }
>>
>> @@ -194,15 +217,19 @@ static u64 read_engine_events(struct perf_event
>> *event)
>> {
>> struct xe_device *xe = container_of(event->pmu, typeof(*xe),
>> pmu.base);
>> struct xe_hw_engine *hwe;
>> - u64 val = 0;
>> + unsigned int function_id;
>> + u64 val = 0, config;
>> +
>> + config = event->attr.config;
>> + function_id = config_to_function_id(config);
>>
>> hwe = event_to_hwe(event);
>> if (!hwe)
>> drm_warn(&xe->drm, "unknown pmu engine\n");
>> - else if (config_to_event_id(event->attr.config) ==
>> XE_PMU_EVENT_ENGINE_ACTIVE_TICKS)
>> - val = xe_guc_engine_activity_active_ticks(hwe, 0);
>> + else if (config_to_event_id(config) ==
>> XE_PMU_EVENT_ENGINE_ACTIVE_TICKS)
>> + val = xe_guc_engine_activity_active_ticks(hwe, function_id);
>> else
>> - val = xe_guc_engine_activity_total_ticks(hwe, 0);
>> + val = xe_guc_engine_activity_total_ticks(hwe, function_id);
>>
>> return val;
>> }
>> @@ -305,6 +332,7 @@ static void xe_pmu_event_del(struct perf_event
>> *event, int flags)
>> }
>>
>> PMU_FORMAT_ATTR(gt, "config:60-63");
>> +PMU_FORMAT_ATTR(function, "config:44-59");
>> PMU_FORMAT_ATTR(engine_class, "config:20-27");
>> PMU_FORMAT_ATTR(engine_instance, "config:12-19");
>> PMU_FORMAT_ATTR(event, "config:0-11");
>> @@ -313,6 +341,7 @@ static struct attribute *pmu_format_attrs[] = {
>> &format_attr_event.attr,
>> &format_attr_engine_class.attr,
>> &format_attr_engine_instance.attr,
>> + &format_attr_function.attr,
>> &format_attr_gt.attr,
>> NULL,
>> };
>> --
>> 2.47.1
>>
^ permalink raw reply [flat|nested] 45+ messages in thread
* [PATCH v4 8/8] drm/xe/pf: Enable per-function per-engine-class activity stats
2025-01-29 10:16 [PATCH v4 0/8] PMU Support for per-engine-class activity Riana Tauro
` (6 preceding siblings ...)
2025-01-29 10:16 ` [PATCH v4 7/8] drm/xe/xe_pmu: Add pmu support for per-function engine activity stats Riana Tauro
@ 2025-01-29 10:16 ` Riana Tauro
2025-01-29 11:38 ` ✓ CI.Patch_applied: success for PMU Support for per-engine-class activity (rev2) Patchwork
` (8 subsequent siblings)
16 siblings, 0 replies; 45+ messages in thread
From: Riana Tauro @ 2025-01-29 10:16 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, umesh.nerlige.ramappa,
lucas.demarchi, vinay.belgaumkar, soham.purkait
Enable per-function per-engine-class activity stats when
sriov_numvfs are set and disable when sriov_numvfs
are set to 0.
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/xe_pci_sriov.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_pci_sriov.c b/drivers/gpu/drm/xe/xe_pci_sriov.c
index aaceee748287..fd0c1284deff 100644
--- a/drivers/gpu/drm/xe/xe_pci_sriov.c
+++ b/drivers/gpu/drm/xe/xe_pci_sriov.c
@@ -7,6 +7,7 @@
#include "xe_device.h"
#include "xe_gt_sriov_pf_config.h"
#include "xe_gt_sriov_pf_control.h"
+#include "xe_guc_engine_activity.h"
#include "xe_pci_sriov.h"
#include "xe_pm.h"
#include "xe_sriov.h"
@@ -62,6 +63,18 @@ static void pf_reset_vfs(struct xe_device *xe, unsigned int num_vfs)
xe_gt_sriov_pf_control_trigger_flr(gt, n);
}
+static int pf_engine_activity_stats(struct xe_device *xe, unsigned int num_vfs, bool enable)
+{
+ struct xe_gt *gt;
+ unsigned int id;
+ int ret = 0;
+
+ for_each_gt(gt, xe, id)
+ ret = xe_guc_engine_activity_function_stats(>->uc.guc, num_vfs, enable);
+
+ return ret;
+}
+
static int pf_enable_vfs(struct xe_device *xe, int num_vfs)
{
struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
@@ -94,6 +107,11 @@ static int pf_enable_vfs(struct xe_device *xe, int num_vfs)
xe_sriov_info(xe, "Enabled %u of %u VF%s\n",
num_vfs, total_vfs, str_plural(total_vfs));
+
+ err = pf_engine_activity_stats(xe, num_vfs, true);
+ if (err < 0)
+ xe_sriov_warn(xe, "Failed to enable function activity stats\n");
+
return num_vfs;
failed:
@@ -110,6 +128,7 @@ static int pf_disable_vfs(struct xe_device *xe)
struct device *dev = xe->drm.dev;
struct pci_dev *pdev = to_pci_dev(dev);
u16 num_vfs = pci_num_vf(pdev);
+ int err;
xe_assert(xe, IS_SRIOV_PF(xe));
xe_sriov_dbg(xe, "disabling %u VF%s\n", num_vfs, str_plural(num_vfs));
@@ -117,6 +136,10 @@ static int pf_disable_vfs(struct xe_device *xe)
if (!num_vfs)
return 0;
+ err = pf_engine_activity_stats(xe, num_vfs, false);
+ if (err < 0)
+ xe_sriov_warn(xe, "Failed to disable function activity stats\n");
+
pci_disable_sriov(pdev);
pf_reset_vfs(xe, num_vfs);
--
2.47.1
^ permalink raw reply related [flat|nested] 45+ messages in thread* ✓ CI.Patch_applied: success for PMU Support for per-engine-class activity (rev2)
2025-01-29 10:16 [PATCH v4 0/8] PMU Support for per-engine-class activity Riana Tauro
` (7 preceding siblings ...)
2025-01-29 10:16 ` [PATCH v4 8/8] drm/xe/pf: Enable per-function per-engine-class " Riana Tauro
@ 2025-01-29 11:38 ` Patchwork
2025-01-29 11:39 ` ✗ CI.checkpatch: warning " Patchwork
` (7 subsequent siblings)
16 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2025-01-29 11:38 UTC (permalink / raw)
To: Riana Tauro; +Cc: intel-xe
== Series Details ==
Series: PMU Support for per-engine-class activity (rev2)
URL : https://patchwork.freedesktop.org/series/143138/
State : success
== Summary ==
=== Applying kernel patches on branch 'drm-tip' with base: ===
Base commit: 683350734da3 drm-tip: 2025y-01m-29d-09h-19m-10s UTC integration manifest
=== git am output follows ===
.git/rebase-apply/patch:493: new blank line at EOF.
+
warning: 1 line adds whitespace errors.
Applying: drm/xe: Add per-engine-class activity support
Applying: drm/xe/trace: Add trace for engine activity
Applying: drm/xe/guc: Expose engine activity only for supported GuC version
Applying: drm/xe/xe_pmu: Add PMU support for per-engine-class activity
Applying: drm/xe/guc: Bump minimum required GuC version to v70.36.0
Applying: drm/xe: Add support for per-function engine activity
Applying: drm/xe/xe_pmu: Add pmu support for per-function engine activity stats
Applying: drm/xe/pf: Enable per-function per-engine-class activity stats
^ permalink raw reply [flat|nested] 45+ messages in thread* ✗ CI.checkpatch: warning for PMU Support for per-engine-class activity (rev2)
2025-01-29 10:16 [PATCH v4 0/8] PMU Support for per-engine-class activity Riana Tauro
` (8 preceding siblings ...)
2025-01-29 11:38 ` ✓ CI.Patch_applied: success for PMU Support for per-engine-class activity (rev2) Patchwork
@ 2025-01-29 11:39 ` Patchwork
2025-01-29 11:40 ` ✓ CI.KUnit: success " Patchwork
` (6 subsequent siblings)
16 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2025-01-29 11:39 UTC (permalink / raw)
To: Riana Tauro; +Cc: intel-xe
== Series Details ==
Series: PMU Support for per-engine-class activity (rev2)
URL : https://patchwork.freedesktop.org/series/143138/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 242d060ad87b12b2a73e32f11093802d44542b0b
Author: Riana Tauro <riana.tauro@intel.com>
Date: Wed Jan 29 15:46:51 2025 +0530
drm/xe/pf: Enable per-function per-engine-class activity stats
Enable per-function per-engine-class activity stats when
sriov_numvfs are set and disable when sriov_numvfs
are set to 0.
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
+ /mt/dim checkpatch 683350734da38bc7332a3b87c9f2faf6bbeeb5a3 drm-intel
a22e3df22e12 drm/xe: Add per-engine-class activity support
-:10: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#10:
Engine Active Ticks(engine-active-ticks) - number of active ticks for engine
-:71: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#71:
new file mode 100644
-:529: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#529: FILE: drivers/gpu/drm/xe/xe_guc_fwif.h:220:
+ struct guc_engine_activity engine_activity[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
total: 0 errors, 3 warnings, 0 checks, 487 lines checked
f88f555a0275 drm/xe/trace: Add trace for engine activity
-:67: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#67: FILE: drivers/gpu/drm/xe/xe_trace_guc.h:109:
+ TP_STRUCT__entry(
-:84: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#84: FILE: drivers/gpu/drm/xe/xe_trace_guc.h:126:
+ TP_fast_assign(
total: 0 errors, 0 warnings, 2 checks, 84 lines checked
e93bf99b5dbb drm/xe/guc: Expose engine activity only for supported GuC version
124a70a5b15b drm/xe/xe_pmu: Add PMU support for per-engine-class activity
-:141: WARNING:SPACE_BEFORE_TAB: please, no space before tabs
#141: FILE: drivers/gpu/drm/xe/xe_pmu.c:78:
+#define XE_PMU_EVENT_ENGINE_TOTAL_TICKS ^I0x03$
-:272: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#272: FILE: drivers/gpu/drm/xe/xe_pmu.c:374:
+XE_EVENT_ATTR_NOUNIT(engine-active-ticks, engine_active_ticks, XE_PMU_EVENT_ENGINE_ACTIVE_TICKS);
^
-:272: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#272: FILE: drivers/gpu/drm/xe/xe_pmu.c:374:
+XE_EVENT_ATTR_NOUNIT(engine-active-ticks, engine_active_ticks, XE_PMU_EVENT_ENGINE_ACTIVE_TICKS);
^
-:273: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#273: FILE: drivers/gpu/drm/xe/xe_pmu.c:375:
+XE_EVENT_ATTR_NOUNIT(engine-total-ticks, engine_total_ticks, XE_PMU_EVENT_ENGINE_TOTAL_TICKS);
^
-:273: CHECK:SPACING: spaces preferred around that '-' (ctx:VxV)
#273: FILE: drivers/gpu/drm/xe/xe_pmu.c:375:
+XE_EVENT_ATTR_NOUNIT(engine-total-ticks, engine_total_ticks, XE_PMU_EVENT_ENGINE_TOTAL_TICKS);
^
total: 0 errors, 1 warnings, 4 checks, 256 lines checked
3c262b0c3548 drm/xe/guc: Bump minimum required GuC version to v70.36.0
68eb772e5f75 drm/xe: Add support for per-function engine activity
b5de7ca45317 drm/xe/xe_pmu: Add pmu support for per-function engine activity stats
242d060ad87b drm/xe/pf: Enable per-function per-engine-class activity stats
^ permalink raw reply [flat|nested] 45+ messages in thread* ✓ CI.KUnit: success for PMU Support for per-engine-class activity (rev2)
2025-01-29 10:16 [PATCH v4 0/8] PMU Support for per-engine-class activity Riana Tauro
` (9 preceding siblings ...)
2025-01-29 11:39 ` ✗ CI.checkpatch: warning " Patchwork
@ 2025-01-29 11:40 ` Patchwork
2025-01-29 11:56 ` ✓ CI.Build: " Patchwork
` (5 subsequent siblings)
16 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2025-01-29 11:40 UTC (permalink / raw)
To: Riana Tauro; +Cc: intel-xe
== Series Details ==
Series: PMU Support for per-engine-class activity (rev2)
URL : https://patchwork.freedesktop.org/series/143138/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[11:39:03] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:39:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
156 | u64 ioread64_lo_hi(const void __iomem *addr)
| ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
163 | u64 ioread64_hi_lo(const void __iomem *addr)
| ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
170 | u64 ioread64be_lo_hi(const void __iomem *addr)
| ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
178 | u64 ioread64be_hi_lo(const void __iomem *addr)
| ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~~~
[11:39:33] Starting KUnit Kernel (1/1)...
[11:39:33] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:39:34] ================== guc_buf (11 subtests) ===================
[11:39:34] [PASSED] test_smallest
[11:39:34] [PASSED] test_largest
[11:39:34] [PASSED] test_granular
[11:39:34] [PASSED] test_unique
[11:39:34] [PASSED] test_overlap
[11:39:34] [PASSED] test_reusable
[11:39:34] [PASSED] test_too_big
[11:39:34] [PASSED] test_flush
[11:39:34] [PASSED] test_lookup
[11:39:34] [PASSED] test_data
[11:39:34] [PASSED] test_class
[11:39:34] ===================== [PASSED] guc_buf =====================
[11:39:34] =================== guc_dbm (7 subtests) ===================
[11:39:34] [PASSED] test_empty
[11:39:34] [PASSED] test_default
[11:39:34] ======================== test_size ========================
[11:39:34] [PASSED] 4
[11:39:34] [PASSED] 8
[11:39:34] [PASSED] 32
[11:39:34] [PASSED] 256
[11:39:34] ==================== [PASSED] test_size ====================
[11:39:34] ======================= test_reuse ========================
[11:39:34] [PASSED] 4
[11:39:34] [PASSED] 8
[11:39:34] [PASSED] 32
[11:39:34] [PASSED] 256
[11:39:34] =================== [PASSED] test_reuse ====================
[11:39:34] =================== test_range_overlap ====================
[11:39:34] [PASSED] 4
[11:39:34] [PASSED] 8
[11:39:34] [PASSED] 32
[11:39:34] [PASSED] 256
[11:39:34] =============== [PASSED] test_range_overlap ================
[11:39:34] =================== test_range_compact ====================
[11:39:34] [PASSED] 4
[11:39:34] [PASSED] 8
[11:39:34] [PASSED] 32
[11:39:34] [PASSED] 256
[11:39:34] =============== [PASSED] test_range_compact ================
[11:39:34] ==================== test_range_spare =====================
[11:39:34] [PASSED] 4
[11:39:34] [PASSED] 8
[11:39:34] [PASSED] 32
[11:39:34] [PASSED] 256
[11:39:34] ================ [PASSED] test_range_spare =================
[11:39:34] ===================== [PASSED] guc_dbm =====================
[11:39:34] =================== guc_idm (6 subtests) ===================
[11:39:34] [PASSED] bad_init
[11:39:34] [PASSED] no_init
[11:39:34] [PASSED] init_fini
[11:39:34] [PASSED] check_used
[11:39:34] [PASSED] check_quota
[11:39:34] [PASSED] check_all
[11:39:34] ===================== [PASSED] guc_idm =====================
[11:39:34] ================== no_relay (3 subtests) ===================
[11:39:34] [PASSED] xe_drops_guc2pf_if_not_ready
[11:39:34] [PASSED] xe_drops_guc2vf_if_not_ready
[11:39:34] [PASSED] xe_rejects_send_if_not_ready
[11:39:34] ==================== [PASSED] no_relay =====================
[11:39:34] ================== pf_relay (14 subtests) ==================
[11:39:34] [PASSED] pf_rejects_guc2pf_too_short
[11:39:34] [PASSED] pf_rejects_guc2pf_too_long
[11:39:34] [PASSED] pf_rejects_guc2pf_no_payload
[11:39:34] [PASSED] pf_fails_no_payload
[11:39:34] [PASSED] pf_fails_bad_origin
[11:39:34] [PASSED] pf_fails_bad_type
[11:39:34] [PASSED] pf_txn_reports_error
[11:39:34] [PASSED] pf_txn_sends_pf2guc
[11:39:34] [PASSED] pf_sends_pf2guc
[11:39:34] [SKIPPED] pf_loopback_nop
[11:39:34] [SKIPPED] pf_loopback_echo
[11:39:34] [SKIPPED] pf_loopback_fail
[11:39:34] [SKIPPED] pf_loopback_busy
[11:39:34] [SKIPPED] pf_loopback_retry
[11:39:34] ==================== [PASSED] pf_relay =====================
[11:39:34] ================== vf_relay (3 subtests) ===================
[11:39:34] [PASSED] vf_rejects_guc2vf_too_short
[11:39:34] [PASSED] vf_rejects_guc2vf_too_long
[11:39:34] [PASSED] vf_rejects_guc2vf_no_payload
[11:39:34] ==================== [PASSED] vf_relay =====================
[11:39:34] ================= pf_service (11 subtests) =================
[11:39:34] [PASSED] pf_negotiate_any
[11:39:34] [PASSED] pf_negotiate_base_match
[11:39:34] [PASSED] pf_negotiate_base_newer
[11:39:34] [PASSED] pf_negotiate_base_next
[11:39:34] [SKIPPED] pf_negotiate_base_older
[11:39:34] [PASSED] pf_negotiate_base_prev
[11:39:34] [PASSED] pf_negotiate_latest_match
[11:39:34] [PASSED] pf_negotiate_latest_newer
[11:39:34] [PASSED] pf_negotiate_latest_next
[11:39:34] [SKIPPED] pf_negotiate_latest_older
[11:39:34] [SKIPPED] pf_negotiate_latest_prev
[11:39:34] =================== [PASSED] pf_service ====================
[11:39:34] ===================== lmtt (1 subtest) =====================
[11:39:34] ======================== test_ops =========================
[11:39:34] [PASSED] 2-level
[11:39:34] [PASSED] multi-level
[11:39:34] ==================== [PASSED] test_ops =====================
[11:39:34] ====================== [PASSED] lmtt =======================
[11:39:34] =================== xe_mocs (2 subtests) ===================
[11:39:34] ================ xe_live_mocs_kernel_kunit ================
[11:39:34] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[11:39:34] ================ xe_live_mocs_reset_kunit =================
[11:39:34] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[11:39:34] ==================== [SKIPPED] xe_mocs =====================
[11:39:34] ================= xe_migrate (2 subtests) ==================
[11:39:34] ================= xe_migrate_sanity_kunit =================
[11:39:34] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[11:39:34] ================== xe_validate_ccs_kunit ==================
[11:39:34] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[11:39:34] =================== [SKIPPED] xe_migrate ===================
[11:39:34] ================== xe_dma_buf (1 subtest) ==================
[11:39:34] ==================== xe_dma_buf_kunit =====================
[11:39:34] ================ [SKIPPED] xe_dma_buf_kunit ================
[11:39:34] =================== [SKIPPED] xe_dma_buf ===================
[11:39:34] ================= xe_bo_shrink (1 subtest) =================
[11:39:34] =================== xe_bo_shrink_kunit ====================
[11:39:34] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[11:39:34] ================== [SKIPPED] xe_bo_shrink ==================
[11:39:34] ==================== xe_bo (2 subtests) ====================
[11:39:34] ================== xe_ccs_migrate_kunit ===================
[11:39:34] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
stty: 'standard input': Inappropriate ioctl for device
[11:39:34] ==================== xe_bo_evict_kunit ====================
[11:39:34] =============== [SKIPPED] xe_bo_evict_kunit ================
[11:39:34] ===================== [SKIPPED] xe_bo ======================
[11:39:34] ==================== args (11 subtests) ====================
[11:39:34] [PASSED] count_args_test
[11:39:34] [PASSED] call_args_example
[11:39:34] [PASSED] call_args_test
[11:39:34] [PASSED] drop_first_arg_example
[11:39:34] [PASSED] drop_first_arg_test
[11:39:34] [PASSED] first_arg_example
[11:39:34] [PASSED] first_arg_test
[11:39:34] [PASSED] last_arg_example
[11:39:34] [PASSED] last_arg_test
[11:39:34] [PASSED] pick_arg_example
[11:39:34] [PASSED] sep_comma_example
[11:39:34] ====================== [PASSED] args =======================
[11:39:34] =================== xe_pci (2 subtests) ====================
[11:39:34] [PASSED] xe_gmdid_graphics_ip
[11:39:34] [PASSED] xe_gmdid_media_ip
[11:39:34] ===================== [PASSED] xe_pci ======================
[11:39:34] =================== xe_rtp (2 subtests) ====================
[11:39:34] =============== xe_rtp_process_to_sr_tests ================
[11:39:34] [PASSED] coalesce-same-reg
[11:39:34] [PASSED] no-match-no-add
[11:39:34] [PASSED] match-or
[11:39:34] [PASSED] match-or-xfail
[11:39:34] [PASSED] no-match-no-add-multiple-rules
[11:39:34] [PASSED] two-regs-two-entries
[11:39:34] [PASSED] clr-one-set-other
[11:39:34] [PASSED] set-field
[11:39:34] [PASSED] conflict-duplicate
[11:39:34] [PASSED] conflict-not-disjoint
[11:39:34] [PASSED] conflict-reg-type
[11:39:34] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[11:39:34] ================== xe_rtp_process_tests ===================
[11:39:34] [PASSED] active1
[11:39:34] [PASSED] active2
[11:39:34] [PASSED] active-inactive
[11:39:34] [PASSED] inactive-active
[11:39:34] [PASSED] inactive-1st_or_active-inactive
[11:39:34] [PASSED] inactive-2nd_or_active-inactive
[11:39:34] [PASSED] inactive-last_or_active-inactive
[11:39:34] [PASSED] inactive-no_or_active-inactive
[11:39:34] ============== [PASSED] xe_rtp_process_tests ===============
[11:39:34] ===================== [PASSED] xe_rtp ======================
[11:39:34] ==================== xe_wa (1 subtest) =====================
[11:39:34] ======================== xe_wa_gt =========================
[11:39:34] [PASSED] TIGERLAKE (B0)
[11:39:34] [PASSED] DG1 (A0)
[11:39:34] [PASSED] DG1 (B0)
[11:39:34] [PASSED] ALDERLAKE_S (A0)
[11:39:34] [PASSED] ALDERLAKE_S (B0)
[11:39:34] [PASSED] ALDERLAKE_S (C0)
[11:39:34] [PASSED] ALDERLAKE_S (D0)
[11:39:34] [PASSED] ALDERLAKE_P (A0)
[11:39:34] [PASSED] ALDERLAKE_P (B0)
[11:39:34] [PASSED] ALDERLAKE_P (C0)
[11:39:34] [PASSED] ALDERLAKE_S_RPLS (D0)
[11:39:34] [PASSED] ALDERLAKE_P_RPLU (E0)
[11:39:34] [PASSED] DG2_G10 (C0)
[11:39:34] [PASSED] DG2_G11 (B1)
[11:39:34] [PASSED] DG2_G12 (A1)
[11:39:34] [PASSED] METEORLAKE (g:A0, m:A0)
[11:39:34] [PASSED] METEORLAKE (g:A0, m:A0)
[11:39:34] [PASSED] METEORLAKE (g:A0, m:A0)
[11:39:34] [PASSED] LUNARLAKE (g:A0, m:A0)
[11:39:34] [PASSED] LUNARLAKE (g:B0, m:A0)
[11:39:34] [PASSED] BATTLEMAGE (g:A0, m:A1)
[11:39:34] ==================== [PASSED] xe_wa_gt =====================
[11:39:34] ====================== [PASSED] xe_wa ======================
[11:39:34] ============================================================
[11:39:34] Testing complete. Ran 133 tests: passed: 117, skipped: 16
[11:39:34] Elapsed time: 30.287s total, 4.195s configuring, 25.775s building, 0.266s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[11:39:34] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:39:35] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
156 | u64 ioread64_lo_hi(const void __iomem *addr)
| ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
163 | u64 ioread64_hi_lo(const void __iomem *addr)
| ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
170 | u64 ioread64be_lo_hi(const void __iomem *addr)
| ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
178 | u64 ioread64be_hi_lo(const void __iomem *addr)
| ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~~~
[11:39:56] Starting KUnit Kernel (1/1)...
[11:39:56] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:39:56] =========== drm_validate_clone_mode (2 subtests) ===========
[11:39:56] ============== drm_test_check_in_clone_mode ===============
[11:39:56] [PASSED] in_clone_mode
[11:39:56] [PASSED] not_in_clone_mode
[11:39:56] ========== [PASSED] drm_test_check_in_clone_mode ===========
[11:39:56] =============== drm_test_check_valid_clones ===============
[11:39:56] [PASSED] not_in_clone_mode
[11:39:56] [PASSED] valid_clone
[11:39:56] [PASSED] invalid_clone
[11:39:56] =========== [PASSED] drm_test_check_valid_clones ===========
[11:39:56] ============= [PASSED] drm_validate_clone_mode =============
[11:39:56] ============= drm_validate_modeset (1 subtest) =============
[11:39:56] [PASSED] drm_test_check_connector_changed_modeset
[11:39:56] ============== [PASSED] drm_validate_modeset ===============
[11:39:56] ================== drm_buddy (7 subtests) ==================
[11:39:56] [PASSED] drm_test_buddy_alloc_limit
[11:39:56] [PASSED] drm_test_buddy_alloc_optimistic
[11:39:56] [PASSED] drm_test_buddy_alloc_pessimistic
[11:39:56] [PASSED] drm_test_buddy_alloc_pathological
[11:39:56] [PASSED] drm_test_buddy_alloc_contiguous
[11:39:56] [PASSED] drm_test_buddy_alloc_clear
[11:39:56] [PASSED] drm_test_buddy_alloc_range_bias
[11:39:56] ==================== [PASSED] drm_buddy ====================
[11:39:56] ============= drm_cmdline_parser (40 subtests) =============
[11:39:56] [PASSED] drm_test_cmdline_force_d_only
[11:39:56] [PASSED] drm_test_cmdline_force_D_only_dvi
[11:39:56] [PASSED] drm_test_cmdline_force_D_only_hdmi
[11:39:56] [PASSED] drm_test_cmdline_force_D_only_not_digital
[11:39:56] [PASSED] drm_test_cmdline_force_e_only
[11:39:56] [PASSED] drm_test_cmdline_res
[11:39:56] [PASSED] drm_test_cmdline_res_vesa
[11:39:56] [PASSED] drm_test_cmdline_res_vesa_rblank
[11:39:56] [PASSED] drm_test_cmdline_res_rblank
[11:39:56] [PASSED] drm_test_cmdline_res_bpp
[11:39:56] [PASSED] drm_test_cmdline_res_refresh
[11:39:56] [PASSED] drm_test_cmdline_res_bpp_refresh
[11:39:56] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[11:39:56] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[11:39:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[11:39:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[11:39:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[11:39:56] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[11:39:56] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[11:39:56] [PASSED] drm_test_cmdline_res_margins_force_on
[11:39:56] [PASSED] drm_test_cmdline_res_vesa_margins
[11:39:56] [PASSED] drm_test_cmdline_name
[11:39:56] [PASSED] drm_test_cmdline_name_bpp
[11:39:56] [PASSED] drm_test_cmdline_name_option
[11:39:56] [PASSED] drm_test_cmdline_name_bpp_option
[11:39:56] [PASSED] drm_test_cmdline_rotate_0
[11:39:56] [PASSED] drm_test_cmdline_rotate_90
[11:39:56] [PASSED] drm_test_cmdline_rotate_180
[11:39:56] [PASSED] drm_test_cmdline_rotate_270
[11:39:56] [PASSED] drm_test_cmdline_hmirror
[11:39:56] [PASSED] drm_test_cmdline_vmirror
[11:39:56] [PASSED] drm_test_cmdline_margin_options
[11:39:56] [PASSED] drm_test_cmdline_multiple_options
[11:39:56] [PASSED] drm_test_cmdline_bpp_extra_and_option
[11:39:56] [PASSED] drm_test_cmdline_extra_and_option
[11:39:56] [PASSED] drm_test_cmdline_freestanding_options
[11:39:56] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[11:39:56] [PASSED] drm_test_cmdline_panel_orientation
[11:39:56] ================ drm_test_cmdline_invalid =================
[11:39:56] [PASSED] margin_only
[11:39:56] [PASSED] interlace_only
[11:39:56] [PASSED] res_missing_x
[11:39:56] [PASSED] res_missing_y
[11:39:56] [PASSED] res_bad_y
[11:39:56] [PASSED] res_missing_y_bpp
[11:39:56] [PASSED] res_bad_bpp
[11:39:56] [PASSED] res_bad_refresh
[11:39:56] [PASSED] res_bpp_refresh_force_on_off
[11:39:56] [PASSED] res_invalid_mode
[11:39:56] [PASSED] res_bpp_wrong_place_mode
[11:39:56] [PASSED] name_bpp_refresh
[11:39:56] [PASSED] name_refresh
[11:39:56] [PASSED] name_refresh_wrong_mode
[11:39:56] [PASSED] name_refresh_invalid_mode
[11:39:56] [PASSED] rotate_multiple
[11:39:56] [PASSED] rotate_invalid_val
[11:39:56] [PASSED] rotate_truncated
[11:39:56] [PASSED] invalid_option
[11:39:56] [PASSED] invalid_tv_option
[11:39:56] [PASSED] truncated_tv_option
[11:39:56] ============ [PASSED] drm_test_cmdline_invalid =============
[11:39:56] =============== drm_test_cmdline_tv_options ===============
[11:39:56] [PASSED] NTSC
[11:39:56] [PASSED] NTSC_443
[11:39:56] [PASSED] NTSC_J
[11:39:56] [PASSED] PAL
[11:39:56] [PASSED] PAL_M
[11:39:56] [PASSED] PAL_N
[11:39:56] [PASSED] SECAM
[11:39:56] [PASSED] MONO_525
[11:39:56] [PASSED] MONO_625
[11:39:56] =========== [PASSED] drm_test_cmdline_tv_options ===========
[11:39:56] =============== [PASSED] drm_cmdline_parser ================
[11:39:56] ========== drmm_connector_hdmi_init (20 subtests) ==========
[11:39:56] [PASSED] drm_test_connector_hdmi_init_valid
[11:39:56] [PASSED] drm_test_connector_hdmi_init_bpc_8
[11:39:56] [PASSED] drm_test_connector_hdmi_init_bpc_10
[11:39:56] [PASSED] drm_test_connector_hdmi_init_bpc_12
[11:39:56] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[11:39:56] [PASSED] drm_test_connector_hdmi_init_bpc_null
[11:39:56] [PASSED] drm_test_connector_hdmi_init_formats_empty
[11:39:56] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[11:39:56] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:39:56] [PASSED] supported_formats=0x9 yuv420_allowed=1
[11:39:56] [PASSED] supported_formats=0x9 yuv420_allowed=0
[11:39:56] [PASSED] supported_formats=0x3 yuv420_allowed=1
[11:39:56] [PASSED] supported_formats=0x3 yuv420_allowed=0
[11:39:56] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:39:56] [PASSED] drm_test_connector_hdmi_init_null_ddc
[11:39:56] [PASSED] drm_test_connector_hdmi_init_null_product
[11:39:56] [PASSED] drm_test_connector_hdmi_init_null_vendor
[11:39:56] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[11:39:56] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[11:39:56] [PASSED] drm_test_connector_hdmi_init_product_valid
[11:39:56] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[11:39:56] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[11:39:56] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[11:39:56] ========= drm_test_connector_hdmi_init_type_valid =========
[11:39:56] [PASSED] HDMI-A
[11:39:56] [PASSED] HDMI-B
[11:39:56] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[11:39:56] ======== drm_test_connector_hdmi_init_type_invalid ========
[11:39:56] [PASSED] Unknown
[11:39:56] [PASSED] VGA
[11:39:56] [PASSED] DVI-I
[11:39:56] [PASSED] DVI-D
[11:39:56] [PASSED] DVI-A
[11:39:56] [PASSED] Composite
[11:39:56] [PASSED] SVIDEO
[11:39:56] [PASSED] LVDS
[11:39:56] [PASSED] Component
[11:39:56] [PASSED] DIN
[11:39:56] [PASSED] DP
[11:39:56] [PASSED] TV
[11:39:56] [PASSED] eDP
[11:39:56] [PASSED] Virtual
[11:39:56] [PASSED] DSI
[11:39:56] [PASSED] DPI
[11:39:56] [PASSED] Writeback
[11:39:56] [PASSED] SPI
[11:39:56] [PASSED] USB
[11:39:56] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[11:39:56] ============ [PASSED] drmm_connector_hdmi_init =============
[11:39:56] ============= drmm_connector_init (3 subtests) =============
[11:39:56] [PASSED] drm_test_drmm_connector_init
[11:39:56] [PASSED] drm_test_drmm_connector_init_null_ddc
[11:39:56] ========= drm_test_drmm_connector_init_type_valid =========
[11:39:56] [PASSED] Unknown
[11:39:56] [PASSED] VGA
[11:39:56] [PASSED] DVI-I
[11:39:56] [PASSED] DVI-D
[11:39:56] [PASSED] DVI-A
[11:39:56] [PASSED] Composite
[11:39:56] [PASSED] SVIDEO
[11:39:56] [PASSED] LVDS
[11:39:56] [PASSED] Component
[11:39:56] [PASSED] DIN
[11:39:56] [PASSED] DP
[11:39:56] [PASSED] HDMI-A
[11:39:56] [PASSED] HDMI-B
[11:39:56] [PASSED] TV
[11:39:56] [PASSED] eDP
[11:39:56] [PASSED] Virtual
[11:39:56] [PASSED] DSI
[11:39:56] [PASSED] DPI
[11:39:56] [PASSED] Writeback
[11:39:56] [PASSED] SPI
[11:39:56] [PASSED] USB
[11:39:56] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[11:39:56] =============== [PASSED] drmm_connector_init ===============
[11:39:56] ========= drm_connector_dynamic_init (6 subtests) ==========
[11:39:56] [PASSED] drm_test_drm_connector_dynamic_init
[11:39:56] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[11:39:56] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[11:39:56] [PASSED] drm_test_drm_connector_dynamic_init_properties
[11:39:56] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[11:39:56] [PASSED] Unknown
[11:39:56] [PASSED] VGA
[11:39:56] [PASSED] DVI-I
[11:39:56] [PASSED] DVI-D
[11:39:56] [PASSED] DVI-A
[11:39:56] [PASSED] Composite
[11:39:56] [PASSED] SVIDEO
[11:39:56] [PASSED] LVDS
[11:39:56] [PASSED] Component
[11:39:56] [PASSED] DIN
[11:39:56] [PASSED] DP
[11:39:56] [PASSED] HDMI-A
[11:39:56] [PASSED] HDMI-B
[11:39:56] [PASSED] TV
[11:39:56] [PASSED] eDP
[11:39:56] [PASSED] Virtual
[11:39:56] [PASSED] DSI
[11:39:56] [PASSED] DPI
[11:39:56] [PASSED] Writeback
[11:39:56] [PASSED] SPI
[11:39:56] [PASSED] USB
[11:39:56] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[11:39:56] ======== drm_test_drm_connector_dynamic_init_name =========
[11:39:56] [PASSED] Unknown
[11:39:56] [PASSED] VGA
[11:39:56] [PASSED] DVI-I
[11:39:56] [PASSED] DVI-D
[11:39:56] [PASSED] DVI-A
[11:39:56] [PASSED] Composite
[11:39:56] [PASSED] SVIDEO
[11:39:56] [PASSED] LVDS
[11:39:56] [PASSED] Component
[11:39:56] [PASSED] DIN
[11:39:56] [PASSED] DP
[11:39:56] [PASSED] HDMI-A
[11:39:56] [PASSED] HDMI-B
[11:39:56] [PASSED] TV
[11:39:56] [PASSED] eDP
[11:39:56] [PASSED] Virtual
[11:39:56] [PASSED] DSI
[11:39:56] [PASSED] DPI
[11:39:56] [PASSED] Writeback
[11:39:56] [PASSED] SPI
[11:39:56] [PASSED] USB
[11:39:56] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[11:39:56] =========== [PASSED] drm_connector_dynamic_init ============
[11:39:56] ==== drm_connector_dynamic_register_early (4 subtests) =====
[11:39:56] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[11:39:56] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[11:39:56] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[11:39:56] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[11:39:56] ====== [PASSED] drm_connector_dynamic_register_early =======
[11:39:56] ======= drm_connector_dynamic_register (7 subtests) ========
[11:39:56] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[11:39:56] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[11:39:56] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[11:39:56] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[11:39:56] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[11:39:56] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[11:39:56] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[11:39:56] ========= [PASSED] drm_connector_dynamic_register ==========
[11:39:56] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[11:39:56] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[11:39:56] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[11:39:56] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[11:39:56] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[11:39:56] ========== drm_test_get_tv_mode_from_name_valid ===========
[11:39:56] [PASSED] NTSC
[11:39:56] [PASSED] NTSC-443
[11:39:56] [PASSED] NTSC-J
[11:39:56] [PASSED] PAL
[11:39:56] [PASSED] PAL-M
[11:39:56] [PASSED] PAL-N
[11:39:56] [PASSED] SECAM
[11:39:56] [PASSED] Mono
[11:39:56] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[11:39:56] [PASSED] drm_test_get_tv_mode_from_name_truncated
[11:39:56] ============ [PASSED] drm_get_tv_mode_from_name ============
[11:39:56] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[11:39:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[11:39:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[11:39:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[11:39:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[11:39:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[11:39:56] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[11:39:56] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[11:39:56] [PASSED] VIC 96
[11:39:56] [PASSED] VIC 97
[11:39:56] [PASSED] VIC 101
[11:39:56] [PASSED] VIC 102
[11:39:56] [PASSED] VIC 106
[11:39:56] [PASSED] VIC 107
[11:39:56] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[11:39:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[11:39:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[11:39:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[11:39:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[11:39:56] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[11:39:56] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[11:39:56] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[11:39:56] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[11:39:56] [PASSED] Automatic
[11:39:56] [PASSED] Full
[11:39:56] [PASSED] Limited 16:235
[11:39:56] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[11:39:56] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[11:39:56] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[11:39:56] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[11:39:56] === drm_test_drm_hdmi_connector_get_output_format_name ====
[11:39:56] [PASSED] RGB
[11:39:56] [PASSED] YUV 4:2:0
[11:39:56] [PASSED] YUV 4:2:2
[11:39:56] [PASSED] YUV 4:4:4
[11:39:56] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[11:39:56] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[11:39:56] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[11:39:56] ============= drm_damage_helper (21 subtests) ==============
[11:39:56] [PASSED] drm_test_damage_iter_no_damage
[11:39:56] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[11:39:56] [PASSED] drm_test_damage_iter_no_damage_src_moved
[11:39:56] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[11:39:56] [PASSED] drm_test_damage_iter_no_damage_not_visible
[11:39:56] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[11:39:56] [PASSED] drm_test_damage_iter_no_damage_no_fb
[11:39:56] [PASSED] drm_test_damage_iter_simple_damage
[11:39:56] [PASSED] drm_test_damage_iter_single_damage
[11:39:56] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[11:39:56] [PASSED] drm_test_damage_iter_single_damage_outside_src
[11:39:56] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[11:39:56] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[11:39:56] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[11:39:56] [PASSED] drm_test_damage_iter_single_damage_src_moved
[11:39:56] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[11:39:56] [PASSED] drm_test_damage_iter_damage
[11:39:56] [PASSED] drm_test_damage_iter_damage_one_intersect
[11:39:56] [PASSED] drm_test_damage_iter_damage_one_outside
[11:39:56] [PASSED] drm_test_damage_iter_damage_src_moved
[11:39:56] [PASSED] drm_test_damage_iter_damage_not_visible
[11:39:56] ================ [PASSED] drm_damage_helper ================
[11:39:56] ============== drm_dp_mst_helper (3 subtests) ==============
[11:39:56] ============== drm_test_dp_mst_calc_pbn_mode ==============
[11:39:56] [PASSED] Clock 154000 BPP 30 DSC disabled
[11:39:56] [PASSED] Clock 234000 BPP 30 DSC disabled
[11:39:56] [PASSED] Clock 297000 BPP 24 DSC disabled
[11:39:56] [PASSED] Clock 332880 BPP 24 DSC enabled
[11:39:56] [PASSED] Clock 324540 BPP 24 DSC enabled
[11:39:56] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[11:39:56] ============== drm_test_dp_mst_calc_pbn_div ===============
[11:39:56] [PASSED] Link rate 2000000 lane count 4
[11:39:56] [PASSED] Link rate 2000000 lane count 2
[11:39:56] [PASSED] Link rate 2000000 lane count 1
[11:39:56] [PASSED] Link rate 1350000 lane count 4
[11:39:56] [PASSED] Link rate 1350000 lane count 2
[11:39:56] [PASSED] Link rate 1350000 lane count 1
[11:39:56] [PASSED] Link rate 1000000 lane count 4
[11:39:56] [PASSED] Link rate 1000000 lane count 2
[11:39:56] [PASSED] Link rate 1000000 lane count 1
[11:39:56] [PASSED] Link rate 810000 lane count 4
[11:39:56] [PASSED] Link rate 810000 lane count 2
[11:39:56] [PASSED] Link rate 810000 lane count 1
[11:39:56] [PASSED] Link rate 540000 lane count 4
[11:39:56] [PASSED] Link rate 540000 lane count 2
[11:39:56] [PASSED] Link rate 540000 lane count 1
[11:39:56] [PASSED] Link rate 270000 lane count 4
[11:39:56] [PASSED] Link rate 270000 lane count 2
[11:39:56] [PASSED] Link rate 270000 lane count 1
[11:39:56] [PASSED] Link rate 162000 lane count 4
[11:39:56] [PASSED] Link rate 162000 lane count 2
[11:39:56] [PASSED] Link rate 162000 lane count 1
[11:39:56] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[11:39:56] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[11:39:56] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[11:39:56] [PASSED] DP_POWER_UP_PHY with port number
[11:39:56] [PASSED] DP_POWER_DOWN_PHY with port number
[11:39:56] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[11:39:56] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[11:39:56] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[11:39:56] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[11:39:56] [PASSED] DP_QUERY_PAYLOAD with port number
[11:39:56] [PASSED] DP_QUERY_PAYLOAD with VCPI
[11:39:56] [PASSED] DP_REMOTE_DPCD_READ with port number
[11:39:56] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[11:39:56] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[11:39:56] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[11:39:56] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[11:39:56] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[11:39:56] [PASSED] DP_REMOTE_I2C_READ with port number
[11:39:56] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[11:39:56] [PASSED] DP_REMOTE_I2C_READ with transactions array
[11:39:56] [PASSED] DP_REMOTE_I2C_WRITE with port number
[11:39:56] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[11:39:56] [PASSED] DP_REMOTE_I2C_WRITE with data array
[11:39:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[11:39:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[11:39:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[11:39:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[11:39:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[11:39:56] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[11:39:56] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[11:39:56] ================ [PASSED] drm_dp_mst_helper ================
[11:39:56] ================== drm_exec (7 subtests) ===================
[11:39:56] [PASSED] sanitycheck
[11:39:56] [PASSED] test_lock
[11:39:56] [PASSED] test_lock_unlock
[11:39:56] [PASSED] test_duplicates
[11:39:56] [PASSED] test_prepare
[11:39:56] [PASSED] test_prepare_array
[11:39:56] [PASSED] test_multiple_loops
[11:39:56] ==================== [PASSED] drm_exec =====================
[11:39:56] =========== drm_format_helper_test (17 subtests) ===========
[11:39:56] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[11:39:56] [PASSED] single_pixel_source_buffer
[11:39:56] [PASSED] single_pixel_clip_rectangle
[11:39:56] [PASSED] well_known_colors
[11:39:56] [PASSED] destination_pitch
[11:39:56] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[11:39:56] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[11:39:56] [PASSED] single_pixel_source_buffer
[11:39:56] [PASSED] single_pixel_clip_rectangle
[11:39:56] [PASSED] well_known_colors
[11:39:56] [PASSED] destination_pitch
[11:39:56] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[11:39:56] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[11:39:56] [PASSED] single_pixel_source_buffer
[11:39:56] [PASSED] single_pixel_clip_rectangle
[11:39:56] [PASSED] well_known_colors
[11:39:56] [PASSED] destination_pitch
[11:39:56] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[11:39:56] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[11:39:56] [PASSED] single_pixel_source_buffer
[11:39:56] [PASSED] single_pixel_clip_rectangle
[11:39:56] [PASSED] well_known_colors
[11:39:56] [PASSED] destination_pitch
[11:39:56] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[11:39:56] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[11:39:56] [PASSED] single_pixel_source_buffer
[11:39:56] [PASSED] single_pixel_clip_rectangle
[11:39:56] [PASSED] well_known_colors
[11:39:56] [PASSED] destination_pitch
[11:39:56] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[11:39:56] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[11:39:56] [PASSED] single_pixel_source_buffer
[11:39:56] [PASSED] single_pixel_clip_rectangle
[11:39:56] [PASSED] well_known_colors
[11:39:56] [PASSED] destination_pitch
[11:39:56] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[11:39:56] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[11:39:56] [PASSED] single_pixel_source_buffer
[11:39:56] [PASSED] single_pixel_clip_rectangle
[11:39:56] [PASSED] well_known_colors
[11:39:56] [PASSED] destination_pitch
[11:39:56] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[11:39:56] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[11:39:56] [PASSED] single_pixel_source_buffer
[11:39:56] [PASSED] single_pixel_clip_rectangle
[11:39:56] [PASSED] well_known_colors
[11:39:56] [PASSED] destination_pitch
[11:39:56] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[11:39:56] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[11:39:56] [PASSED] single_pixel_source_buffer
[11:39:56] [PASSED] single_pixel_clip_rectangle
[11:39:56] [PASSED] well_known_colors
[11:39:56] [PASSED] destination_pitch
[11:39:56] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[11:39:56] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[11:39:56] [PASSED] single_pixel_source_buffer
[11:39:56] [PASSED] single_pixel_clip_rectangle
[11:39:56] [PASSED] well_known_colors
[11:39:56] [PASSED] destination_pitch
[11:39:56] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[11:39:56] ============== drm_test_fb_xrgb8888_to_mono ===============
[11:39:56] [PASSED] single_pixel_source_buffer
[11:39:56] [PASSED] single_pixel_clip_rectangle
[11:39:56] [PASSED] well_known_colors
[11:39:56] [PASSED] destination_pitch
[11:39:56] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[11:39:56] ==================== drm_test_fb_swab =====================
[11:39:56] [PASSED] single_pixel_source_buffer
[11:39:56] [PASSED] single_pixel_clip_rectangle
[11:39:56] [PASSED] well_known_colors
[11:39:56] [PASSED] destination_pitch
[11:39:56] ================ [PASSED] drm_test_fb_swab =================
[11:39:56] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[11:39:56] [PASSED] single_pixel_source_buffer
[11:39:56] [PASSED] single_pixel_clip_rectangle
[11:39:56] [PASSED] well_known_colors
[11:39:56] [PASSED] destination_pitch
[11:39:56] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[11:39:56] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[11:39:56] [PASSED] single_pixel_source_buffer
[11:39:56] [PASSED] single_pixel_clip_rectangle
[11:39:56] [PASSED] well_known_colors
[11:39:56] [PASSED] destination_pitch
[11:39:56] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[11:39:56] ================= drm_test_fb_clip_offset =================
[11:39:56] [PASSED] pass through
[11:39:56] [PASSED] horizontal offset
[11:39:56] [PASSED] vertical offset
[11:39:56] [PASSED] horizontal and vertical offset
[11:39:56] [PASSED] horizontal offset (custom pitch)
[11:39:56] [PASSED] vertical offset (custom pitch)
[11:39:56] [PASSED] horizontal and vertical offset (custom pitch)
[11:39:56] ============= [PASSED] drm_test_fb_clip_offset =============
[11:39:56] ============== drm_test_fb_build_fourcc_list ==============
[11:39:56] [PASSED] no native formats
[11:39:56] [PASSED] XRGB8888 as native format
[11:39:56] [PASSED] remove duplicates
[11:39:56] [PASSED] convert alpha formats
[11:39:56] [PASSED] random formats
[11:39:56] ========== [PASSED] drm_test_fb_build_fourcc_list ==========
[11:39:56] =================== drm_test_fb_memcpy ====================
[11:39:56] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[11:39:56] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[11:39:56] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[11:39:56] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[11:39:56] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[11:39:56] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[11:39:56] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[11:39:56] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[11:39:56] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[11:39:56] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[11:39:56] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[11:39:56] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[11:39:56] =============== [PASSED] drm_test_fb_memcpy ================
[11:39:56] ============= [PASSED] drm_format_helper_test ==============
[11:39:56] ================= drm_format (18 subtests) =================
[11:39:56] [PASSED] drm_test_format_block_width_invalid
[11:39:56] [PASSED] drm_test_format_block_width_one_plane
[11:39:56] [PASSED] drm_test_format_block_width_two_plane
[11:39:56] [PASSED] drm_test_format_block_width_three_plane
[11:39:56] [PASSED] drm_test_format_block_width_tiled
[11:39:56] [PASSED] drm_test_format_block_height_invalid
[11:39:56] [PASSED] drm_test_format_block_height_one_plane
[11:39:56] [PASSED] drm_test_format_block_height_two_plane
[11:39:56] [PASSED] drm_test_format_block_height_three_plane
[11:39:56] [PASSED] drm_test_format_block_height_tiled
[11:39:56] [PASSED] drm_test_format_min_pitch_invalid
[11:39:56] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[11:39:56] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[11:39:56] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[11:39:56] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[11:39:56] [PASSED] drm_test_format_min_pitch_two_plane
[11:39:56] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[11:39:56] [PASSED] drm_test_format_min_pitch_tiled
[11:39:56] =================== [PASSED] drm_format ====================
[11:39:56] ============== drm_framebuffer (10 subtests) ===============
[11:39:56] ========== drm_test_framebuffer_check_src_coords ==========
[11:39:56] [PASSED] Success: source fits into fb
[11:39:56] [PASSED] Fail: overflowing fb with x-axis coordinate
[11:39:56] [PASSED] Fail: overflowing fb with y-axis coordinate
[11:39:56] [PASSED] Fail: overflowing fb with source width
[11:39:56] [PASSED] Fail: overflowing fb with source height
[11:39:56] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[11:39:56] [PASSED] drm_test_framebuffer_cleanup
[11:39:56] =============== drm_test_framebuffer_create ===============
[11:39:56] [PASSED] ABGR8888 normal sizes
[11:39:56] [PASSED] ABGR8888 max sizes
[11:39:56] [PASSED] ABGR8888 pitch greater than min required
[11:39:56] [PASSED] ABGR8888 pitch less than min required
[11:39:56] [PASSED] ABGR8888 Invalid width
[11:39:56] [PASSED] ABGR8888 Invalid buffer handle
[11:39:56] [PASSED] No pixel format
[11:39:56] [PASSED] ABGR8888 Width 0
[11:39:56] [PASSED] ABGR8888 Height 0
[11:39:56] [PASSED] ABGR8888 Out of bound height * pitch combination
[11:39:56] [PASSED] ABGR8888 Large buffer offset
[11:39:56] [PASSED] ABGR8888 Buffer offset for inexistent plane
[11:39:56] [PASSED] ABGR8888 Invalid flag
[11:39:56] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[11:39:56] [PASSED] ABGR8888 Valid buffer modifier
[11:39:56] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[11:39:56] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[11:39:56] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[11:39:56] [PASSED] NV12 Normal sizes
[11:39:56] [PASSED] NV12 Max sizes
[11:39:56] [PASSED] NV12 Invalid pitch
[11:39:56] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[11:39:56] [PASSED] NV12 different modifier per-plane
[11:39:56] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[11:39:56] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[11:39:56] [PASSED] NV12 Modifier for inexistent plane
[11:39:56] [PASSED] NV12 Handle for inexistent plane
[11:39:56] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[11:39:56] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[11:39:56] [PASSED] YVU420 Normal sizes
[11:39:56] [PASSED] YVU420 Max sizes
[11:39:56] [PASSED] YVU420 Invalid pitch
[11:39:56] [PASSED] YVU420 Different pitches
[11:39:56] [PASSED] YVU420 Different buffer offsets/pitches
[11:39:56] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[11:39:56] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[11:39:56] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[11:39:56] [PASSED] YVU420 Valid modifier
[11:39:56] [PASSED] YVU420 Different modifiers per plane
[11:39:56] [PASSED] YVU420 Modifier for inexistent plane
[11:39:56] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[11:39:56] [PASSED] X0L2 Normal sizes
[11:39:56] [PASSED] X0L2 Max sizes
[11:39:56] [PASSED] X0L2 Invalid pitch
[11:39:56] [PASSED] X0L2 Pitch greater than minimum required
[11:39:56] [PASSED] X0L2 Handle for inexistent plane
[11:39:56] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[11:39:56] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[11:39:56] [PASSED] X0L2 Valid modifier
[11:39:56] [PASSED] X0L2 Modifier for inexistent plane
[11:39:56] =========== [PASSED] drm_test_framebuffer_create ===========
[11:39:56] [PASSED] drm_test_framebuffer_free
[11:39:56] [PASSED] drm_test_framebuffer_init
[11:39:56] [PASSED] drm_test_framebuffer_init_bad_format
[11:39:56] [PASSED] drm_test_framebuffer_init_dev_mismatch
[11:39:56] [PASSED] drm_test_framebuffer_lookup
[11:39:56] [PASSED] drm_test_framebuffer_lookup_inexistent
[11:39:56] [PASSED] drm_test_framebuffer_modifiers_not_supported
[11:39:56] ================= [PASSED] drm_framebuffer =================
[11:39:56] ================ drm_gem_shmem (8 subtests) ================
[11:39:56] [PASSED] drm_gem_shmem_test_obj_create
[11:39:56] [PASSED] drm_gem_shmem_test_obj_create_private
[11:39:56] [PASSED] drm_gem_shmem_test_pin_pages
[11:39:56] [PASSED] drm_gem_shmem_test_vmap
[11:39:56] [PASSED] drm_gem_shmem_test_get_pages_sgt
[11:39:56] [PASSED] drm_gem_shmem_test_get_sg_table
[11:39:56] [PASSED] drm_gem_shmem_test_madvise
[11:39:56] [PASSED] drm_gem_shmem_test_purge
[11:39:56] ================== [PASSED] drm_gem_shmem ==================
[11:39:56] === drm_atomic_helper_connector_hdmi_check (23 subtests) ===
[11:39:56] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[11:39:56] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[11:39:56] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[11:39:56] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[11:39:56] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[11:39:56] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[11:39:56] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[11:39:56] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[11:39:56] [PASSED] drm_test_check_disable_connector
[11:39:56] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[11:39:56] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback
[11:39:56] [PASSED] drm_test_check_max_tmds_rate_format_fallback
[11:39:56] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[11:39:56] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[11:39:56] [PASSED] drm_test_check_output_bpc_dvi
[11:39:56] [PASSED] drm_test_check_output_bpc_format_vic_1
[11:39:56] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[11:39:56] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[11:39:56] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[11:39:56] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[11:39:56] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[11:39:56] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[11:39:56] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[11:39:56] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[11:39:56] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[11:39:56] [PASSED] drm_test_check_broadcast_rgb_value
[11:39:56] [PASSED] drm_test_check_bpc_8_value
[11:39:56] [PASSED] drm_test_check_bpc_10_value
[11:39:56] [PASSED] drm_test_check_bpc_12_value
[11:39:56] [PASSED] drm_test_check_format_value
[11:39:56] [PASSED] drm_test_check_tmds_char_value
[11:39:56] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[11:39:56] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[11:39:56] [PASSED] drm_test_check_mode_valid
[11:39:56] [PASSED] drm_test_check_mode_valid_reject
[11:39:56] [PASSED] drm_test_check_mode_valid_reject_rate
[11:39:56] [PASSED] drm_test_check_mode_valid_reject_max_clock
[11:39:56] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[11:39:56] ================= drm_managed (2 subtests) =================
[11:39:56] [PASSED] drm_test_managed_release_action
[11:39:56] [PASSED] drm_test_managed_run_action
[11:39:56] =================== [PASSED] drm_managed ===================
[11:39:56] =================== drm_mm (6 subtests) ====================
[11:39:56] [PASSED] drm_test_mm_init
[11:39:56] [PASSED] drm_test_mm_debug
[11:39:56] [PASSED] drm_test_mm_align32
[11:39:56] [PASSED] drm_test_mm_align64
[11:39:56] [PASSED] drm_test_mm_lowest
[11:39:56] [PASSED] drm_test_mm_highest
[11:39:56] ===================== [PASSED] drm_mm ======================
[11:39:56] ============= drm_modes_analog_tv (5 subtests) =============
[11:39:56] [PASSED] drm_test_modes_analog_tv_mono_576i
[11:39:56] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[11:39:56] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[11:39:56] [PASSED] drm_test_modes_analog_tv_pal_576i
[11:39:56] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[11:39:56] =============== [PASSED] drm_modes_analog_tv ===============
[11:39:56] ============== drm_plane_helper (2 subtests) ===============
[11:39:56] =============== drm_test_check_plane_state ================
[11:39:56] [PASSED] clipping_simple
[11:39:56] [PASSED] clipping_rotate_reflect
[11:39:56] [PASSED] positioning_simple
[11:39:56] [PASSED] upscaling
[11:39:56] [PASSED] downscaling
[11:39:56] [PASSED] rounding1
[11:39:56] [PASSED] rounding2
[11:39:56] [PASSED] rounding3
[11:39:56] [PASSED] rounding4
[11:39:56] =========== [PASSED] drm_test_check_plane_state ============
[11:39:56] =========== drm_test_check_invalid_plane_state ============
[11:39:56] [PASSED] positioning_invalid
[11:39:56] [PASSED] upscaling_invalid
[11:39:56] [PASSED] downscaling_invalid
[11:39:56] ======= [PASSED] drm_test_check_invalid_plane_state ========
[11:39:56] ================ [PASSED] drm_plane_helper =================
[11:39:56] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[11:39:56] ====== drm_test_connector_helper_tv_get_modes_check =======
[11:39:56] [PASSED] None
[11:39:56] [PASSED] PAL
[11:39:56] [PASSED] NTSC
[11:39:56] [PASSED] Both, NTSC Default
[11:39:56] [PASSED] Both, PAL Default
[11:39:56] [PASSED] Both, NTSC Default, with PAL on command-line
[11:39:56] [PASSED] Both, PAL Default, with NTSC on command-line
[11:39:56] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[11:39:56] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[11:39:56] ================== drm_rect (9 subtests) ===================
[11:39:56] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[11:39:56] [PASSED] drm_test_rect_clip_scaled_not_clipped
[11:39:56] [PASSED] drm_test_rect_clip_scaled_clipped
[11:39:56] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[11:39:56] ================= drm_test_rect_intersect =================
[11:39:56] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[11:39:56] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[11:39:56] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[11:39:56] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[11:39:56] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[11:39:56] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[11:39:56] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[11:39:56] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[11:39:56] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[11:39:56] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[11:39:56] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[11:39:56] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[11:39:56] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[11:39:56] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[11:39:56] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[11:39:56] ============= [PASSED] drm_test_rect_intersect =============
[11:39:56] ================ drm_test_rect_calc_hscale ================
[11:39:56] [PASSED] normal use
[11:39:56] [PASSED] out of max range
[11:39:56] [PASSED] out of min range
[11:39:56] [PASSED] zero dst
[11:39:56] [PASSED] negative src
[11:39:56] [PASSED] negative dst
[11:39:56] ============ [PASSED] drm_test_rect_calc_hscale ============
[11:39:56] ================ drm_test_rect_calc_vscale ================
[11:39:56] [PASSED] normal use
[11:39:56] [PASSED] out of max range
[11:39:56] [PASSED] out of min range
[11:39:56] [PASSED] zero dst
[11:39:56] [PASSED] negative src
[11:39:56] [PASSED] negative dst
[11:39:56] ============ [PASSED] drm_test_rect_calc_vscale ============
[11:39:56] ================== drm_test_rect_rotate ===================
[11:39:56] [PASSED] reflect-x
[11:39:56] [PASSED] reflect-y
[11:39:56] [PASSED] rotate-0
[11:39:56] [PASSED] rotate-90
[11:39:56] [PASSED] rotate-180
[11:39:56] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[11:39:56] ============== [PASSED] drm_test_rect_rotate ===============
[11:39:56] ================ drm_test_rect_rotate_inv =================
[11:39:56] [PASSED] reflect-x
[11:39:56] [PASSED] reflect-y
[11:39:56] [PASSED] rotate-0
[11:39:56] [PASSED] rotate-90
[11:39:56] [PASSED] rotate-180
[11:39:56] [PASSED] rotate-270
[11:39:56] ============ [PASSED] drm_test_rect_rotate_inv =============
[11:39:56] ==================== [PASSED] drm_rect =====================
[11:39:56] ============================================================
[11:39:56] Testing complete. Ran 598 tests: passed: 598
[11:39:56] Elapsed time: 22.431s total, 1.634s configuring, 20.629s building, 0.127s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[11:39:56] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:39:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
[11:40:06] Starting KUnit Kernel (1/1)...
[11:40:06] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:40:06] ================= ttm_device (5 subtests) ==================
[11:40:06] [PASSED] ttm_device_init_basic
[11:40:06] [PASSED] ttm_device_init_multiple
[11:40:06] [PASSED] ttm_device_fini_basic
[11:40:06] [PASSED] ttm_device_init_no_vma_man
[11:40:06] ================== ttm_device_init_pools ==================
[11:40:06] [PASSED] No DMA allocations, no DMA32 required
[11:40:06] [PASSED] DMA allocations, DMA32 required
[11:40:06] [PASSED] No DMA allocations, DMA32 required
[11:40:06] [PASSED] DMA allocations, no DMA32 required
[11:40:06] ============== [PASSED] ttm_device_init_pools ==============
[11:40:06] =================== [PASSED] ttm_device ====================
[11:40:06] ================== ttm_pool (8 subtests) ===================
[11:40:06] ================== ttm_pool_alloc_basic ===================
[11:40:06] [PASSED] One page
[11:40:06] [PASSED] More than one page
[11:40:06] [PASSED] Above the allocation limit
[11:40:06] [PASSED] One page, with coherent DMA mappings enabled
[11:40:06] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:40:06] ============== [PASSED] ttm_pool_alloc_basic ===============
[11:40:06] ============== ttm_pool_alloc_basic_dma_addr ==============
[11:40:06] [PASSED] One page
[11:40:06] [PASSED] More than one page
[11:40:06] [PASSED] Above the allocation limit
[11:40:06] [PASSED] One page, with coherent DMA mappings enabled
[11:40:06] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:40:06] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[11:40:06] [PASSED] ttm_pool_alloc_order_caching_match
[11:40:06] [PASSED] ttm_pool_alloc_caching_mismatch
[11:40:06] [PASSED] ttm_pool_alloc_order_mismatch
[11:40:06] [PASSED] ttm_pool_free_dma_alloc
[11:40:06] [PASSED] ttm_pool_free_no_dma_alloc
[11:40:06] [PASSED] ttm_pool_fini_basic
[11:40:06] ==================== [PASSED] ttm_pool =====================
[11:40:06] ================ ttm_resource (8 subtests) =================
[11:40:06] ================= ttm_resource_init_basic =================
[11:40:06] [PASSED] Init resource in TTM_PL_SYSTEM
[11:40:06] [PASSED] Init resource in TTM_PL_VRAM
[11:40:06] [PASSED] Init resource in a private placement
[11:40:06] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[11:40:06] ============= [PASSED] ttm_resource_init_basic =============
[11:40:06] [PASSED] ttm_resource_init_pinned
[11:40:06] [PASSED] ttm_resource_fini_basic
[11:40:06] [PASSED] ttm_resource_manager_init_basic
[11:40:06] [PASSED] ttm_resource_manager_usage_basic
[11:40:06] [PASSED] ttm_resource_manager_set_used_basic
[11:40:06] [PASSED] ttm_sys_man_alloc_basic
[11:40:06] [PASSED] ttm_sys_man_free_basic
[11:40:06] ================== [PASSED] ttm_resource ===================
[11:40:06] =================== ttm_tt (15 subtests) ===================
[11:40:06] ==================== ttm_tt_init_basic ====================
[11:40:06] [PASSED] Page-aligned size
[11:40:06] [PASSED] Extra pages requested
[11:40:06] ================ [PASSED] ttm_tt_init_basic ================
[11:40:06] [PASSED] ttm_tt_init_misaligned
[11:40:06] [PASSED] ttm_tt_fini_basic
[11:40:06] [PASSED] ttm_tt_fini_sg
[11:40:06] [PASSED] ttm_tt_fini_shmem
[11:40:06] [PASSED] ttm_tt_create_basic
[11:40:06] [PASSED] ttm_tt_create_invalid_bo_type
[11:40:06] [PASSED] ttm_tt_create_ttm_exists
[11:40:06] [PASSED] ttm_tt_create_failed
[11:40:06] [PASSED] ttm_tt_destroy_basic
[11:40:06] [PASSED] ttm_tt_populate_null_ttm
[11:40:06] [PASSED] ttm_tt_populate_populated_ttm
[11:40:06] [PASSED] ttm_tt_unpopulate_basic
[11:40:06] [PASSED] ttm_tt_unpopulate_empty_ttm
[11:40:06] [PASSED] ttm_tt_swapin_basic
[11:40:06] ===================== [PASSED] ttm_tt ======================
[11:40:06] =================== ttm_bo (14 subtests) ===================
[11:40:06] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[11:40:06] [PASSED] Cannot be interrupted and sleeps
[11:40:06] [PASSED] Cannot be interrupted, locks straight away
[11:40:06] [PASSED] Can be interrupted, sleeps
[11:40:06] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[11:40:06] [PASSED] ttm_bo_reserve_locked_no_sleep
[11:40:06] [PASSED] ttm_bo_reserve_no_wait_ticket
[11:40:06] [PASSED] ttm_bo_reserve_double_resv
[11:40:06] [PASSED] ttm_bo_reserve_interrupted
[11:40:06] [PASSED] ttm_bo_reserve_deadlock
[11:40:06] [PASSED] ttm_bo_unreserve_basic
[11:40:06] [PASSED] ttm_bo_unreserve_pinned
[11:40:06] [PASSED] ttm_bo_unreserve_bulk
[11:40:06] [PASSED] ttm_bo_put_basic
[11:40:06] [PASSED] ttm_bo_put_shared_resv
[11:40:06] [PASSED] ttm_bo_pin_basic
[11:40:06] [PASSED] ttm_bo_pin_unpin_resource
[11:40:06] [PASSED] ttm_bo_multiple_pin_one_unpin
[11:40:06] ===================== [PASSED] ttm_bo ======================
[11:40:06] ============== ttm_bo_validate (22 subtests) ===============
[11:40:06] ============== ttm_bo_init_reserved_sys_man ===============
[11:40:06] [PASSED] Buffer object for userspace
[11:40:06] [PASSED] Kernel buffer object
[11:40:06] [PASSED] Shared buffer object
[11:40:06] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[11:40:06] ============== ttm_bo_init_reserved_mock_man ==============
[11:40:06] [PASSED] Buffer object for userspace
[11:40:06] [PASSED] Kernel buffer object
[11:40:06] [PASSED] Shared buffer object
[11:40:06] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[11:40:06] [PASSED] ttm_bo_init_reserved_resv
[11:40:06] ================== ttm_bo_validate_basic ==================
[11:40:06] [PASSED] Buffer object for userspace
[11:40:06] [PASSED] Kernel buffer object
[11:40:06] [PASSED] Shared buffer object
[11:40:06] ============== [PASSED] ttm_bo_validate_basic ==============
[11:40:06] [PASSED] ttm_bo_validate_invalid_placement
[11:40:06] ============= ttm_bo_validate_same_placement ==============
[11:40:06] [PASSED] System manager
[11:40:06] [PASSED] VRAM manager
[11:40:06] ========= [PASSED] ttm_bo_validate_same_placement ==========
[11:40:06] [PASSED] ttm_bo_validate_failed_alloc
[11:40:06] [PASSED] ttm_bo_validate_pinned
[11:40:06] [PASSED] ttm_bo_validate_busy_placement
[11:40:06] ================ ttm_bo_validate_multihop =================
[11:40:06] [PASSED] Buffer object for userspace
[11:40:06] [PASSED] Kernel buffer object
[11:40:06] [PASSED] Shared buffer object
[11:40:06] ============ [PASSED] ttm_bo_validate_multihop =============
[11:40:06] ========== ttm_bo_validate_no_placement_signaled ==========
[11:40:06] [PASSED] Buffer object in system domain, no page vector
[11:40:06] [PASSED] Buffer object in system domain with an existing page vector
[11:40:06] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[11:40:06] ======== ttm_bo_validate_no_placement_not_signaled ========
[11:40:06] [PASSED] Buffer object for userspace
[11:40:06] [PASSED] Kernel buffer object
[11:40:06] [PASSED] Shared buffer object
[11:40:06] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[11:40:06] [PASSED] ttm_bo_validate_move_fence_signaled
[11:40:06] ========= ttm_bo_validate_move_fence_not_signaled =========
[11:40:06] [PASSED] Waits for GPU
[11:40:06] [PASSED] Tries to lock straight away
[11:40:06] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[11:40:06] [PASSED] ttm_bo_validate_swapout
[11:40:06] [PASSED] ttm_bo_validate_happy_evict
[11:40:06] [PASSED] ttm_bo_validate_all_pinned_evict
[11:40:06] [PASSED] ttm_bo_validate_allowed_only_evict
[11:40:06] [PASSED] ttm_bo_validate_deleted_evict
[11:40:06] [PASSED] ttm_bo_validate_busy_domain_evict
[11:40:06] [PASSED] ttm_bo_validate_evict_gutting
[11:40:06] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[11:40:06] ================= [PASSED] ttm_bo_validate =================
[11:40:06] ============================================================
[11:40:06] Testing complete. Ran 102 tests: passed: 102
[11:40:06] Elapsed time: 9.877s total, 1.680s configuring, 7.580s building, 0.527s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 45+ messages in thread* ✓ CI.Build: success for PMU Support for per-engine-class activity (rev2)
2025-01-29 10:16 [PATCH v4 0/8] PMU Support for per-engine-class activity Riana Tauro
` (10 preceding siblings ...)
2025-01-29 11:40 ` ✓ CI.KUnit: success " Patchwork
@ 2025-01-29 11:56 ` Patchwork
2025-01-29 11:58 ` ✗ CI.Hooks: failure " Patchwork
` (4 subsequent siblings)
16 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2025-01-29 11:56 UTC (permalink / raw)
To: Riana Tauro; +Cc: intel-xe
== Series Details ==
Series: PMU Support for per-engine-class activity (rev2)
URL : https://patchwork.freedesktop.org/series/143138/
State : success
== Summary ==
lib/modules/6.13.0-xe+/kernel/arch/x86/events/rapl.ko
lib/modules/6.13.0-xe+/kernel/arch/x86/kvm/
lib/modules/6.13.0-xe+/kernel/arch/x86/kvm/kvm.ko
lib/modules/6.13.0-xe+/kernel/arch/x86/kvm/kvm-intel.ko
lib/modules/6.13.0-xe+/kernel/arch/x86/kvm/kvm-amd.ko
lib/modules/6.13.0-xe+/kernel/kernel/
lib/modules/6.13.0-xe+/kernel/kernel/kheaders.ko
lib/modules/6.13.0-xe+/kernel/crypto/
lib/modules/6.13.0-xe+/kernel/crypto/ecrdsa_generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/xcbc.ko
lib/modules/6.13.0-xe+/kernel/crypto/serpent_generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/aria_generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/crypto_simd.ko
lib/modules/6.13.0-xe+/kernel/crypto/adiantum.ko
lib/modules/6.13.0-xe+/kernel/crypto/tcrypt.ko
lib/modules/6.13.0-xe+/kernel/crypto/crypto_engine.ko
lib/modules/6.13.0-xe+/kernel/crypto/zstd.ko
lib/modules/6.13.0-xe+/kernel/crypto/asymmetric_keys/
lib/modules/6.13.0-xe+/kernel/crypto/asymmetric_keys/pkcs7_test_key.ko
lib/modules/6.13.0-xe+/kernel/crypto/asymmetric_keys/pkcs8_key_parser.ko
lib/modules/6.13.0-xe+/kernel/crypto/des_generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/xctr.ko
lib/modules/6.13.0-xe+/kernel/crypto/authenc.ko
lib/modules/6.13.0-xe+/kernel/crypto/sm4_generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/keywrap.ko
lib/modules/6.13.0-xe+/kernel/crypto/camellia_generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/sm3.ko
lib/modules/6.13.0-xe+/kernel/crypto/pcrypt.ko
lib/modules/6.13.0-xe+/kernel/crypto/aegis128.ko
lib/modules/6.13.0-xe+/kernel/crypto/af_alg.ko
lib/modules/6.13.0-xe+/kernel/crypto/algif_aead.ko
lib/modules/6.13.0-xe+/kernel/crypto/cmac.ko
lib/modules/6.13.0-xe+/kernel/crypto/sm3_generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/aes_ti.ko
lib/modules/6.13.0-xe+/kernel/crypto/chacha_generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/poly1305_generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/nhpoly1305.ko
lib/modules/6.13.0-xe+/kernel/crypto/crc32_generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/essiv.ko
lib/modules/6.13.0-xe+/kernel/crypto/ccm.ko
lib/modules/6.13.0-xe+/kernel/crypto/wp512.ko
lib/modules/6.13.0-xe+/kernel/crypto/streebog_generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/authencesn.ko
lib/modules/6.13.0-xe+/kernel/crypto/echainiv.ko
lib/modules/6.13.0-xe+/kernel/crypto/lrw.ko
lib/modules/6.13.0-xe+/kernel/crypto/cryptd.ko
lib/modules/6.13.0-xe+/kernel/crypto/crypto_user.ko
lib/modules/6.13.0-xe+/kernel/crypto/algif_hash.ko
lib/modules/6.13.0-xe+/kernel/crypto/vmac.ko
lib/modules/6.13.0-xe+/kernel/crypto/polyval-generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/hctr2.ko
lib/modules/6.13.0-xe+/kernel/crypto/842.ko
lib/modules/6.13.0-xe+/kernel/crypto/pcbc.ko
lib/modules/6.13.0-xe+/kernel/crypto/ansi_cprng.ko
lib/modules/6.13.0-xe+/kernel/crypto/cast6_generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/twofish_common.ko
lib/modules/6.13.0-xe+/kernel/crypto/twofish_generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/lz4hc.ko
lib/modules/6.13.0-xe+/kernel/crypto/blowfish_generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/md4.ko
lib/modules/6.13.0-xe+/kernel/crypto/chacha20poly1305.ko
lib/modules/6.13.0-xe+/kernel/crypto/curve25519-generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/lz4.ko
lib/modules/6.13.0-xe+/kernel/crypto/rmd160.ko
lib/modules/6.13.0-xe+/kernel/crypto/algif_skcipher.ko
lib/modules/6.13.0-xe+/kernel/crypto/cast5_generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/fcrypt.ko
lib/modules/6.13.0-xe+/kernel/crypto/ecdsa_generic.ko
lib/modules/6.13.0-xe+/kernel/crypto/sm4.ko
lib/modules/6.13.0-xe+/kernel/crypto/cast_common.ko
lib/modules/6.13.0-xe+/kernel/crypto/blowfish_common.ko
lib/modules/6.13.0-xe+/kernel/crypto/michael_mic.ko
lib/modules/6.13.0-xe+/kernel/crypto/async_tx/
lib/modules/6.13.0-xe+/kernel/crypto/async_tx/async_xor.ko
lib/modules/6.13.0-xe+/kernel/crypto/async_tx/async_tx.ko
lib/modules/6.13.0-xe+/kernel/crypto/async_tx/async_memcpy.ko
lib/modules/6.13.0-xe+/kernel/crypto/async_tx/async_pq.ko
lib/modules/6.13.0-xe+/kernel/crypto/async_tx/async_raid6_recov.ko
lib/modules/6.13.0-xe+/kernel/crypto/algif_rng.ko
lib/modules/6.13.0-xe+/kernel/block/
lib/modules/6.13.0-xe+/kernel/block/bfq.ko
lib/modules/6.13.0-xe+/kernel/block/kyber-iosched.ko
lib/modules/6.13.0-xe+/build
lib/modules/6.13.0-xe+/modules.alias.bin
lib/modules/6.13.0-xe+/modules.builtin
lib/modules/6.13.0-xe+/modules.softdep
lib/modules/6.13.0-xe+/modules.alias
lib/modules/6.13.0-xe+/modules.order
lib/modules/6.13.0-xe+/modules.symbols
lib/modules/6.13.0-xe+/modules.dep.bin
+ mv kernel-nodebug.tar.gz ..
+ cd ..
+ rm -rf archive
++ date +%s
+ echo -e '\e[0Ksection_end:1738151793:package_x86_64_nodebug\r\e[0K'
+ sync
^[[0Ksection_end:1738151793:package_x86_64_nodebug
^[[0K
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 45+ messages in thread* ✗ CI.Hooks: failure for PMU Support for per-engine-class activity (rev2)
2025-01-29 10:16 [PATCH v4 0/8] PMU Support for per-engine-class activity Riana Tauro
` (11 preceding siblings ...)
2025-01-29 11:56 ` ✓ CI.Build: " Patchwork
@ 2025-01-29 11:58 ` Patchwork
2025-01-29 12:00 ` ✓ CI.checksparse: success " Patchwork
` (3 subsequent siblings)
16 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2025-01-29 11:58 UTC (permalink / raw)
To: Riana Tauro; +Cc: intel-xe
== Series Details ==
Series: PMU Support for per-engine-class activity (rev2)
URL : https://patchwork.freedesktop.org/series/143138/
State : failure
== Summary ==
run-parts: executing /workspace/ci/hooks/00-showenv
+ grep -Ei '(^|\W)CI_'
+ export
declare -x CI_KERNEL_BUILD_DIR="/workspace/kernel/build64-default"
declare -x CI_KERNEL_SRC_DIR="/workspace/kernel"
declare -x CI_TOOLS_SRC_DIR="/workspace/ci"
declare -x CI_WORKSPACE_DIR="/workspace"
run-parts: executing /workspace/ci/hooks/10-build-W1
+ SRC_DIR=/workspace/kernel
+ RESTORE_DISPLAY_CONFIG=0
+ '[' -n /workspace/kernel/build64-default ']'
+ BUILD_DIR=/workspace/kernel/build64-default
+ cd /workspace/kernel
++ nproc
+ make -j48 O=/workspace/kernel/build64-default modules_prepare
make[1]: Entering directory '/workspace/kernel/build64-default'
GEN Makefile
mkdir -p /workspace/kernel/build64-default/tools/objtool && make O=/workspace/kernel/build64-default subdir=tools/objtool --no-print-directory -C objtool
CALL ../scripts/checksyscalls.sh
INSTALL libsubcmd_headers
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/exec-cmd.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/help.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/pager.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/parse-options.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/run-command.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/sigchain.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/subcmd-config.o
LD /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd-in.o
AR /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd.a
CC /workspace/kernel/build64-default/tools/objtool/weak.o
CC /workspace/kernel/build64-default/tools/objtool/check.o
CC /workspace/kernel/build64-default/tools/objtool/special.o
CC /workspace/kernel/build64-default/tools/objtool/builtin-check.o
CC /workspace/kernel/build64-default/tools/objtool/elf.o
CC /workspace/kernel/build64-default/tools/objtool/objtool.o
CC /workspace/kernel/build64-default/tools/objtool/orc_gen.o
CC /workspace/kernel/build64-default/tools/objtool/orc_dump.o
CC /workspace/kernel/build64-default/tools/objtool/libstring.o
CC /workspace/kernel/build64-default/tools/objtool/arch/x86/special.o
CC /workspace/kernel/build64-default/tools/objtool/libctype.o
CC /workspace/kernel/build64-default/tools/objtool/str_error_r.o
CC /workspace/kernel/build64-default/tools/objtool/arch/x86/decode.o
CC /workspace/kernel/build64-default/tools/objtool/arch/x86/orc.o
CC /workspace/kernel/build64-default/tools/objtool/librbtree.o
LD /workspace/kernel/build64-default/tools/objtool/arch/x86/objtool-in.o
LD /workspace/kernel/build64-default/tools/objtool/objtool-in.o
LINK /workspace/kernel/build64-default/tools/objtool/objtool
make[1]: Leaving directory '/workspace/kernel/build64-default'
++ nproc
+ make -j48 O=/workspace/kernel/build64-default W=1 drivers/gpu/drm/xe
make[1]: Entering directory '/workspace/kernel/build64-default'
make[2]: Nothing to be done for 'drivers/gpu/drm/xe'.
make[1]: Leaving directory '/workspace/kernel/build64-default'
run-parts: executing /workspace/ci/hooks/11-build-32b
+++ realpath /workspace/ci/hooks/11-build-32b
++ dirname /workspace/ci/hooks/11-build-32b
+ THIS_SCRIPT_DIR=/workspace/ci/hooks
+ SRC_DIR=/workspace/kernel
+ TOOLS_SRC_DIR=/workspace/ci
+ '[' -n /workspace/kernel/build64-default ']'
+ BUILD_DIR=/workspace/kernel/build64-default
+ BUILD_DIR=/workspace/kernel/build64-default/build32
+ cd /workspace/kernel
+ mkdir -p /workspace/kernel/build64-default/build32
++ nproc
+ make -j48 ARCH=i386 O=/workspace/kernel/build64-default/build32 defconfig
make[1]: Entering directory '/workspace/kernel/build64-default/build32'
GEN Makefile
HOSTCC scripts/basic/fixdep
HOSTCC scripts/kconfig/conf.o
HOSTCC scripts/kconfig/confdata.o
HOSTCC scripts/kconfig/expr.o
LEX scripts/kconfig/lexer.lex.c
YACC scripts/kconfig/parser.tab.[ch]
HOSTCC scripts/kconfig/menu.o
HOSTCC scripts/kconfig/preprocess.o
HOSTCC scripts/kconfig/util.o
HOSTCC scripts/kconfig/symbol.o
HOSTCC scripts/kconfig/lexer.lex.o
HOSTCC scripts/kconfig/parser.tab.o
HOSTLD scripts/kconfig/conf
*** Default configuration is based on 'i386_defconfig'
#
# configuration written to .config
#
make[1]: Leaving directory '/workspace/kernel/build64-default/build32'
+ cd /workspace/kernel/build64-default/build32
+ /workspace/kernel/scripts/kconfig/merge_config.sh .config /workspace/ci/kernel/fragments/10-xe.fragment
Using .config as base
Merging /workspace/ci/kernel/fragments/10-xe.fragment
Value of CONFIG_DRM_XE is redefined by fragment /workspace/ci/kernel/fragments/10-xe.fragment:
Previous value: # CONFIG_DRM_XE is not set
New value: CONFIG_DRM_XE=m
GEN Makefile
WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
Selected by [m]:
- DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] && HAS_IOPORT [=y]
#
# configuration written to .config
#
Value requested for CONFIG_HAVE_UID16 not in final .config
Requested value: CONFIG_HAVE_UID16=y
Actual value:
Value requested for CONFIG_UID16 not in final .config
Requested value: CONFIG_UID16=y
Actual value:
Value requested for CONFIG_X86_32 not in final .config
Requested value: CONFIG_X86_32=y
Actual value:
Value requested for CONFIG_OUTPUT_FORMAT not in final .config
Requested value: CONFIG_OUTPUT_FORMAT="elf32-i386"
Actual value: CONFIG_OUTPUT_FORMAT="elf64-x86-64"
Value requested for CONFIG_ARCH_MMAP_RND_BITS_MIN not in final .config
Requested value: CONFIG_ARCH_MMAP_RND_BITS_MIN=8
Actual value: CONFIG_ARCH_MMAP_RND_BITS_MIN=28
Value requested for CONFIG_ARCH_MMAP_RND_BITS_MAX not in final .config
Requested value: CONFIG_ARCH_MMAP_RND_BITS_MAX=16
Actual value: CONFIG_ARCH_MMAP_RND_BITS_MAX=32
Value requested for CONFIG_PGTABLE_LEVELS not in final .config
Requested value: CONFIG_PGTABLE_LEVELS=2
Actual value: CONFIG_PGTABLE_LEVELS=5
Value requested for CONFIG_X86_BIGSMP not in final .config
Requested value: # CONFIG_X86_BIGSMP is not set
Actual value:
Value requested for CONFIG_X86_INTEL_QUARK not in final .config
Requested value: # CONFIG_X86_INTEL_QUARK is not set
Actual value:
Value requested for CONFIG_X86_RDC321X not in final .config
Requested value: # CONFIG_X86_RDC321X is not set
Actual value:
Value requested for CONFIG_X86_32_NON_STANDARD not in final .config
Requested value: # CONFIG_X86_32_NON_STANDARD is not set
Actual value:
Value requested for CONFIG_X86_32_IRIS not in final .config
Requested value: # CONFIG_X86_32_IRIS is not set
Actual value:
Value requested for CONFIG_M486SX not in final .config
Requested value: # CONFIG_M486SX is not set
Actual value:
Value requested for CONFIG_M486 not in final .config
Requested value: # CONFIG_M486 is not set
Actual value:
Value requested for CONFIG_M586 not in final .config
Requested value: # CONFIG_M586 is not set
Actual value:
Value requested for CONFIG_M586TSC not in final .config
Requested value: # CONFIG_M586TSC is not set
Actual value:
Value requested for CONFIG_M586MMX not in final .config
Requested value: # CONFIG_M586MMX is not set
Actual value:
Value requested for CONFIG_M686 not in final .config
Requested value: CONFIG_M686=y
Actual value:
Value requested for CONFIG_MPENTIUMII not in final .config
Requested value: # CONFIG_MPENTIUMII is not set
Actual value:
Value requested for CONFIG_MPENTIUMIII not in final .config
Requested value: # CONFIG_MPENTIUMIII is not set
Actual value:
Value requested for CONFIG_MPENTIUMM not in final .config
Requested value: # CONFIG_MPENTIUMM is not set
Actual value:
Value requested for CONFIG_MPENTIUM4 not in final .config
Requested value: # CONFIG_MPENTIUM4 is not set
Actual value:
Value requested for CONFIG_MK6 not in final .config
Requested value: # CONFIG_MK6 is not set
Actual value:
Value requested for CONFIG_MK7 not in final .config
Requested value: # CONFIG_MK7 is not set
Actual value:
Value requested for CONFIG_MCRUSOE not in final .config
Requested value: # CONFIG_MCRUSOE is not set
Actual value:
Value requested for CONFIG_MEFFICEON not in final .config
Requested value: # CONFIG_MEFFICEON is not set
Actual value:
Value requested for CONFIG_MWINCHIPC6 not in final .config
Requested value: # CONFIG_MWINCHIPC6 is not set
Actual value:
Value requested for CONFIG_MWINCHIP3D not in final .config
Requested value: # CONFIG_MWINCHIP3D is not set
Actual value:
Value requested for CONFIG_MELAN not in final .config
Requested value: # CONFIG_MELAN is not set
Actual value:
Value requested for CONFIG_MGEODEGX1 not in final .config
Requested value: # CONFIG_MGEODEGX1 is not set
Actual value:
Value requested for CONFIG_MGEODE_LX not in final .config
Requested value: # CONFIG_MGEODE_LX is not set
Actual value:
Value requested for CONFIG_MCYRIXIII not in final .config
Requested value: # CONFIG_MCYRIXIII is not set
Actual value:
Value requested for CONFIG_MVIAC3_2 not in final .config
Requested value: # CONFIG_MVIAC3_2 is not set
Actual value:
Value requested for CONFIG_MVIAC7 not in final .config
Requested value: # CONFIG_MVIAC7 is not set
Actual value:
Value requested for CONFIG_X86_GENERIC not in final .config
Requested value: # CONFIG_X86_GENERIC is not set
Actual value:
Value requested for CONFIG_X86_INTERNODE_CACHE_SHIFT not in final .config
Requested value: CONFIG_X86_INTERNODE_CACHE_SHIFT=5
Actual value: CONFIG_X86_INTERNODE_CACHE_SHIFT=6
Value requested for CONFIG_X86_L1_CACHE_SHIFT not in final .config
Requested value: CONFIG_X86_L1_CACHE_SHIFT=5
Actual value: CONFIG_X86_L1_CACHE_SHIFT=6
Value requested for CONFIG_X86_USE_PPRO_CHECKSUM not in final .config
Requested value: CONFIG_X86_USE_PPRO_CHECKSUM=y
Actual value:
Value requested for CONFIG_X86_MINIMUM_CPU_FAMILY not in final .config
Requested value: CONFIG_X86_MINIMUM_CPU_FAMILY=6
Actual value: CONFIG_X86_MINIMUM_CPU_FAMILY=64
Value requested for CONFIG_CPU_SUP_TRANSMETA_32 not in final .config
Requested value: CONFIG_CPU_SUP_TRANSMETA_32=y
Actual value:
Value requested for CONFIG_CPU_SUP_VORTEX_32 not in final .config
Requested value: CONFIG_CPU_SUP_VORTEX_32=y
Actual value:
Value requested for CONFIG_HPET_TIMER not in final .config
Requested value: # CONFIG_HPET_TIMER is not set
Actual value: CONFIG_HPET_TIMER=y
Value requested for CONFIG_NR_CPUS_RANGE_END not in final .config
Requested value: CONFIG_NR_CPUS_RANGE_END=8
Actual value: CONFIG_NR_CPUS_RANGE_END=512
Value requested for CONFIG_NR_CPUS_DEFAULT not in final .config
Requested value: CONFIG_NR_CPUS_DEFAULT=8
Actual value: CONFIG_NR_CPUS_DEFAULT=64
Value requested for CONFIG_X86_ANCIENT_MCE not in final .config
Requested value: # CONFIG_X86_ANCIENT_MCE is not set
Actual value:
Value requested for CONFIG_X86_LEGACY_VM86 not in final .config
Requested value: # CONFIG_X86_LEGACY_VM86 is not set
Actual value:
Value requested for CONFIG_X86_ESPFIX32 not in final .config
Requested value: CONFIG_X86_ESPFIX32=y
Actual value:
Value requested for CONFIG_TOSHIBA not in final .config
Requested value: # CONFIG_TOSHIBA is not set
Actual value:
Value requested for CONFIG_X86_REBOOTFIXUPS not in final .config
Requested value: # CONFIG_X86_REBOOTFIXUPS is not set
Actual value:
Value requested for CONFIG_MICROCODE_INITRD32 not in final .config
Requested value: CONFIG_MICROCODE_INITRD32=y
Actual value:
Value requested for CONFIG_NOHIGHMEM not in final .config
Requested value: # CONFIG_NOHIGHMEM is not set
Actual value:
Value requested for CONFIG_HIGHMEM4G not in final .config
Requested value: CONFIG_HIGHMEM4G=y
Actual value:
Value requested for CONFIG_HIGHMEM64G not in final .config
Requested value: # CONFIG_HIGHMEM64G is not set
Actual value:
Value requested for CONFIG_VMSPLIT_3G not in final .config
Requested value: CONFIG_VMSPLIT_3G=y
Actual value:
Value requested for CONFIG_VMSPLIT_3G_OPT not in final .config
Requested value: # CONFIG_VMSPLIT_3G_OPT is not set
Actual value:
Value requested for CONFIG_VMSPLIT_2G not in final .config
Requested value: # CONFIG_VMSPLIT_2G is not set
Actual value:
Value requested for CONFIG_VMSPLIT_2G_OPT not in final .config
Requested value: # CONFIG_VMSPLIT_2G_OPT is not set
Actual value:
Value requested for CONFIG_VMSPLIT_1G not in final .config
Requested value: # CONFIG_VMSPLIT_1G is not set
Actual value:
Value requested for CONFIG_PAGE_OFFSET not in final .config
Requested value: CONFIG_PAGE_OFFSET=0xC0000000
Actual value:
Value requested for CONFIG_HIGHMEM not in final .config
Requested value: CONFIG_HIGHMEM=y
Actual value:
Value requested for CONFIG_X86_PAE not in final .config
Requested value: # CONFIG_X86_PAE is not set
Actual value:
Value requested for CONFIG_ARCH_FLATMEM_ENABLE not in final .config
Requested value: CONFIG_ARCH_FLATMEM_ENABLE=y
Actual value:
Value requested for CONFIG_ARCH_SELECT_MEMORY_MODEL not in final .config
Requested value: CONFIG_ARCH_SELECT_MEMORY_MODEL=y
Actual value:
Value requested for CONFIG_ILLEGAL_POINTER_VALUE not in final .config
Requested value: CONFIG_ILLEGAL_POINTER_VALUE=0
Actual value: CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
Value requested for CONFIG_HIGHPTE not in final .config
Requested value: # CONFIG_HIGHPTE is not set
Actual value:
Value requested for CONFIG_COMPAT_VDSO not in final .config
Requested value: # CONFIG_COMPAT_VDSO is not set
Actual value:
Value requested for CONFIG_FUNCTION_PADDING_CFI not in final .config
Requested value: CONFIG_FUNCTION_PADDING_CFI=0
Actual value: CONFIG_FUNCTION_PADDING_CFI=11
Value requested for CONFIG_FUNCTION_PADDING_BYTES not in final .config
Requested value: CONFIG_FUNCTION_PADDING_BYTES=4
Actual value: CONFIG_FUNCTION_PADDING_BYTES=16
Value requested for CONFIG_APM not in final .config
Requested value: # CONFIG_APM is not set
Actual value:
Value requested for CONFIG_X86_POWERNOW_K6 not in final .config
Requested value: # CONFIG_X86_POWERNOW_K6 is not set
Actual value:
Value requested for CONFIG_X86_POWERNOW_K7 not in final .config
Requested value: # CONFIG_X86_POWERNOW_K7 is not set
Actual value:
Value requested for CONFIG_X86_GX_SUSPMOD not in final .config
Requested value: # CONFIG_X86_GX_SUSPMOD is not set
Actual value:
Value requested for CONFIG_X86_SPEEDSTEP_ICH not in final .config
Requested value: # CONFIG_X86_SPEEDSTEP_ICH is not set
Actual value:
Value requested for CONFIG_X86_SPEEDSTEP_SMI not in final .config
Requested value: # CONFIG_X86_SPEEDSTEP_SMI is not set
Actual value:
Value requested for CONFIG_X86_CPUFREQ_NFORCE2 not in final .config
Requested value: # CONFIG_X86_CPUFREQ_NFORCE2 is not set
Actual value:
Value requested for CONFIG_X86_LONGRUN not in final .config
Requested value: # CONFIG_X86_LONGRUN is not set
Actual value:
Value requested for CONFIG_X86_LONGHAUL not in final .config
Requested value: # CONFIG_X86_LONGHAUL is not set
Actual value:
Value requested for CONFIG_X86_E_POWERSAVER not in final .config
Requested value: # CONFIG_X86_E_POWERSAVER is not set
Actual value:
Value requested for CONFIG_PCI_GOBIOS not in final .config
Requested value: # CONFIG_PCI_GOBIOS is not set
Actual value:
Value requested for CONFIG_PCI_GOMMCONFIG not in final .config
Requested value: # CONFIG_PCI_GOMMCONFIG is not set
Actual value:
Value requested for CONFIG_PCI_GODIRECT not in final .config
Requested value: # CONFIG_PCI_GODIRECT is not set
Actual value:
Value requested for CONFIG_PCI_GOANY not in final .config
Requested value: CONFIG_PCI_GOANY=y
Actual value:
Value requested for CONFIG_PCI_BIOS not in final .config
Requested value: CONFIG_PCI_BIOS=y
Actual value:
Value requested for CONFIG_ISA not in final .config
Requested value: # CONFIG_ISA is not set
Actual value:
Value requested for CONFIG_SCx200 not in final .config
Requested value: # CONFIG_SCx200 is not set
Actual value:
Value requested for CONFIG_OLPC not in final .config
Requested value: # CONFIG_OLPC is not set
Actual value:
Value requested for CONFIG_ALIX not in final .config
Requested value: # CONFIG_ALIX is not set
Actual value:
Value requested for CONFIG_NET5501 not in final .config
Requested value: # CONFIG_NET5501 is not set
Actual value:
Value requested for CONFIG_GEOS not in final .config
Requested value: # CONFIG_GEOS is not set
Actual value:
Value requested for CONFIG_COMPAT_32 not in final .config
Requested value: CONFIG_COMPAT_32=y
Actual value:
Value requested for CONFIG_HAVE_ATOMIC_IOMAP not in final .config
Requested value: CONFIG_HAVE_ATOMIC_IOMAP=y
Actual value:
Value requested for CONFIG_ARCH_32BIT_OFF_T not in final .config
Requested value: CONFIG_ARCH_32BIT_OFF_T=y
Actual value:
Value requested for CONFIG_ARCH_WANT_IPC_PARSE_VERSION not in final .config
Requested value: CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
Actual value:
Value requested for CONFIG_MODULES_USE_ELF_REL not in final .config
Requested value: CONFIG_MODULES_USE_ELF_REL=y
Actual value:
Value requested for CONFIG_ARCH_MMAP_RND_BITS not in final .config
Requested value: CONFIG_ARCH_MMAP_RND_BITS=8
Actual value: CONFIG_ARCH_MMAP_RND_BITS=28
Value requested for CONFIG_CLONE_BACKWARDS not in final .config
Requested value: CONFIG_CLONE_BACKWARDS=y
Actual value:
Value requested for CONFIG_OLD_SIGSUSPEND3 not in final .config
Requested value: CONFIG_OLD_SIGSUSPEND3=y
Actual value:
Value requested for CONFIG_OLD_SIGACTION not in final .config
Requested value: CONFIG_OLD_SIGACTION=y
Actual value:
Value requested for CONFIG_ARCH_SPLIT_ARG64 not in final .config
Requested value: CONFIG_ARCH_SPLIT_ARG64=y
Actual value:
Value requested for CONFIG_FUNCTION_ALIGNMENT not in final .config
Requested value: CONFIG_FUNCTION_ALIGNMENT=4
Actual value: CONFIG_FUNCTION_ALIGNMENT=16
Value requested for CONFIG_SELECT_MEMORY_MODEL not in final .config
Requested value: CONFIG_SELECT_MEMORY_MODEL=y
Actual value:
Value requested for CONFIG_FLATMEM_MANUAL not in final .config
Requested value: CONFIG_FLATMEM_MANUAL=y
Actual value:
Value requested for CONFIG_SPARSEMEM_MANUAL not in final .config
Requested value: # CONFIG_SPARSEMEM_MANUAL is not set
Actual value:
Value requested for CONFIG_FLATMEM not in final .config
Requested value: CONFIG_FLATMEM=y
Actual value:
Value requested for CONFIG_SPARSEMEM_STATIC not in final .config
Requested value: CONFIG_SPARSEMEM_STATIC=y
Actual value:
Value requested for CONFIG_BOUNCE not in final .config
Requested value: CONFIG_BOUNCE=y
Actual value:
Value requested for CONFIG_KMAP_LOCAL not in final .config
Requested value: CONFIG_KMAP_LOCAL=y
Actual value:
Value requested for CONFIG_HOTPLUG_PCI_COMPAQ not in final .config
Requested value: # CONFIG_HOTPLUG_PCI_COMPAQ is not set
Actual value:
Value requested for CONFIG_HOTPLUG_PCI_IBM not in final .config
Requested value: # CONFIG_HOTPLUG_PCI_IBM is not set
Actual value:
Value requested for CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH not in final .config
Requested value: CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH=y
Actual value:
Value requested for CONFIG_PCH_PHUB not in final .config
Requested value: # CONFIG_PCH_PHUB is not set
Actual value:
Value requested for CONFIG_SCSI_NSP32 not in final .config
Requested value: # CONFIG_SCSI_NSP32 is not set
Actual value:
Value requested for CONFIG_PATA_CS5520 not in final .config
Requested value: # CONFIG_PATA_CS5520 is not set
Actual value:
Value requested for CONFIG_PATA_CS5530 not in final .config
Requested value: # CONFIG_PATA_CS5530 is not set
Actual value:
Value requested for CONFIG_PATA_CS5535 not in final .config
Requested value: # CONFIG_PATA_CS5535 is not set
Actual value:
Value requested for CONFIG_PATA_CS5536 not in final .config
Requested value: # CONFIG_PATA_CS5536 is not set
Actual value:
Value requested for CONFIG_PATA_SC1200 not in final .config
Requested value: # CONFIG_PATA_SC1200 is not set
Actual value:
Value requested for CONFIG_PCH_GBE not in final .config
Requested value: # CONFIG_PCH_GBE is not set
Actual value:
Value requested for CONFIG_INPUT_WISTRON_BTNS not in final .config
Requested value: # CONFIG_INPUT_WISTRON_BTNS is not set
Actual value:
Value requested for CONFIG_SERIAL_TIMBERDALE not in final .config
Requested value: # CONFIG_SERIAL_TIMBERDALE is not set
Actual value:
Value requested for CONFIG_SERIAL_PCH_UART not in final .config
Requested value: # CONFIG_SERIAL_PCH_UART is not set
Actual value:
Value requested for CONFIG_HW_RANDOM_GEODE not in final .config
Requested value: CONFIG_HW_RANDOM_GEODE=y
Actual value:
Value requested for CONFIG_SONYPI not in final .config
Requested value: # CONFIG_SONYPI is not set
Actual value:
Value requested for CONFIG_PC8736x_GPIO not in final .config
Requested value: # CONFIG_PC8736x_GPIO is not set
Actual value:
Value requested for CONFIG_NSC_GPIO not in final .config
Requested value: # CONFIG_NSC_GPIO is not set
Actual value:
Value requested for CONFIG_I2C_EG20T not in final .config
Requested value: # CONFIG_I2C_EG20T is not set
Actual value:
Value requested for CONFIG_SCx200_ACB not in final .config
Requested value: # CONFIG_SCx200_ACB is not set
Actual value:
Value requested for CONFIG_PTP_1588_CLOCK_PCH not in final .config
Requested value: # CONFIG_PTP_1588_CLOCK_PCH is not set
Actual value:
Value requested for CONFIG_SBC8360_WDT not in final .config
Requested value: # CONFIG_SBC8360_WDT is not set
Actual value:
Value requested for CONFIG_SBC7240_WDT not in final .config
Requested value: # CONFIG_SBC7240_WDT is not set
Actual value:
Value requested for CONFIG_MFD_CS5535 not in final .config
Requested value: # CONFIG_MFD_CS5535 is not set
Actual value:
Value requested for CONFIG_AGP_ALI not in final .config
Requested value: # CONFIG_AGP_ALI is not set
Actual value:
Value requested for CONFIG_AGP_ATI not in final .config
Requested value: # CONFIG_AGP_ATI is not set
Actual value:
Value requested for CONFIG_AGP_AMD not in final .config
Requested value: # CONFIG_AGP_AMD is not set
Actual value:
Value requested for CONFIG_AGP_NVIDIA not in final .config
Requested value: # CONFIG_AGP_NVIDIA is not set
Actual value:
Value requested for CONFIG_AGP_SWORKS not in final .config
Requested value: # CONFIG_AGP_SWORKS is not set
Actual value:
Value requested for CONFIG_AGP_EFFICEON not in final .config
Requested value: # CONFIG_AGP_EFFICEON is not set
Actual value:
Value requested for CONFIG_SND_CS5530 not in final .config
Requested value: # CONFIG_SND_CS5530 is not set
Actual value:
Value requested for CONFIG_SND_CS5535AUDIO not in final .config
Requested value: # CONFIG_SND_CS5535AUDIO is not set
Actual value:
Value requested for CONFIG_SND_SIS7019 not in final .config
Requested value: # CONFIG_SND_SIS7019 is not set
Actual value:
Value requested for CONFIG_LEDS_OT200 not in final .config
Requested value: # CONFIG_LEDS_OT200 is not set
Actual value:
Value requested for CONFIG_PCH_DMA not in final .config
Requested value: # CONFIG_PCH_DMA is not set
Actual value:
Value requested for CONFIG_CLKSRC_I8253 not in final .config
Requested value: CONFIG_CLKSRC_I8253=y
Actual value:
Value requested for CONFIG_MAILBOX not in final .config
Requested value: # CONFIG_MAILBOX is not set
Actual value: CONFIG_MAILBOX=y
Value requested for CONFIG_CRYPTO_SERPENT_SSE2_586 not in final .config
Requested value: # CONFIG_CRYPTO_SERPENT_SSE2_586 is not set
Actual value:
Value requested for CONFIG_CRYPTO_TWOFISH_586 not in final .config
Requested value: # CONFIG_CRYPTO_TWOFISH_586 is not set
Actual value:
Value requested for CONFIG_CRYPTO_DEV_GEODE not in final .config
Requested value: # CONFIG_CRYPTO_DEV_GEODE is not set
Actual value:
Value requested for CONFIG_CRYPTO_DEV_HIFN_795X not in final .config
Requested value: # CONFIG_CRYPTO_DEV_HIFN_795X is not set
Actual value:
Value requested for CONFIG_CRYPTO_LIB_POLY1305_RSIZE not in final .config
Requested value: CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
Actual value: CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11
Value requested for CONFIG_AUDIT_GENERIC not in final .config
Requested value: CONFIG_AUDIT_GENERIC=y
Actual value:
Value requested for CONFIG_GENERIC_VDSO_32 not in final .config
Requested value: CONFIG_GENERIC_VDSO_32=y
Actual value:
Value requested for CONFIG_DEBUG_KMAP_LOCAL not in final .config
Requested value: # CONFIG_DEBUG_KMAP_LOCAL is not set
Actual value:
Value requested for CONFIG_DEBUG_HIGHMEM not in final .config
Requested value: # CONFIG_DEBUG_HIGHMEM is not set
Actual value:
Value requested for CONFIG_HAVE_DEBUG_STACKOVERFLOW not in final .config
Requested value: CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
Actual value:
Value requested for CONFIG_DEBUG_STACKOVERFLOW not in final .config
Requested value: # CONFIG_DEBUG_STACKOVERFLOW is not set
Actual value:
Value requested for CONFIG_HAVE_FUNCTION_GRAPH_TRACER not in final .config
Requested value: CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
Actual value:
Value requested for CONFIG_HAVE_FUNCTION_GRAPH_RETVAL not in final .config
Requested value: CONFIG_HAVE_FUNCTION_GRAPH_RETVAL=y
Actual value:
Value requested for CONFIG_DRM_KUNIT_TEST not in final .config
Requested value: CONFIG_DRM_KUNIT_TEST=m
Actual value:
Value requested for CONFIG_DRM_XE_WERROR not in final .config
Requested value: CONFIG_DRM_XE_WERROR=y
Actual value:
Value requested for CONFIG_DRM_XE_DEBUG not in final .config
Requested value: CONFIG_DRM_XE_DEBUG=y
Actual value:
Value requested for CONFIG_DRM_XE_DEBUG_MEM not in final .config
Requested value: CONFIG_DRM_XE_DEBUG_MEM=y
Actual value:
Value requested for CONFIG_DRM_XE_KUNIT_TEST not in final .config
Requested value: CONFIG_DRM_XE_KUNIT_TEST=m
Actual value:
++ nproc
+ make -j48 ARCH=i386 olddefconfig
GEN Makefile
WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
Selected by [m]:
- DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] && HAS_IOPORT [=y]
#
# configuration written to .config
#
++ nproc
+ make -j48 ARCH=i386
SYNC include/config/auto.conf.cmd
GEN Makefile
WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
Selected by [m]:
- DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] && HAS_IOPORT [=y]
WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
Selected by [m]:
- DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] && HAS_IOPORT [=y]
WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
Selected by [m]:
- DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] && HAS_IOPORT [=y]
GEN Makefile
WRAP arch/x86/include/generated/uapi/asm/bpf_perf_event.h
WRAP arch/x86/include/generated/uapi/asm/errno.h
WRAP arch/x86/include/generated/uapi/asm/ioctl.h
WRAP arch/x86/include/generated/uapi/asm/fcntl.h
UPD include/generated/uapi/linux/version.h
WRAP arch/x86/include/generated/uapi/asm/ioctls.h
WRAP arch/x86/include/generated/uapi/asm/ipcbuf.h
WRAP arch/x86/include/generated/uapi/asm/param.h
WRAP arch/x86/include/generated/uapi/asm/poll.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_32.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_64.h
WRAP arch/x86/include/generated/uapi/asm/socket.h
WRAP arch/x86/include/generated/uapi/asm/resource.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_x32.h
WRAP arch/x86/include/generated/uapi/asm/sockios.h
WRAP arch/x86/include/generated/uapi/asm/termbits.h
SYSTBL arch/x86/include/generated/asm/syscalls_32.h
WRAP arch/x86/include/generated/uapi/asm/termios.h
WRAP arch/x86/include/generated/uapi/asm/types.h
HOSTCC arch/x86/tools/relocs_32.o
HOSTCC arch/x86/tools/relocs_64.o
HOSTCC arch/x86/tools/relocs_common.o
UPD include/generated/compile.h
WRAP arch/x86/include/generated/asm/early_ioremap.h
WRAP arch/x86/include/generated/asm/mcs_spinlock.h
WRAP arch/x86/include/generated/asm/mmzone.h
WRAP arch/x86/include/generated/asm/irq_regs.h
WRAP arch/x86/include/generated/asm/kmap_size.h
WRAP arch/x86/include/generated/asm/local64.h
WRAP arch/x86/include/generated/asm/mmiowb.h
WRAP arch/x86/include/generated/asm/module.lds.h
HOSTCC scripts/kallsyms
HOSTCC scripts/sorttable
WRAP arch/x86/include/generated/asm/rwonce.h
HOSTCC scripts/asn1_compiler
HOSTCC scripts/selinux/mdp/mdp
HOSTLD arch/x86/tools/relocs
UPD include/config/kernel.release
UPD include/generated/utsrelease.h
CC scripts/mod/empty.o
HOSTCC scripts/mod/mk_elfconfig
CC scripts/mod/devicetable-offsets.s
UPD scripts/mod/devicetable-offsets.h
MKELF scripts/mod/elfconfig.h
HOSTCC scripts/mod/modpost.o
HOSTCC scripts/mod/file2alias.o
HOSTCC scripts/mod/sumversion.o
HOSTCC scripts/mod/symsearch.o
HOSTLD scripts/mod/modpost
CC kernel/bounds.s
CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-arch-fallback.h
CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-instrumented.h
CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-long.h
UPD include/generated/timeconst.h
UPD include/generated/bounds.h
CC arch/x86/kernel/asm-offsets.s
UPD include/generated/asm-offsets.h
CALL /workspace/kernel/scripts/checksyscalls.sh
LDS scripts/module.lds
HOSTCC usr/gen_init_cpio
CC init/main.o
CC init/do_mounts.o
CC certs/system_keyring.o
CC ipc/util.o
CC init/do_mounts_initrd.o
CC security/commoncap.o
UPD init/utsversion-tmp.h
CC ipc/msgutil.o
CC init/initramfs.o
CC security/lsm_syscalls.o
CC ipc/msg.o
CC init/calibrate.o
CC security/min_addr.o
CC block/bdev.o
CC ipc/sem.o
CC mm/filemap.o
AS arch/x86/entry/entry.o
CC io_uring/io_uring.o
CC init/init_task.o
AS arch/x86/lib/atomic64_cx8_32.o
HOSTCC security/selinux/genheaders
AR arch/x86/crypto/built-in.a
AR arch/x86/net/built-in.a
CC arch/x86/realmode/init.o
AS arch/x86/entry/entry_32.o
CC security/keys/gc.o
CC arch/x86/power/cpu.o
CC arch/x86/video/video-common.o
CC arch/x86/pci/i386.o
AR arch/x86/entry/vsyscall/built-in.a
CC block/partitions/core.o
AR virt/lib/built-in.a
CC arch/x86/events/amd/core.o
CC security/integrity/iint.o
CC arch/x86/events/intel/core.o
AR arch/x86/platform/atom/built-in.a
AR drivers/cache/built-in.a
CC arch/x86/events/zhaoxin/core.o
CC arch/x86/virt/svm/cmdline.o
CC arch/x86/mm/pat/set_memory.o
AR virt/built-in.a
CC lib/math/div64.o
CC arch/x86/kernel/fpu/init.o
CC net/core/sock.o
CC fs/notify/dnotify/dnotify.o
AR arch/x86/platform/ce4100/built-in.a
CC sound/core/seq/seq.o
AR sound/i2c/other/built-in.a
CC sound/core/seq/seq_lock.o
CC lib/crypto/mpi/generic_mpih-lshift.o
AR drivers/irqchip/built-in.a
AR sound/i2c/built-in.a
AR sound/drivers/opl3/built-in.a
AS arch/x86/lib/checksum_32.o
CC arch/x86/entry/vdso/vma.o
CC sound/core/sound.o
CC arch/x86/platform/efi/memmap.o
AR sound/drivers/opl4/built-in.a
CC sound/core/init.o
AR drivers/bus/mhi/built-in.a
AR sound/drivers/mpu401/built-in.a
CC kernel/sched/core.o
CC lib/zlib_inflate/inffast.o
AR drivers/bus/built-in.a
CC arch/x86/lib/cmdline.o
AR sound/drivers/vx/built-in.a
CC crypto/asymmetric_keys/asymmetric_type.o
AR sound/drivers/pcsp/built-in.a
AR drivers/pwm/built-in.a
AR sound/drivers/built-in.a
AR drivers/leds/trigger/built-in.a
CC arch/x86/power/hibernate_32.o
AR arch/x86/virt/svm/built-in.a
AR drivers/leds/blink/built-in.a
AR arch/x86/virt/vmx/built-in.a
AR drivers/leds/simple/built-in.a
AR arch/x86/virt/built-in.a
CC drivers/leds/led-core.o
AS arch/x86/lib/cmpxchg8b_emu.o
CC lib/math/gcd.o
CC lib/math/lcm.o
CC arch/x86/lib/cpu.o
GEN security/selinux/flask.h security/selinux/av_permissions.h
CC security/selinux/avc.o
CC block/fops.o
CC lib/zlib_inflate/inflate.o
CC lib/math/int_log.o
CC crypto/asymmetric_keys/restrict.o
CC lib/math/int_pow.o
GEN usr/initramfs_data.cpio
COPY usr/initramfs_inc_data
AS usr/initramfs_data.o
HOSTCC certs/extract-cert
AR usr/built-in.a
CC arch/x86/kernel/fpu/bugs.o
CC fs/notify/inotify/inotify_fsnotify.o
CC lib/math/int_sqrt.o
CC arch/x86/pci/init.o
CC lib/math/reciprocal_div.o
CC arch/x86/kernel/fpu/core.o
CC lib/math/rational.o
CC arch/x86/lib/delay.o
CC sound/core/seq/seq_clientmgr.o
AS arch/x86/realmode/rm/header.o
CC lib/crypto/mpi/generic_mpih-mul1.o
AS arch/x86/realmode/rm/trampoline_32.o
AR arch/x86/video/built-in.a
AS arch/x86/realmode/rm/stack.o
CC kernel/locking/mutex.o
CC arch/x86/mm/init.o
AS arch/x86/realmode/rm/reboot.o
CERT certs/x509_certificate_list
CERT certs/signing_key.x509
AR fs/notify/fanotify/built-in.a
AS certs/system_certificates.o
AS arch/x86/realmode/rm/wakeup_asm.o
CC arch/x86/entry/vdso/extable.o
CC security/integrity/integrity_audit.o
CC drivers/pci/msi/pcidev_msi.o
AR certs/built-in.a
LDS arch/x86/entry/vdso/vdso32/vdso32.lds
CC arch/x86/realmode/rm/wakemain.o
CC arch/x86/mm/init_32.o
CC drivers/leds/led-class.o
CC drivers/pci/pcie/portdrv.o
AR sound/isa/ad1816a/built-in.a
CC block/partitions/msdos.o
CC arch/x86/entry/syscall_32.o
AR sound/isa/ad1848/built-in.a
CC crypto/asymmetric_keys/signature.o
CC security/keys/key.o
AR sound/isa/cs423x/built-in.a
CC crypto/api.o
CC arch/x86/realmode/rm/video-mode.o
AR sound/isa/es1688/built-in.a
AR sound/isa/galaxy/built-in.a
AR fs/notify/dnotify/built-in.a
CC sound/core/seq/seq_memory.o
CC arch/x86/platform/efi/quirks.o
CC lib/crypto/mpi/generic_mpih-mul2.o
AR sound/isa/gus/built-in.a
AR sound/isa/msnd/built-in.a
AR sound/pci/ac97/built-in.a
AR sound/pci/ali5451/built-in.a
AR sound/isa/opti9xx/built-in.a
AS arch/x86/power/hibernate_asm_32.o
AR sound/pci/asihpi/built-in.a
AS arch/x86/lib/getuser.o
AR sound/isa/sb/built-in.a
AR sound/pci/au88x0/built-in.a
CC arch/x86/power/hibernate.o
AR sound/isa/wavefront/built-in.a
AR sound/pci/aw2/built-in.a
GEN arch/x86/lib/inat-tables.c
CC lib/zlib_inflate/infutil.o
AR sound/isa/wss/built-in.a
AS arch/x86/realmode/rm/copy.o
AR sound/pci/ctxfi/built-in.a
CC kernel/power/qos.o
AR sound/isa/built-in.a
CC arch/x86/lib/insn-eval.o
AR arch/x86/events/zhaoxin/built-in.a
AR sound/pci/ca0106/built-in.a
AS arch/x86/realmode/rm/bioscall.o
CC lib/zlib_deflate/deflate.o
AR arch/x86/platform/geode/built-in.a
AR sound/pci/cs46xx/built-in.a
CC fs/notify/inotify/inotify_user.o
CC lib/zlib_deflate/deftree.o
CC arch/x86/realmode/rm/regs.o
AR lib/math/built-in.a
AR sound/pci/cs5535audio/built-in.a
CC security/selinux/hooks.o
AR sound/pci/lola/built-in.a
AR sound/pci/lx6464es/built-in.a
CC lib/zlib_deflate/deflate_syms.o
CC arch/x86/realmode/rm/video-vga.o
AR sound/pci/echoaudio/built-in.a
AR sound/pci/emu10k1/built-in.a
CC crypto/cipher.o
CC sound/pci/hda/hda_bind.o
CC arch/x86/pci/pcbios.o
CC io_uring/opdef.o
CC arch/x86/realmode/rm/video-vesa.o
CC block/bio.o
CC block/elevator.o
CC arch/x86/realmode/rm/video-bios.o
CC crypto/asymmetric_keys/public_key.o
ASN.1 crypto/asymmetric_keys/x509.asn1.[ch]
CC drivers/leds/led-triggers.o
CC arch/x86/events/amd/lbr.o
CC lib/zlib_inflate/inftrees.o
CC lib/lzo/lzo1x_compress.o
CC lib/lzo/lzo1x_decompress_safe.o
PASYMS arch/x86/realmode/rm/pasyms.h
CC io_uring/kbuf.o
CC block/blk-core.o
LDS arch/x86/realmode/rm/realmode.lds
LD arch/x86/realmode/rm/realmode.elf
CC fs/notify/fsnotify.o
CC drivers/pci/msi/api.o
RELOCS arch/x86/realmode/rm/realmode.relocs
OBJCOPY arch/x86/realmode/rm/realmode.bin
AS arch/x86/realmode/rmpiggy.o
AR arch/x86/realmode/built-in.a
CC kernel/sched/fair.o
CC lib/crypto/mpi/generic_mpih-mul3.o
CC lib/zlib_inflate/inflate_syms.o
AR security/integrity/built-in.a
CC init/version.o
CC arch/x86/mm/pat/memtype.o
AS arch/x86/entry/vdso/vdso32/note.o
CC arch/x86/kernel/cpu/mce/core.o
AS arch/x86/entry/vdso/vdso32/system_call.o
AS arch/x86/entry/vdso/vdso32/sigreturn.o
CC arch/x86/entry/vdso/vdso32/vclock_gettime.o
CC drivers/pci/pcie/rcec.o
AR arch/x86/power/built-in.a
CC block/partitions/efi.o
CC arch/x86/kernel/cpu/mtrr/mtrr.o
CC arch/x86/mm/pat/memtype_interval.o
CC sound/core/seq/seq_queue.o
AR drivers/pci/pwrctrl/built-in.a
CC arch/x86/kernel/acpi/boot.o
CC arch/x86/kernel/apic/apic.o
CC arch/x86/kernel/apic/apic_common.o
CC arch/x86/kernel/apic/apic_noop.o
AR init/built-in.a
CC arch/x86/kernel/apic/ipi.o
CC arch/x86/kernel/fpu/regset.o
CC arch/x86/pci/mmconfig_32.o
CC arch/x86/platform/efi/efi.o
CC security/keys/keyring.o
CC sound/pci/hda/hda_codec.o
CC ipc/shm.o
AR lib/zlib_inflate/built-in.a
AR lib/lzo/built-in.a
CC io_uring/rsrc.o
CC arch/x86/mm/fault.o
AR lib/zlib_deflate/built-in.a
CC arch/x86/lib/insn.o
CC arch/x86/lib/kaslr.o
AR sound/pci/ice1712/built-in.a
CC arch/x86/entry/vdso/vdso32/vgetcpu.o
CC arch/x86/events/core.o
CC sound/core/seq/seq_fifo.o
ASN.1 crypto/asymmetric_keys/x509_akid.asn1.[ch]
CC crypto/asymmetric_keys/x509_loader.o
CC kernel/printk/printk.o
CC drivers/video/console/dummycon.o
CC arch/x86/pci/direct.o
CC kernel/locking/semaphore.o
AR drivers/leds/built-in.a
AR fs/notify/inotify/built-in.a
CC kernel/printk/printk_safe.o
CC security/selinux/selinuxfs.o
CC lib/crypto/mpi/generic_mpih-rshift.o
CC arch/x86/events/probe.o
CC kernel/power/main.o
CC kernel/power/console.o
CC drivers/pci/msi/msi.o
CC arch/x86/events/amd/ibs.o
CC crypto/asymmetric_keys/x509_public_key.o
CC arch/x86/kernel/cpu/microcode/core.o
CC arch/x86/lib/memcpy_32.o
AS arch/x86/lib/memmove_32.o
CC arch/x86/lib/misc.o
HOSTCC arch/x86/entry/vdso/vdso2c
CC arch/x86/lib/pc-conf-reg.o
CC fs/notify/notification.o
CC drivers/pci/pcie/bwctrl.o
CC kernel/power/process.o
AS arch/x86/lib/putuser.o
CC kernel/power/suspend.o
CC arch/x86/kernel/cpu/mtrr/if.o
CC arch/x86/kernel/cpu/mtrr/generic.o
CC arch/x86/platform/efi/efi_32.o
CC sound/core/memory.o
CC security/keys/keyctl.o
AS arch/x86/lib/retpoline.o
AR arch/x86/mm/pat/built-in.a
CC arch/x86/lib/string_32.o
CC security/security.o
AR block/partitions/built-in.a
CC security/keys/permission.o
CC sound/core/seq/seq_prioq.o
CC crypto/compress.o
CC arch/x86/lib/strstr_32.o
CC arch/x86/kernel/fpu/signal.o
CC drivers/video/console/vgacon.o
CC arch/x86/lib/usercopy.o
CC lib/crypto/mpi/generic_mpih-sub1.o
CC net/core/request_sock.o
CC arch/x86/pci/mmconfig-shared.o
CC kernel/locking/rwsem.o
CC arch/x86/entry/vdso/vdso32-setup.o
ASN.1 crypto/asymmetric_keys/pkcs7.asn1.[ch]
CC crypto/asymmetric_keys/pkcs7_trust.o
CC arch/x86/kernel/acpi/sleep.o
CC sound/core/control.o
CC drivers/pci/msi/irqdomain.o
CC arch/x86/kernel/cpu/microcode/intel.o
AR sound/ppc/built-in.a
CC arch/x86/lib/usercopy_32.o
CC fs/nfs_common/nfsacl.o
CC fs/notify/group.o
CC drivers/pci/pcie/aspm.o
VDSO arch/x86/entry/vdso/vdso32.so.dbg
CC mm/mempool.o
CC lib/crypto/mpi/generic_mpih-add1.o
CC arch/x86/pci/fixup.o
CC ipc/syscall.o
OBJCOPY arch/x86/entry/vdso/vdso32.so
VDSO2C arch/x86/entry/vdso/vdso-image-32.c
CC arch/x86/entry/vdso/vdso-image-32.o
CC security/keys/process_keys.o
CC kernel/sched/build_policy.o
CC crypto/asymmetric_keys/pkcs7_verify.o
CC sound/core/seq/seq_timer.o
CC arch/x86/mm/ioremap.o
CC arch/x86/events/utils.o
AS arch/x86/platform/efi/efi_stub_32.o
CC io_uring/notif.o
CC arch/x86/platform/efi/runtime-map.o
CC sound/pci/hda/hda_jack.o
CC arch/x86/lib/msr-smp.o
CC kernel/locking/percpu-rwsem.o
CC fs/iomap/trace.o
CC drivers/pci/pcie/pme.o
CC arch/x86/events/intel/bts.o
AR arch/x86/entry/vdso/built-in.a
CC arch/x86/entry/common.o
CC arch/x86/kernel/cpu/mce/severity.o
CC arch/x86/kernel/cpu/mce/genpool.o
CC arch/x86/events/amd/uncore.o
CC arch/x86/kernel/fpu/xstate.o
CC arch/x86/kernel/apic/vector.o
CC arch/x86/kernel/cpu/mtrr/cleanup.o
CC block/blk-sysfs.o
AS arch/x86/kernel/acpi/wakeup_32.o
CC arch/x86/kernel/acpi/cstate.o
CC kernel/power/hibernate.o
CC arch/x86/lib/cache-smp.o
CC crypto/asymmetric_keys/x509.asn1.o
CC crypto/asymmetric_keys/x509_akid.asn1.o
CC drivers/pci/hotplug/pci_hotplug_core.o
AR drivers/video/console/built-in.a
CC crypto/asymmetric_keys/x509_cert_parser.o
AR drivers/pci/msi/built-in.a
CC drivers/video/backlight/backlight.o
CC net/core/skbuff.o
AS arch/x86/entry/thunk.o
CC arch/x86/events/intel/ds.o
CC fs/nfs_common/grace.o
CC lib/crypto/mpi/mpicoder.o
CC fs/notify/mark.o
CC io_uring/tctx.o
CC arch/x86/kernel/cpu/mce/intel.o
CC arch/x86/kernel/cpu/microcode/amd.o
CC arch/x86/lib/msr.o
CC mm/oom_kill.o
CC ipc/ipc_sysctl.o
CC kernel/locking/spinlock.o
CC sound/core/seq/seq_system.o
CC arch/x86/kernel/cpu/mce/amd.o
AR sound/arm/built-in.a
CC crypto/algapi.o
AR arch/x86/platform/efi/built-in.a
AR drivers/video/fbdev/core/built-in.a
CC arch/x86/pci/acpi.o
AR arch/x86/platform/iris/built-in.a
CC drivers/video/aperture.o
AR drivers/video/fbdev/omap/built-in.a
CC arch/x86/platform/intel/iosf_mbi.o
AR arch/x86/platform/intel-mid/built-in.a
AR drivers/video/fbdev/omap2/omapfb/dss/built-in.a
AR arch/x86/platform/intel-quark/built-in.a
CC sound/core/seq/seq_ports.o
CC lib/crypto/mpi/mpi-add.o
CC arch/x86/mm/extable.o
AR drivers/video/fbdev/omap2/omapfb/displays/built-in.a
CC block/blk-flush.o
AR drivers/video/fbdev/omap2/omapfb/built-in.a
AR drivers/video/fbdev/omap2/built-in.a
AR arch/x86/kernel/acpi/built-in.a
AR drivers/video/fbdev/built-in.a
CC drivers/video/cmdline.o
CC block/blk-settings.o
CC security/keys/request_key.o
AR arch/x86/entry/built-in.a
CC arch/x86/kernel/cpu/mce/threshold.o
CC crypto/asymmetric_keys/pkcs7.asn1.o
CC crypto/asymmetric_keys/pkcs7_parser.o
CC sound/pci/hda/hda_auto_parser.o
CC arch/x86/events/intel/knc.o
CC kernel/irq/irqdesc.o
CC kernel/locking/osq_lock.o
CC net/core/datagram.o
CC kernel/printk/nbcon.o
CC arch/x86/kernel/cpu/mtrr/amd.o
CC arch/x86/kernel/kprobes/core.o
AR drivers/pci/pcie/built-in.a
CC net/core/stream.o
CC sound/pci/hda/hda_sysfs.o
CC ipc/mqueue.o
CC arch/x86/kernel/cpu/cacheinfo.o
CC fs/nfs_common/common.o
CC drivers/pci/hotplug/acpi_pcihp.o
CC fs/iomap/iter.o
CC security/lsm_audit.o
CC mm/fadvise.o
AR drivers/video/backlight/built-in.a
CC arch/x86/events/rapl.o
CC kernel/locking/qspinlock.o
AR arch/x86/events/amd/built-in.a
CC sound/pci/hda/hda_controller.o
CC io_uring/filetable.o
CC fs/notify/fdinfo.o
AS arch/x86/lib/msr-reg.o
AR arch/x86/kernel/cpu/microcode/built-in.a
CC arch/x86/mm/mmap.o
CC arch/x86/lib/msr-reg-export.o
AR arch/x86/kernel/fpu/built-in.a
CC io_uring/rw.o
CC lib/crypto/mpi/mpi-bit.o
AR arch/x86/platform/intel/built-in.a
AR crypto/asymmetric_keys/built-in.a
CC fs/iomap/buffered-io.o
AR arch/x86/platform/olpc/built-in.a
CC arch/x86/pci/legacy.o
AR arch/x86/platform/scx200/built-in.a
AR arch/x86/platform/ts5500/built-in.a
AR arch/x86/platform/uv/built-in.a
AR arch/x86/platform/built-in.a
CC sound/core/seq/seq_info.o
CC arch/x86/events/intel/lbr.o
AS arch/x86/lib/hweight.o
CC arch/x86/kernel/cpu/mtrr/cyrix.o
AR sound/pci/korg1212/built-in.a
CC drivers/video/nomodeset.o
CC arch/x86/mm/pgtable.o
CC kernel/power/snapshot.o
CC arch/x86/lib/iomem.o
CC security/selinux/netlink.o
CC arch/x86/mm/physaddr.o
CC security/device_cgroup.o
CC kernel/locking/rtmutex_api.o
CC kernel/irq/handle.o
CC io_uring/net.o
CC block/blk-ioc.o
CC arch/x86/kernel/apic/init.o
CC security/keys/request_key_auth.o
CC fs/quota/dquot.o
CC security/keys/user_defined.o
CC kernel/printk/printk_ringbuffer.o
AR fs/nfs_common/built-in.a
CC sound/pci/hda/hda_proc.o
AR drivers/pci/hotplug/built-in.a
AR drivers/pci/controller/dwc/built-in.a
AR drivers/pci/controller/mobiveil/built-in.a
AR drivers/pci/controller/plda/built-in.a
CC crypto/scatterwalk.o
AR drivers/pci/controller/built-in.a
CC drivers/video/hdmi.o
AR drivers/pci/switch/built-in.a
CC drivers/pci/access.o
AR fs/notify/built-in.a
CC kernel/irq/manage.o
CC security/selinux/nlmsgtab.o
CC arch/x86/lib/atomic64_32.o
CC lib/crypto/mpi/mpi-cmp.o
CC io_uring/poll.o
CC arch/x86/kernel/kprobes/opt.o
CC lib/lz4/lz4_decompress.o
AR sound/sh/built-in.a
CC arch/x86/kernel/cpu/scattered.o
CC arch/x86/lib/inat.o
AR arch/x86/lib/built-in.a
LDS arch/x86/kernel/vmlinux.lds
CC arch/x86/pci/irq.o
CC sound/core/seq/seq_dummy.o
CC kernel/locking/qrwlock.o
CC net/core/scm.o
CC kernel/irq/spurious.o
CC mm/maccess.o
CC io_uring/eventfd.o
CC kernel/rcu/update.o
CC arch/x86/kernel/cpu/mtrr/centaur.o
AR arch/x86/lib/lib.a
CC arch/x86/kernel/apic/hw_nmi.o
AR kernel/livepatch/built-in.a
CC arch/x86/kernel/cpu/topology_common.o
CC drivers/pci/bus.o
AR arch/x86/kernel/cpu/mce/built-in.a
CC drivers/pci/probe.o
AR sound/pci/mixart/built-in.a
AR drivers/idle/built-in.a
CC kernel/irq/resend.o
CC kernel/sched/build_utility.o
CC fs/proc/task_mmu.o
CC arch/x86/mm/tlb.o
CC sound/core/misc.o
CC sound/core/device.o
CC block/blk-map.o
CC security/keys/proc.o
CC fs/quota/quota_v2.o
CC net/core/gen_stats.o
CC crypto/proc.o
CC kernel/printk/sysctl.o
CC kernel/dma/mapping.o
CC lib/crypto/mpi/mpi-sub-ui.o
CC ipc/namespace.o
CC io_uring/uring_cmd.o
CC kernel/power/swap.o
AR kernel/locking/built-in.a
CC sound/core/info.o
CC fs/iomap/direct-io.o
CC arch/x86/kernel/cpu/mtrr/legacy.o
AR sound/core/seq/built-in.a
CC lib/crypto/memneq.o
CC lib/crypto/mpi/mpi-div.o
AR drivers/video/built-in.a
CC lib/zstd/zstd_decompress_module.o
CC arch/x86/mm/cpu_entry_area.o
CC arch/x86/pci/common.o
CC kernel/rcu/sync.o
CC kernel/rcu/srcutree.o
CC arch/x86/kernel/apic/io_apic.o
CC mm/page-writeback.o
AR arch/x86/kernel/kprobes/built-in.a
CC arch/x86/kernel/apic/msi.o
CC kernel/dma/direct.o
CC lib/crypto/utils.o
CC arch/x86/events/intel/p4.o
AR kernel/printk/built-in.a
CC kernel/rcu/tree.o
CC lib/xz/xz_dec_syms.o
CC security/selinux/netif.o
CC sound/pci/hda/hda_hwdep.o
CC net/ethernet/eth.o
CC block/blk-merge.o
CC arch/x86/events/intel/p6.o
AR arch/x86/kernel/cpu/mtrr/built-in.a
CC arch/x86/kernel/cpu/topology_ext.o
CC security/keys/sysctl.o
CC fs/kernfs/mount.o
CC lib/zstd/decompress/huf_decompress.o
CC crypto/aead.o
CC fs/sysfs/file.o
CC ipc/mq_sysctl.o
CC fs/devpts/inode.o
CC fs/kernfs/inode.o
CC lib/xz/xz_dec_stream.o
CC fs/kernfs/dir.o
CC kernel/entry/common.o
AR lib/lz4/built-in.a
CC fs/sysfs/dir.o
CC kernel/irq/chip.o
CC lib/crypto/mpi/mpi-mod.o
CC security/keys/keyctl_pkey.o
AR sound/pci/nm256/built-in.a
CC kernel/entry/syscall_user_dispatch.o
AR sound/pci/oxygen/built-in.a
CC arch/x86/mm/maccess.o
AR net/802/built-in.a
CC fs/proc/inode.o
CC fs/kernfs/file.o
CC arch/x86/kernel/cpu/topology_amd.o
AR ipc/built-in.a
CC arch/x86/events/intel/pt.o
CC fs/quota/quota_tree.o
CC sound/core/isadma.o
CC fs/proc/root.o
AR drivers/char/ipmi/built-in.a
CC fs/kernfs/symlink.o
CC kernel/irq/dummychip.o
CC arch/x86/pci/early.o
CC arch/x86/pci/bus_numa.o
CC sound/pci/hda/hda_intel.o
CC arch/x86/mm/pgprot.o
CC lib/xz/xz_dec_lzma2.o
CC fs/proc/base.o
CC fs/iomap/fiemap.o
CC kernel/module/main.o
CC kernel/module/strict_rwx.o
CC io_uring/openclose.o
CC drivers/pci/host-bridge.o
CC io_uring/sqpoll.o
CC lib/crypto/mpi/mpi-mul.o
CC arch/x86/kernel/cpu/common.o
CC kernel/dma/ops_helpers.o
AR fs/devpts/built-in.a
CC fs/sysfs/symlink.o
CC kernel/power/user.o
CC arch/x86/kernel/apic/probe_32.o
CC lib/crypto/chacha.o
CC fs/quota/quota.o
CC sound/core/vmaster.o
AR security/keys/built-in.a
CC crypto/geniv.o
CC kernel/rcu/rcu_segcblist.o
CC fs/quota/kqid.o
CC fs/sysfs/mount.o
CC kernel/time/time.o
CC mm/folio-compat.o
CC security/selinux/netnode.o
CC net/sched/sch_generic.o
CC arch/x86/mm/pgtable_32.o
CC kernel/futex/core.o
CC security/selinux/netport.o
CC kernel/irq/devres.o
CC net/sched/sch_mq.o
AR net/ethernet/built-in.a
CC arch/x86/pci/amd_bus.o
CC arch/x86/events/intel/uncore.o
CC fs/netfs/buffered_read.o
AR kernel/entry/built-in.a
CC arch/x86/mm/iomap_32.o
CC arch/x86/kernel/cpu/rdrand.o
CC crypto/lskcipher.o
CC fs/proc/generic.o
CC lib/zstd/decompress/zstd_ddict.o
CC fs/iomap/seek.o
CC mm/readahead.o
CC lib/crypto/mpi/mpih-cmp.o
CC fs/ext4/balloc.o
CC lib/xz/xz_dec_bcj.o
CC fs/jbd2/transaction.o
CC kernel/module/kmod.o
CC drivers/pci/remove.o
AR arch/x86/kernel/apic/built-in.a
CC net/netlink/af_netlink.o
AR net/bpf/built-in.a
CC block/blk-timeout.o
AR fs/kernfs/built-in.a
CC lib/zstd/decompress/zstd_decompress.o
CC arch/x86/events/msr.o
CC sound/core/ctljack.o
CC lib/dim/dim.o
CC lib/fonts/fonts.o
CC lib/argv_split.o
CC kernel/power/poweroff.o
CC arch/x86/events/intel/uncore_nhmex.o
CC net/netlink/genetlink.o
CC fs/iomap/swapfile.o
CC kernel/dma/remap.o
CC kernel/irq/autoprobe.o
CC security/selinux/status.o
CC fs/sysfs/group.o
CC fs/quota/netlink.o
AS arch/x86/kernel/head_32.o
CC drivers/acpi/acpica/dsargs.o
AR kernel/power/built-in.a
CC arch/x86/kernel/cpu/match.o
CC fs/ramfs/inode.o
CC arch/x86/mm/hugetlbpage.o
CC sound/core/jack.o
CC lib/fonts/font_8x16.o
CC lib/dim/net_dim.o
CC drivers/pci/pci.o
AR lib/xz/built-in.a
CC arch/x86/kernel/cpu/bugs.o
CC kernel/time/timer.o
CC lib/crypto/mpi/mpih-div.o
AR arch/x86/pci/built-in.a
CC kernel/futex/syscalls.o
AR sound/pci/hda/built-in.a
CC fs/proc/array.o
CC security/selinux/ss/ebitmap.o
AR sound/pci/pcxhr/built-in.a
AR sound/pci/riptide/built-in.a
CC kernel/irq/irqdomain.o
AR sound/pci/rme9652/built-in.a
AR sound/pci/trident/built-in.a
AR sound/pci/ymfpci/built-in.a
AR sound/pci/vx222/built-in.a
AR sound/pci/built-in.a
CC mm/swap.o
CC net/core/gen_estimator.o
CC block/blk-lib.o
CC block/blk-mq.o
CC block/blk-mq-tag.o
CC block/blk-stat.o
CC arch/x86/kernel/head32.o
CC drivers/acpi/acpica/dscontrol.o
AR lib/fonts/built-in.a
CC arch/x86/mm/dump_pagetables.o
CC io_uring/xattr.o
CC lib/crypto/mpi/mpih-mul.o
CC kernel/futex/pi.o
AR kernel/dma/built-in.a
CC security/selinux/ss/hashtab.o
CC kernel/cgroup/cgroup.o
CC crypto/skcipher.o
CC lib/zstd/decompress/zstd_decompress_block.o
CC lib/crypto/aes.o
CC mm/truncate.o
AR sound/synth/emux/built-in.a
AR sound/synth/built-in.a
CC lib/dim/rdma_dim.o
CC lib/crypto/mpi/mpi-pow.o
AR fs/iomap/built-in.a
CC kernel/module/tree_lookup.o
AR fs/sysfs/built-in.a
CC net/core/net_namespace.o
CC arch/x86/kernel/cpu/aperfmperf.o
CC fs/netfs/buffered_write.o
CC sound/core/hwdep.o
AR fs/quota/built-in.a
CC block/blk-mq-sysfs.o
CC drivers/acpi/acpica/dsdebug.o
CC kernel/irq/proc.o
CC fs/ramfs/file-mmu.o
AR sound/usb/misc/built-in.a
AR sound/usb/usx2y/built-in.a
AR kernel/sched/built-in.a
AR sound/usb/caiaq/built-in.a
CC kernel/irq/migration.o
CC kernel/irq/cpuhotplug.o
AR sound/usb/6fire/built-in.a
AR sound/usb/hiface/built-in.a
CC fs/proc/fd.o
AR sound/usb/bcd2000/built-in.a
AR sound/usb/built-in.a
CC arch/x86/mm/highmem_32.o
CC kernel/time/hrtimer.o
CC fs/hugetlbfs/inode.o
AR sound/firewire/built-in.a
CC net/sched/sch_frag.o
CC lib/bug.o
AR lib/dim/built-in.a
CC kernel/irq/pm.o
CC arch/x86/events/intel/uncore_snb.o
CC arch/x86/kernel/ebda.o
CC lib/zstd/zstd_common_module.o
CC net/core/secure_seq.o
CC kernel/cgroup/rstat.o
CC drivers/acpi/acpica/dsfield.o
CC fs/jbd2/commit.o
AR sound/sparc/built-in.a
CC kernel/trace/trace_clock.o
CC kernel/futex/requeue.o
CC kernel/module/kallsyms.o
CC lib/crypto/mpi/mpiutil.o
CC kernel/futex/waitwake.o
CC kernel/irq/msi.o
CC kernel/irq/affinity.o
CC io_uring/nop.o
CC lib/buildid.o
CC lib/crypto/arc4.o
CC drivers/pci/pci-driver.o
CC mm/vmscan.o
CC arch/x86/kernel/platform-quirks.o
CC security/selinux/ss/symtab.o
CC sound/core/timer.o
CC fs/fat/cache.o
CC fs/ext4/bitmap.o
AR fs/ramfs/built-in.a
CC kernel/module/procfs.o
CC kernel/bpf/core.o
CC fs/proc/proc_tty.o
CC arch/x86/kernel/cpu/cpuid-deps.o
CC kernel/trace/ring_buffer.o
CC drivers/acpi/acpica/dsinit.o
CC security/selinux/ss/sidtab.o
AR arch/x86/mm/built-in.a
CC crypto/seqiv.o
AR sound/spi/built-in.a
CC net/core/flow_dissector.o
CC drivers/pnp/core.o
CC drivers/pnp/pnpacpi/core.o
CC drivers/pnp/pnpacpi/rsparser.o
CC fs/jbd2/recovery.o
CC net/core/sysctl_net_core.o
CC fs/fat/dir.o
CC sound/core/hrtimer.o
CC kernel/trace/trace.o
CC drivers/acpi/acpica/dsmethod.o
CC fs/ext4/block_validity.o
CC fs/netfs/direct_read.o
AR lib/crypto/mpi/built-in.a
CC lib/crypto/gf128mul.o
CC drivers/pci/search.o
CC lib/clz_tab.o
CC arch/x86/kernel/cpu/umwait.o
AR drivers/acpi/pmic/built-in.a
CC block/blk-mq-cpumap.o
CC security/selinux/ss/avtab.o
CC crypto/echainiv.o
CC sound/core/pcm.o
CC net/netlink/policy.o
CC drivers/pnp/card.o
AR kernel/futex/built-in.a
CC kernel/irq/matrix.o
AR kernel/rcu/built-in.a
CC kernel/time/sleep_timeout.o
CC io_uring/fs.o
AR drivers/amba/built-in.a
CC arch/x86/events/intel/uncore_snbep.o
CC fs/fat/fatent.o
CC kernel/module/sysfs.o
CC lib/zstd/common/debug.o
CC fs/proc/cmdline.o
CC kernel/events/core.o
CC kernel/fork.o
CC net/sched/sch_api.o
MKCAP arch/x86/kernel/cpu/capflags.c
CC drivers/acpi/acpica/dsmthdat.o
CC crypto/ahash.o
CC drivers/pci/rom.o
CC fs/netfs/direct_write.o
CC arch/x86/kernel/process_32.o
CC security/selinux/ss/policydb.o
CC kernel/exec_domain.o
CC net/sched/sch_blackhole.o
CC fs/jbd2/checkpoint.o
CC lib/crypto/blake2s.o
AR fs/hugetlbfs/built-in.a
CC drivers/pci/setup-res.o
AR drivers/pnp/pnpacpi/built-in.a
CC net/core/dev.o
CC kernel/time/timekeeping.o
CC fs/netfs/iterator.o
AR drivers/clk/actions/built-in.a
CC lib/zstd/common/entropy_common.o
CC kernel/cgroup/namespace.o
AR drivers/clk/analogbits/built-in.a
CC drivers/acpi/acpica/dsobject.o
AR drivers/clk/bcm/built-in.a
AR drivers/clk/imgtec/built-in.a
CC lib/crypto/blake2s-generic.o
CC fs/ext4/dir.o
CC kernel/trace/trace_output.o
AR drivers/clk/imx/built-in.a
AR drivers/clk/ingenic/built-in.a
AR drivers/clk/mediatek/built-in.a
AR drivers/clk/microchip/built-in.a
AR drivers/clk/mstar/built-in.a
AR drivers/clk/mvebu/built-in.a
CC fs/proc/consoles.o
AR drivers/clk/ralink/built-in.a
CC kernel/time/ntp.o
AR drivers/clk/renesas/built-in.a
AR drivers/clk/socfpga/built-in.a
AR drivers/clk/sophgo/built-in.a
CC drivers/pnp/driver.o
AR drivers/clk/sprd/built-in.a
CC lib/zstd/common/error_private.o
CC kernel/time/clocksource.o
AR drivers/clk/starfive/built-in.a
AR drivers/clk/sunxi-ng/built-in.a
AR drivers/clk/ti/built-in.a
CC lib/zstd/common/fse_decompress.o
AR drivers/clk/versatile/built-in.a
CC lib/cmdline.o
AR drivers/clk/xilinx/built-in.a
AR drivers/clk/built-in.a
AR kernel/module/built-in.a
CC lib/cpumask.o
CC drivers/acpi/acpica/dsopcode.o
CC drivers/pnp/resource.o
CC drivers/pnp/manager.o
CC io_uring/splice.o
CC drivers/acpi/acpica/dspkginit.o
CC drivers/acpi/acpica/dsutils.o
CC sound/core/pcm_native.o
CC net/sched/cls_api.o
AR net/netlink/built-in.a
CC lib/crypto/sha1.o
CC drivers/dma/dw/core.o
AR drivers/soc/apple/built-in.a
AR drivers/soc/aspeed/built-in.a
AR drivers/soc/bcm/built-in.a
CC block/blk-mq-sched.o
AR drivers/soc/fsl/built-in.a
CC sound/core/pcm_lib.o
AR drivers/soc/fujitsu/built-in.a
CC kernel/events/ring_buffer.o
AR sound/parisc/built-in.a
CC drivers/pnp/support.o
AR drivers/soc/hisilicon/built-in.a
AR drivers/soc/imx/built-in.a
AR drivers/soc/ixp4xx/built-in.a
CC kernel/events/callchain.o
AR drivers/soc/loongson/built-in.a
AR drivers/soc/mediatek/built-in.a
AR drivers/soc/microchip/built-in.a
CC lib/crypto/sha256.o
AR drivers/soc/nuvoton/built-in.a
CC fs/fat/file.o
AR drivers/soc/pxa/built-in.a
AR drivers/soc/amlogic/built-in.a
AR drivers/soc/qcom/built-in.a
CC fs/proc/cpuinfo.o
AR drivers/soc/renesas/built-in.a
CC crypto/shash.o
CC lib/zstd/common/zstd_common.o
AR drivers/soc/rockchip/built-in.a
AR kernel/irq/built-in.a
AR drivers/soc/sunxi/built-in.a
CC drivers/acpi/dptf/int340x_thermal.o
AR drivers/soc/ti/built-in.a
CC drivers/pci/irq.o
AR drivers/soc/versatile/built-in.a
CC drivers/dma/dw/dw.o
CC drivers/acpi/x86/apple.o
AR drivers/soc/xilinx/built-in.a
CC block/ioctl.o
CC fs/jbd2/revoke.o
AR drivers/soc/built-in.a
CC drivers/dma/hsu/hsu.o
CC fs/jbd2/journal.o
AR lib/zstd/built-in.a
CC arch/x86/kernel/cpu/powerflags.o
CC kernel/trace/trace_seq.o
CC arch/x86/events/intel/uncore_discovery.o
CC drivers/acpi/acpica/dswexec.o
CC crypto/akcipher.o
AR drivers/dma/idxd/built-in.a
CC crypto/sig.o
CC fs/netfs/locking.o
CC net/core/dev_addr_lists.o
CC mm/shrinker.o
CC fs/ext4/ext4_jbd2.o
AR sound/pcmcia/vx/built-in.a
AR sound/pcmcia/pdaudiocf/built-in.a
AR sound/pcmcia/built-in.a
CC drivers/pci/vpd.o
CC arch/x86/kernel/signal.o
CC fs/proc/devices.o
CC net/ethtool/ioctl.o
AR drivers/acpi/dptf/built-in.a
CC kernel/cgroup/cgroup-v1.o
CC io_uring/sync.o
AR lib/crypto/built-in.a
CC lib/ctype.o
CC drivers/acpi/acpica/dswload.o
CC lib/dec_and_lock.o
CC drivers/acpi/x86/cmos_rtc.o
CC mm/shmem.o
CC drivers/pnp/interface.o
CC sound/core/pcm_misc.o
AR sound/mips/built-in.a
CC sound/core/pcm_memory.o
CC arch/x86/events/intel/cstate.o
CC lib/decompress.o
CC drivers/pci/setup-bus.o
CC kernel/time/jiffies.o
CC lib/decompress_bunzip2.o
CC drivers/dma/dw/idma32.o
CC drivers/pci/vc.o
CC drivers/virtio/virtio.o
AR drivers/dma/hsu/built-in.a
CC drivers/tty/vt/vt_ioctl.o
CC drivers/tty/hvc/hvc_console.o
CC kernel/time/timer_list.o
CC fs/fat/inode.o
CC drivers/char/hw_random/core.o
CC fs/fat/misc.o
CC drivers/pnp/quirks.o
CC drivers/acpi/acpica/dswload2.o
CC drivers/tty/serial/8250/8250_core.o
CC drivers/char/agp/backend.o
AR drivers/dma/amd/built-in.a
CC block/genhd.o
CC block/ioprio.o
CC crypto/kpp.o
CC fs/proc/interrupts.o
AR kernel/bpf/built-in.a
CC net/sched/act_api.o
CC fs/netfs/main.o
CC fs/ext4/extents.o
CC net/core/dst.o
CC drivers/acpi/x86/lpss.o
CC drivers/acpi/x86/s2idle.o
CC drivers/acpi/x86/utils.o
CC drivers/acpi/acpica/dswscope.o
CC kernel/events/hw_breakpoint.o
CC drivers/acpi/tables.o
CC io_uring/msg_ring.o
CC fs/fat/nfs.o
CC security/selinux/ss/services.o
CC drivers/acpi/x86/blacklist.o
CC fs/proc/loadavg.o
CC fs/proc/meminfo.o
CC fs/proc/stat.o
CC drivers/dma/dw/acpi.o
CC kernel/cgroup/freezer.o
CC mm/util.o
CC lib/decompress_inflate.o
AR arch/x86/events/intel/built-in.a
AR arch/x86/events/built-in.a
CC lib/decompress_unlz4.o
CC drivers/tty/serial/8250/8250_platform.o
CC drivers/acpi/acpica/dswstate.o
CC drivers/virtio/virtio_ring.o
CC kernel/time/timeconv.o
CC drivers/char/agp/generic.o
CC drivers/char/hw_random/intel-rng.o
CC drivers/pnp/system.o
AR drivers/iommu/amd/built-in.a
AR drivers/tty/hvc/built-in.a
AR drivers/iommu/intel/built-in.a
CC fs/isofs/namei.o
AR drivers/iommu/arm/arm-smmu/built-in.a
AR drivers/iommu/arm/arm-smmu-v3/built-in.a
ASN.1 crypto/rsapubkey.asn1.[ch]
AR drivers/iommu/arm/built-in.a
ASN.1 crypto/rsaprivkey.asn1.[ch]
CC crypto/rsa.o
CC net/netfilter/core.o
AR drivers/iommu/iommufd/built-in.a
AR drivers/iommu/riscv/built-in.a
CC net/netfilter/nf_log.o
CC drivers/iommu/iommu.o
CC net/ipv4/netfilter/nf_defrag_ipv4.o
CC net/ipv4/route.o
CC net/netfilter/nf_queue.o
CC fs/proc/uptime.o
CC drivers/tty/vt/vc_screen.o
CC sound/core/memalloc.o
CC net/ethtool/common.o
CC fs/nfs/client.o
CC kernel/time/timecounter.o
CC drivers/acpi/acpica/evevent.o
CC drivers/tty/serial/8250/8250_pnp.o
CC net/ipv4/inetpeer.o
CC kernel/time/alarmtimer.o
AR drivers/acpi/x86/built-in.a
CC drivers/tty/vt/selection.o
CC kernel/trace/trace_stat.o
CC lib/decompress_unlzma.o
CC drivers/virtio/virtio_anchor.o
AR drivers/dma/dw/built-in.a
AR drivers/dma/mediatek/built-in.a
CC block/badblocks.o
AR drivers/dma/qcom/built-in.a
CC security/selinux/ss/conditional.o
AR drivers/dma/stm32/built-in.a
AR drivers/pnp/built-in.a
AR drivers/dma/ti/built-in.a
CC kernel/cgroup/legacy_freezer.o
AR drivers/dma/xilinx/built-in.a
CC io_uring/advise.o
CC drivers/dma/dmaengine.o
CC io_uring/epoll.o
CC security/selinux/ss/mls.o
CC fs/fat/namei_vfat.o
CC drivers/char/hw_random/amd-rng.o
CC fs/ext4/extents_status.o
CC fs/isofs/inode.o
CC drivers/acpi/acpica/evgpe.o
CC drivers/acpi/acpica/evgpeblk.o
CC fs/nfs/dir.o
CC drivers/pci/mmap.o
CC kernel/trace/trace_printk.o
CC crypto/rsa_helper.o
AR fs/jbd2/built-in.a
CC kernel/events/uprobes.o
CC fs/proc/util.o
CC fs/exportfs/expfs.o
CC fs/fat/namei_msdos.o
CC drivers/char/agp/isoch.o
CC drivers/char/hw_random/geode-rng.o
CC drivers/tty/serial/8250/8250_rsa.o
CC fs/netfs/misc.o
CC crypto/rsa-pkcs1pad.o
CC sound/core/pcm_timer.o
CC drivers/tty/vt/keyboard.o
CC net/sched/sch_fifo.o
CC lib/decompress_unlzo.o
CC drivers/acpi/acpica/evgpeinit.o
CC kernel/cgroup/pids.o
CC kernel/panic.o
CC arch/x86/kernel/signal_32.o
CC mm/mmzone.o
CC net/ipv4/netfilter/nf_reject_ipv4.o
CC sound/core/seq_device.o
AR drivers/tty/ipwireless/built-in.a
CC net/ipv4/protocol.o
CC drivers/tty/serial/serial_core.o
CC io_uring/statx.o
CC net/ipv4/ip_input.o
CC fs/proc/version.o
CC block/blk-rq-qos.o
CC net/ethtool/netlink.o
CC kernel/time/posix-timers.o
CC drivers/pci/devres.o
CC drivers/char/agp/amd64-agp.o
CC net/sched/cls_cgroup.o
AR fs/exportfs/built-in.a
CC fs/ext4/file.o
CC net/netfilter/nf_sockopt.o
CC drivers/acpi/acpica/evgpeutil.o
CC kernel/trace/pid_list.o
CC drivers/virtio/virtio_pci_modern_dev.o
CC drivers/char/hw_random/via-rng.o
CC fs/nfs/file.o
CC drivers/tty/serial/8250/8250_port.o
CC drivers/dma/virt-dma.o
CC lib/decompress_unxz.o
CC lib/decompress_unzstd.o
CC kernel/time/posix-cpu-timers.o
CC drivers/tty/tty_io.o
CC kernel/cgroup/rdma.o
CC mm/vmstat.o
CC crypto/rsassa-pkcs1.o
AR sound/core/built-in.a
CC fs/ext4/fsmap.o
AR sound/soc/built-in.a
AR sound/atmel/built-in.a
CC sound/hda/hda_bus_type.o
CC net/core/netevent.o
CC fs/proc/softirqs.o
CC fs/isofs/dir.o
AR fs/fat/built-in.a
CC fs/proc/namespaces.o
CC arch/x86/kernel/cpu/topology.o
CC drivers/acpi/acpica/evglock.o
CC drivers/iommu/iommu-traces.o
CC net/core/neighbour.o
CC fs/netfs/objects.o
AR drivers/char/hw_random/built-in.a
CC kernel/trace/trace_sched_switch.o
CC block/disk-events.o
AR drivers/gpu/host1x/built-in.a
CC io_uring/timeout.o
AR drivers/gpu/vga/built-in.a
CC kernel/trace/trace_nop.o
CC fs/ext4/fsync.o
AR drivers/gpu/drm/tests/built-in.a
AR drivers/gpu/drm/arm/built-in.a
CC lib/dump_stack.o
CC drivers/pci/proc.o
AR drivers/gpu/drm/clients/built-in.a
CC drivers/char/agp/intel-agp.o
CC drivers/tty/serial/8250/8250_dma.o
CC drivers/gpu/drm/display/drm_display_helper_mod.o
CC security/selinux/ss/context.o
CC drivers/acpi/acpica/evhandler.o
CC drivers/dma/acpi-dma.o
CC drivers/virtio/virtio_pci_legacy_dev.o
CC drivers/tty/vt/vt.o
CC kernel/cgroup/cpuset.o
CC crypto/acompress.o
CC net/ipv4/netfilter/ip_tables.o
CC drivers/tty/serial/serial_base_bus.o
CC drivers/iommu/iommu-sysfs.o
CC sound/hda/hdac_bus.o
CC net/netfilter/utils.o
CC sound/hda/hdac_device.o
CC arch/x86/kernel/cpu/proc.o
CC kernel/trace/blktrace.o
CC net/sched/ematch.o
CC fs/isofs/util.o
CC drivers/gpu/drm/display/drm_dp_dual_mode_helper.o
CC net/ethtool/bitset.o
CC fs/proc/self.o
CC drivers/tty/serial/serial_ctrl.o
CC mm/backing-dev.o
CC drivers/char/mem.o
CC drivers/acpi/acpica/evmisc.o
CC drivers/connector/cn_queue.o
CC block/blk-ia-ranges.o
CC arch/x86/kernel/cpu/feat_ctl.o
CC kernel/time/posix-clock.o
CC lib/earlycpio.o
CC kernel/cpu.o
CC sound/hda/hdac_sysfs.o
CC lib/extable.o
CC fs/netfs/read_collect.o
CC drivers/virtio/virtio_pci_modern.o
CC drivers/char/agp/intel-gtt.o
CC arch/x86/kernel/traps.o
AR drivers/dma/built-in.a
CC drivers/iommu/dma-iommu.o
CC drivers/char/random.o
CC drivers/gpu/drm/ttm/ttm_tt.o
CC drivers/pci/pci-sysfs.o
CC io_uring/fdinfo.o
CC drivers/iommu/iova.o
CC block/early-lookup.o
CC fs/proc/thread_self.o
CC drivers/acpi/acpica/evregion.o
CC fs/isofs/rock.o
CC io_uring/cancel.o
CC drivers/gpu/drm/i915/i915_config.o
CC security/selinux/netlabel.o
CC drivers/virtio/virtio_pci_common.o
CC crypto/scompress.o
CC arch/x86/kernel/cpu/intel.o
CC fs/nfs/getroot.o
CC drivers/tty/serial/serial_port.o
CC lib/flex_proportions.o
AR kernel/events/built-in.a
CC drivers/gpu/drm/display/drm_dp_helper.o
CC drivers/pci/slot.o
CC net/ethtool/strset.o
CC drivers/gpu/drm/i915/i915_driver.o
AR sound/x86/built-in.a
CC drivers/acpi/acpica/evrgnini.o
CC drivers/connector/connector.o
CC drivers/acpi/osi.o
CC drivers/gpu/drm/i915/i915_drm_client.o
AR net/sched/built-in.a
CC drivers/tty/serial/8250/8250_dwlib.o
CC fs/isofs/export.o
CC arch/x86/kernel/cpu/tsx.o
CC kernel/time/itimer.o
AR sound/xen/built-in.a
CC crypto/algboss.o
CC fs/ext4/hash.o
CC net/netfilter/nfnetlink.o
CC drivers/gpu/drm/ttm/ttm_bo.o
CC fs/proc/proc_sysctl.o
CC lib/idr.o
CC sound/hda/hdac_regmap.o
CC net/ethtool/linkinfo.o
CC mm/mm_init.o
CC block/bounce.o
CC fs/netfs/read_pgpriv2.o
CC drivers/char/misc.o
CC drivers/acpi/acpica/evsci.o
CC drivers/acpi/osl.o
CC drivers/base/power/sysfs.o
CC net/ipv4/netfilter/iptable_filter.o
AR drivers/gpu/drm/renesas/rcar-du/built-in.a
AR drivers/char/agp/built-in.a
AR drivers/gpu/drm/renesas/rz-du/built-in.a
CC drivers/char/virtio_console.o
AR drivers/gpu/drm/renesas/built-in.a
CC drivers/char/hpet.o
CC drivers/gpu/drm/ttm/ttm_bo_util.o
CC net/ipv4/netfilter/iptable_mangle.o
CC kernel/exit.o
CC drivers/acpi/acpica/evxface.o
CC arch/x86/kernel/cpu/intel_epb.o
CC io_uring/waitid.o
CC drivers/gpu/drm/i915/i915_getparam.o
CC drivers/virtio/virtio_pci_legacy.o
CC kernel/trace/trace_events.o
CC net/ipv4/ip_fragment.o
CC drivers/tty/serial/earlycon.o
CC drivers/base/power/generic_ops.o
CC fs/isofs/joliet.o
CC lib/iomem_copy.o
CC drivers/pci/pci-acpi.o
CC drivers/block/loop.o
CC drivers/tty/serial/8250/8250_pcilib.o
CC fs/nfs/inode.o
CC lib/irq_regs.o
CC drivers/block/virtio_blk.o
CC drivers/gpu/drm/display/drm_dp_mst_topology.o
CC fs/ext4/ialloc.o
CC kernel/cgroup/misc.o
AR drivers/iommu/built-in.a
CC fs/ext4/indirect.o
AR security/selinux/built-in.a
AR security/built-in.a
CC drivers/gpu/drm/display/drm_dsc_helper.o
CC drivers/connector/cn_proc.o
CC fs/netfs/read_retry.o
CC arch/x86/kernel/cpu/amd.o
CC sound/hda/hdac_controller.o
CC net/netfilter/nfnetlink_log.o
CC crypto/testmgr.o
CC drivers/acpi/acpica/evxfevnt.o
CC kernel/time/clockevents.o
CC kernel/time/tick-common.o
CC lib/is_single_threaded.o
CC drivers/base/power/common.o
CC drivers/misc/eeprom/eeprom_93cx6.o
CC net/ethtool/linkmodes.o
CC net/core/rtnetlink.o
AR drivers/misc/cb710/built-in.a
CC sound/hda/hdac_stream.o
CC drivers/virtio/virtio_pci_admin_legacy_io.o
COPY drivers/tty/vt/defkeymap.c
CC drivers/tty/vt/consolemap.o
CC drivers/gpu/drm/ttm/ttm_bo_vm.o
AR drivers/mfd/built-in.a
CC drivers/pci/iomap.o
CC sound/hda/array.o
CC fs/isofs/compress.o
CC block/bsg.o
CC fs/netfs/write_collect.o
CC fs/netfs/write_issue.o
CC drivers/virtio/virtio_input.o
CC drivers/acpi/acpica/evxfgpe.o
CC drivers/tty/serial/8250/8250_early.o
CC crypto/cmac.o
CC io_uring/register.o
CC lib/klist.o
CC crypto/hmac.o
CC kernel/cgroup/debug.o
CC drivers/gpu/drm/i915/i915_ioctl.o
CC mm/percpu.o
CC drivers/base/power/qos.o
AR drivers/misc/eeprom/built-in.a
CC net/ipv4/netfilter/ipt_REJECT.o
AR drivers/misc/lis3lv02d/built-in.a
AR drivers/misc/cardreader/built-in.a
AR drivers/misc/keba/built-in.a
AR drivers/misc/built-in.a
CC block/blk-cgroup.o
AR drivers/gpu/drm/omapdrm/built-in.a
CC sound/hda/hdmi_chmap.o
CC sound/hda/trace.o
CC drivers/acpi/acpica/evxfregn.o
CC fs/proc/proc_net.o
CC fs/lockd/clntlock.o
CC lib/kobject.o
CC drivers/char/nvram.o
CC net/core/utils.o
CC arch/x86/kernel/idt.o
CC net/ethtool/rss.o
CC arch/x86/kernel/cpu/hygon.o
CC net/xfrm/xfrm_policy.o
CC drivers/acpi/acpica/exconcat.o
CC mm/slab_common.o
CC fs/proc/kcore.o
CC net/ipv4/ip_forward.o
CC drivers/pci/quirks.o
AR drivers/nfc/built-in.a
CC net/ipv4/ip_options.o
CC drivers/gpu/drm/ttm/ttm_module.o
CC fs/ext4/inline.o
AR drivers/connector/built-in.a
CC drivers/tty/serial/8250/8250_exar.o
AR drivers/gpu/drm/tilcdc/built-in.a
CC fs/lockd/clntproc.o
CC arch/x86/kernel/irq.o
CC kernel/time/tick-broadcast.o
CC drivers/base/power/runtime.o
AR fs/isofs/built-in.a
HOSTCC drivers/tty/vt/conmakehash
CC arch/x86/kernel/irq_32.o
CC crypto/crypto_null.o
CC block/blk-ioprio.o
CC drivers/virtio/virtio_dma_buf.o
CC drivers/gpu/drm/display/drm_hdcp_helper.o
AR drivers/block/built-in.a
CC drivers/gpu/drm/i915/i915_irq.o
AR kernel/cgroup/built-in.a
CC drivers/base/power/wakeirq.o
CC arch/x86/kernel/cpu/centaur.o
CC kernel/softirq.o
CC drivers/acpi/acpica/exconfig.o
CC drivers/tty/vt/defkeymap.o
CC net/netfilter/nf_conntrack_core.o
CC lib/kobject_uevent.o
CC net/ethtool/linkstate.o
CC net/core/link_watch.o
CONMK drivers/tty/vt/consolemap_deftbl.c
CC drivers/gpu/drm/ttm/ttm_execbuf_util.o
CC drivers/tty/vt/consolemap_deftbl.o
AR drivers/tty/vt/built-in.a
CC drivers/gpu/drm/ttm/ttm_range_manager.o
CC drivers/base/firmware_loader/builtin/main.o
CC [M] net/ipv4/netfilter/iptable_nat.o
CC fs/nfs/super.o
AR drivers/char/built-in.a
CC sound/hda/hdac_component.o
CC drivers/gpu/drm/ttm/ttm_resource.o
AR fs/netfs/built-in.a
CC net/unix/af_unix.o
CC net/core/filter.o
CC block/blk-iolatency.o
CC arch/x86/kernel/cpu/transmeta.o
CC drivers/acpi/acpica/exconvrt.o
CC crypto/md5.o
CC io_uring/truncate.o
CC fs/lockd/clntxdr.o
AR drivers/virtio/built-in.a
AR drivers/dax/hmem/built-in.a
AR drivers/dax/built-in.a
CC drivers/gpu/drm/display/drm_hdmi_helper.o
CC kernel/time/tick-broadcast-hrtimer.o
CC fs/proc/vmcore.o
CC kernel/trace/trace_export.o
CC net/unix/garbage.o
CC net/ipv4/ip_output.o
AR drivers/base/firmware_loader/builtin/built-in.a
CC drivers/base/firmware_loader/main.o
CC drivers/gpu/drm/virtio/virtgpu_drv.o
CC drivers/dma-buf/dma-buf.o
CC drivers/pci/pci-label.o
CC drivers/acpi/acpica/excreate.o
CC drivers/tty/serial/8250/8250_lpss.o
AR drivers/gpu/drm/imx/built-in.a
CC mm/compaction.o
CC net/core/sock_diag.o
CC arch/x86/kernel/dumpstack_32.o
CC drivers/base/power/main.o
CC drivers/base/power/wakeup.o
CC arch/x86/kernel/cpu/zhaoxin.o
CC kernel/time/tick-oneshot.o
AR sound/virtio/built-in.a
CC sound/hda/hdac_i915.o
CC drivers/base/regmap/regmap.o
CC kernel/time/tick-sched.o
CC kernel/time/timer_migration.o
CC crypto/sha256_generic.o
CC drivers/acpi/acpica/exdebug.o
CC net/unix/sysctl_net_unix.o
CC mm/show_mem.o
CC net/ethtool/debug.o
CC drivers/gpu/drm/i915/i915_mitigations.o
CC drivers/base/power/wakeup_stats.o
CC drivers/dma-buf/dma-fence.o
CC drivers/gpu/drm/ttm/ttm_pool.o
CC drivers/acpi/acpica/exdump.o
CC lib/logic_pio.o
CC net/xfrm/xfrm_state.o
CC fs/ext4/inode.o
CC drivers/pci/vgaarb.o
CC kernel/trace/trace_event_perf.o
CC arch/x86/kernel/cpu/vortex.o
CC io_uring/memmap.o
CC drivers/gpu/drm/virtio/virtgpu_kms.o
CC fs/lockd/host.o
CC fs/lockd/svc.o
AR net/ipv4/netfilter/built-in.a
CC fs/proc/kmsg.o
CC sound/hda/intel-dsp-config.o
CC net/ipv6/netfilter/ip6_tables.o
CC drivers/tty/serial/8250/8250_mid.o
CC drivers/gpu/drm/ttm/ttm_device.o
CC net/packet/af_packet.o
CC drivers/gpu/drm/virtio/virtgpu_gem.o
CC drivers/acpi/acpica/exfield.o
CC net/netfilter/nf_conntrack_standalone.o
AR drivers/base/firmware_loader/built-in.a
CC crypto/sha512_generic.o
CC net/core/dev_ioctl.o
CC drivers/gpu/drm/display/drm_scdc_helper.o
AR net/dsa/built-in.a
CC fs/nls/nls_base.o
CC arch/x86/kernel/cpu/perfctr-watchdog.o
CC block/blk-iocost.o
CC drivers/base/regmap/regcache.o
AR fs/unicode/built-in.a
CC fs/lockd/svclock.o
CC arch/x86/kernel/time.o
CC fs/nfs/io.o
CC drivers/acpi/utils.o
CC lib/maple_tree.o
CC fs/proc/page.o
CC drivers/gpu/drm/ttm/ttm_sys_manager.o
CC fs/ext4/ioctl.o
CC drivers/acpi/acpica/exfldio.o
CC kernel/resource.o
CC net/ethtool/wol.o
CC drivers/gpu/drm/i915/i915_module.o
CC io_uring/io-wq.o
CC net/xfrm/xfrm_hash.o
CC fs/nls/nls_cp437.o
CC sound/hda/intel-nhlt.o
CC fs/nls/nls_ascii.o
CC fs/nls/nls_iso8859-1.o
CC kernel/trace/trace_events_filter.o
CC drivers/gpu/drm/i915/i915_params.o
CC mm/interval_tree.o
CC fs/nfs/direct.o
CC drivers/tty/serial/8250/8250_pci.o
CC net/sunrpc/auth_gss/auth_gss.o
CC drivers/gpu/drm/virtio/virtgpu_vram.o
CC arch/x86/kernel/cpu/vmware.o
AR drivers/pci/built-in.a
CC drivers/dma-buf/dma-fence-array.o
CC drivers/gpu/drm/ttm/ttm_agp_backend.o
CC crypto/sha3_generic.o
CC arch/x86/kernel/cpu/hypervisor.o
AR drivers/gpu/drm/display/built-in.a
CC kernel/time/vsyscall.o
CC drivers/base/power/trace.o
CC net/ipv6/netfilter/ip6table_filter.o
CC drivers/acpi/acpica/exmisc.o
CC fs/ext4/mballoc.o
CC fs/nls/nls_utf8.o
CC drivers/gpu/drm/i915/i915_pci.o
CC net/sunrpc/clnt.o
CC net/ethtool/features.o
CC kernel/sysctl.o
CC drivers/tty/serial/8250/8250_pericom.o
CC net/core/tso.o
AR fs/proc/built-in.a
CC kernel/trace/trace_events_trigger.o
CC sound/hda/intel-sdw-acpi.o
AR net/wireless/tests/built-in.a
CC net/wireless/core.o
CC net/netfilter/nf_conntrack_expect.o
CC net/xfrm/xfrm_input.o
AR net/unix/built-in.a
CC block/mq-deadline.o
CC net/ipv4/ip_sockglue.o
CC kernel/time/timekeeping_debug.o
CC arch/x86/kernel/cpu/mshyperv.o
CC net/wireless/sysfs.o
CC crypto/ecb.o
AR fs/nls/built-in.a
CC drivers/gpu/drm/i915/i915_scatterlist.o
CC drivers/dma-buf/dma-fence-chain.o
CC drivers/acpi/acpica/exmutex.o
CC sound/sound_core.o
CC drivers/base/regmap/regcache-rbtree.o
CC fs/lockd/svcshare.o
CC net/xfrm/xfrm_output.o
CC block/kyber-iosched.o
AR drivers/gpu/drm/ttm/built-in.a
CC net/ipv6/af_inet6.o
CC drivers/gpu/drm/virtio/virtgpu_display.o
CC drivers/base/regmap/regcache-flat.o
CC drivers/tty/n_tty.o
AR drivers/base/power/built-in.a
CC net/netfilter/nf_conntrack_helper.o
CC block/blk-mq-pci.o
AR sound/hda/built-in.a
CC net/ethtool/privflags.o
CC net/ipv4/inet_hashtables.o
CC mm/list_lru.o
CC drivers/acpi/acpica/exnames.o
CC crypto/cbc.o
CC sound/last.o
CC kernel/trace/trace_eprobe.o
CC net/ipv6/anycast.o
CC io_uring/futex.o
CC kernel/time/namespace.o
CC drivers/dma-buf/dma-fence-unwrap.o
CC net/ipv6/netfilter/ip6table_mangle.o
CC drivers/gpu/drm/virtio/virtgpu_vq.o
AR drivers/tty/serial/8250/built-in.a
AR drivers/tty/serial/built-in.a
AR net/mac80211/tests/built-in.a
CC net/mac80211/main.o
CC net/wireless/radiotap.o
CC fs/ext4/migrate.o
CC drivers/gpu/drm/i915/i915_switcheroo.o
CC fs/autofs/init.o
CC drivers/acpi/acpica/exoparg1.o
CC drivers/base/regmap/regcache-maple.o
CC arch/x86/kernel/cpu/debugfs.o
AR sound/built-in.a
CC drivers/gpu/drm/virtio/virtgpu_fence.o
CC crypto/ctr.o
CC net/mac80211/status.o
CC fs/nfs/pagelist.o
CC fs/nfs/read.o
CC fs/nfs/symlink.o
CC mm/workingset.o
CC fs/lockd/svcproc.o
CC fs/lockd/svcsubs.o
CC fs/lockd/mon.o
CC drivers/dma-buf/dma-resv.o
AR drivers/gpu/drm/i2c/built-in.a
CC net/wireless/util.o
CC net/ethtool/rings.o
CC drivers/acpi/acpica/exoparg2.o
CC net/ipv6/netfilter/nf_defrag_ipv6_hooks.o
CC drivers/gpu/drm/i915/i915_sysfs.o
CC arch/x86/kernel/ioport.o
CC crypto/gcm.o
AR kernel/time/built-in.a
CC fs/9p/vfs_super.o
CC net/netfilter/nf_conntrack_proto.o
CC fs/autofs/inode.o
CC arch/x86/kernel/cpu/bus_lock.o
CC net/mac80211/driver-ops.o
CC drivers/base/regmap/regmap-debugfs.o
CC net/netlabel/netlabel_user.o
CC io_uring/napi.o
CC net/sunrpc/auth_gss/gss_generic_token.o
CC net/xfrm/xfrm_sysctl.o
CC block/blk-mq-virtio.o
CC drivers/tty/tty_ioctl.o
CC fs/9p/vfs_inode.o
AR net/packet/built-in.a
CC arch/x86/kernel/dumpstack.o
CC net/mac80211/sta_info.o
CC drivers/acpi/acpica/exoparg3.o
AR drivers/cxl/core/built-in.a
AR drivers/cxl/built-in.a
CC kernel/trace/trace_kprobe.o
CC drivers/dma-buf/sync_file.o
AR drivers/base/test/built-in.a
CC net/ipv4/inet_timewait_sock.o
AR drivers/gpu/drm/panel/built-in.a
CC lib/memcat_p.o
AR fs/hostfs/built-in.a
CC net/netfilter/nf_conntrack_proto_generic.o
CC fs/lockd/trace.o
CC mm/debug.o
CC drivers/gpu/drm/virtio/virtgpu_object.o
CC fs/9p/vfs_inode_dotl.o
CC block/blk-mq-debugfs.o
CC drivers/tty/tty_ldisc.o
CC drivers/tty/tty_buffer.o
CC drivers/gpu/drm/i915/i915_utils.o
CC drivers/acpi/acpica/exoparg6.o
CC net/ipv6/ip6_output.o
CC net/wireless/reg.o
CC fs/autofs/root.o
AR drivers/gpu/drm/bridge/analogix/built-in.a
AR drivers/gpu/drm/bridge/cadence/built-in.a
CC net/wireless/scan.o
CC fs/autofs/symlink.o
CC kernel/capability.o
AR drivers/gpu/drm/bridge/imx/built-in.a
AR drivers/base/regmap/built-in.a
CC drivers/base/component.o
CC net/ethtool/channels.o
AR drivers/gpu/drm/bridge/synopsys/built-in.a
CC fs/9p/vfs_addr.o
CC fs/lockd/xdr.o
AR drivers/gpu/drm/bridge/built-in.a
CC net/sunrpc/auth_gss/gss_mech_switch.o
CC arch/x86/kernel/cpu/capflags.o
CC net/sunrpc/xprt.o
CC crypto/ccm.o
AR arch/x86/kernel/cpu/built-in.a
CC net/ipv4/inet_connection_sock.o
AR drivers/dma-buf/built-in.a
CC arch/x86/kernel/nmi.o
CC net/wireless/nl80211.o
CC fs/autofs/waitq.o
CC net/netlabel/netlabel_kapi.o
CC drivers/acpi/acpica/exprep.o
CC net/ipv6/netfilter/nf_conntrack_reasm.o
CC net/xfrm/xfrm_replay.o
CC drivers/gpu/drm/virtio/virtgpu_debugfs.o
CC mm/gup.o
CC kernel/ptrace.o
CC block/blk-pm.o
CC net/mac80211/wep.o
CC fs/lockd/clnt4xdr.o
CC drivers/tty/tty_port.o
CC lib/nmi_backtrace.o
CC net/ipv4/tcp.o
CC net/core/sock_reuseport.o
CC net/netfilter/nf_conntrack_proto_tcp.o
CC drivers/gpu/drm/i915/intel_clock_gating.o
CC kernel/trace/error_report-traces.o
CC drivers/acpi/acpica/exregion.o
CC fs/nfs/unlink.o
CC kernel/user.o
AR io_uring/built-in.a
CC net/ipv4/tcp_input.o
CC drivers/macintosh/mac_hid.o
CC fs/lockd/xdr4.o
CC drivers/base/core.o
CC drivers/base/bus.o
CC fs/9p/vfs_file.o
CC lib/objpool.o
CC lib/plist.o
CC net/rfkill/core.o
CC crypto/aes_generic.o
CC fs/autofs/expire.o
CC drivers/acpi/acpica/exresnte.o
CC drivers/gpu/drm/virtio/virtgpu_plane.o
CC net/ethtool/coalesce.o
CC net/mac80211/aead_api.o
CC drivers/tty/tty_mutex.o
CC block/holder.o
CC arch/x86/kernel/ldt.o
CC net/wireless/mlme.o
CC net/sunrpc/auth_gss/svcauth_gss.o
CC crypto/crc32c_generic.o
AR drivers/macintosh/built-in.a
CC net/ipv6/ip6_input.o
CC mm/mmap_lock.o
CC kernel/trace/power-traces.o
CC net/ethtool/pause.o
CC drivers/base/dd.o
CC fs/nfs/write.o
CC drivers/acpi/acpica/exresolv.o
CC net/netlabel/netlabel_domainhash.o
CC fs/debugfs/inode.o
CC net/xfrm/xfrm_device.o
CC net/netfilter/nf_conntrack_proto_udp.o
CC net/ipv6/netfilter/nf_reject_ipv6.o
CC fs/9p/vfs_dir.o
CC drivers/base/syscore.o
CC fs/autofs/dev-ioctl.o
CC net/mac80211/wpa.o
CC net/xfrm/xfrm_nat_keepalive.o
CC drivers/tty/tty_ldsem.o
CC crypto/authenc.o
AR block/built-in.a
CC fs/ext4/mmp.o
CC drivers/gpu/drm/i915/intel_cpu_info.o
CC fs/debugfs/file.o
CC drivers/acpi/acpica/exresop.o
CC fs/nfs/namespace.o
CC drivers/gpu/drm/virtio/virtgpu_ioctl.o
CC drivers/gpu/drm/virtio/virtgpu_prime.o
AR drivers/scsi/pcmcia/built-in.a
CC drivers/gpu/drm/i915/intel_device_info.o
CC drivers/scsi/scsi.o
CC net/rfkill/input.o
CC fs/lockd/svc4proc.o
CC arch/x86/kernel/setup.o
CC lib/radix-tree.o
CC fs/9p/vfs_dentry.o
CC net/core/fib_notifier.o
CC fs/9p/v9fs.o
CC fs/lockd/procfs.o
CC drivers/acpi/acpica/exserial.o
CC arch/x86/kernel/x86_init.o
AR drivers/gpu/drm/hisilicon/built-in.a
CC net/ipv4/tcp_output.o
CC net/ethtool/eee.o
CC net/sunrpc/auth_gss/gss_rpc_upcall.o
CC drivers/tty/tty_baudrate.o
CC mm/highmem.o
AR net/rfkill/built-in.a
CC net/sunrpc/auth_gss/gss_rpc_xdr.o
CC mm/memory.o
AR fs/autofs/built-in.a
CC fs/ext4/move_extent.o
CC net/ipv4/tcp_timer.o
CC net/sunrpc/socklib.o
CC fs/9p/fid.o
CC net/core/xdp.o
CC net/9p/mod.o
CC drivers/acpi/reboot.o
CC drivers/acpi/acpica/exstore.o
CC net/xfrm/xfrm_algo.o
CC drivers/gpu/drm/virtio/virtgpu_trace_points.o
CC kernel/trace/rpm-traces.o
CC crypto/authencesn.o
CC net/netfilter/nf_conntrack_proto_icmp.o
CC net/netlabel/netlabel_addrlist.o
CC drivers/gpu/drm/virtio/virtgpu_submit.o
CC drivers/base/driver.o
CC drivers/tty/tty_jobctrl.o
CC net/core/flow_offload.o
CC arch/x86/kernel/i8259.o
CC fs/tracefs/inode.o
CC drivers/gpu/drm/i915/intel_memory_region.o
CC lib/ratelimit.o
CC net/ipv6/netfilter/ip6t_ipv6header.o
AR fs/debugfs/built-in.a
CC arch/x86/kernel/irqinit.o
CC net/mac80211/scan.o
CC lib/rbtree.o
CC net/9p/client.o
CC net/dns_resolver/dns_key.o
CC drivers/acpi/acpica/exstoren.o
CC net/netfilter/nf_conntrack_extend.o
CC drivers/scsi/hosts.o
AR fs/lockd/built-in.a
CC net/wireless/ibss.o
CC net/dns_resolver/dns_query.o
CC kernel/trace/trace_dynevent.o
CC fs/nfs/mount_clnt.o
AR drivers/nvme/common/built-in.a
CC net/ethtool/tsinfo.o
AR drivers/nvme/host/built-in.a
AR drivers/nvme/target/built-in.a
AR drivers/nvme/built-in.a
CC kernel/signal.o
CC fs/tracefs/event_inode.o
CC crypto/lzo.o
CC fs/9p/xattr.o
CC drivers/base/class.o
CC net/ipv6/netfilter/ip6t_REJECT.o
CC net/sunrpc/auth_gss/trace.o
CC lib/seq_buf.o
CC drivers/acpi/acpica/exstorob.o
CC lib/siphash.o
CC drivers/tty/n_null.o
CC fs/ext4/namei.o
CC [M] fs/efivarfs/inode.o
CC fs/ext4/page-io.o
CC net/xfrm/xfrm_user.o
CC net/wireless/sme.o
CC net/wireless/chan.o
AR drivers/gpu/drm/virtio/built-in.a
CC drivers/acpi/nvs.o
CC drivers/scsi/scsi_ioctl.o
CC net/netfilter/nf_conntrack_acct.o
CC lib/string.o
CC drivers/acpi/acpica/exsystem.o
CC drivers/gpu/drm/i915/intel_pcode.o
CC arch/x86/kernel/jump_label.o
CC net/netlabel/netlabel_mgmt.o
CC drivers/ata/libata-core.o
AR net/dns_resolver/built-in.a
CC net/ipv6/addrconf.o
CC crypto/lzo-rle.o
CC net/sunrpc/auth_gss/gss_krb5_mech.o
CC fs/open.o
AR drivers/net/phy/mediatek/built-in.a
CC net/9p/error.o
AR drivers/net/phy/qcom/built-in.a
CC drivers/net/phy/mdio-boardinfo.o
CC drivers/net/phy/stubs.o
CC drivers/base/platform.o
CC lib/timerqueue.o
AR drivers/gpu/drm/mxsfb/built-in.a
CC net/mac80211/offchannel.o
AR fs/9p/built-in.a
CC kernel/trace/trace_probe.o
CC kernel/sys.o
CC drivers/tty/pty.o
CC drivers/net/phy/mdio_devres.o
CC net/wireless/ethtool.o
CC net/core/gro.o
CC drivers/firewire/init_ohci1394_dma.o
CC [M] fs/efivarfs/file.o
CC drivers/acpi/acpica/extrace.o
AR drivers/net/pse-pd/built-in.a
CC lib/union_find.o
CC net/sunrpc/xprtsock.o
CC net/ethtool/cabletest.o
CC net/ipv4/tcp_ipv4.o
CC lib/vsprintf.o
AR fs/tracefs/built-in.a
CC drivers/base/cpu.o
CC net/sunrpc/auth_gss/gss_krb5_seal.o
CC fs/nfs/nfstrace.o
CC fs/ext4/readpage.o
CC drivers/acpi/acpica/exutils.o
CC net/mac80211/ht.o
CC crypto/rng.o
CC arch/x86/kernel/irq_work.o
AR net/ipv6/netfilter/built-in.a
CC net/mac80211/agg-tx.o
CC net/handshake/alert.o
CC net/handshake/genl.o
CC drivers/scsi/scsicam.o
CC [M] fs/efivarfs/super.o
CC net/9p/protocol.o
CC net/netfilter/nf_conntrack_seqadj.o
CC drivers/acpi/acpica/hwacpi.o
CC kernel/trace/trace_uprobe.o
CC kernel/umh.o
AR drivers/firewire/built-in.a
CC drivers/tty/tty_audit.o
CC kernel/trace/rethook.o
CC drivers/gpu/drm/i915/intel_region_ttm.o
CC drivers/net/phy/phy.o
CC net/ipv4/tcp_minisocks.o
CC net/devres.o
CC crypto/drbg.o
CC drivers/base/firmware.o
CC drivers/acpi/acpica/hwesleep.o
CC net/netlabel/netlabel_unlabeled.o
CC drivers/gpu/drm/i915/intel_runtime_pm.o
CC drivers/scsi/scsi_error.o
CC net/sunrpc/auth_gss/gss_krb5_unseal.o
CC net/ethtool/tunnels.o
CC drivers/net/mdio/acpi_mdio.o
CC net/sunrpc/sched.o
CC arch/x86/kernel/probe_roms.o
CC drivers/base/init.o
CC drivers/acpi/acpica/hwgpe.o
CC drivers/acpi/acpica/hwregs.o
CC [M] fs/efivarfs/vars.o
CC drivers/tty/sysrq.o
CC lib/win_minmax.o
CC net/sunrpc/auth.o
CC fs/nfs/export.o
CC net/9p/trans_common.o
CC crypto/jitterentropy.o
CC drivers/ata/libata-scsi.o
CC fs/read_write.o
CC net/socket.o
CC mm/mincore.o
CC net/core/netdev-genl.o
CC net/9p/trans_fd.o
CC net/handshake/netlink.o
CC drivers/gpu/drm/i915/intel_sbi.o
CC net/ipv4/tcp_cong.o
CC fs/ext4/resize.o
CC net/netfilter/nf_conntrack_proto_icmpv6.o
CC net/netlabel/netlabel_cipso_v4.o
CC drivers/net/mdio/fwnode_mdio.o
CC drivers/acpi/acpica/hwsleep.o
CC crypto/jitterentropy-kcapi.o
CC drivers/acpi/wakeup.o
AR net/xfrm/built-in.a
CC drivers/base/map.o
CC net/wireless/mesh.o
CC net/ethtool/fec.o
CC arch/x86/kernel/sys_ia32.o
CC net/sunrpc/auth_null.o
LD [M] fs/efivarfs/efivarfs.o
CC fs/file_table.o
CC net/sunrpc/auth_gss/gss_krb5_wrap.o
CC drivers/cdrom/cdrom.o
CC drivers/acpi/acpica/hwvalid.o
CC net/ipv4/tcp_metrics.o
AR drivers/auxdisplay/built-in.a
AR drivers/gpu/drm/tiny/built-in.a
CC drivers/net/phy/phy-c45.o
AR drivers/tty/built-in.a
CC crypto/ghash-generic.o
CC drivers/ata/libata-eh.o
CC net/handshake/request.o
CC fs/super.o
CC net/sunrpc/auth_tls.o
CC drivers/base/devres.o
CC drivers/acpi/sleep.o
CC net/ipv4/tcp_fastopen.o
CC drivers/base/attribute_container.o
CC drivers/net/phy/phy-core.o
CC mm/mlock.o
AR kernel/trace/built-in.a
CC kernel/workqueue.o
CC drivers/scsi/scsi_lib.o
AR drivers/net/pcs/built-in.a
CC net/sysctl_net.o
CC drivers/acpi/acpica/hwxface.o
CC drivers/gpu/drm/i915/intel_step.o
AR drivers/net/mdio/built-in.a
AR drivers/gpu/drm/xlnx/built-in.a
CC net/core/netdev-genl-gen.o
CC net/mac80211/agg-rx.o
CC lib/xarray.o
CC crypto/hash_info.o
CC drivers/pcmcia/cs.o
CC arch/x86/kernel/ksysfs.o
CC drivers/pcmcia/socket_sysfs.o
CC crypto/rsapubkey.asn1.o
CC net/mac80211/vht.o
CC crypto/rsaprivkey.asn1.o
AR crypto/built-in.a
CC net/9p/trans_virtio.o
CC drivers/acpi/acpica/hwxfsleep.o
CC net/mac80211/he.o
CC drivers/pcmcia/cardbus.o
CC net/netlabel/netlabel_calipso.o
CC net/netfilter/nf_conntrack_netlink.o
CC net/ethtool/eeprom.o
CC net/netfilter/nf_conntrack_ftp.o
CC net/ipv6/addrlabel.o
CC drivers/pcmcia/ds.o
CC net/sunrpc/auth_gss/gss_krb5_crypto.o
CC drivers/ata/libata-transport.o
CC drivers/base/transport_class.o
CC net/wireless/ap.o
CC net/ethtool/stats.o
CC drivers/usb/common/common.o
CC drivers/acpi/acpica/hwpci.o
CC drivers/usb/core/usb.o
CC arch/x86/kernel/bootflag.o
CC drivers/usb/core/hub.o
CC net/core/gso.o
CC fs/ext4/super.o
CC net/sunrpc/auth_gss/gss_krb5_keys.o
CC mm/mmap.o
CC drivers/base/topology.o
CC drivers/gpu/drm/i915/intel_uncore.o
CC net/wireless/trace.o
CC drivers/input/serio/serio.o
CC drivers/scsi/constants.o
CC drivers/net/phy/phy_device.o
CC net/handshake/tlshd.o
CC drivers/input/serio/i8042.o
CC drivers/input/keyboard/atkbd.o
CC net/handshake/trace.o
CC drivers/acpi/acpica/nsaccess.o
CC net/ethtool/phc_vclocks.o
CC arch/x86/kernel/e820.o
CC net/netfilter/nf_conntrack_irc.o
AR drivers/usb/phy/built-in.a
CC net/ipv4/tcp_rate.o
CC net/wireless/ocb.o
CC drivers/usb/common/debug.o
AR drivers/cdrom/built-in.a
CC drivers/gpu/drm/i915/intel_uncore_trace.o
CC mm/mmu_gather.o
CC drivers/pcmcia/pcmcia_resource.o
AR net/netlabel/built-in.a
CC drivers/base/container.o
CC net/wireless/pmsr.o
AR drivers/usb/common/built-in.a
CC lib/lockref.o
CC drivers/rtc/lib.o
GEN net/wireless/shipped-certs.c
CC fs/char_dev.o
CC mm/mprotect.o
CC drivers/acpi/acpica/nsalloc.o
CC fs/nfs/sysfs.o
AR net/9p/built-in.a
CC drivers/net/phy/linkmode.o
CC lib/bcd.o
AR drivers/gpu/drm/gud/built-in.a
CC net/ipv6/route.o
CC drivers/pcmcia/cistpl.o
CC drivers/acpi/device_sysfs.o
CC fs/ext4/symlink.o
CC net/sunrpc/auth_unix.o
CC kernel/pid.o
CC drivers/gpu/drm/i915/intel_wakeref.o
CC lib/sort.o
CC drivers/scsi/scsi_lib_dma.o
CC drivers/input/serio/serport.o
CC drivers/acpi/device_pm.o
CC drivers/base/property.o
CC lib/parser.o
CC drivers/base/cacheinfo.o
CC drivers/acpi/acpica/nsarguments.o
CC net/core/net-sysfs.o
CC net/ethtool/mm.o
CC drivers/rtc/class.o
AR drivers/input/keyboard/built-in.a
CC drivers/input/mouse/psmouse-base.o
AR drivers/input/joystick/built-in.a
CC drivers/i2c/algos/i2c-algo-bit.o
AR drivers/i3c/built-in.a
CC arch/x86/kernel/pci-dma.o
AR net/sunrpc/auth_gss/built-in.a
CC fs/ext4/sysfs.o
CC drivers/input/serio/libps2.o
CC lib/debug_locks.o
CC drivers/ata/libata-trace.o
CC drivers/acpi/proc.o
CC drivers/rtc/interface.o
CC net/core/hotdata.o
CC arch/x86/kernel/quirks.o
CC drivers/acpi/acpica/nsconvert.o
CC arch/x86/kernel/kdebugfs.o
AR drivers/media/i2c/built-in.a
CC net/ipv4/tcp_recovery.o
CC arch/x86/kernel/alternative.o
AR drivers/media/tuners/built-in.a
CC drivers/scsi/scsi_scan.o
AR drivers/media/rc/keymaps/built-in.a
AR drivers/media/rc/built-in.a
CC mm/mremap.o
CC lib/random32.o
CC drivers/net/phy/phy_link_topology.o
AR drivers/media/common/b2c2/built-in.a
AR drivers/media/common/saa7146/built-in.a
AR drivers/media/common/siano/built-in.a
AR drivers/media/common/v4l2-tpg/built-in.a
CC net/mac80211/s1g.o
CC drivers/usb/core/hcd.o
AR drivers/media/common/videobuf2/built-in.a
AR drivers/media/common/built-in.a
AR net/handshake/built-in.a
CC drivers/usb/mon/mon_main.o
AR drivers/media/platform/allegro-dvt/built-in.a
AR drivers/media/platform/amlogic/meson-ge2d/built-in.a
AR drivers/media/platform/amlogic/built-in.a
AR drivers/media/platform/amphion/built-in.a
AR drivers/media/platform/aspeed/built-in.a
AR drivers/media/platform/atmel/built-in.a
AR drivers/media/platform/broadcom/built-in.a
AR drivers/media/platform/cadence/built-in.a
CC fs/stat.o
CC net/netfilter/nf_conntrack_sip.o
CC kernel/task_work.o
AR drivers/media/platform/chips-media/coda/built-in.a
AR drivers/media/platform/chips-media/wave5/built-in.a
AR drivers/media/platform/chips-media/built-in.a
CC fs/nfs/fs_context.o
CC net/core/netdev_rx_queue.o
AR drivers/media/platform/imagination/built-in.a
AR drivers/media/platform/intel/built-in.a
AR drivers/media/platform/marvell/built-in.a
AR drivers/input/tablet/built-in.a
AR drivers/media/platform/mediatek/jpeg/built-in.a
AR drivers/media/platform/microchip/built-in.a
CC drivers/acpi/acpica/nsdump.o
CC net/sunrpc/svc.o
AR drivers/media/platform/mediatek/mdp/built-in.a
CC drivers/usb/mon/mon_stat.o
AR drivers/media/platform/mediatek/vcodec/common/built-in.a
AR drivers/media/platform/mediatek/vcodec/encoder/built-in.a
CC lib/bust_spinlocks.o
CC mm/msync.o
AR drivers/media/platform/mediatek/vcodec/decoder/built-in.a
AR drivers/media/platform/mediatek/vcodec/built-in.a
AR drivers/media/platform/mediatek/vpu/built-in.a
AR drivers/media/platform/mediatek/mdp3/built-in.a
AR drivers/media/platform/mediatek/built-in.a
CC net/ethtool/module.o
CC mm/page_vma_mapped.o
AR drivers/media/platform/nuvoton/built-in.a
AR drivers/media/platform/nvidia/tegra-vde/built-in.a
AR drivers/media/platform/nvidia/built-in.a
CC mm/pagewalk.o
AR drivers/media/platform/nxp/dw100/built-in.a
AR drivers/media/platform/nxp/imx-jpeg/built-in.a
AR drivers/media/platform/nxp/imx8-isi/built-in.a
AR drivers/media/platform/qcom/camss/built-in.a
AR drivers/media/platform/qcom/venus/built-in.a
AR drivers/media/platform/nxp/built-in.a
AR drivers/media/platform/qcom/built-in.a
AR drivers/media/platform/raspberrypi/pisp_be/built-in.a
AR drivers/gpu/drm/solomon/built-in.a
CC mm/pgtable-generic.o
CC [M] drivers/gpu/drm/scheduler/sched_main.o
AR drivers/media/platform/raspberrypi/rp1-cfe/built-in.a
AR drivers/media/platform/raspberrypi/built-in.a
CC drivers/acpi/acpica/nseval.o
CC drivers/pcmcia/pcmcia_cis.o
HOSTCC drivers/gpu/drm/xe/xe_gen_wa_oob
AR drivers/media/platform/renesas/rcar-vin/built-in.a
AR drivers/input/serio/built-in.a
AR drivers/i2c/algos/built-in.a
CC drivers/pcmcia/rsrc_mgr.o
AR drivers/media/platform/renesas/rzg2l-cru/built-in.a
CC drivers/i2c/busses/i2c-i801.o
AR drivers/media/platform/renesas/vsp1/built-in.a
AR drivers/i2c/muxes/built-in.a
AR drivers/media/platform/renesas/built-in.a
CC drivers/acpi/acpica/nsinit.o
CC mm/rmap.o
CC drivers/acpi/acpica/nsload.o
AR drivers/media/platform/rockchip/rga/built-in.a
CC net/ipv6/ip6_fib.o
CC drivers/base/swnode.o
AR drivers/media/platform/rockchip/rkisp1/built-in.a
AR drivers/media/platform/rockchip/built-in.a
AR drivers/media/platform/samsung/exynos-gsc/built-in.a
AR drivers/media/platform/samsung/exynos4-is/built-in.a
GEN xe_wa_oob.c xe_wa_oob.h
AR drivers/media/platform/samsung/s3c-camif/built-in.a
CC [M] drivers/gpu/drm/xe/xe_bb.o
AR drivers/media/platform/samsung/s5p-g2d/built-in.a
AR drivers/media/platform/samsung/s5p-jpeg/built-in.a
GEN drivers/scsi/scsi_devinfo_tbl.c
CC kernel/extable.o
AR drivers/media/platform/samsung/s5p-mfc/built-in.a
AR drivers/media/platform/samsung/built-in.a
CC drivers/input/mouse/synaptics.o
CC fs/nfs/nfsroot.o
AR drivers/media/platform/st/sti/bdisp/built-in.a
AR drivers/media/platform/st/sti/c8sectpfe/built-in.a
AR drivers/media/platform/st/sti/delta/built-in.a
AR drivers/media/platform/st/sti/hva/built-in.a
CC arch/x86/kernel/i8253.o
AR drivers/media/platform/st/stm32/built-in.a
AR drivers/media/platform/st/built-in.a
CC drivers/gpu/drm/i915/vlv_sideband.o
CC drivers/usb/mon/mon_text.o
AR drivers/media/platform/sunxi/sun4i-csi/built-in.a
CC net/sunrpc/svcsock.o
CC drivers/ata/libata-sata.o
AR drivers/media/platform/sunxi/sun6i-csi/built-in.a
CC drivers/net/phy/mdio_bus.o
AR drivers/media/platform/sunxi/sun6i-mipi-csi2/built-in.a
AR drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/built-in.a
AR drivers/media/platform/sunxi/sun8i-di/built-in.a
AR drivers/media/platform/sunxi/sun8i-rotate/built-in.a
CC drivers/gpu/drm/i915/vlv_suspend.o
AR drivers/media/platform/sunxi/built-in.a
CC lib/kasprintf.o
AR drivers/media/platform/ti/am437x/built-in.a
CC drivers/gpu/drm/i915/soc/intel_dram.o
AR drivers/media/platform/ti/cal/built-in.a
AR drivers/media/platform/ti/vpe/built-in.a
AR drivers/media/platform/ti/davinci/built-in.a
AR drivers/media/platform/ti/j721e-csi2rx/built-in.a
CC arch/x86/kernel/hw_breakpoint.o
AR drivers/media/platform/ti/omap/built-in.a
CC drivers/acpi/acpica/nsnames.o
AR drivers/media/platform/ti/omap3isp/built-in.a
AR drivers/media/platform/ti/built-in.a
AR drivers/media/platform/verisilicon/built-in.a
AR drivers/media/platform/via/built-in.a
AR drivers/input/touchscreen/built-in.a
AR drivers/media/platform/xilinx/built-in.a
CC net/netfilter/nf_nat_core.o
AR drivers/media/platform/built-in.a
CC net/netfilter/nf_nat_proto.o
CC net/sunrpc/svcauth.o
AR drivers/media/pci/ttpci/built-in.a
AR drivers/media/pci/b2c2/built-in.a
CC drivers/scsi/scsi_devinfo.o
AR drivers/media/pci/pluto2/built-in.a
CC drivers/input/mouse/focaltech.o
AR drivers/media/pci/dm1105/built-in.a
AR drivers/media/pci/pt1/built-in.a
CC net/ipv4/tcp_ulp.o
CC net/ipv6/ipv6_sockglue.o
CC [M] drivers/gpu/drm/xe/xe_bo.o
AR drivers/media/pci/pt3/built-in.a
AR drivers/media/pci/mantis/built-in.a
AR drivers/media/pci/ngene/built-in.a
AR drivers/media/pci/ddbridge/built-in.a
AR drivers/media/pci/saa7146/built-in.a
CC net/ipv6/ndisc.o
CC [M] drivers/gpu/drm/xe/xe_bo_evict.o
AR drivers/media/pci/smipcie/built-in.a
CC drivers/rtc/nvmem.o
AR drivers/media/pci/netup_unidvb/built-in.a
CC lib/bitmap.o
AR drivers/media/pci/intel/ipu3/built-in.a
CC [M] drivers/gpu/drm/xe/xe_devcoredump.o
AR drivers/media/pci/intel/ivsc/built-in.a
AR drivers/media/pci/intel/built-in.a
AR drivers/media/pci/built-in.a
AR drivers/media/usb/b2c2/built-in.a
AR drivers/media/usb/dvb-usb/built-in.a
AR drivers/net/ethernet/3com/built-in.a
AR drivers/media/usb/dvb-usb-v2/built-in.a
CC drivers/net/ethernet/8390/ne2k-pci.o
AR drivers/media/usb/s2255/built-in.a
AR drivers/media/usb/siano/built-in.a
CC drivers/ata/libata-sff.o
AR drivers/media/usb/ttusb-budget/built-in.a
AR drivers/media/usb/ttusb-dec/built-in.a
AR drivers/media/usb/built-in.a
CC net/core/net-procfs.o
CC drivers/acpi/acpica/nsobject.o
AR drivers/media/mmc/siano/built-in.a
AR drivers/media/mmc/built-in.a
CC drivers/pcmcia/rsrc_nonstatic.o
AR drivers/media/firewire/built-in.a
CC drivers/usb/core/urb.o
AR drivers/media/spi/built-in.a
AR drivers/media/test-drivers/built-in.a
CC net/ethtool/cmis_fw_update.o
AR drivers/media/built-in.a
CC drivers/base/auxiliary.o
CC drivers/net/ethernet/8390/8390.o
CC drivers/acpi/bus.o
AR drivers/input/misc/built-in.a
CC drivers/usb/host/pci-quirks.o
CC kernel/params.o
CC drivers/usb/mon/mon_bin.o
AR drivers/i2c/busses/built-in.a
CC drivers/i2c/i2c-boardinfo.o
CC drivers/rtc/dev.o
CC kernel/kthread.o
CC net/core/netpoll.o
CC mm/vmalloc.o
CC drivers/acpi/acpica/nsparse.o
CC [M] drivers/gpu/drm/scheduler/sched_fence.o
CC arch/x86/kernel/tsc.o
CC drivers/scsi/scsi_sysctl.o
CC drivers/base/devtmpfs.o
CC net/netfilter/nf_nat_helper.o
CC drivers/input/mouse/alps.o
CC lib/scatterlist.o
CC net/mac80211/ibss.o
CC net/ipv4/tcp_offload.o
CC drivers/gpu/drm/i915/soc/intel_gmch.o
CC drivers/net/phy/mdio_device.o
CC drivers/input/input.o
CC drivers/usb/class/usblp.o
CC [M] drivers/gpu/drm/scheduler/sched_entity.o
CC drivers/acpi/acpica/nspredef.o
CC net/ipv6/udp.o
CC drivers/pcmcia/yenta_socket.o
CC drivers/usb/core/message.o
CC mm/vma.o
CC drivers/rtc/proc.o
CC lib/list_sort.o
CC fs/nfs/sysctl.o
CC drivers/input/mouse/byd.o
CC drivers/i2c/i2c-core-base.o
CC drivers/scsi/scsi_proc.o
CC drivers/ata/libata-pmp.o
AR drivers/pps/clients/built-in.a
CC drivers/usb/host/ehci-hcd.o
CC net/wireless/shipped-certs.o
CC net/ethtool/cmis_cdb.o
AR drivers/pps/generators/built-in.a
CC drivers/pps/pps.o
CC drivers/usb/host/ehci-pci.o
CC fs/exec.o
AR drivers/net/wireless/admtek/built-in.a
AR drivers/net/wireless/ath/built-in.a
AR drivers/net/wireless/atmel/built-in.a
AR drivers/net/wireless/broadcom/built-in.a
CC drivers/acpi/acpica/nsprepkg.o
AR drivers/net/ethernet/8390/built-in.a
CC drivers/usb/host/ohci-hcd.o
AR drivers/net/wireless/intel/built-in.a
AR drivers/net/wireless/intersil/built-in.a
AR drivers/net/ethernet/adaptec/built-in.a
CC drivers/ptp/ptp_clock.o
CC drivers/power/supply/power_supply_core.o
AR drivers/net/wireless/marvell/built-in.a
AR drivers/net/ethernet/agere/built-in.a
AR drivers/usb/mon/built-in.a
AR drivers/net/wireless/mediatek/built-in.a
AR drivers/net/ethernet/alacritech/built-in.a
CC drivers/gpu/drm/i915/soc/intel_pch.o
AR drivers/net/wireless/microchip/built-in.a
AR drivers/net/ethernet/alteon/built-in.a
AR drivers/net/wireless/purelifi/built-in.a
AR drivers/net/ethernet/amazon/built-in.a
AR drivers/net/wireless/quantenna/built-in.a
AR drivers/net/ethernet/amd/built-in.a
AR drivers/net/ethernet/aquantia/built-in.a
AR drivers/net/wireless/ralink/built-in.a
AR drivers/net/wireless/realtek/built-in.a
AR drivers/net/ethernet/arc/built-in.a
AR drivers/net/wireless/rsi/built-in.a
AR drivers/net/ethernet/asix/built-in.a
AR drivers/net/wireless/silabs/built-in.a
AR drivers/net/ethernet/atheros/built-in.a
AR drivers/net/wireless/st/built-in.a
AR drivers/net/ethernet/cadence/built-in.a
AR drivers/net/wireless/ti/built-in.a
CC drivers/net/ethernet/broadcom/bnx2.o
AR drivers/net/wireless/zydas/built-in.a
CC drivers/base/module.o
AR drivers/net/wireless/virtual/built-in.a
AR drivers/net/wireless/built-in.a
CC drivers/net/phy/swphy.o
CC drivers/rtc/sysfs.o
LD [M] drivers/gpu/drm/scheduler/gpu-sched.o
CC drivers/net/phy/fixed_phy.o
CC drivers/acpi/glue.o
CC drivers/acpi/acpica/nsrepair.o
CC arch/x86/kernel/tsc_msr.o
AR drivers/usb/class/built-in.a
CC net/netfilter/nf_nat_masquerade.o
CC [M] drivers/gpu/drm/xe/xe_device.o
CC drivers/usb/host/ohci-pci.o
CC drivers/ata/libata-acpi.o
CC drivers/gpu/drm/drm_atomic.o
CC kernel/sys_ni.o
CC drivers/usb/storage/scsiglue.o
CC drivers/pps/kapi.o
CC drivers/usb/storage/protocol.o
CC lib/uuid.o
CC drivers/base/auxiliary_sysfs.o
CC drivers/net/ethernet/broadcom/tg3.o
CC net/ethtool/pse-pd.o
CC drivers/scsi/scsi_debugfs.o
CC drivers/net/phy/realtek.o
CC drivers/input/input-compat.o
CC lib/iov_iter.o
CC net/core/fib_rules.o
CC drivers/acpi/acpica/nsrepair2.o
CC mm/process_vm_access.o
CC kernel/nsproxy.o
CC arch/x86/kernel/io_delay.o
CC fs/nfs/nfs3super.o
CC drivers/power/supply/power_supply_sysfs.o
CC net/ipv4/tcp_plb.o
CC drivers/input/mouse/logips2pp.o
CC net/sunrpc/svcauth_unix.o
CC drivers/rtc/rtc-mc146818-lib.o
CC arch/x86/kernel/rtc.o
AR drivers/pcmcia/built-in.a
CC drivers/power/supply/power_supply_leds.o
CC drivers/input/mouse/lifebook.o
CC kernel/notifier.o
CC drivers/base/devcoredump.o
CC drivers/usb/host/uhci-hcd.o
CC drivers/ptp/ptp_chardev.o
CC drivers/pps/sysfs.o
CC drivers/acpi/acpica/nssearch.o
CC fs/pipe.o
CC drivers/usb/core/driver.o
CC drivers/gpu/drm/i915/soc/intel_rom.o
CC drivers/hwmon/hwmon.o
CC drivers/i2c/i2c-core-smbus.o
CC drivers/gpu/drm/drm_atomic_uapi.o
CC mm/page_alloc.o
CC net/ipv4/datagram.o
CC drivers/base/platform-msi.o
CC drivers/scsi/scsi_trace.o
AR drivers/net/ethernet/brocade/built-in.a
CC drivers/usb/core/config.o
CC drivers/gpu/drm/i915/i915_memcpy.o
CC drivers/usb/storage/transport.o
CC drivers/power/supply/power_supply_hwmon.o
CC drivers/acpi/acpica/nsutils.o
AR drivers/pps/built-in.a
CC drivers/rtc/rtc-cmos.o
CC net/core/net-traces.o
CC net/ethtool/plca.o
CC drivers/ata/libata-pata-timings.o
CC kernel/ksysfs.o
CC fs/namei.o
CC arch/x86/kernel/resource.o
CC drivers/input/mouse/trackpoint.o
CC net/sunrpc/addr.o
CC drivers/input/input-mt.o
CC [M] drivers/gpu/drm/xe/xe_device_sysfs.o
CC drivers/base/physical_location.o
CC drivers/scsi/scsi_logging.o
CC drivers/gpu/drm/i915/i915_mm.o
CC drivers/usb/core/file.o
CC net/netfilter/nf_nat_ftp.o
AS arch/x86/kernel/irqflags.o
CC arch/x86/kernel/static_call.o
AR drivers/net/phy/built-in.a
CC arch/x86/kernel/process.o
CC net/ipv6/udplite.o
CC fs/nfs/nfs3client.o
CC drivers/base/trace.o
CC drivers/acpi/acpica/nswalk.o
AR drivers/power/supply/built-in.a
AR drivers/power/built-in.a
CC drivers/input/input-poller.o
CC drivers/ptp/ptp_sysfs.o
CC net/ipv4/raw.o
CC net/ipv4/udp.o
CC drivers/acpi/scan.o
CC drivers/usb/core/buffer.o
CC net/ethtool/phy.o
CC net/mac80211/iface.o
CC net/sunrpc/rpcb_clnt.o
CC net/ipv4/udplite.o
CC kernel/cred.o
AR drivers/usb/misc/built-in.a
CC drivers/usb/early/ehci-dbgp.o
AR drivers/net/ethernet/cavium/common/built-in.a
AR drivers/net/ethernet/cavium/thunder/built-in.a
CC drivers/ata/ahci.o
CC drivers/acpi/acpica/nsxfeval.o
CC arch/x86/kernel/ptrace.o
AR drivers/net/ethernet/cavium/liquidio/built-in.a
AR drivers/net/ethernet/cavium/octeon/built-in.a
CC drivers/input/mouse/cypress_ps2.o
AR drivers/net/ethernet/cavium/built-in.a
CC drivers/usb/storage/usb.o
CC drivers/gpu/drm/i915/i915_sw_fence.o
AR drivers/net/ethernet/chelsio/built-in.a
CC drivers/input/ff-core.o
AR drivers/net/usb/built-in.a
CC drivers/ptp/ptp_vclock.o
CC drivers/ata/libahci.o
CC net/core/selftests.o
AR drivers/thermal/broadcom/built-in.a
CC drivers/scsi/scsi_pm.o
AR drivers/thermal/renesas/built-in.a
AR drivers/thermal/samsung/built-in.a
CC drivers/thermal/intel/intel_tcc.o
AR drivers/rtc/built-in.a
AR drivers/hwmon/built-in.a
CC drivers/net/mii.o
CC drivers/net/loopback.o
CC [M] drivers/gpu/drm/xe/xe_dma_buf.o
CC drivers/ptp/ptp_kvm_x86.o
CC drivers/input/mouse/psmouse-smbus.o
CC drivers/usb/core/sysfs.o
CC drivers/i2c/i2c-core-acpi.o
CC drivers/acpi/mipi-disco-img.o
CC mm/page_frag_cache.o
CC fs/ext4/xattr.o
AR drivers/base/built-in.a
CC drivers/ata/ata_piix.o
CC lib/clz_ctz.o
CC drivers/thermal/intel/therm_throt.o
CC drivers/acpi/acpica/nsxfname.o
CC drivers/usb/host/xhci.o
CC net/core/ptp_classifier.o
CC kernel/reboot.o
CC lib/bsearch.o
CC net/ipv6/raw.o
CC fs/nfs/nfs3proc.o
CC net/netfilter/nf_nat_irc.o
CC drivers/gpu/drm/i915/i915_sw_fence_work.o
CC drivers/gpu/drm/drm_auth.o
CC net/ipv4/udp_offload.o
CC drivers/scsi/scsi_bsg.o
AR drivers/thermal/st/built-in.a
CC drivers/net/netconsole.o
AR drivers/thermal/qcom/built-in.a
AR net/ethtool/built-in.a
AR drivers/usb/early/built-in.a
CC drivers/input/touchscreen.o
CC drivers/acpi/acpica/nsxfobj.o
CC net/ipv4/arp.o
CC fs/nfs/nfs3xdr.o
CC net/ipv6/icmp.o
CC drivers/ptp/ptp_kvm_common.o
CC net/mac80211/link.o
CC fs/nfs/nfs3acl.o
CC arch/x86/kernel/tls.o
CC drivers/gpu/drm/i915/i915_syncmap.o
AR drivers/input/mouse/built-in.a
AR drivers/net/ethernet/cisco/built-in.a
CC [M] drivers/gpu/drm/xe/xe_drm_client.o
CC drivers/usb/storage/initializers.o
CC net/ipv6/mcast.o
CC lib/find_bit.o
CC drivers/gpu/drm/drm_blend.o
CC kernel/async.o
CC arch/x86/kernel/step.o
CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.o
CC drivers/i2c/i2c-smbus.o
CC drivers/usb/core/endpoint.o
CC arch/x86/kernel/i8237.o
CC arch/x86/kernel/stacktrace.o
CC drivers/acpi/acpica/psargs.o
CC fs/fcntl.o
CC lib/llist.o
CC drivers/usb/host/xhci-mem.o
CC net/sunrpc/timer.o
CC fs/ext4/xattr_hurd.o
CC drivers/input/ff-memless.o
CC drivers/gpu/drm/i915/i915_user_extensions.o
CC kernel/range.o
CC lib/lwq.o
CC [M] drivers/gpu/drm/xe/xe_guc_engine_activity.o
CC drivers/scsi/scsi_common.o
CC mm/init-mm.o
CC drivers/acpi/resource.o
AR drivers/ptp/built-in.a
AR drivers/net/ethernet/cortina/built-in.a
CC drivers/acpi/acpi_processor.o
CC kernel/smpboot.o
CC drivers/scsi/scsi_transport_spi.o
CC net/netfilter/nf_nat_sip.o
CC lib/memweight.o
CC fs/ext4/xattr_trusted.o
CC drivers/usb/storage/sierra_ms.o
CC drivers/ata/pata_amd.o
CC drivers/acpi/acpica/psloop.o
CC lib/kfifo.o
CC mm/memblock.o
CC fs/nfs/nfs4proc.o
CC net/mac80211/rate.o
AR drivers/thermal/intel/built-in.a
AR drivers/thermal/tegra/built-in.a
CC drivers/gpu/drm/i915/i915_debugfs.o
CC drivers/gpu/drm/i915/i915_debugfs_params.o
AR drivers/thermal/mediatek/built-in.a
CC drivers/usb/core/devio.o
CC drivers/thermal/thermal_core.o
CC drivers/scsi/virtio_scsi.o
CC arch/x86/kernel/reboot.o
CC fs/ext4/xattr_user.o
CC net/ipv4/icmp.o
AR drivers/i2c/built-in.a
CC drivers/acpi/acpica/psobject.o
CC arch/x86/kernel/msr.o
CC net/sunrpc/xdr.o
CC fs/ioctl.o
CC drivers/thermal/thermal_sysfs.o
CC net/mac80211/michael.o
CC kernel/ucount.o
CC net/core/netprio_cgroup.o
CC drivers/acpi/processor_core.o
CC drivers/input/sparse-keymap.o
CC drivers/gpu/drm/drm_bridge.o
CC arch/x86/kernel/cpuid.o
CC [M] drivers/gpu/drm/xe/xe_exec.o
CC drivers/thermal/thermal_trip.o
CC net/mac80211/tkip.o
CC lib/percpu-refcount.o
CC kernel/regset.o
CC drivers/acpi/acpica/psopcode.o
CC drivers/usb/storage/option_ms.o
CC net/ipv4/devinet.o
CC drivers/ata/pata_oldpiix.o
CC fs/readdir.o
CC [M] drivers/gpu/drm/xe/xe_execlist.o
CC net/netfilter/x_tables.o
CC fs/ext4/fast_commit.o
CC fs/ext4/orphan.o
CC drivers/acpi/acpica/psopinfo.o
AR drivers/net/ethernet/dec/tulip/built-in.a
AR drivers/net/ethernet/dec/built-in.a
CC arch/x86/kernel/early-quirks.o
CC fs/ext4/acl.o
CC fs/select.o
CC net/core/netclassid_cgroup.o
CC drivers/scsi/sd.o
AR drivers/watchdog/built-in.a
CC net/netfilter/xt_tcpudp.o
CC mm/slub.o
CC drivers/gpu/drm/i915/i915_pmu.o
CC drivers/usb/host/xhci-ext-caps.o
CC kernel/ksyms_common.o
AR drivers/net/ethernet/dlink/built-in.a
CC net/ipv4/af_inet.o
CC drivers/input/vivaldi-fmap.o
CC drivers/md/md.o
CC drivers/acpi/acpica/psparse.o
CC lib/rhashtable.o
CC net/sunrpc/sunrpc_syms.o
CC net/core/dst_cache.o
CC net/ipv4/igmp.o
CC drivers/usb/storage/usual-tables.o
CC drivers/acpi/processor_pdc.o
CC mm/madvise.o
CC arch/x86/kernel/smp.o
AR drivers/net/ethernet/emulex/built-in.a
CC drivers/ata/pata_sch.o
CC drivers/md/md-bitmap.o
CC [M] drivers/gpu/drm/xe/xe_exec_queue.o
CC drivers/input/input-leds.o
CC drivers/input/evdev.o
CC drivers/acpi/acpica/psscope.o
CC arch/x86/kernel/smpboot.o
CC kernel/groups.o
CC drivers/usb/host/xhci-ring.o
CC drivers/thermal/thermal_helpers.o
CC drivers/usb/core/notify.o
CC net/netfilter/xt_CONNSECMARK.o
CC net/ipv4/fib_frontend.o
CC net/mac80211/aes_cmac.o
CC drivers/net/virtio_net.o
CC lib/base64.o
CC arch/x86/kernel/tsc_sync.o
CC net/sunrpc/cache.o
CC drivers/thermal/thermal_thresholds.o
CC drivers/acpi/ec.o
AR drivers/net/ethernet/engleder/built-in.a
AR drivers/net/ethernet/ezchip/built-in.a
CC kernel/kcmp.o
CC drivers/acpi/acpica/pstree.o
CC drivers/acpi/acpica/psutils.o
AR drivers/usb/storage/built-in.a
CC net/ipv4/fib_semantics.o
CC net/mac80211/aes_gmac.o
CC mm/page_io.o
CC net/ipv6/reassembly.o
CC drivers/cpufreq/cpufreq.o
CC net/sunrpc/rpc_pipe.o
CC drivers/ata/pata_mpiix.o
AR net/wireless/built-in.a
CC net/mac80211/fils_aead.o
CC drivers/cpuidle/governors/menu.o
CC drivers/usb/core/generic.o
CC drivers/acpi/acpica/pswalk.o
CC [M] drivers/gpu/drm/xe/xe_force_wake.o
CC drivers/md/md-autodetect.o
AR drivers/net/ethernet/fujitsu/built-in.a
CC drivers/cpuidle/governors/haltpoll.o
CC net/core/gro_cells.o
CC drivers/thermal/thermal_hwmon.o
CC lib/once.o
CC lib/refcount.o
CC net/core/failover.o
CC drivers/gpu/drm/i915/gt/gen2_engine_cs.o
AR drivers/input/built-in.a
CC net/ipv6/tcp_ipv6.o
AR drivers/mmc/built-in.a
CC drivers/cpuidle/cpuidle.o
CC net/sunrpc/sysfs.o
CC net/mac80211/cfg.o
CC drivers/acpi/acpica/psxface.o
CC kernel/freezer.o
CC fs/nfs/nfs4xdr.o
CC mm/swap_state.o
CC net/netfilter/xt_NFLOG.o
CC drivers/net/net_failover.o
CC lib/rcuref.o
CC drivers/cpuidle/driver.o
CC drivers/usb/host/xhci-hub.o
CC arch/x86/kernel/setup_percpu.o
CC drivers/thermal/gov_step_wise.o
AR drivers/ufs/built-in.a
CC fs/nfs/nfs4state.o
CC lib/usercopy.o
CC drivers/usb/core/quirks.o
CC drivers/md/dm.o
CC drivers/ata/ata_generic.o
CC drivers/acpi/acpica/rsaddr.o
AR drivers/firmware/arm_ffa/built-in.a
CC arch/x86/kernel/mpparse.o
AR drivers/firmware/arm_scmi/built-in.a
CC mm/swapfile.o
AR drivers/firmware/broadcom/built-in.a
AR drivers/firmware/cirrus/built-in.a
AR drivers/firmware/meson/built-in.a
AR drivers/firmware/microchip/built-in.a
CC drivers/firmware/efi/efi-bgrt.o
CC drivers/firmware/efi/libstub/efi-stub-helper.o
CC fs/dcache.o
CC drivers/acpi/acpica/rscalc.o
CC fs/ext4/xattr_security.o
CC [M] drivers/gpu/drm/xe/xe_ggtt.o
AR drivers/net/ethernet/fungible/built-in.a
CC lib/errseq.o
CC lib/bucket_locks.o
CC arch/x86/kernel/trace_clock.o
AR drivers/cpuidle/governors/built-in.a
CC net/mac80211/ethtool.o
CC drivers/thermal/gov_user_space.o
CC net/netfilter/xt_SECMARK.o
CC drivers/md/dm-table.o
CC fs/inode.o
CC fs/attr.o
CC net/netfilter/xt_TCPMSS.o
AR net/core/built-in.a
CC drivers/gpu/drm/i915/gt/gen6_engine_cs.o
CC kernel/profile.o
CC drivers/cpufreq/freq_table.o
CC drivers/cpuidle/governor.o
CC fs/nfs/nfs4renewd.o
CC drivers/scsi/sr.o
CC lib/generic-radix-tree.o
CC net/sunrpc/svc_xprt.o
CC drivers/gpu/drm/drm_cache.o
CC drivers/usb/core/devices.o
AR drivers/net/ethernet/google/built-in.a
CC drivers/acpi/acpica/rscreate.o
CC [M] drivers/gpu/drm/xe/xe_gpu_scheduler.o
CC fs/bad_inode.o
AR drivers/ata/built-in.a
CC drivers/gpu/drm/drm_color_mgmt.o
CC drivers/acpi/dock.o
CC drivers/firmware/efi/libstub/gop.o
AR drivers/thermal/built-in.a
CC drivers/gpu/drm/i915/gt/gen6_ppgtt.o
CC drivers/md/dm-target.o
CC kernel/stacktrace.o
AR drivers/firmware/imx/built-in.a
CC drivers/cpuidle/sysfs.o
CC drivers/usb/host/xhci-dbg.o
CC fs/nfs/nfs4super.o
AR drivers/net/ethernet/hisilicon/built-in.a
CC net/ipv4/fib_trie.o
AR drivers/net/ethernet/huawei/built-in.a
CC drivers/firmware/efi/efi.o
CC arch/x86/kernel/trace.o
CC net/sunrpc/xprtmultipath.o
AR fs/ext4/built-in.a
CC lib/bitmap-str.o
CC drivers/gpu/drm/drm_connector.o
CC drivers/cpufreq/cpufreq_performance.o
CC drivers/acpi/acpica/rsdumpinfo.o
CC drivers/gpu/drm/drm_crtc.o
CC net/ipv4/fib_notifier.o
CC drivers/scsi/sr_ioctl.o
CC drivers/firmware/efi/vars.o
CC net/mac80211/rx.o
CC drivers/gpu/drm/i915/gt/gen7_renderclear.o
CC net/mac80211/spectmgmt.o
CC [M] drivers/gpu/drm/xe/xe_gsc.o
CC drivers/usb/host/xhci-trace.o
CC lib/string_helpers.o
CC net/ipv4/inet_fragment.o
CC drivers/cpuidle/poll_state.o
CC drivers/acpi/acpica/rsinfo.o
CC drivers/usb/core/phy.o
CC drivers/net/ethernet/intel/e1000/e1000_main.o
CC net/netfilter/xt_conntrack.o
CC kernel/dma.o
CC drivers/cpufreq/cpufreq_userspace.o
CC drivers/firmware/efi/libstub/secureboot.o
AR drivers/net/ethernet/i825xx/built-in.a
CC drivers/usb/core/port.o
CC mm/swap_slots.o
CC drivers/firmware/efi/libstub/tpm.o
CC drivers/cpufreq/cpufreq_ondemand.o
CC drivers/net/ethernet/intel/e1000e/82571.o
CC arch/x86/kernel/rethook.o
CC drivers/cpuidle/cpuidle-haltpoll.o
CC drivers/net/ethernet/intel/e1000/e1000_hw.o
AR drivers/crypto/stm32/built-in.a
AR drivers/crypto/xilinx/built-in.a
AR drivers/crypto/hisilicon/built-in.a
AR drivers/crypto/intel/keembay/built-in.a
AR drivers/crypto/intel/ixp4xx/built-in.a
AR drivers/crypto/intel/built-in.a
CC drivers/firmware/efi/reboot.o
AR drivers/crypto/starfive/built-in.a
CC drivers/firmware/efi/memattr.o
AR drivers/crypto/built-in.a
CC drivers/acpi/acpica/rsio.o
CC drivers/firmware/efi/tpm.o
CC fs/nfs/nfs4file.o
CC arch/x86/kernel/vmcore_info_32.o
CC drivers/net/ethernet/intel/e1000e/ich8lan.o
CC drivers/firmware/efi/libstub/file.o
CC drivers/acpi/acpica/rsirq.o
CC kernel/smp.o
CC drivers/clocksource/acpi_pm.o
CC drivers/scsi/sr_vendor.o
CC net/sunrpc/stats.o
AR drivers/cpuidle/built-in.a
CC net/ipv6/ping.o
CC drivers/clocksource/i8253.o
CC mm/dmapool.o
CC drivers/md/dm-linear.o
CC fs/file.o
CC net/sunrpc/sysctl.o
CC net/netfilter/xt_policy.o
CC [M] drivers/gpu/drm/xe/xe_gsc_debugfs.o
CC lib/hexdump.o
CC drivers/gpu/drm/i915/gt/gen8_engine_cs.o
CC drivers/net/ethernet/intel/e1000/e1000_ethtool.o
AR drivers/firmware/psci/built-in.a
CC drivers/usb/host/xhci-debugfs.o
CC drivers/gpu/drm/drm_displayid.o
CC lib/kstrtox.o
CC drivers/cpufreq/cpufreq_governor.o
CC drivers/acpi/acpica/rslist.o
AR drivers/net/ethernet/broadcom/built-in.a
CC drivers/hid/usbhid/hid-core.o
CC drivers/hid/usbhid/hiddev.o
CC net/mac80211/tx.o
CC drivers/cpufreq/cpufreq_governor_attr_set.o
CC drivers/usb/core/hcd-pci.o
CC net/ipv6/exthdrs.o
CC drivers/hid/hid-core.o
CC arch/x86/kernel/machine_kexec_32.o
CC drivers/firmware/efi/libstub/mem.o
CC drivers/hid/hid-input.o
CC drivers/acpi/acpica/rsmemory.o
CC drivers/usb/host/xhci-pci.o
CC drivers/firmware/efi/memmap.o
CC drivers/gpu/drm/i915/gt/gen8_ppgtt.o
CC drivers/scsi/sg.o
CC net/ipv4/ping.o
CC drivers/firmware/efi/libstub/random.o
AR drivers/clocksource/built-in.a
CC lib/iomap.o
AR drivers/firmware/qcom/built-in.a
CC fs/filesystems.o
CC drivers/net/ethernet/intel/e100.o
CC drivers/hid/hid-quirks.o
CC mm/hugetlb.o
CC drivers/net/ethernet/intel/e1000e/80003es2lan.o
CC drivers/acpi/acpica/rsmisc.o
CC drivers/usb/core/usb-acpi.o
CC drivers/hid/usbhid/hid-pidff.o
CC drivers/md/dm-stripe.o
CC drivers/acpi/pci_root.o
CC [M] drivers/gpu/drm/xe/xe_gsc_proxy.o
CC drivers/cpufreq/acpi-cpufreq.o
CC fs/nfs/delegation.o
CC drivers/firmware/efi/libstub/randomalloc.o
CC drivers/firmware/efi/capsule.o
AS arch/x86/kernel/relocate_kernel_32.o
CC drivers/acpi/acpica/rsserial.o
AR drivers/platform/x86/amd/built-in.a
AR drivers/platform/x86/intel/built-in.a
CC drivers/platform/x86/wmi.o
CC arch/x86/kernel/crash_dump_32.o
CC kernel/uid16.o
AR drivers/platform/surface/built-in.a
CC drivers/platform/x86/wmi-bmof.o
CC fs/nfs/nfs4idmap.o
CC [M] drivers/gpu/drm/xe/xe_gsc_submit.o
CC net/netfilter/xt_state.o
CC [M] drivers/gpu/drm/xe/xe_gt.o
CC drivers/hid/hid-debug.o
CC net/mac80211/key.o
AR drivers/net/ethernet/microsoft/built-in.a
CC net/ipv4/ip_tunnel_core.o
CC lib/iomap_copy.o
CC lib/devres.o
CC kernel/kallsyms.o
CC drivers/acpi/acpica/rsutils.o
CC drivers/acpi/pci_link.o
CC kernel/acct.o
CC net/ipv6/datagram.o
CC [M] net/netfilter/nf_log_syslog.o
CC drivers/net/ethernet/intel/e1000/e1000_param.o
AR drivers/usb/core/built-in.a
CC drivers/firmware/efi/esrt.o
CC fs/nfs/callback.o
CC drivers/acpi/acpica/rsxface.o
CC drivers/md/dm-ioctl.o
CC drivers/firmware/efi/libstub/pci.o
CC drivers/net/ethernet/intel/e1000e/mac.o
CC drivers/gpu/drm/drm_drv.o
CC arch/x86/kernel/crash.o
CC lib/check_signature.o
CC drivers/cpufreq/amd-pstate.o
CC drivers/acpi/pci_irq.o
AR drivers/usb/host/built-in.a
AR drivers/net/ethernet/litex/built-in.a
AR drivers/usb/built-in.a
AR drivers/firmware/smccc/built-in.a
CC arch/x86/kernel/module.o
CC drivers/scsi/scsi_sysfs.o
CC net/mac80211/util.o
CC drivers/hid/hidraw.o
CC drivers/net/ethernet/intel/e1000e/manage.o
CC lib/interval_tree.o
CC lib/assoc_array.o
CC drivers/platform/x86/eeepc-laptop.o
AR net/sunrpc/built-in.a
CC net/ipv4/gre_offload.o
AR drivers/net/ethernet/marvell/octeon_ep/built-in.a
CC drivers/md/dm-io.o
CC drivers/acpi/acpica/tbdata.o
AR drivers/net/ethernet/marvell/octeon_ep_vf/built-in.a
AR drivers/net/ethernet/marvell/octeontx2/built-in.a
CC drivers/acpi/acpi_apd.o
AR drivers/net/ethernet/marvell/prestera/built-in.a
CC drivers/gpu/drm/i915/gt/intel_breadcrumbs.o
CC drivers/net/ethernet/marvell/sky2.o
AR drivers/hid/usbhid/built-in.a
CC drivers/gpu/drm/drm_dumb_buffers.o
CC drivers/firmware/efi/runtime-wrappers.o
CC drivers/gpu/drm/i915/gt/intel_context.o
CC drivers/platform/x86/p2sb.o
CC kernel/vmcore_info.o
CC drivers/acpi/acpi_platform.o
CC fs/namespace.o
CC mm/mmu_notifier.o
CC fs/nfs/callback_xdr.o
CC drivers/cpufreq/amd-pstate-trace.o
CC drivers/net/ethernet/intel/e1000e/nvm.o
CC drivers/firmware/efi/libstub/skip_spaces.o
CC drivers/net/ethernet/intel/e1000e/phy.o
CC drivers/firmware/efi/libstub/lib-cmdline.o
CC drivers/md/dm-kcopyd.o
AR drivers/firmware/tegra/built-in.a
CC [M] drivers/gpu/drm/xe/xe_gt_ccs_mode.o
AR drivers/net/ethernet/mellanox/built-in.a
CC drivers/gpu/drm/i915/gt/intel_context_sseu.o
CC drivers/hid/hid-generic.o
CC net/ipv4/metrics.o
CC drivers/firmware/efi/libstub/lib-ctype.o
CC arch/x86/kernel/doublefault_32.o
CC mm/migrate.o
CC drivers/firmware/efi/libstub/alignedmem.o
CC mm/page_counter.o
CC fs/nfs/callback_proc.o
CC drivers/acpi/acpica/tbfadt.o
CC drivers/mailbox/mailbox.o
CC lib/bitrev.o
AR drivers/net/ethernet/intel/e1000/built-in.a
CC drivers/acpi/acpica/tbfind.o
CC net/ipv6/ip6_flowlabel.o
CC net/mac80211/parse.o
AR drivers/net/ethernet/meta/built-in.a
CC mm/hugetlb_cgroup.o
CC drivers/firmware/efi/capsule-loader.o
CC kernel/elfcorehdr.o
CC net/ipv4/netlink.o
CC arch/x86/kernel/early_printk.o
CC fs/seq_file.o
CC [M] drivers/gpu/drm/xe/xe_gt_clock.o
CC drivers/firmware/efi/libstub/relocate.o
CC drivers/firmware/efi/libstub/printk.o
CC drivers/gpu/drm/i915/gt/intel_engine_cs.o
CC [M] net/netfilter/xt_mark.o
CC drivers/gpu/drm/i915/gt/intel_engine_heartbeat.o
AR drivers/firmware/xilinx/built-in.a
CC drivers/cpufreq/intel_pstate.o
CC mm/early_ioremap.o
AR drivers/scsi/built-in.a
CC drivers/net/ethernet/intel/e1000e/param.o
CC drivers/net/ethernet/intel/e1000e/ethtool.o
CC kernel/crash_reserve.o
CC drivers/gpu/drm/drm_edid.o
AR drivers/platform/x86/built-in.a
CC lib/crc-ccitt.o
AR drivers/platform/built-in.a
CC drivers/gpu/drm/drm_eld.o
CC lib/crc16.o
CC drivers/acpi/acpica/tbinstal.o
CC net/ipv4/nexthop.o
CC drivers/hid/hid-a4tech.o
CC drivers/gpu/drm/i915/gt/intel_engine_pm.o
CC drivers/firmware/efi/earlycon.o
CC net/mac80211/wme.o
CC drivers/mailbox/pcc.o
CC drivers/acpi/acpi_pnp.o
CC fs/nfs/nfs4namespace.o
CC drivers/firmware/dmi_scan.o
CC fs/xattr.o
CC arch/x86/kernel/hpet.o
CC arch/x86/kernel/amd_nb.o
HOSTCC lib/gen_crc32table
AR drivers/perf/built-in.a
CC drivers/md/dm-sysfs.o
CC mm/secretmem.o
CC drivers/acpi/acpica/tbprint.o
CC [M] net/netfilter/xt_nat.o
CC net/mac80211/chan.o
CC drivers/firmware/efi/libstub/vsprintf.o
CC lib/xxhash.o
AR drivers/hwtracing/intel_th/built-in.a
CC drivers/hid/hid-apple.o
CC drivers/hid/hid-belkin.o
CC drivers/acpi/power.o
CC kernel/kexec_core.o
CC drivers/acpi/acpica/tbutils.o
CC [M] drivers/gpu/drm/xe/xe_gt_freq.o
CC drivers/gpu/drm/drm_encoder.o
CC fs/libfs.o
CC drivers/hid/hid-cherry.o
CC drivers/firmware/efi/libstub/x86-stub.o
CC net/ipv6/inet6_connection_sock.o
CC drivers/acpi/event.o
CC drivers/md/dm-stats.o
CC drivers/gpu/drm/drm_file.o
CC fs/fs-writeback.o
CC arch/x86/kernel/kvm.o
AR drivers/mailbox/built-in.a
CC drivers/firmware/efi/libstub/smbios.o
CC [M] net/netfilter/xt_LOG.o
CC [M] net/netfilter/xt_MASQUERADE.o
CC fs/nfs/nfs4getroot.o
CC net/ipv6/udp_offload.o
CC drivers/md/dm-rq.o
CC [M] drivers/gpu/drm/xe/xe_gt_idle.o
AR drivers/android/built-in.a
CC [M] net/netfilter/xt_addrtype.o
CC drivers/acpi/acpica/tbxface.o
AR drivers/nvmem/layouts/built-in.a
CC drivers/nvmem/core.o
CC drivers/firmware/dmi-id.o
CC lib/genalloc.o
CC mm/hmm.o
CC fs/pnode.o
CC [M] drivers/gpu/drm/xe/xe_gt_mcr.o
CC drivers/acpi/evged.o
STUBCPY drivers/firmware/efi/libstub/alignedmem.stub.o
CC fs/nfs/nfs4client.o
AR drivers/net/ethernet/micrel/built-in.a
CC net/mac80211/trace.o
AR drivers/firmware/efi/built-in.a
CC drivers/gpu/drm/drm_fourcc.o
CC drivers/net/ethernet/intel/e1000e/netdev.o
CC drivers/gpu/drm/i915/gt/intel_engine_user.o
STUBCPY drivers/firmware/efi/libstub/efi-stub-helper.stub.o
CC drivers/hid/hid-chicony.o
CC fs/nfs/nfs4session.o
CC fs/nfs/dns_resolve.o
CC net/ipv4/udp_tunnel_stub.o
CC mm/memfd.o
CC drivers/acpi/acpica/tbxfload.o
CC [M] drivers/gpu/drm/xe/xe_gt_pagefault.o
CC drivers/acpi/sysfs.o
CC drivers/gpu/drm/drm_framebuffer.o
CC kernel/crash_core.o
STUBCPY drivers/firmware/efi/libstub/file.stub.o
STUBCPY drivers/firmware/efi/libstub/gop.stub.o
STUBCPY drivers/firmware/efi/libstub/lib-cmdline.stub.o
CC [M] drivers/gpu/drm/xe/xe_gt_sysfs.o
STUBCPY drivers/firmware/efi/libstub/lib-ctype.stub.o
STUBCPY drivers/firmware/efi/libstub/mem.stub.o
STUBCPY drivers/firmware/efi/libstub/pci.stub.o
STUBCPY drivers/firmware/efi/libstub/printk.stub.o
STUBCPY drivers/firmware/efi/libstub/random.stub.o
STUBCPY drivers/firmware/efi/libstub/randomalloc.stub.o
STUBCPY drivers/firmware/efi/libstub/relocate.stub.o
STUBCPY drivers/firmware/efi/libstub/secureboot.stub.o
CC [M] drivers/gpu/drm/xe/xe_gt_throttle.o
STUBCPY drivers/firmware/efi/libstub/skip_spaces.stub.o
STUBCPY drivers/firmware/efi/libstub/smbios.stub.o
STUBCPY drivers/firmware/efi/libstub/tpm.stub.o
STUBCPY drivers/firmware/efi/libstub/vsprintf.stub.o
STUBCPY drivers/firmware/efi/libstub/x86-stub.stub.o
CC drivers/acpi/property.o
CC net/mac80211/mlme.o
AR drivers/firmware/efi/libstub/lib.a
CC lib/percpu_counter.o
CC drivers/firmware/memmap.o
AR drivers/net/ethernet/marvell/built-in.a
CC drivers/net/ethernet/intel/e1000e/ptp.o
CC drivers/hid/hid-cypress.o
CC drivers/acpi/acpica/tbxfroot.o
CC fs/nfs/nfs4trace.o
AR drivers/net/ethernet/microchip/built-in.a
CC fs/nfs/nfs4sysctl.o
CC drivers/hid/hid-ezkey.o
CC lib/audit.o
AR drivers/cpufreq/built-in.a
CC drivers/hid/hid-gyration.o
CC arch/x86/kernel/kvmclock.o
CC drivers/hid/hid-ite.o
CC drivers/acpi/debugfs.o
CC drivers/md/dm-io-rewind.o
CC arch/x86/kernel/paravirt.o
CC lib/syscall.o
CC net/ipv6/seg6.o
CC drivers/gpu/drm/drm_gem.o
CC net/ipv4/ip_tunnel.o
CC [M] drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o
CC drivers/acpi/acpica/utaddress.o
AR drivers/net/ethernet/mscc/built-in.a
AR drivers/nvmem/built-in.a
CC net/ipv6/fib6_notifier.o
CC net/ipv4/sysctl_net_ipv4.o
CC drivers/acpi/acpica/utalloc.o
CC net/mac80211/tdls.o
CC mm/ptdump.o
CC drivers/md/dm-builtin.o
CC kernel/kexec.o
AR net/netfilter/built-in.a
CC drivers/gpu/drm/drm_ioctl.o
CC drivers/gpu/drm/i915/gt/intel_execlists_submission.o
CC drivers/acpi/acpi_lpat.o
CC arch/x86/kernel/pvclock.o
CC drivers/hid/hid-kensington.o
CC drivers/gpu/drm/drm_lease.o
CC lib/errname.o
CC fs/splice.o
AR drivers/firmware/built-in.a
CC net/ipv4/proc.o
CC drivers/acpi/acpi_pcc.o
CC lib/nlattr.o
CC fs/sync.o
CC drivers/gpu/drm/i915/gt/intel_ggtt.o
AR drivers/net/ethernet/myricom/built-in.a
CC net/ipv6/rpl.o
CC arch/x86/kernel/pcspeaker.o
CC drivers/acpi/acpica/utascii.o
CC drivers/acpi/ac.o
CC [M] drivers/gpu/drm/xe/xe_gt_topology.o
CC drivers/acpi/acpica/utbuffer.o
CC drivers/md/dm-raid1.o
AR drivers/net/ethernet/natsemi/built-in.a
CC drivers/acpi/button.o
CC drivers/gpu/drm/drm_managed.o
CC mm/execmem.o
CC net/mac80211/ocb.o
CC drivers/acpi/fan_core.o
CC lib/cpu_rmap.o
CC kernel/utsname.o
CC fs/utimes.o
CC net/ipv4/fib_rules.o
CC net/ipv6/ioam6.o
CC drivers/md/dm-log.o
CC drivers/acpi/acpica/utcksum.o
CC drivers/gpu/drm/i915/gt/intel_ggtt_fencing.o
CC lib/dynamic_queue_limits.o
CC net/ipv4/ipmr.o
CC lib/glob.o
AR drivers/net/ethernet/neterion/built-in.a
CC arch/x86/kernel/check.o
CC drivers/hid/hid-lg.o
CC drivers/gpu/drm/i915/gt/intel_gt.o
CC arch/x86/kernel/uprobes.o
CC [M] drivers/gpu/drm/xe/xe_guc.o
CC arch/x86/kernel/perf_regs.o
CC net/mac80211/airtime.o
CC fs/d_path.o
CC net/ipv4/ipmr_base.o
CC lib/strncpy_from_user.o
CC kernel/pid_namespace.o
CC fs/stack.o
AR drivers/net/ethernet/netronome/built-in.a
CC arch/x86/kernel/tracepoint.o
AR drivers/net/ethernet/ni/built-in.a
CC arch/x86/kernel/itmt.o
CC drivers/acpi/acpica/utcopy.o
CC drivers/gpu/drm/drm_mm.o
CC net/ipv4/syncookies.o
CC net/ipv6/sysctl_net_ipv6.o
CC kernel/stop_machine.o
AR mm/built-in.a
CC drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.o
CC drivers/acpi/acpica/utexcep.o
CC net/mac80211/eht.o
CC fs/fs_struct.o
CC drivers/net/ethernet/nvidia/forcedeth.o
AR drivers/net/ethernet/oki-semi/built-in.a
CC drivers/md/dm-region-hash.o
CC drivers/acpi/fan_attr.o
CC net/ipv6/xfrm6_policy.o
CC drivers/hid/hid-lgff.o
CC drivers/acpi/acpica/utdebug.o
AR drivers/net/ethernet/packetengines/built-in.a
CC kernel/audit.o
AR drivers/net/ethernet/qlogic/built-in.a
CC lib/strnlen_user.o
CC [M] drivers/gpu/drm/xe/xe_guc_ads.o
CC drivers/acpi/acpica/utdecode.o
CC net/ipv4/tunnel4.o
CC fs/statfs.o
CC kernel/auditfilter.o
CC [M] drivers/gpu/drm/xe/xe_guc_buf.o
CC drivers/hid/hid-lg4ff.o
CC lib/net_utils.o
CC drivers/gpu/drm/drm_mode_config.o
CC drivers/md/dm-zero.o
CC fs/fs_pin.o
CC arch/x86/kernel/umip.o
CC drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.o
CC fs/nsfs.o
CC drivers/acpi/fan_hwmon.o
CC drivers/hid/hid-lg-g15.o
CC net/mac80211/led.o
CC drivers/gpu/drm/i915/gt/intel_gt_clock_utils.o
CC kernel/auditsc.o
CC arch/x86/kernel/unwind_frame.o
CC drivers/acpi/acpica/utdelete.o
AR drivers/net/ethernet/qualcomm/emac/built-in.a
AR drivers/net/ethernet/qualcomm/built-in.a
CC drivers/gpu/drm/i915/gt/intel_gt_debugfs.o
CC drivers/gpu/drm/drm_mode_object.o
CC kernel/audit_watch.o
CC [M] drivers/gpu/drm/xe/xe_guc_capture.o
CC drivers/gpu/drm/drm_modes.o
CC drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.o
CC net/ipv6/xfrm6_state.o
CC net/mac80211/pm.o
CC drivers/acpi/acpi_video.o
CC fs/fs_types.o
CC kernel/audit_fsnotify.o
CC lib/sg_pool.o
CC drivers/acpi/video_detect.o
CC net/ipv4/ipconfig.o
CC net/ipv4/netfilter.o
CC drivers/gpu/drm/drm_modeset_lock.o
AR drivers/md/built-in.a
CC net/mac80211/rc80211_minstrel_ht.o
CC drivers/hid/hid-microsoft.o
CC net/mac80211/wbrf.o
CC drivers/acpi/acpica/uterror.o
CC drivers/net/ethernet/realtek/8139too.o
CC lib/stackdepot.o
CC drivers/gpu/drm/drm_plane.o
CC kernel/audit_tree.o
CC drivers/acpi/processor_driver.o
CC drivers/gpu/drm/drm_prime.o
CC fs/fs_context.o
CC net/ipv4/tcp_cubic.o
AR drivers/net/ethernet/renesas/built-in.a
CC drivers/gpu/drm/drm_print.o
AR arch/x86/kernel/built-in.a
AR arch/x86/built-in.a
CC [M] drivers/gpu/drm/xe/xe_guc_ct.o
CC lib/asn1_decoder.o
CC kernel/kprobes.o
CC drivers/hid/hid-monterey.o
CC [M] drivers/gpu/drm/xe/xe_guc_db_mgr.o
CC drivers/acpi/acpica/uteval.o
CC drivers/net/ethernet/realtek/r8169_main.o
CC drivers/gpu/drm/drm_property.o
CC drivers/acpi/acpica/utglobal.o
CC drivers/acpi/acpica/uthex.o
CC net/ipv4/tcp_sigpool.o
AR fs/nfs/built-in.a
CC net/ipv6/xfrm6_input.o
CC fs/fs_parser.o
CC drivers/acpi/processor_thermal.o
CC drivers/gpu/drm/i915/gt/intel_gt_irq.o
CC drivers/net/ethernet/realtek/r8169_firmware.o
CC drivers/hid/hid-ntrig.o
CC drivers/gpu/drm/drm_rect.o
CC drivers/gpu/drm/i915/gt/intel_gt_mcr.o
CC drivers/gpu/drm/drm_syncobj.o
CC net/ipv4/cipso_ipv4.o
CC drivers/hid/hid-pl.o
CC fs/fsopen.o
CC net/ipv4/xfrm4_policy.o
CC net/ipv6/xfrm6_output.o
CC drivers/acpi/acpica/utids.o
GEN lib/oid_registry_data.c
CC drivers/net/ethernet/realtek/r8169_phy_config.o
CC drivers/gpu/drm/i915/gt/intel_gt_pm.o
CC kernel/seccomp.o
CC net/ipv6/xfrm6_protocol.o
CC lib/ucs2_string.o
AR drivers/net/ethernet/rdc/built-in.a
CC lib/sbitmap.o
CC [M] drivers/gpu/drm/xe/xe_guc_hwconfig.o
CC drivers/hid/hid-petalynx.o
CC drivers/acpi/acpica/utinit.o
CC net/ipv6/netfilter.o
CC drivers/acpi/processor_idle.o
CC drivers/gpu/drm/drm_sysfs.o
/workspace/kernel/drivers/gpu/drm/xe/xe_guc_ct.c: In function ‘xe_guc_ct_snapshot_print’:
CC drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.o
CC kernel/relay.o
/workspace/kernel/drivers/gpu/drm/xe/xe_guc_ct.c:1727:58: error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘size_t’ {aka ‘unsigned int’} [-Werror=format=]
1727 | drm_printf(p, "[CTB].length: 0x%lx\n", snapshot->ctb_size);
| ~~^ ~~~~~~~~~~~~~~~~~~
| | |
| | size_t {aka unsigned int}
| long unsigned int
| %x
CC fs/init.o
CC lib/group_cpus.o
AR drivers/net/ethernet/rocker/built-in.a
CC net/ipv4/xfrm4_state.o
CC [M] drivers/gpu/drm/xe/xe_guc_id_mgr.o
CC net/ipv6/proc.o
CC net/ipv6/syncookies.o
CC [M] drivers/gpu/drm/xe/xe_guc_klv_helpers.o
CC drivers/gpu/drm/drm_trace_points.o
CC drivers/acpi/processor_throttling.o
CC kernel/utsname_sysctl.o
CC drivers/acpi/acpica/utlock.o
AR drivers/net/ethernet/intel/e1000e/built-in.a
CC drivers/gpu/drm/drm_vblank.o
AR drivers/net/ethernet/intel/built-in.a
AR drivers/net/ethernet/samsung/built-in.a
CC net/ipv4/xfrm4_input.o
CC lib/fw_table.o
CC fs/kernel_read_file.o
CC [M] drivers/gpu/drm/xe/xe_guc_log.o
CC drivers/acpi/acpica/utmath.o
CC drivers/acpi/processor_perflib.o
CC drivers/hid/hid-redragon.o
CC kernel/delayacct.o
CC drivers/gpu/drm/drm_vblank_work.o
CC drivers/gpu/drm/i915/gt/intel_gt_pm_irq.o
AR drivers/net/ethernet/seeq/built-in.a
CC kernel/taskstats.o
CC drivers/gpu/drm/drm_vma_manager.o
CC net/ipv6/calipso.o
cc1: all warnings being treated as errors
make[6]: *** [/workspace/kernel/scripts/Makefile.build:194: drivers/gpu/drm/xe/xe_guc_ct.o] Error 1
make[6]: *** Waiting for unfinished jobs....
CC fs/mnt_idmapping.o
CC kernel/tsacct.o
AR lib/lib.a
CC drivers/gpu/drm/drm_writeback.o
CC kernel/tracepoint.o
CC net/ipv6/ah6.o
CC kernel/irq_work.o
CC drivers/gpu/drm/drm_panel.o
CC kernel/static_call.o
CC drivers/acpi/acpica/utmisc.o
CC drivers/gpu/drm/i915/gt/intel_gt_requests.o
AR drivers/net/ethernet/nvidia/built-in.a
CC drivers/acpi/container.o
GEN lib/crc32table.h
CC drivers/gpu/drm/i915/gt/intel_gt_sysfs.o
CC lib/oid_registry.o
CC drivers/gpu/drm/drm_pci.o
CC net/ipv6/esp6.o
CC kernel/padata.o
CC net/ipv4/xfrm4_output.o
CC drivers/gpu/drm/drm_debugfs.o
CC drivers/acpi/acpica/utmutex.o
CC kernel/jump_label.o
CC kernel/context_tracking.o
CC drivers/hid/hid-samsung.o
AR drivers/net/ethernet/silan/built-in.a
CC fs/remap_range.o
CC net/ipv4/xfrm4_protocol.o
CC net/ipv6/sit.o
CC drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.o
CC drivers/hid/hid-sony.o
CC drivers/acpi/thermal_lib.o
/workspace/kernel/drivers/gpu/drm/xe/xe_guc_log.c: In function ‘xe_guc_log_snapshot_print’:
/workspace/kernel/drivers/gpu/drm/xe/xe_guc_log.c:207:42: error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 3 has type ‘size_t’ {aka ‘unsigned int’} [-Werror=format=]
207 | drm_printf(p, "[LOG].length: 0x%lx\n", snapshot->size);
| ~~^ ~~~~~~~~~~~~~~
| | |
| | size_t {aka unsigned int}
| long unsigned int
| %x
AR drivers/net/ethernet/sis/built-in.a
CC fs/pidfs.o
CC net/ipv6/addrconf_core.o
CC kernel/iomem.o
CC drivers/acpi/acpica/utnonansi.o
CC fs/buffer.o
CC drivers/hid/hid-sunplus.o
CC lib/crc32.o
CC drivers/gpu/drm/drm_debugfs_crc.o
cc1: all warnings being treated as errors
make[6]: *** [/workspace/kernel/scripts/Makefile.build:194: drivers/gpu/drm/xe/xe_guc_log.o] Error 1
make[5]: *** [/workspace/kernel/scripts/Makefile.build:440: drivers/gpu/drm/xe] Error 2
make[5]: *** Waiting for unfinished jobs....
CC net/ipv6/exthdrs_core.o
CC kernel/rseq.o
CC drivers/hid/hid-topseed.o
CC fs/mpage.o
CC net/ipv6/ip6_checksum.o
CC drivers/gpu/drm/i915/gt/intel_gtt.o
CC drivers/acpi/thermal.o
AR drivers/net/ethernet/sfc/built-in.a
CC fs/proc_namespace.o
CC net/ipv6/ip6_icmp.o
AR drivers/net/ethernet/smsc/built-in.a
CC drivers/acpi/nhlt.o
CC drivers/gpu/drm/i915/gt/intel_llc.o
CC net/ipv6/output_core.o
CC drivers/acpi/acpica/utobject.o
CC drivers/acpi/acpi_memhotplug.o
CC drivers/gpu/drm/i915/gt/intel_lrc.o
AR drivers/net/ethernet/socionext/built-in.a
CC net/ipv6/protocol.o
CC drivers/acpi/ioapic.o
CC fs/direct-io.o
AR drivers/net/ethernet/stmicro/built-in.a
CC drivers/acpi/acpica/utosi.o
CC net/ipv6/ip6_offload.o
CC drivers/acpi/acpica/utownerid.o
CC drivers/acpi/acpica/utpredef.o
CC net/ipv6/tcpv6_offload.o
CC net/ipv6/exthdrs_offload.o
AR lib/built-in.a
CC fs/eventpoll.o
CC drivers/acpi/battery.o
AR drivers/net/ethernet/sun/built-in.a
CC drivers/acpi/acpica/utresdecode.o
CC drivers/gpu/drm/i915/gt/intel_migrate.o
CC drivers/acpi/acpica/utresrc.o
AR drivers/net/ethernet/tehuti/built-in.a
CC drivers/acpi/bgrt.o
CC net/ipv6/inet6_hashtables.o
CC drivers/acpi/spcr.o
AR drivers/net/ethernet/ti/built-in.a
CC drivers/acpi/acpica/utstate.o
CC net/ipv6/mcast_snoop.o
CC fs/anon_inodes.o
CC drivers/gpu/drm/i915/gt/intel_mocs.o
CC fs/signalfd.o
AR drivers/net/ethernet/vertexcom/built-in.a
CC drivers/gpu/drm/i915/gt/intel_ppgtt.o
CC drivers/gpu/drm/i915/gt/intel_rc6.o
AR drivers/net/ethernet/via/built-in.a
CC drivers/gpu/drm/i915/gt/intel_region_lmem.o
CC drivers/gpu/drm/i915/gt/intel_renderstate.o
CC fs/timerfd.o
CC drivers/gpu/drm/i915/gt/intel_reset.o
CC drivers/acpi/acpica/utstring.o
CC fs/eventfd.o
CC drivers/acpi/acpica/utstrsuppt.o
CC fs/aio.o
AR net/ipv4/built-in.a
CC fs/locks.o
AR drivers/net/ethernet/wangxun/built-in.a
CC drivers/gpu/drm/i915/gt/intel_ring.o
AR drivers/net/ethernet/wiznet/built-in.a
AR kernel/built-in.a
CC drivers/gpu/drm/i915/gt/intel_ring_submission.o
CC drivers/gpu/drm/i915/gt/intel_rps.o
AR drivers/hid/built-in.a
CC fs/binfmt_misc.o
AR drivers/net/ethernet/xilinx/built-in.a
CC drivers/acpi/acpica/utstrtoul64.o
AR drivers/net/ethernet/xircom/built-in.a
CC drivers/gpu/drm/i915/gt/intel_sa_media.o
AR drivers/net/ethernet/synopsys/built-in.a
CC fs/binfmt_script.o
CC drivers/acpi/acpica/utxface.o
AR drivers/net/ethernet/pensando/built-in.a
CC drivers/gpu/drm/i915/gt/intel_sseu.o
CC fs/binfmt_elf.o
CC drivers/acpi/acpica/utxfinit.o
CC drivers/gpu/drm/i915/gt/intel_sseu_debugfs.o
CC drivers/acpi/acpica/utxferror.o
AR drivers/net/ethernet/realtek/built-in.a
AR drivers/net/ethernet/built-in.a
CC fs/mbcache.o
CC drivers/gpu/drm/i915/gt/intel_timeline.o
CC drivers/acpi/acpica/utxfmutex.o
AR drivers/net/built-in.a
CC drivers/gpu/drm/i915/gt/intel_tlb.o
CC fs/posix_acl.o
CC fs/coredump.o
CC drivers/gpu/drm/i915/gt/intel_wopcm.o
CC fs/drop_caches.o
CC drivers/gpu/drm/i915/gt/intel_workarounds.o
CC fs/sysctls.o
CC drivers/gpu/drm/i915/gt/shmem_utils.o
CC fs/fhandle.o
CC drivers/gpu/drm/i915/gt/sysfs_engines.o
CC drivers/gpu/drm/i915/gt/intel_ggtt_gmch.o
CC drivers/gpu/drm/i915/gt/gen6_renderstate.o
CC drivers/gpu/drm/i915/gt/gen7_renderstate.o
CC drivers/gpu/drm/i915/gt/gen8_renderstate.o
CC drivers/gpu/drm/i915/gt/gen9_renderstate.o
AR drivers/acpi/acpica/built-in.a
AR drivers/acpi/built-in.a
CC drivers/gpu/drm/i915/gem/i915_gem_busy.o
CC drivers/gpu/drm/i915/gem/i915_gem_clflush.o
CC drivers/gpu/drm/i915/gem/i915_gem_context.o
CC drivers/gpu/drm/i915/gem/i915_gem_create.o
CC drivers/gpu/drm/i915/gem/i915_gem_dmabuf.o
CC drivers/gpu/drm/i915/gem/i915_gem_domain.o
CC drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o
CC drivers/gpu/drm/i915/gem/i915_gem_internal.o
CC drivers/gpu/drm/i915/gem/i915_gem_lmem.o
CC drivers/gpu/drm/i915/gem/i915_gem_mman.o
CC drivers/gpu/drm/i915/gem/i915_gem_object.o
CC drivers/gpu/drm/i915/gem/i915_gem_pages.o
CC drivers/gpu/drm/i915/gem/i915_gem_phys.o
CC drivers/gpu/drm/i915/gem/i915_gem_pm.o
CC drivers/gpu/drm/i915/gem/i915_gem_region.o
CC drivers/gpu/drm/i915/gem/i915_gem_shmem.o
CC drivers/gpu/drm/i915/gem/i915_gem_shrinker.o
CC drivers/gpu/drm/i915/gem/i915_gem_stolen.o
CC drivers/gpu/drm/i915/gem/i915_gem_throttle.o
CC drivers/gpu/drm/i915/gem/i915_gem_tiling.o
CC drivers/gpu/drm/i915/gem/i915_gem_ttm.o
CC drivers/gpu/drm/i915/gem/i915_gem_ttm_move.o
CC drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.o
AR net/ipv6/built-in.a
CC drivers/gpu/drm/i915/gem/i915_gem_userptr.o
CC drivers/gpu/drm/i915/gem/i915_gem_wait.o
CC drivers/gpu/drm/i915/gem/i915_gemfs.o
CC drivers/gpu/drm/i915/i915_active.o
CC drivers/gpu/drm/i915/i915_cmd_parser.o
CC drivers/gpu/drm/i915/i915_deps.o
CC drivers/gpu/drm/i915/i915_gem.o
CC drivers/gpu/drm/i915/i915_gem_evict.o
CC drivers/gpu/drm/i915/i915_gem_gtt.o
CC drivers/gpu/drm/i915/i915_gem_ww.o
CC drivers/gpu/drm/i915/i915_query.o
AR net/mac80211/built-in.a
AR net/built-in.a
CC drivers/gpu/drm/i915/i915_request.o
CC drivers/gpu/drm/i915/i915_scheduler.o
CC drivers/gpu/drm/i915/i915_trace_points.o
CC drivers/gpu/drm/i915/i915_ttm_buddy_manager.o
CC drivers/gpu/drm/i915/i915_vma.o
CC drivers/gpu/drm/i915/i915_vma_resource.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_capture.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_ct.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_fw.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_log.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_rc.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o
CC drivers/gpu/drm/i915/gt/uc/intel_huc.o
CC drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.o
CC drivers/gpu/drm/i915/gt/uc/intel_huc_fw.o
CC drivers/gpu/drm/i915/gt/uc/intel_uc.o
CC drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.o
CC drivers/gpu/drm/i915/gt/uc/intel_uc_fw.o
CC drivers/gpu/drm/i915/gt/intel_gsc.o
CC drivers/gpu/drm/i915/i915_hwmon.o
AR fs/built-in.a
CC drivers/gpu/drm/i915/display/hsw_ips.o
CC drivers/gpu/drm/i915/display/i9xx_plane.o
CC drivers/gpu/drm/i915/display/i9xx_display_sr.o
CC drivers/gpu/drm/i915/display/i9xx_wm.o
CC drivers/gpu/drm/i915/display/intel_alpm.o
CC drivers/gpu/drm/i915/display/intel_atomic.o
CC drivers/gpu/drm/i915/display/intel_atomic_plane.o
CC drivers/gpu/drm/i915/display/intel_audio.o
CC drivers/gpu/drm/i915/display/intel_bios.o
CC drivers/gpu/drm/i915/display/intel_bo.o
CC drivers/gpu/drm/i915/display/intel_bw.o
CC drivers/gpu/drm/i915/display/intel_cdclk.o
CC drivers/gpu/drm/i915/display/intel_cmtg.o
CC drivers/gpu/drm/i915/display/intel_color.o
CC drivers/gpu/drm/i915/display/intel_combo_phy.o
CC drivers/gpu/drm/i915/display/intel_connector.o
CC drivers/gpu/drm/i915/display/intel_crtc.o
CC drivers/gpu/drm/i915/display/intel_crtc_state_dump.o
CC drivers/gpu/drm/i915/display/intel_cursor.o
CC drivers/gpu/drm/i915/display/intel_display.o
CC drivers/gpu/drm/i915/display/intel_display_conversion.o
CC drivers/gpu/drm/i915/display/intel_display_driver.o
CC drivers/gpu/drm/i915/display/intel_display_irq.o
CC drivers/gpu/drm/i915/display/intel_display_params.o
CC drivers/gpu/drm/i915/display/intel_display_power.o
CC drivers/gpu/drm/i915/display/intel_display_power_map.o
CC drivers/gpu/drm/i915/display/intel_display_power_well.o
CC drivers/gpu/drm/i915/display/intel_display_reset.o
CC drivers/gpu/drm/i915/display/intel_display_rps.o
CC drivers/gpu/drm/i915/display/intel_display_snapshot.o
CC drivers/gpu/drm/i915/display/intel_display_wa.o
CC drivers/gpu/drm/i915/display/intel_dmc.o
CC drivers/gpu/drm/i915/display/intel_dmc_wl.o
CC drivers/gpu/drm/i915/display/intel_dpio_phy.o
CC drivers/gpu/drm/i915/display/intel_dpll.o
CC drivers/gpu/drm/i915/display/intel_dpll_mgr.o
CC drivers/gpu/drm/i915/display/intel_dpt.o
CC drivers/gpu/drm/i915/display/intel_dpt_common.o
CC drivers/gpu/drm/i915/display/intel_drrs.o
CC drivers/gpu/drm/i915/display/intel_dsb.o
CC drivers/gpu/drm/i915/display/intel_dsb_buffer.o
CC drivers/gpu/drm/i915/display/intel_fb.o
CC drivers/gpu/drm/i915/display/intel_fb_bo.o
CC drivers/gpu/drm/i915/display/intel_fb_pin.o
CC drivers/gpu/drm/i915/display/intel_fbc.o
CC drivers/gpu/drm/i915/display/intel_fdi.o
CC drivers/gpu/drm/i915/display/intel_fifo_underrun.o
CC drivers/gpu/drm/i915/display/intel_frontbuffer.o
CC drivers/gpu/drm/i915/display/intel_global_state.o
CC drivers/gpu/drm/i915/display/intel_hdcp.o
CC drivers/gpu/drm/i915/display/intel_hdcp_gsc.o
CC drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.o
CC drivers/gpu/drm/i915/display/intel_hotplug.o
CC drivers/gpu/drm/i915/display/intel_hotplug_irq.o
CC drivers/gpu/drm/i915/display/intel_hti.o
CC drivers/gpu/drm/i915/display/intel_link_bw.o
CC drivers/gpu/drm/i915/display/intel_load_detect.o
CC drivers/gpu/drm/i915/display/intel_lpe_audio.o
CC drivers/gpu/drm/i915/display/intel_modeset_lock.o
CC drivers/gpu/drm/i915/display/intel_modeset_setup.o
CC drivers/gpu/drm/i915/display/intel_modeset_verify.o
CC drivers/gpu/drm/i915/display/intel_overlay.o
CC drivers/gpu/drm/i915/display/intel_pch_display.o
CC drivers/gpu/drm/i915/display/intel_pch_refclk.o
CC drivers/gpu/drm/i915/display/intel_plane_initial.o
CC drivers/gpu/drm/i915/display/intel_pmdemand.o
CC drivers/gpu/drm/i915/display/intel_psr.o
CC drivers/gpu/drm/i915/display/intel_quirks.o
CC drivers/gpu/drm/i915/display/intel_sprite.o
CC drivers/gpu/drm/i915/display/intel_sprite_uapi.o
CC drivers/gpu/drm/i915/display/intel_tc.o
CC drivers/gpu/drm/i915/display/intel_vblank.o
CC drivers/gpu/drm/i915/display/intel_vga.o
CC drivers/gpu/drm/i915/display/intel_wm.o
CC drivers/gpu/drm/i915/display/skl_scaler.o
CC drivers/gpu/drm/i915/display/skl_universal_plane.o
CC drivers/gpu/drm/i915/display/skl_watermark.o
CC drivers/gpu/drm/i915/display/intel_acpi.o
CC drivers/gpu/drm/i915/display/intel_opregion.o
CC drivers/gpu/drm/i915/display/intel_display_debugfs.o
CC drivers/gpu/drm/i915/display/intel_display_debugfs_params.o
CC drivers/gpu/drm/i915/display/intel_pipe_crc.o
CC drivers/gpu/drm/i915/display/dvo_ch7017.o
CC drivers/gpu/drm/i915/display/dvo_ch7xxx.o
CC drivers/gpu/drm/i915/display/dvo_ivch.o
CC drivers/gpu/drm/i915/display/dvo_ns2501.o
CC drivers/gpu/drm/i915/display/dvo_sil164.o
CC drivers/gpu/drm/i915/display/dvo_tfp410.o
CC drivers/gpu/drm/i915/display/g4x_dp.o
CC drivers/gpu/drm/i915/display/g4x_hdmi.o
CC drivers/gpu/drm/i915/display/icl_dsi.o
CC drivers/gpu/drm/i915/display/intel_backlight.o
CC drivers/gpu/drm/i915/display/intel_crt.o
CC drivers/gpu/drm/i915/display/intel_cx0_phy.o
CC drivers/gpu/drm/i915/display/intel_ddi.o
CC drivers/gpu/drm/i915/display/intel_ddi_buf_trans.o
CC drivers/gpu/drm/i915/display/intel_display_device.o
CC drivers/gpu/drm/i915/display/intel_display_trace.o
CC drivers/gpu/drm/i915/display/intel_dkl_phy.o
CC drivers/gpu/drm/i915/display/intel_dp.o
CC drivers/gpu/drm/i915/display/intel_dp_aux.o
CC drivers/gpu/drm/i915/display/intel_dp_aux_backlight.o
CC drivers/gpu/drm/i915/display/intel_dp_hdcp.o
CC drivers/gpu/drm/i915/display/intel_dp_link_training.o
CC drivers/gpu/drm/i915/display/intel_dp_mst.o
CC drivers/gpu/drm/i915/display/intel_dp_test.o
CC drivers/gpu/drm/i915/display/intel_dsi.o
CC drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.o
CC drivers/gpu/drm/i915/display/intel_dsi_vbt.o
CC drivers/gpu/drm/i915/display/intel_dvo.o
CC drivers/gpu/drm/i915/display/intel_encoder.o
CC drivers/gpu/drm/i915/display/intel_gmbus.o
CC drivers/gpu/drm/i915/display/intel_hdmi.o
CC drivers/gpu/drm/i915/display/intel_lspcon.o
CC drivers/gpu/drm/i915/display/intel_lvds.o
CC drivers/gpu/drm/i915/display/intel_panel.o
CC drivers/gpu/drm/i915/display/intel_pfit.o
CC drivers/gpu/drm/i915/display/intel_pps.o
CC drivers/gpu/drm/i915/display/intel_qp_tables.o
CC drivers/gpu/drm/i915/display/intel_sdvo.o
CC drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.o
CC drivers/gpu/drm/i915/display/intel_snps_phy.o
CC drivers/gpu/drm/i915/display/intel_tv.o
CC drivers/gpu/drm/i915/display/intel_vdsc.o
CC drivers/gpu/drm/i915/display/intel_vrr.o
CC drivers/gpu/drm/i915/display/vlv_dsi.o
CC drivers/gpu/drm/i915/display/vlv_dsi_pll.o
CC drivers/gpu/drm/i915/i915_perf.o
CC drivers/gpu/drm/i915/pxp/intel_pxp.o
CC drivers/gpu/drm/i915/pxp/intel_pxp_huc.o
CC drivers/gpu/drm/i915/pxp/intel_pxp_tee.o
CC drivers/gpu/drm/i915/i915_gpu_error.o
CC drivers/gpu/drm/i915/i915_vgpu.o
AR drivers/gpu/drm/i915/built-in.a
make[4]: *** [/workspace/kernel/scripts/Makefile.build:440: drivers/gpu/drm] Error 2
make[3]: *** [/workspace/kernel/scripts/Makefile.build:440: drivers/gpu] Error 2
make[2]: *** [/workspace/kernel/scripts/Makefile.build:440: drivers] Error 2
make[1]: *** [/workspace/kernel/Makefile:1989: .] Error 2
make: *** [/workspace/kernel/Makefile:251: __sub-make] Error 2
run-parts: /workspace/ci/hooks/11-build-32b exited with return code 2
^ permalink raw reply [flat|nested] 45+ messages in thread* ✓ CI.checksparse: success for PMU Support for per-engine-class activity (rev2)
2025-01-29 10:16 [PATCH v4 0/8] PMU Support for per-engine-class activity Riana Tauro
` (12 preceding siblings ...)
2025-01-29 11:58 ` ✗ CI.Hooks: failure " Patchwork
@ 2025-01-29 12:00 ` Patchwork
2025-01-29 12:36 ` ✗ Xe.CI.BAT: failure " Patchwork
` (2 subsequent siblings)
16 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2025-01-29 12:00 UTC (permalink / raw)
To: Riana Tauro; +Cc: intel-xe
== Series Details ==
Series: PMU Support for per-engine-class activity (rev2)
URL : https://patchwork.freedesktop.org/series/143138/
State : success
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 683350734da38bc7332a3b87c9f2faf6bbeeb5a3
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
Okay!
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 45+ messages in thread* ✗ Xe.CI.BAT: failure for PMU Support for per-engine-class activity (rev2)
2025-01-29 10:16 [PATCH v4 0/8] PMU Support for per-engine-class activity Riana Tauro
` (13 preceding siblings ...)
2025-01-29 12:00 ` ✓ CI.checksparse: success " Patchwork
@ 2025-01-29 12:36 ` Patchwork
2025-01-29 21:35 ` ✗ Xe.CI.Full: " Patchwork
2025-01-30 0:06 ` [PATCH v4 0/8] PMU Support for per-engine-class activity Umesh Nerlige Ramappa
16 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2025-01-29 12:36 UTC (permalink / raw)
To: Riana Tauro; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 6636 bytes --]
== Series Details ==
Series: PMU Support for per-engine-class activity (rev2)
URL : https://patchwork.freedesktop.org/series/143138/
State : failure
== Summary ==
CI Bug Log - changes from xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3_BAT -> xe-pw-143138v2_BAT
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-143138v2_BAT absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-143138v2_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (8 -> 8)
------------------------------
Additional (1): bat-bmg-2
Missing (1): bat-adlp-vm
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-143138v2_BAT:
### IGT changes ###
#### Possible regressions ####
* igt@core_hotunplug@unbind-rebind:
- bat-atsm-2: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/bat-atsm-2/igt@core_hotunplug@unbind-rebind.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/bat-atsm-2/igt@core_hotunplug@unbind-rebind.html
Known issues
------------
Here are the changes found in xe-pw-143138v2_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@nullptr:
- bat-bmg-2: NOTRUN -> [SKIP][3] ([Intel XE#2134]) +4 other tests skip
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/bat-bmg-2/igt@fbdev@nullptr.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-bmg-2: NOTRUN -> [SKIP][4] ([Intel XE#2233])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/bat-bmg-2/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- bat-bmg-2: NOTRUN -> [SKIP][5] ([Intel XE#2489] / [Intel XE#3419]) +13 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/bat-bmg-2/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
* igt@kms_flip@basic-flip-vs-modeset:
- bat-bmg-2: NOTRUN -> [SKIP][6] ([Intel XE#2482]) +3 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/bat-bmg-2/igt@kms_flip@basic-flip-vs-modeset.html
* igt@kms_frontbuffer_tracking@basic:
- bat-bmg-2: NOTRUN -> [SKIP][7] ([Intel XE#2434] / [Intel XE#2548])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/bat-bmg-2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_psr@psr-sprite-plane-onoff:
- bat-bmg-2: NOTRUN -> [SKIP][8] ([Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/bat-bmg-2/igt@kms_psr@psr-sprite-plane-onoff.html
* igt@sriov_basic@enable-vfs-autoprobe-off:
- bat-bmg-2: NOTRUN -> [SKIP][9] ([Intel XE#1091] / [Intel XE#2849]) +1 other test skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/bat-bmg-2/igt@sriov_basic@enable-vfs-autoprobe-off.html
* igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit:
- bat-bmg-2: NOTRUN -> [SKIP][10] ([Intel XE#2229])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/bat-bmg-2/igt@xe_live_ktest@xe_bo@xe_ccs_migrate_kunit.html
* igt@xe_pat@pat-index-xehpc:
- bat-bmg-2: NOTRUN -> [SKIP][11] ([Intel XE#1420])
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/bat-bmg-2/igt@xe_pat@pat-index-xehpc.html
* igt@xe_pat@pat-index-xelp:
- bat-bmg-2: NOTRUN -> [SKIP][12] ([Intel XE#2245])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/bat-bmg-2/igt@xe_pat@pat-index-xelp.html
* igt@xe_pat@pat-index-xelpg:
- bat-bmg-2: NOTRUN -> [SKIP][13] ([Intel XE#2236])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/bat-bmg-2/igt@xe_pat@pat-index-xelpg.html
* igt@xe_sriov_flr@flr-vf1-clear:
- bat-bmg-2: NOTRUN -> [SKIP][14] ([Intel XE#3342])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/bat-bmg-2/igt@xe_sriov_flr@flr-vf1-clear.html
#### Possible fixes ####
* igt@xe_exec_basic@twice-bindexecqueue-rebind:
- bat-adlp-vf: [DMESG-WARN][15] ([Intel XE#3970] / [Intel XE#4078]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/bat-adlp-vf/igt@xe_exec_basic@twice-bindexecqueue-rebind.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/bat-adlp-vf/igt@xe_exec_basic@twice-bindexecqueue-rebind.html
[Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
[Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
[Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
[Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
[Intel XE#2233]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2233
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2236]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2236
[Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
[Intel XE#2434]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2434
[Intel XE#2482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2482
[Intel XE#2489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2489
[Intel XE#2548]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2548
[Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
[Intel XE#3419]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3419
[Intel XE#3970]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3970
[Intel XE#4078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4078
Build changes
-------------
* Linux: xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3 -> xe-pw-143138v2
IGT_8214: 7a8a3744466fbb89127201077f030033c72df948 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3: 683350734da38bc7332a3b87c9f2faf6bbeeb5a3
xe-pw-143138v2: 143138v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/index.html
[-- Attachment #2: Type: text/html, Size: 7493 bytes --]
^ permalink raw reply [flat|nested] 45+ messages in thread* ✗ Xe.CI.Full: failure for PMU Support for per-engine-class activity (rev2)
2025-01-29 10:16 [PATCH v4 0/8] PMU Support for per-engine-class activity Riana Tauro
` (14 preceding siblings ...)
2025-01-29 12:36 ` ✗ Xe.CI.BAT: failure " Patchwork
@ 2025-01-29 21:35 ` Patchwork
2025-01-30 0:06 ` [PATCH v4 0/8] PMU Support for per-engine-class activity Umesh Nerlige Ramappa
16 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2025-01-29 21:35 UTC (permalink / raw)
To: Riana Tauro; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 150441 bytes --]
== Series Details ==
Series: PMU Support for per-engine-class activity (rev2)
URL : https://patchwork.freedesktop.org/series/143138/
State : failure
== Summary ==
CI Bug Log - changes from xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3_full -> xe-pw-143138v2_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-143138v2_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-143138v2_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-143138v2_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_mmap_write_crc@main:
- shard-adlp: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-4/igt@kms_mmap_write_crc@main.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-6/igt@kms_mmap_write_crc@main.html
* igt@xe_fault_injection@inject-fault-probe-function-wait_for_lmem_ready:
- shard-adlp: [PASS][3] -> [ABORT][4] +3 other tests abort
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-2/igt@xe_fault_injection@inject-fault-probe-function-wait_for_lmem_ready.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-9/igt@xe_fault_injection@inject-fault-probe-function-wait_for_lmem_ready.html
Known issues
------------
Here are the changes found in xe-pw-143138v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_setmaster@master-drop-set-user:
- shard-bmg: [PASS][5] -> [FAIL][6] ([Intel XE#3249])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@core_setmaster@master-drop-set-user.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@core_setmaster@master-drop-set-user.html
* igt@fbdev@info:
- shard-bmg: [PASS][7] -> [SKIP][8] ([Intel XE#2134]) +1 other test skip
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-7/igt@fbdev@info.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@fbdev@info.html
* igt@fbdev@unaligned-read:
- shard-dg2-set2: NOTRUN -> [SKIP][9] ([Intel XE#2134])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@fbdev@unaligned-read.html
* igt@fbdev@unaligned-write:
- shard-dg2-set2: [PASS][10] -> [SKIP][11] ([Intel XE#2134])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@fbdev@unaligned-write.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@fbdev@unaligned-write.html
* igt@kms_atomic@plane-invalid-params-fence:
- shard-dg2-set2: [PASS][12] -> [SKIP][13] ([Intel XE#2423] / [i915#2575]) +72 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_atomic@plane-invalid-params-fence.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_atomic@plane-invalid-params-fence.html
* igt@kms_big_fb@4-tiled-addfb-size-overflow:
- shard-dg2-set2: [PASS][14] -> [SKIP][15] ([Intel XE#2136]) +23 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_big_fb@4-tiled-addfb-size-overflow.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_big_fb@4-tiled-addfb-size-overflow.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-adlp: NOTRUN -> [SKIP][16] ([Intel XE#1124]) +1 other test skip
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@linear-16bpp-rotate-270:
- shard-lnl: NOTRUN -> [SKIP][17] ([Intel XE#1407])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_big_fb@linear-16bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-addfb:
- shard-bmg: [PASS][18] -> [SKIP][19] ([Intel XE#2136]) +19 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_big_fb@x-tiled-addfb.html
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_big_fb@x-tiled-addfb.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
- shard-dg2-set2: NOTRUN -> [SKIP][20] ([Intel XE#2136]) +13 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- shard-dg2-set2: NOTRUN -> [SKIP][21] ([Intel XE#1124]) +1 other test skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-lnl: NOTRUN -> [SKIP][22] ([Intel XE#1124])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
- shard-lnl: NOTRUN -> [SKIP][23] ([Intel XE#2191])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
* igt@kms_ccs@bad-pixel-format-yf-tiled-ccs:
- shard-lnl: NOTRUN -> [SKIP][24] ([Intel XE#2887]) +2 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-d-hdmi-a-3:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#2652] / [Intel XE#787]) +7 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-d-hdmi-a-3.html
* igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-2:
- shard-dg2-set2: NOTRUN -> [SKIP][26] ([Intel XE#455] / [Intel XE#787]) +21 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-432/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-2.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-d-dp-2:
- shard-dg2-set2: NOTRUN -> [ABORT][27] ([Intel XE#2625])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-432/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-d-dp-2.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs:
- shard-lnl: NOTRUN -> [SKIP][28] ([Intel XE#3432])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs@pipe-b-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][29] ([Intel XE#787]) +153 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs@pipe-b-dp-4.html
* igt@kms_cdclk@mode-transition@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][30] ([Intel XE#314]) +3 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html
* igt@kms_chamelium_color@ctm-negative:
- shard-adlp: NOTRUN -> [SKIP][31] ([Intel XE#306])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-2/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_edid@dp-edid-read:
- shard-lnl: NOTRUN -> [SKIP][32] ([Intel XE#373])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_chamelium_edid@dp-edid-read.html
* igt@kms_content_protection@atomic@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][33] ([Intel XE#1178])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_content_protection@atomic@pipe-a-dp-2.html
* igt@kms_content_protection@lic-type-0@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [FAIL][34] ([Intel XE#3304])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_content_protection@lic-type-0@pipe-a-dp-4.html
* igt@kms_content_protection@srm@pipe-a-dp-2:
- shard-dg2-set2: NOTRUN -> [FAIL][35] ([Intel XE#1178])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-432/igt@kms_content_protection@srm@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-lnl: NOTRUN -> [SKIP][36] ([Intel XE#2321])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x32:
- shard-lnl: NOTRUN -> [SKIP][37] ([Intel XE#1424])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
* igt@kms_cursor_crc@cursor-suspend:
- shard-bmg: [PASS][38] -> [DMESG-WARN][39] ([Intel XE#4172]) +10 other tests dmesg-warn
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-7/igt@kms_cursor_crc@cursor-suspend.html
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-1/igt@kms_cursor_crc@cursor-suspend.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-lnl: NOTRUN -> [SKIP][40] ([Intel XE#309])
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-bmg: [PASS][41] -> [SKIP][42] ([Intel XE#2291])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions:
- shard-dg2-set2: [PASS][43] -> [INCOMPLETE][44] ([Intel XE#3226])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-463/igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-434/igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
- shard-bmg: [PASS][45] -> [DMESG-WARN][46] ([Intel XE#877])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-lnl: NOTRUN -> [SKIP][47] ([Intel XE#323])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3:
- shard-bmg: NOTRUN -> [FAIL][48] ([Intel XE#3321]) +2 other tests fail
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-7/igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3.html
* igt@kms_flip@2x-flip-vs-panning:
- shard-lnl: NOTRUN -> [SKIP][49] ([Intel XE#1421])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_flip@2x-flip-vs-panning.html
* igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset:
- shard-bmg: [PASS][50] -> [SKIP][51] ([Intel XE#2316])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-adlp: [PASS][52] -> [DMESG-WARN][53] ([Intel XE#2953]) +2 other tests dmesg-warn
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-4/igt@kms_flip@flip-vs-suspend-interruptible.html
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-6/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset@d-hdmi-a3:
- shard-bmg: NOTRUN -> [DMESG-WARN][54] ([Intel XE#4172]) +5 other tests dmesg-warn
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset@d-hdmi-a3.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
- shard-lnl: NOTRUN -> [SKIP][55] ([Intel XE#1401] / [Intel XE#1745])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][56] ([Intel XE#1401])
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][57] ([Intel XE#2293]) +5 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
- shard-dg2-set2: NOTRUN -> [SKIP][58] ([Intel XE#455]) +3 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-432/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling:
- shard-dg2-set2: [PASS][59] -> [SKIP][60] ([Intel XE#2136] / [Intel XE#2351]) +6 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling.html
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render:
- shard-lnl: NOTRUN -> [SKIP][61] ([Intel XE#656]) +4 other tests skip
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render:
- shard-lnl: NOTRUN -> [SKIP][62] ([Intel XE#651]) +2 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-msflip-blt:
- shard-adlp: NOTRUN -> [SKIP][63] ([Intel XE#656]) +2 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-msflip-blt.html
- shard-dg2-set2: NOTRUN -> [SKIP][64] ([Intel XE#651]) +1 other test skip
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc:
- shard-dg2-set2: NOTRUN -> [SKIP][65] ([Intel XE#2136] / [Intel XE#2351]) +4 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcdrrs-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt:
- shard-adlp: NOTRUN -> [SKIP][66] ([Intel XE#653])
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff:
- shard-dg2-set2: NOTRUN -> [SKIP][67] ([Intel XE#653])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html
* igt@kms_hdmi_inject@inject-audio:
- shard-lnl: NOTRUN -> [SKIP][68] ([Intel XE#1470] / [Intel XE#2853])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_hdr@static-toggle-suspend:
- shard-lnl: NOTRUN -> [SKIP][69] ([Intel XE#1503])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-lnl: NOTRUN -> [SKIP][70] ([Intel XE#2934])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_lease@possible-crtcs-filtering:
- shard-bmg: [PASS][71] -> [SKIP][72] ([Intel XE#2423]) +79 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-7/igt@kms_lease@possible-crtcs-filtering.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_lease@possible-crtcs-filtering.html
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-2:
- shard-dg2-set2: NOTRUN -> [ABORT][73] ([Intel XE#1033] / [Intel XE#2625] / [Intel XE#4080])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-432/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-d-hdmi-a-2.html
* igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256:
- shard-dg2-set2: NOTRUN -> [FAIL][74] ([Intel XE#616]) +2 other tests fail
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-466/igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256.html
* igt@kms_plane_lowres@tiling-yf:
- shard-lnl: NOTRUN -> [SKIP][75] ([Intel XE#599])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_multiple@tiling-4:
- shard-adlp: NOTRUN -> [SKIP][76] ([Intel XE#455])
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-6/igt@kms_plane_multiple@tiling-4.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c:
- shard-lnl: NOTRUN -> [SKIP][77] ([Intel XE#2763]) +3 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-pixel-format@pipe-c.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b:
- shard-dg2-set2: NOTRUN -> [SKIP][78] ([Intel XE#2763]) +2 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d:
- shard-dg2-set2: NOTRUN -> [SKIP][79] ([Intel XE#2763] / [Intel XE#455])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a:
- shard-bmg: NOTRUN -> [SKIP][80] ([Intel XE#2763]) +7 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a.html
* igt@kms_pm_rpm@basic-rte:
- shard-bmg: [PASS][81] -> [SKIP][82] ([Intel XE#2446]) +1 other test skip
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_pm_rpm@basic-rte.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_pm_rpm@basic-rte.html
* igt@kms_pm_rpm@i2c:
- shard-dg2-set2: [PASS][83] -> [SKIP][84] ([Intel XE#2446]) +2 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_pm_rpm@i2c.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_pm_rpm@i2c.html
* igt@kms_pm_rpm@system-suspend-modeset:
- shard-dg2-set2: NOTRUN -> [SKIP][85] ([Intel XE#2446]) +1 other test skip
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_pm_rpm@system-suspend-modeset.html
* igt@kms_psr@fbc-pr-dpms:
- shard-lnl: NOTRUN -> [SKIP][86] ([Intel XE#1406]) +1 other test skip
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_psr@fbc-pr-dpms.html
* igt@kms_psr@pr-primary-page-flip:
- shard-dg2-set2: NOTRUN -> [SKIP][87] ([Intel XE#2850] / [Intel XE#929])
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_psr@pr-primary-page-flip.html
* igt@kms_psr@psr-basic:
- shard-adlp: NOTRUN -> [SKIP][88] ([Intel XE#2850] / [Intel XE#929]) +1 other test skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-2/igt@kms_psr@psr-basic.html
* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-lnl: NOTRUN -> [SKIP][89] ([Intel XE#1435])
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_setmode@invalid-clone-exclusive-crtc.html
* igt@kms_tv_load_detect@load-detect:
- shard-lnl: NOTRUN -> [SKIP][90] ([Intel XE#330])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_tv_load_detect@load-detect.html
* igt@kms_vrr@flipline:
- shard-dg2-set2: NOTRUN -> [SKIP][91] ([Intel XE#2423] / [i915#2575]) +13 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_vrr@flipline.html
* igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute:
- shard-dg2-set2: NOTRUN -> [SKIP][92] ([Intel XE#1280] / [Intel XE#455])
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-432/igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute.html
* igt@xe_eudebug@multigpu-basic-client-many:
- shard-lnl: NOTRUN -> [SKIP][93] ([Intel XE#2905])
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@xe_eudebug@multigpu-basic-client-many.html
* igt@xe_evict@evict-beng-small-external:
- shard-adlp: NOTRUN -> [SKIP][94] ([Intel XE#261] / [Intel XE#688])
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-6/igt@xe_evict@evict-beng-small-external.html
* igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-samefd:
- shard-lnl: NOTRUN -> [SKIP][95] ([Intel XE#688]) +1 other test skip
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-samefd.html
* igt@xe_exec_basic@many-null-rebind:
- shard-dg2-set2: [PASS][96] -> [SKIP][97] ([Intel XE#1130]) +126 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@xe_exec_basic@many-null-rebind.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@xe_exec_basic@many-null-rebind.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-rebind:
- shard-dg2-set2: [PASS][98] -> [SKIP][99] ([Intel XE#1392]) +1 other test skip
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-rebind.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-rebind.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate-race:
- shard-adlp: NOTRUN -> [SKIP][100] ([Intel XE#1392])
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-2/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate-race.html
* igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race:
- shard-lnl: NOTRUN -> [SKIP][101] ([Intel XE#1392])
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race.html
* igt@xe_exec_fault_mode@twice-userptr-rebind-imm:
- shard-dg2-set2: NOTRUN -> [SKIP][102] ([Intel XE#1130]) +21 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@xe_exec_fault_mode@twice-userptr-rebind-imm.html
* igt@xe_exec_threads@threads-bal-userptr-invalidate:
- shard-dg2-set2: [PASS][103] -> [DMESG-WARN][104] ([Intel XE#1033])
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-434/igt@xe_exec_threads@threads-bal-userptr-invalidate.html
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-434/igt@xe_exec_threads@threads-bal-userptr-invalidate.html
* igt@xe_fault_injection@inject-fault-probe-function-xe_ggtt_init_early:
- shard-bmg: [PASS][105] -> [SKIP][106] ([Intel XE#1130]) +176 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@xe_fault_injection@inject-fault-probe-function-xe_ggtt_init_early.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@xe_fault_injection@inject-fault-probe-function-xe_ggtt_init_early.html
* igt@xe_live_ktest@xe_migrate:
- shard-bmg: [PASS][107] -> [SKIP][108] ([Intel XE#1192]) +1 other test skip
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-4/igt@xe_live_ktest@xe_migrate.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-2/igt@xe_live_ktest@xe_migrate.html
* igt@xe_media_fill@media-fill:
- shard-lnl: NOTRUN -> [SKIP][109] ([Intel XE#560])
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@xe_media_fill@media-fill.html
* igt@xe_module_load@many-reload:
- shard-bmg: [PASS][110] -> [FAIL][111] ([Intel XE#3546])
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-7/igt@xe_module_load@many-reload.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@xe_module_load@many-reload.html
* igt@xe_module_load@reload-no-display:
- shard-dg2-set2: [PASS][112] -> [FAIL][113] ([Intel XE#3546])
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@xe_module_load@reload-no-display.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@xe_module_load@reload-no-display.html
* igt@xe_noexec_ping_pong:
- shard-adlp: NOTRUN -> [SKIP][114] ([Intel XE#379])
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-6/igt@xe_noexec_ping_pong.html
* igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p:
- shard-dg2-set2: NOTRUN -> [FAIL][115] ([Intel XE#1173])
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@xe_peer2peer@write@write-gpua-vram01-gpub-system-p2p.html
* igt@xe_pm@s2idle-vm-bind-unbind-all:
- shard-dg2-set2: [PASS][116] -> [ABORT][117] ([Intel XE#1358] / [Intel XE#1794])
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@xe_pm@s2idle-vm-bind-unbind-all.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-432/igt@xe_pm@s2idle-vm-bind-unbind-all.html
* igt@xe_pm@s4-mocs:
- shard-adlp: [PASS][118] -> [ABORT][119] ([Intel XE#1358] / [Intel XE#1794]) +1 other test abort
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-3/igt@xe_pm@s4-mocs.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-9/igt@xe_pm@s4-mocs.html
#### Possible fixes ####
* igt@core_getversion@basic:
- shard-dg2-set2: [FAIL][120] ([Intel XE#3440]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@core_getversion@basic.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@core_getversion@basic.html
* igt@fbdev@eof:
- shard-dg2-set2: [SKIP][122] ([Intel XE#2134]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@fbdev@eof.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-466/igt@fbdev@eof.html
* igt@fbdev@nullptr:
- shard-bmg: [SKIP][124] ([Intel XE#2134]) -> [PASS][125] +1 other test pass
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@fbdev@nullptr.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@fbdev@nullptr.html
* igt@kms_3d:
- shard-dg2-set2: [SKIP][126] ([Intel XE#2423]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_3d.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_3d.html
* igt@kms_atomic_transition@modeset-transition-nonblocking-fencing:
- shard-dg2-set2: [SKIP][128] ([Intel XE#2423] / [i915#2575]) -> [PASS][129] +84 other tests pass
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing.html
* igt@kms_big_fb@linear-16bpp-rotate-180:
- shard-bmg: [SKIP][130] ([Intel XE#2136]) -> [PASS][131] +18 other tests pass
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_big_fb@linear-16bpp-rotate-180.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_big_fb@linear-16bpp-rotate-180.html
* igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
- shard-dg2-set2: [DMESG-WARN][132] -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-434/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-434/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-bmg: [SKIP][134] ([Intel XE#2291]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_display_modes@extended-mode-basic@pipe-b-hdmi-a-3-pipe-d-dp-2:
- shard-bmg: [DMESG-WARN][136] ([Intel XE#877]) -> [PASS][137] +2 other tests pass
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-5/igt@kms_display_modes@extended-mode-basic@pipe-b-hdmi-a-3-pipe-d-dp-2.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-1/igt@kms_display_modes@extended-mode-basic@pipe-b-hdmi-a-3-pipe-d-dp-2.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-dp2-hdmi-a3:
- shard-bmg: [FAIL][138] ([Intel XE#3321]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-dp2-hdmi-a3.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-dp2-hdmi-a3.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-bmg: [SKIP][140] ([Intel XE#2423]) -> [PASS][141] +67 other tests pass
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_flip@2x-plain-flip-fb-recreate.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_flip@2x-plain-flip-fb-recreate.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-bmg: [FAIL][142] ([Intel XE#2882]) -> [PASS][143] +1 other test pass
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-2/igt@kms_flip@plain-flip-fb-recreate.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-4/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc:
- shard-adlp: [DMESG-WARN][144] ([Intel XE#4173]) -> [PASS][145] +6 other tests pass
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff:
- shard-dg2-set2: [SKIP][146] ([Intel XE#2136] / [Intel XE#2351]) -> [PASS][147] +5 other tests pass
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc:
- shard-dg2-set2: [SKIP][148] ([Intel XE#2136]) -> [PASS][149] +20 other tests pass
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
* igt@kms_plane@plane-panning-bottom-right-suspend:
- shard-bmg: [DMESG-WARN][150] ([Intel XE#4172]) -> [PASS][151] +9 other tests pass
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-5/igt@kms_plane@plane-panning-bottom-right-suspend.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-7/igt@kms_plane@plane-panning-bottom-right-suspend.html
* igt@kms_plane_scaling@plane-upscale-20x20-with-modifiers:
- shard-adlp: [DMESG-WARN][152] -> [PASS][153] +2 other tests pass
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-8/igt@kms_plane_scaling@plane-upscale-20x20-with-modifiers.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-8/igt@kms_plane_scaling@plane-upscale-20x20-with-modifiers.html
* igt@kms_pm_dc@dc5-dpms:
- shard-dg2-set2: [DMESG-WARN][154] ([Intel XE#1033]) -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-434/igt@kms_pm_dc@dc5-dpms.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-434/igt@kms_pm_dc@dc5-dpms.html
* igt@kms_pm_rpm@cursor-dpms:
- shard-dg2-set2: [SKIP][156] ([Intel XE#2446]) -> [PASS][157] +3 other tests pass
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_pm_rpm@cursor-dpms.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-466/igt@kms_pm_rpm@cursor-dpms.html
* igt@kms_pm_rpm@legacy-planes-dpms:
- shard-bmg: [SKIP][158] ([Intel XE#2446]) -> [PASS][159] +2 other tests pass
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_pm_rpm@legacy-planes-dpms.html
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_pm_rpm@legacy-planes-dpms.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1:
- shard-lnl: [FAIL][160] ([Intel XE#899]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-lnl-2/igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1.html
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@kms_universal_plane@cursor-fb-leak@pipe-c-edp-1.html
* igt@kms_vblank@ts-continuation-dpms-suspend:
- shard-adlp: [DMESG-WARN][162] ([Intel XE#2953]) -> [PASS][163] +3 other tests pass
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-3/igt@kms_vblank@ts-continuation-dpms-suspend.html
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-4/igt@kms_vblank@ts-continuation-dpms-suspend.html
* igt@xe_exec_balancer@many-parallel-userptr-invalidate:
- shard-bmg: [SKIP][164] ([Intel XE#1130]) -> [PASS][165] +168 other tests pass
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@xe_exec_balancer@many-parallel-userptr-invalidate.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@xe_exec_balancer@many-parallel-userptr-invalidate.html
* igt@xe_exec_balancer@once-parallel-rebind:
- shard-dg2-set2: [SKIP][166] ([Intel XE#1130]) -> [PASS][167] +141 other tests pass
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@xe_exec_balancer@once-parallel-rebind.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@xe_exec_balancer@once-parallel-rebind.html
* igt@xe_exec_basic@multigpu-no-exec-basic-defer-bind:
- shard-dg2-set2: [SKIP][168] ([Intel XE#1392]) -> [PASS][169] +1 other test pass
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-basic-defer-bind.html
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@xe_exec_basic@multigpu-no-exec-basic-defer-bind.html
* igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit:
- shard-bmg: [FAIL][170] ([Intel XE#1999]) -> [PASS][171] +2 other tests pass
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit.html
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit.html
* igt@xe_module_load@load:
- shard-adlp: ([PASS][172], [SKIP][173], [PASS][174], [PASS][175], [PASS][176], [PASS][177], [PASS][178], [PASS][179], [PASS][180], [PASS][181], [PASS][182], [PASS][183], [PASS][184], [PASS][185], [PASS][186], [PASS][187], [PASS][188], [PASS][189], [PASS][190], [PASS][191], [PASS][192], [PASS][193], [PASS][194], [PASS][195], [PASS][196], [PASS][197]) ([Intel XE#378]) -> ([PASS][198], [PASS][199], [PASS][200], [PASS][201], [PASS][202], [PASS][203], [PASS][204], [PASS][205], [PASS][206], [PASS][207], [PASS][208], [PASS][209], [PASS][210], [PASS][211], [PASS][212], [PASS][213], [PASS][214], [PASS][215], [PASS][216], [PASS][217], [PASS][218], [PASS][219], [PASS][220], [PASS][221], [PASS][222])
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-3/igt@xe_module_load@load.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-2/igt@xe_module_load@load.html
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-2/igt@xe_module_load@load.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-4/igt@xe_module_load@load.html
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-2/igt@xe_module_load@load.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-2/igt@xe_module_load@load.html
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-2/igt@xe_module_load@load.html
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-4/igt@xe_module_load@load.html
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-9/igt@xe_module_load@load.html
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-4/igt@xe_module_load@load.html
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-4/igt@xe_module_load@load.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-9/igt@xe_module_load@load.html
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-9/igt@xe_module_load@load.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-8/igt@xe_module_load@load.html
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-8/igt@xe_module_load@load.html
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-8/igt@xe_module_load@load.html
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-8/igt@xe_module_load@load.html
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-9/igt@xe_module_load@load.html
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-6/igt@xe_module_load@load.html
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-6/igt@xe_module_load@load.html
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-6/igt@xe_module_load@load.html
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-6/igt@xe_module_load@load.html
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-3/igt@xe_module_load@load.html
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-3/igt@xe_module_load@load.html
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-3/igt@xe_module_load@load.html
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-3/igt@xe_module_load@load.html
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-9/igt@xe_module_load@load.html
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-9/igt@xe_module_load@load.html
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-3/igt@xe_module_load@load.html
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-6/igt@xe_module_load@load.html
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-9/igt@xe_module_load@load.html
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-9/igt@xe_module_load@load.html
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-9/igt@xe_module_load@load.html
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-6/igt@xe_module_load@load.html
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-6/igt@xe_module_load@load.html
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-6/igt@xe_module_load@load.html
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-4/igt@xe_module_load@load.html
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-2/igt@xe_module_load@load.html
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-4/igt@xe_module_load@load.html
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-2/igt@xe_module_load@load.html
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-4/igt@xe_module_load@load.html
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-4/igt@xe_module_load@load.html
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-3/igt@xe_module_load@load.html
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-3/igt@xe_module_load@load.html
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-3/igt@xe_module_load@load.html
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-2/igt@xe_module_load@load.html
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-2/igt@xe_module_load@load.html
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-2/igt@xe_module_load@load.html
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-8/igt@xe_module_load@load.html
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-8/igt@xe_module_load@load.html
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-8/igt@xe_module_load@load.html
* igt@xe_pm@s3-mocs:
- shard-dg2-set2: [DMESG-WARN][223] ([Intel XE#1033] / [Intel XE#569]) -> [PASS][224]
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-434/igt@xe_pm@s3-mocs.html
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-434/igt@xe_pm@s3-mocs.html
* igt@xe_pm@s4-d3hot-basic-exec:
- shard-lnl: [ABORT][225] ([Intel XE#1358] / [Intel XE#1607]) -> [PASS][226]
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-lnl-2/igt@xe_pm@s4-d3hot-basic-exec.html
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-lnl-8/igt@xe_pm@s4-d3hot-basic-exec.html
* igt@xe_pm@s4-vm-bind-unbind-all:
- shard-adlp: [ABORT][227] ([Intel XE#1358] / [Intel XE#1607] / [Intel XE#1794]) -> [PASS][228] +1 other test pass
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-adlp-9/igt@xe_pm@s4-vm-bind-unbind-all.html
[228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-adlp-6/igt@xe_pm@s4-vm-bind-unbind-all.html
- shard-dg2-set2: [ABORT][229] ([Intel XE#1358] / [Intel XE#1794]) -> [PASS][230]
[229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@xe_pm@s4-vm-bind-unbind-all.html
[230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@xe_pm@s4-vm-bind-unbind-all.html
#### Warnings ####
* igt@kms_async_flips@invalid-async-flip:
- shard-dg2-set2: [SKIP][231] ([Intel XE#2423] / [i915#2575]) -> [SKIP][232] ([Intel XE#873])
[231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_async_flips@invalid-async-flip.html
[232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_async_flips@invalid-async-flip.html
* igt@kms_async_flips@invalid-async-flip-atomic:
- shard-dg2-set2: [SKIP][233] ([Intel XE#3768]) -> [SKIP][234] ([Intel XE#2423] / [i915#2575])
[233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@kms_async_flips@invalid-async-flip-atomic.html
[234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_async_flips@invalid-async-flip-atomic.html
- shard-bmg: [SKIP][235] ([Intel XE#3768]) -> [SKIP][236] ([Intel XE#2423])
[235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-4/igt@kms_async_flips@invalid-async-flip-atomic.html
[236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_async_flips@invalid-async-flip-atomic.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-270:
- shard-dg2-set2: [SKIP][237] ([Intel XE#316]) -> [SKIP][238] ([Intel XE#2136] / [Intel XE#2351])
[237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html
[238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-270:
- shard-dg2-set2: [SKIP][239] ([Intel XE#2136]) -> [SKIP][240] ([Intel XE#316]) +1 other test skip
[239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
[240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-64bpp-rotate-90:
- shard-bmg: [SKIP][241] ([Intel XE#2136]) -> [SKIP][242] ([Intel XE#2327]) +5 other tests skip
[241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
[242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@linear-16bpp-rotate-90:
- shard-dg2-set2: [SKIP][243] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][244] ([Intel XE#316])
[243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_big_fb@linear-16bpp-rotate-90.html
[244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_big_fb@linear-16bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-bmg: [SKIP][245] ([Intel XE#2327]) -> [SKIP][246] ([Intel XE#2136]) +1 other test skip
[245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-7/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
[246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-270:
- shard-dg2-set2: [SKIP][247] ([Intel XE#316]) -> [SKIP][248] ([Intel XE#2136]) +3 other tests skip
[247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
[248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-90:
- shard-dg2-set2: [SKIP][249] ([Intel XE#1124]) -> [SKIP][250] ([Intel XE#2136]) +7 other tests skip
[249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@kms_big_fb@y-tiled-16bpp-rotate-90.html
[250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_big_fb@y-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-180:
- shard-dg2-set2: [SKIP][251] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][252] ([Intel XE#1124])
[251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
[252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-466/igt@kms_big_fb@y-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-bmg: [SKIP][253] ([Intel XE#1124]) -> [SKIP][254] ([Intel XE#2136]) +8 other tests skip
[253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
[254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb:
- shard-bmg: [SKIP][255] ([Intel XE#2136]) -> [SKIP][256] ([Intel XE#2328])
[255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_big_fb@y-tiled-addfb.html
[256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_big_fb@y-tiled-addfb.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-dg2-set2: [SKIP][257] ([Intel XE#1124]) -> [SKIP][258] ([Intel XE#2136] / [Intel XE#2351]) +1 other test skip
[257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
[258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
- shard-bmg: [SKIP][259] ([Intel XE#2136]) -> [SKIP][260] ([Intel XE#1124]) +9 other tests skip
[259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
[260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-bmg: [SKIP][261] ([Intel XE#607]) -> [SKIP][262] ([Intel XE#2136])
[261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
[262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-addfb-size-overflow:
- shard-dg2-set2: [SKIP][263] ([Intel XE#2136]) -> [SKIP][264] ([Intel XE#610])
[263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
[264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-dg2-set2: [SKIP][265] ([Intel XE#2136]) -> [SKIP][266] ([Intel XE#1124]) +4 other tests skip
[265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
[266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-466/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p:
- shard-bmg: [SKIP][267] ([Intel XE#2423]) -> [SKIP][268] ([Intel XE#2314] / [Intel XE#2894])
[267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html
[268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html
* igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p:
- shard-dg2-set2: [SKIP][269] ([Intel XE#2423] / [i915#2575]) -> [SKIP][270] ([Intel XE#2191]) +1 other test skip
[269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html
[270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html
* igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p:
- shard-dg2-set2: [SKIP][271] ([Intel XE#2191]) -> [SKIP][272] ([Intel XE#2423] / [i915#2575]) +1 other test skip
[271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html
[272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html
* igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p:
- shard-bmg: [SKIP][273] ([Intel XE#2314] / [Intel XE#2894]) -> [SKIP][274] ([Intel XE#2423]) +2 other tests skip
[273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-7/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html
[274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html
* igt@kms_bw@linear-tiling-1-displays-2560x1440p:
- shard-dg2-set2: [SKIP][275] ([Intel XE#367]) -> [SKIP][276] ([Intel XE#2423] / [i915#2575]) +1 other test skip
[275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html
[276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html
* igt@kms_bw@linear-tiling-4-displays-2160x1440p:
- shard-bmg: [SKIP][277] ([Intel XE#2423]) -> [SKIP][278] ([Intel XE#367]) +3 other tests skip
[277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html
[278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html
* igt@kms_bw@linear-tiling-4-displays-2560x1440p:
- shard-dg2-set2: [SKIP][279] ([Intel XE#2423] / [i915#2575]) -> [SKIP][280] ([Intel XE#367]) +3 other tests skip
[279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html
[280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-466/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs:
- shard-bmg: [SKIP][281] ([Intel XE#2887]) -> [SKIP][282] ([Intel XE#2136]) +17 other tests skip
[281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-4/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs.html
[282]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
- shard-bmg: [SKIP][283] ([Intel XE#2136]) -> [SKIP][284] ([Intel XE#2652] / [Intel XE#787]) +1 other test skip
[283]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
[284]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs:
- shard-bmg: [SKIP][285] ([Intel XE#2136]) -> [SKIP][286] ([Intel XE#2887]) +11 other tests skip
[285]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs.html
[286]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs:
- shard-dg2-set2: [SKIP][287] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][288] ([Intel XE#455] / [Intel XE#787]) +2 other tests skip
[287]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs.html
[288]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
- shard-dg2-set2: [SKIP][289] ([Intel XE#2136]) -> [SKIP][290] ([Intel XE#2907])
[289]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
[290]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-432/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs:
- shard-dg2-set2: [SKIP][291] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][292] ([Intel XE#2136]) +7 other tests skip
[291]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs.html
[292]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc:
- shard-dg2-set2: [SKIP][293] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][294] ([Intel XE#2136] / [Intel XE#2351]) +3 other tests skip
[293]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc.html
[294]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
- shard-bmg: [SKIP][295] ([Intel XE#3432]) -> [SKIP][296] ([Intel XE#2136]) +1 other test skip
[295]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
[296]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc:
- shard-dg2-set2: [SKIP][297] ([Intel XE#2136]) -> [ABORT][298] ([Intel XE#2625])
[297]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc.html
[298]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-432/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
- shard-dg2-set2: [SKIP][299] ([Intel XE#3442]) -> [SKIP][300] ([Intel XE#2136])
[299]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
[300]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-ccs:
- shard-bmg: [SKIP][301] ([Intel XE#2136]) -> [SKIP][302] ([Intel XE#3432]) +1 other test skip
[301]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs.html
[302]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
- shard-dg2-set2: [SKIP][303] ([Intel XE#2907]) -> [SKIP][304] ([Intel XE#2136])
[303]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html
[304]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs:
- shard-dg2-set2: [SKIP][305] ([Intel XE#2136]) -> [SKIP][306] ([Intel XE#455] / [Intel XE#787]) +10 other tests skip
[305]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs.html
[306]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs.html
* igt@kms_cdclk@mode-transition-all-outputs:
- shard-dg2-set2: [SKIP][307] ([Intel XE#314]) -> [SKIP][308] ([Intel XE#2136] / [Intel XE#2351])
[307]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_cdclk@mode-transition-all-outputs.html
[308]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_cdclk@mode-transition-all-outputs.html
* igt@kms_cdclk@plane-scaling:
- shard-bmg: [SKIP][309] ([Intel XE#2724]) -> [SKIP][310] ([Intel XE#2136])
[309]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-4/igt@kms_cdclk@plane-scaling.html
[310]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-bmg: [SKIP][311] ([Intel XE#2423]) -> [SKIP][312] ([Intel XE#2252]) +8 other tests skip
[311]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_chamelium_audio@hdmi-audio-edid.html
[312]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_chamelium_color@ctm-0-25:
- shard-bmg: [SKIP][313] ([Intel XE#2423]) -> [SKIP][314] ([Intel XE#2325])
[313]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_chamelium_color@ctm-0-25.html
[314]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_chamelium_color@ctm-0-25.html
* igt@kms_chamelium_color@degamma:
- shard-bmg: [SKIP][315] ([Intel XE#2325]) -> [SKIP][316] ([Intel XE#2423])
[315]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-7/igt@kms_chamelium_color@degamma.html
[316]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_chamelium_color@degamma.html
* igt@kms_chamelium_edid@dp-edid-resolution-list:
- shard-bmg: [SKIP][317] ([Intel XE#2252]) -> [SKIP][318] ([Intel XE#2423]) +10 other tests skip
[317]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-4/igt@kms_chamelium_edid@dp-edid-resolution-list.html
[318]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_chamelium_edid@dp-edid-resolution-list.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- shard-dg2-set2: [SKIP][319] ([Intel XE#2423] / [i915#2575]) -> [SKIP][320] ([Intel XE#373]) +7 other tests skip
[319]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
[320]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
- shard-dg2-set2: [SKIP][321] ([Intel XE#373]) -> [SKIP][322] ([Intel XE#2423] / [i915#2575]) +6 other tests skip
[321]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
[322]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
* igt@kms_content_protection@atomic:
- shard-bmg: [SKIP][323] ([Intel XE#2423]) -> [FAIL][324] ([Intel XE#1178])
[323]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_content_protection@atomic.html
[324]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@content-type-change:
- shard-bmg: [SKIP][325] ([Intel XE#2341]) -> [SKIP][326] ([Intel XE#2423]) +1 other test skip
[325]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_content_protection@content-type-change.html
[326]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-dg2-set2: [SKIP][327] ([Intel XE#2423] / [i915#2575]) -> [SKIP][328] ([Intel XE#307])
[327]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_content_protection@dp-mst-lic-type-1.html
[328]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-432/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@lic-type-0:
- shard-dg2-set2: [SKIP][329] ([Intel XE#2423] / [i915#2575]) -> [FAIL][330] ([Intel XE#1178])
[329]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_content_protection@lic-type-0.html
[330]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@srm:
- shard-bmg: [FAIL][331] ([Intel XE#1178]) -> [SKIP][332] ([Intel XE#2341])
[331]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_content_protection@srm.html
[332]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent:
- shard-bmg: [SKIP][333] ([Intel XE#2423]) -> [SKIP][334] ([Intel XE#2341]) +1 other test skip
[333]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_content_protection@uevent.html
[334]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-dg2-set2: [SKIP][335] ([Intel XE#308]) -> [SKIP][336] ([Intel XE#2423] / [i915#2575])
[335]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_cursor_crc@cursor-onscreen-512x170.html
[336]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-bmg: [SKIP][337] ([Intel XE#2321]) -> [SKIP][338] ([Intel XE#2423]) +1 other test skip
[337]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_cursor_crc@cursor-random-512x170.html
[338]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-max-size:
- shard-bmg: [SKIP][339] ([Intel XE#2320]) -> [SKIP][340] ([Intel XE#2423]) +3 other tests skip
[339]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-7/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
[340]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
* igt@kms_cursor_crc@cursor-sliding-256x85:
- shard-bmg: [SKIP][341] ([Intel XE#2423]) -> [SKIP][342] ([Intel XE#2320]) +4 other tests skip
[341]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_cursor_crc@cursor-sliding-256x85.html
[342]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_cursor_crc@cursor-sliding-256x85.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-bmg: [SKIP][343] ([Intel XE#2423]) -> [SKIP][344] ([Intel XE#2321]) +3 other tests skip
[343]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_cursor_crc@cursor-sliding-512x512.html
[344]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-bmg: [SKIP][345] ([Intel XE#2423]) -> [SKIP][346] ([Intel XE#2286]) +1 other test skip
[345]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[346]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-dg2-set2: [SKIP][347] ([Intel XE#2423] / [i915#2575]) -> [SKIP][348] ([Intel XE#323])
[347]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
[348]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-bmg: [SKIP][349] ([Intel XE#2423]) -> [SKIP][350] ([Intel XE#2291]) +2 other tests skip
[349]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
[350]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
- shard-bmg: [SKIP][351] ([Intel XE#2291]) -> [SKIP][352] ([Intel XE#2423])
[351]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
[352]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-bmg: [SKIP][353] ([Intel XE#2286]) -> [SKIP][354] ([Intel XE#2423])
[353]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
[354]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-bmg: [SKIP][355] ([Intel XE#1508]) -> [SKIP][356] ([Intel XE#2136])
[355]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-7/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
[356]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-bmg: [SKIP][357] ([Intel XE#2136]) -> [SKIP][358] ([Intel XE#2244])
[357]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_dsc@dsc-fractional-bpp.html
[358]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-dg2-set2: [SKIP][359] ([Intel XE#455]) -> [SKIP][360] ([Intel XE#2136] / [Intel XE#2351]) +1 other test skip
[359]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@kms_dsc@dsc-with-bpc-formats.html
[360]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_fbcon_fbt@fbc:
- shard-bmg: [SKIP][361] ([Intel XE#4156]) -> [SKIP][362] ([Intel XE#2136])
[361]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-4/igt@kms_fbcon_fbt@fbc.html
[362]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_fbcon_fbt@fbc.html
* igt@kms_fbcon_fbt@psr:
- shard-bmg: [SKIP][363] ([Intel XE#776]) -> [SKIP][364] ([Intel XE#2136])
[363]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_fbcon_fbt@psr.html
[364]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_fbcon_fbt@psr.html
* igt@kms_feature_discovery@chamelium:
- shard-dg2-set2: [SKIP][365] ([Intel XE#2423] / [i915#2575]) -> [SKIP][366] ([Intel XE#701])
[365]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_feature_discovery@chamelium.html
[366]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@display-3x:
- shard-dg2-set2: [SKIP][367] ([Intel XE#703]) -> [SKIP][368] ([Intel XE#2423] / [i915#2575])
[367]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_feature_discovery@display-3x.html
[368]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_feature_discovery@display-3x.html
* igt@kms_feature_discovery@dp-mst:
- shard-dg2-set2: [SKIP][369] ([Intel XE#1137]) -> [SKIP][370] ([Intel XE#2423] / [i915#2575])
[369]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_feature_discovery@dp-mst.html
[370]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr1:
- shard-bmg: [SKIP][371] ([Intel XE#2423]) -> [SKIP][372] ([Intel XE#2374])
[371]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_feature_discovery@psr1.html
[372]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_feature_discovery@psr1.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-bmg: [DMESG-WARN][373] ([Intel XE#4172]) -> [SKIP][374] ([Intel XE#2316])
[373]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
[374]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-bmg: [SKIP][375] ([Intel XE#2316]) -> [SKIP][376] ([Intel XE#2423]) +1 other test skip
[375]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
[376]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-bmg: [SKIP][377] ([Intel XE#2316]) -> [FAIL][378] ([Intel XE#3321])
[377]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_flip@2x-flip-vs-expired-vblank.html
[378]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-7/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-bmg: [SKIP][379] ([Intel XE#2423]) -> [SKIP][380] ([Intel XE#2316]) +3 other tests skip
[379]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_flip@2x-modeset-vs-vblank-race.html
[380]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-bmg: [FAIL][381] ([Intel XE#3321]) -> [SKIP][382] ([Intel XE#2423])
[381]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-4/igt@kms_flip@flip-vs-expired-vblank.html
[382]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_flip@flip-vs-expired-vblank.html
- shard-dg2-set2: [FAIL][383] ([Intel XE#301]) -> [SKIP][384] ([Intel XE#2423] / [i915#2575])
[383]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank.html
[384]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling:
- shard-dg2-set2: [SKIP][385] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][386] ([Intel XE#455]) +2 other tests skip
[385]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html
[386]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-466/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-bmg: [SKIP][387] ([Intel XE#2136]) -> [SKIP][388] ([Intel XE#2293] / [Intel XE#2380]) +5 other tests skip
[387]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
[388]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
- shard-dg2-set2: [SKIP][389] ([Intel XE#2136]) -> [SKIP][390] ([Intel XE#455]) +1 other test skip
[389]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
[390]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-432/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
- shard-bmg: [SKIP][391] ([Intel XE#2293] / [Intel XE#2380]) -> [SKIP][392] ([Intel XE#2136]) +2 other tests skip
[391]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
[392]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling:
- shard-dg2-set2: [SKIP][393] ([Intel XE#455]) -> [SKIP][394] ([Intel XE#2136]) +2 other tests skip
[393]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html
[394]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html
* igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-blt:
- shard-bmg: [SKIP][395] ([Intel XE#2136]) -> [SKIP][396] ([Intel XE#2311]) +23 other tests skip
[395]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-blt.html
[396]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render:
- shard-bmg: [SKIP][397] ([Intel XE#2311]) -> [SKIP][398] ([Intel XE#2136]) +23 other tests skip
[397]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html
[398]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][399] ([Intel XE#2312]) -> [SKIP][400] ([Intel XE#2311]) +3 other tests skip
[399]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-mmap-wc.html
[400]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff:
- shard-dg2-set2: [SKIP][401] ([Intel XE#2136]) -> [SKIP][402] ([Intel XE#651]) +14 other tests skip
[401]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff.html
[402]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt:
- shard-bmg: [SKIP][403] ([Intel XE#2312]) -> [SKIP][404] ([Intel XE#2136]) +8 other tests skip
[403]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html
[404]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen:
- shard-dg2-set2: [SKIP][405] ([Intel XE#651]) -> [SKIP][406] ([Intel XE#2136] / [Intel XE#2351]) +7 other tests skip
[405]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html
[406]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt:
- shard-bmg: [SKIP][407] ([Intel XE#2136]) -> [SKIP][408] ([Intel XE#4141]) +9 other tests skip
[407]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html
[408]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt:
- shard-bmg: [SKIP][409] ([Intel XE#4141]) -> [SKIP][410] ([Intel XE#2312])
[409]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt.html
[410]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
- shard-bmg: [SKIP][411] ([Intel XE#2312]) -> [SKIP][412] ([Intel XE#4141]) +2 other tests skip
[411]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
[412]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-tiling-linear:
- shard-bmg: [SKIP][413] ([Intel XE#4141]) -> [SKIP][414] ([Intel XE#2136]) +11 other tests skip
[413]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
[414]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-tiling-linear.html
* igt@kms_frontbuffer_tracking@fbc-tiling-y:
- shard-dg2-set2: [SKIP][415] ([Intel XE#658]) -> [SKIP][416] ([Intel XE#2136] / [Intel XE#2351]) +1 other test skip
[415]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
[416]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-rte:
- shard-dg2-set2: [SKIP][417] ([Intel XE#651]) -> [SKIP][418] ([Intel XE#2136]) +15 other tests skip
[417]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-1p-rte.html
[418]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcdrrs-1p-rte.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt:
- shard-bmg: [SKIP][419] ([Intel XE#2311]) -> [SKIP][420] ([Intel XE#2312]) +3 other tests skip
[419]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt.html
[420]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-pgflip-blt:
- shard-dg2-set2: [SKIP][421] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][422] ([Intel XE#651]) +8 other tests skip
[421]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-pgflip-blt.html
[422]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt:
- shard-dg2-set2: [SKIP][423] ([Intel XE#2136]) -> [SKIP][424] ([Intel XE#653]) +24 other tests skip
[423]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html
[424]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][425] ([Intel XE#2313]) -> [SKIP][426] ([Intel XE#2136]) +23 other tests skip
[425]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
[426]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt:
- shard-bmg: [SKIP][427] ([Intel XE#2312]) -> [SKIP][428] ([Intel XE#2313]) +3 other tests skip
[427]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt.html
[428]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render:
- shard-bmg: [SKIP][429] ([Intel XE#2313]) -> [SKIP][430] ([Intel XE#2312]) +3 other tests skip
[429]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html
[430]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
- shard-bmg: [SKIP][431] ([Intel XE#2136]) -> [SKIP][432] ([Intel XE#2313]) +20 other tests skip
[431]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
[432]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-bmg: [SKIP][433] ([Intel XE#2352]) -> [SKIP][434] ([Intel XE#2136])
[433]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
[434]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt:
- shard-bmg: [SKIP][435] ([Intel XE#2136]) -> [SKIP][436] ([Intel XE#2312]) +17 other tests skip
[435]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt.html
[436]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-dg2-set2: [SKIP][437] ([Intel XE#653]) -> [SKIP][438] ([Intel XE#2136] / [Intel XE#2351]) +6 other tests skip
[437]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
[438]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render:
- shard-dg2-set2: [SKIP][439] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][440] ([Intel XE#653]) +2 other tests skip
[439]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render.html
[440]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-slowdraw:
- shard-dg2-set2: [SKIP][441] ([Intel XE#653]) -> [SKIP][442] ([Intel XE#2136]) +18 other tests skip
[441]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@kms_frontbuffer_tracking@psr-slowdraw.html
[442]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-slowdraw.html
* igt@kms_hdr@invalid-hdr:
- shard-dg2-set2: [SKIP][443] ([Intel XE#455]) -> [SKIP][444] ([Intel XE#2423] / [i915#2575]) +5 other tests skip
[443]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@kms_hdr@invalid-hdr.html
[444]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@static-toggle-suspend:
- shard-bmg: [DMESG-WARN][445] ([Intel XE#4172]) -> [SKIP][446] ([Intel XE#2423])
[445]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_hdr@static-toggle-suspend.html
[446]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_joiner@basic-big-joiner:
- shard-bmg: [SKIP][447] ([Intel XE#346]) -> [SKIP][448] ([Intel XE#2136])
[447]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_joiner@basic-big-joiner.html
[448]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_joiner@basic-big-joiner.html
* igt@kms_joiner@basic-ultra-joiner:
- shard-dg2-set2: [SKIP][449] ([Intel XE#2136]) -> [SKIP][450] ([Intel XE#2927])
[449]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_joiner@basic-ultra-joiner.html
[450]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-466/igt@kms_joiner@basic-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-bmg: [SKIP][451] ([Intel XE#2934]) -> [SKIP][452] ([Intel XE#2136])
[451]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
[452]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-bmg: [SKIP][453] ([Intel XE#2136]) -> [SKIP][454] ([Intel XE#2927])
[453]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_joiner@invalid-modeset-ultra-joiner.html
[454]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_panel_fitting@legacy:
- shard-bmg: [SKIP][455] ([Intel XE#2486]) -> [SKIP][456] ([Intel XE#2423])
[455]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_panel_fitting@legacy.html
[456]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_panel_fitting@legacy.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- shard-dg2-set2: [DMESG-WARN][457] ([Intel XE#1033]) -> [ABORT][458] ([Intel XE#1033] / [Intel XE#2625] / [Intel XE#4080])
[457]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-466/igt@kms_pipe_crc_basic@suspend-read-crc.html
[458]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-432/igt@kms_pipe_crc_basic@suspend-read-crc.html
* igt@kms_plane_cursor@primary:
- shard-dg2-set2: [SKIP][459] ([Intel XE#2423] / [i915#2575]) -> [FAIL][460] ([Intel XE#616])
[459]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_plane_cursor@primary.html
[460]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-466/igt@kms_plane_cursor@primary.html
* igt@kms_plane_lowres@tiling-yf:
- shard-bmg: [SKIP][461] ([Intel XE#2393]) -> [SKIP][462] ([Intel XE#2423])
[461]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_plane_lowres@tiling-yf.html
[462]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_multiple@tiling-y:
- shard-bmg: [SKIP][463] ([Intel XE#2423]) -> [SKIP][464] ([Intel XE#2493])
[463]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_plane_multiple@tiling-y.html
[464]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_plane_multiple@tiling-y.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20:
- shard-dg2-set2: [SKIP][465] ([Intel XE#2423] / [i915#2575]) -> [SKIP][466] ([Intel XE#2763] / [Intel XE#455])
[465]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20.html
[466]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
- shard-bmg: [SKIP][467] ([Intel XE#2763]) -> [SKIP][468] ([Intel XE#2423]) +1 other test skip
[467]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-7/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html
[468]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25:
- shard-dg2-set2: [SKIP][469] ([Intel XE#2763] / [Intel XE#455]) -> [SKIP][470] ([Intel XE#2423] / [i915#2575]) +5 other tests skip
[469]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
[470]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75:
- shard-bmg: [SKIP][471] ([Intel XE#2423]) -> [SKIP][472] ([Intel XE#2763]) +1 other test skip
[471]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html
[472]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html
* igt@kms_pm_backlight@bad-brightness:
- shard-dg2-set2: [SKIP][473] ([Intel XE#2136]) -> [SKIP][474] ([Intel XE#870])
[473]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_pm_backlight@bad-brightness.html
[474]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_pm_backlight@bad-brightness.html
* igt@kms_pm_backlight@fade:
- shard-bmg: [SKIP][475] ([Intel XE#2136]) -> [SKIP][476] ([Intel XE#870]) +1 other test skip
[475]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_pm_backlight@fade.html
[476]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_pm_backlight@fade.html
* igt@kms_pm_dc@dc5-psr:
- shard-bmg: [SKIP][477] ([Intel XE#2136]) -> [SKIP][478] ([Intel XE#2392]) +1 other test skip
[477]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_pm_dc@dc5-psr.html
[478]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_pm_dc@dc5-psr.html
* igt@kms_pm_dc@dc5-retention-flops:
- shard-bmg: [SKIP][479] ([Intel XE#3309]) -> [SKIP][480] ([Intel XE#2136])
[479]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-7/igt@kms_pm_dc@dc5-retention-flops.html
[480]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_pm_dc@dc5-retention-flops.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-bmg: [SKIP][481] ([Intel XE#2499]) -> [SKIP][482] ([Intel XE#2136])
[481]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-4/igt@kms_pm_lpsp@kms-lpsp.html
[482]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@dpms-mode-unset-lpsp:
- shard-bmg: [SKIP][483] ([Intel XE#2446]) -> [SKIP][484] ([Intel XE#1439] / [Intel XE#836])
[483]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
[484]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf:
- shard-bmg: [SKIP][485] ([Intel XE#1489]) -> [SKIP][486] ([Intel XE#2136]) +7 other tests skip
[485]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html
[486]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
- shard-bmg: [SKIP][487] ([Intel XE#2136]) -> [SKIP][488] ([Intel XE#1489]) +7 other tests skip
[487]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
[488]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
- shard-dg2-set2: [SKIP][489] ([Intel XE#1489]) -> [SKIP][490] ([Intel XE#2136]) +6 other tests skip
[489]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html
[490]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html
* igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
- shard-dg2-set2: [SKIP][491] ([Intel XE#2136]) -> [SKIP][492] ([Intel XE#1489]) +7 other tests skip
[491]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html
[492]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-p010:
- shard-bmg: [SKIP][493] ([Intel XE#2387]) -> [SKIP][494] ([Intel XE#2136])
[493]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_psr2_su@page_flip-p010.html
[494]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@fbc-pr-cursor-blt:
- shard-bmg: [SKIP][495] ([Intel XE#2136]) -> [SKIP][496] ([Intel XE#2234] / [Intel XE#2850]) +15 other tests skip
[495]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_psr@fbc-pr-cursor-blt.html
[496]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_psr@fbc-pr-cursor-blt.html
* igt@kms_psr@fbc-psr-sprite-plane-onoff:
- shard-dg2-set2: [SKIP][497] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][498] ([Intel XE#2136] / [Intel XE#2351]) +5 other tests skip
[497]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_psr@fbc-psr-sprite-plane-onoff.html
[498]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_psr@fbc-psr-sprite-plane-onoff.html
* igt@kms_psr@fbc-psr2-primary-page-flip:
- shard-dg2-set2: [SKIP][499] ([Intel XE#2136] / [Intel XE#2351]) -> [SKIP][500] ([Intel XE#2850] / [Intel XE#929])
[499]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_psr@fbc-psr2-primary-page-flip.html
[500]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_psr@fbc-psr2-primary-page-flip.html
* igt@kms_psr@fbc-psr2-primary-render:
- shard-dg2-set2: [SKIP][501] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][502] ([Intel XE#2136]) +7 other tests skip
[501]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@kms_psr@fbc-psr2-primary-render.html
[502]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_psr@fbc-psr2-primary-render.html
* igt@kms_psr@fbc-psr2-sprite-plane-move:
- shard-dg2-set2: [SKIP][503] ([Intel XE#2136]) -> [SKIP][504] ([Intel XE#2850] / [Intel XE#929]) +12 other tests skip
[503]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_psr@fbc-psr2-sprite-plane-move.html
[504]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-466/igt@kms_psr@fbc-psr2-sprite-plane-move.html
* igt@kms_psr@pr-sprite-plane-onoff:
- shard-bmg: [SKIP][505] ([Intel XE#2234] / [Intel XE#2850]) -> [SKIP][506] ([Intel XE#2136]) +13 other tests skip
[505]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-4/igt@kms_psr@pr-sprite-plane-onoff.html
[506]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_psr@pr-sprite-plane-onoff.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-dg2-set2: [SKIP][507] ([Intel XE#2136]) -> [SKIP][508] ([Intel XE#2939])
[507]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
[508]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-bmg: [SKIP][509] ([Intel XE#3414] / [Intel XE#3904]) -> [SKIP][510] ([Intel XE#2423]) +1 other test skip
[509]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_rotation_crc@primary-rotation-90.html
[510]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
- shard-dg2-set2: [SKIP][511] ([Intel XE#2423] / [i915#2575]) -> [SKIP][512] ([Intel XE#1127])
[511]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
[512]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-466/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg2-set2: [SKIP][513] ([Intel XE#2423] / [i915#2575]) -> [SKIP][514] ([Intel XE#3414])
[513]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
[514]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-dg2-set2: [SKIP][515] ([Intel XE#3414]) -> [SKIP][516] ([Intel XE#2423] / [i915#2575]) +2 other tests skip
[515]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@kms_rotation_crc@sprite-rotation-270.html
[516]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_scaling_modes@scaling-mode-full-aspect:
- shard-bmg: [SKIP][517] ([Intel XE#2413]) -> [SKIP][518] ([Intel XE#2423])
[517]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_scaling_modes@scaling-mode-full-aspect.html
[518]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_scaling_modes@scaling-mode-full-aspect.html
* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-bmg: [SKIP][519] ([Intel XE#1435]) -> [SKIP][520] ([Intel XE#2423])
[519]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_setmode@invalid-clone-exclusive-crtc.html
[520]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_setmode@invalid-clone-exclusive-crtc.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [SKIP][521] ([Intel XE#2426]) -> [SKIP][522] ([Intel XE#2423])
[521]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern.html
[522]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern.html
- shard-dg2-set2: [SKIP][523] ([Intel XE#362]) -> [FAIL][524] ([Intel XE#1729])
[523]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern.html
[524]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-434/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tv_load_detect@load-detect:
- shard-bmg: [SKIP][525] ([Intel XE#2450]) -> [SKIP][526] ([Intel XE#2423])
[525]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@kms_tv_load_detect@load-detect.html
[526]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_tv_load_detect@load-detect.html
* igt@kms_vblank@wait-busy-hang:
- shard-bmg: [SKIP][527] ([Intel XE#2423]) -> [DMESG-WARN][528] ([Intel XE#4172]) +6 other tests dmesg-warn
[527]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_vblank@wait-busy-hang.html
[528]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_vblank@wait-busy-hang.html
* igt@kms_vrr@cmrr:
- shard-bmg: [SKIP][529] ([Intel XE#2168]) -> [SKIP][530] ([Intel XE#2423])
[529]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@kms_vrr@cmrr.html
[530]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_vrr@cmrr.html
* igt@kms_vrr@flip-dpms:
- shard-dg2-set2: [SKIP][531] ([Intel XE#2423] / [i915#2575]) -> [SKIP][532] ([Intel XE#455]) +7 other tests skip
[531]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_vrr@flip-dpms.html
[532]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-466/igt@kms_vrr@flip-dpms.html
* igt@kms_vrr@flip-suspend:
- shard-bmg: [SKIP][533] ([Intel XE#1499]) -> [SKIP][534] ([Intel XE#2423])
[533]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-7/igt@kms_vrr@flip-suspend.html
[534]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_vrr@flip-suspend.html
* igt@kms_vrr@lobf:
- shard-bmg: [SKIP][535] ([Intel XE#2423]) -> [SKIP][536] ([Intel XE#2168])
[535]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@kms_vrr@lobf.html
[536]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@kms_vrr@lobf.html
* igt@kms_writeback@writeback-fb-id-xrgb2101010:
- shard-bmg: [SKIP][537] ([Intel XE#756]) -> [SKIP][538] ([Intel XE#2423])
[537]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-4/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
[538]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
- shard-dg2-set2: [SKIP][539] ([Intel XE#756]) -> [SKIP][540] ([Intel XE#2423] / [i915#2575])
[539]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
[540]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-dg2-set2: [SKIP][541] ([Intel XE#2423] / [i915#2575]) -> [SKIP][542] ([Intel XE#756])
[541]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@kms_writeback@writeback-pixel-formats.html
[542]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@kms_writeback@writeback-pixel-formats.html
* igt@sriov_basic@enable-vfs-autoprobe-off:
- shard-dg2-set2: [SKIP][543] ([Intel XE#2423] / [i915#2575]) -> [SKIP][544] ([Intel XE#1091] / [Intel XE#2849])
[543]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@sriov_basic@enable-vfs-autoprobe-off.html
[544]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-466/igt@sriov_basic@enable-vfs-autoprobe-off.html
* igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
- shard-dg2-set2: [SKIP][545] ([Intel XE#1091] / [Intel XE#2849]) -> [SKIP][546] ([Intel XE#2423] / [i915#2575])
[545]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
[546]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
* igt@xe_compute_preempt@compute-preempt-many:
- shard-dg2-set2: [SKIP][547] ([Intel XE#1280] / [Intel XE#455]) -> [SKIP][548] ([Intel XE#1130])
[547]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@xe_compute_preempt@compute-preempt-many.html
[548]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@xe_compute_preempt@compute-preempt-many.html
* igt@xe_compute_preempt@compute-threadgroup-preempt:
- shard-dg2-set2: [SKIP][549] ([Intel XE#1130]) -> [SKIP][550] ([Intel XE#1280] / [Intel XE#455])
[549]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@xe_compute_preempt@compute-threadgroup-preempt.html
[550]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-432/igt@xe_compute_preempt@compute-threadgroup-preempt.html
* igt@xe_copy_basic@mem-set-linear-0x369:
- shard-dg2-set2: [SKIP][551] ([Intel XE#1130]) -> [SKIP][552] ([Intel XE#1126])
[551]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@xe_copy_basic@mem-set-linear-0x369.html
[552]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@xe_copy_basic@mem-set-linear-0x369.html
* igt@xe_eudebug@basic-vm-access-parameters:
- shard-dg2-set2: [SKIP][553] ([Intel XE#1130]) -> [SKIP][554] ([Intel XE#2905]) +11 other tests skip
[553]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@xe_eudebug@basic-vm-access-parameters.html
[554]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@xe_eudebug@basic-vm-access-parameters.html
* igt@xe_eudebug@basic-vm-access-parameters-userptr:
- shard-bmg: [SKIP][555] ([Intel XE#1130]) -> [SKIP][556] ([Intel XE#3889])
[555]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@xe_eudebug@basic-vm-access-parameters-userptr.html
[556]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@xe_eudebug@basic-vm-access-parameters-userptr.html
* igt@xe_eudebug@basic-vm-bind-metadata-discovery:
- shard-bmg: [SKIP][557] ([Intel XE#1130]) -> [SKIP][558] ([Intel XE#2905]) +9 other tests skip
[557]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html
[558]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@xe_eudebug@basic-vm-bind-metadata-discovery.html
* igt@xe_eudebug@basic-vm-bind-ufence-delay-ack:
- shard-dg2-set2: [SKIP][559] ([Intel XE#3889]) -> [SKIP][560] ([Intel XE#1130])
[559]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@xe_eudebug@basic-vm-bind-ufence-delay-ack.html
[560]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@xe_eudebug@basic-vm-bind-ufence-delay-ack.html
* igt@xe_eudebug_online@interrupt-all-set-breakpoint:
- shard-dg2-set2: [SKIP][561] ([Intel XE#2905]) -> [SKIP][562] ([Intel XE#1130]) +9 other tests skip
[561]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@xe_eudebug_online@interrupt-all-set-breakpoint.html
[562]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@xe_eudebug_online@interrupt-all-set-breakpoint.html
* igt@xe_eudebug_online@single-step-one:
- shard-bmg: [SKIP][563] ([Intel XE#2905]) -> [SKIP][564] ([Intel XE#1130]) +7 other tests skip
[563]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@xe_eudebug_online@single-step-one.html
[564]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@xe_eudebug_online@single-step-one.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr:
- shard-bmg: [SKIP][565] ([Intel XE#2322]) -> [SKIP][566] ([Intel XE#1130]) +9 other tests skip
[565]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-6/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html
[566]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html
* igt@xe_exec_basic@multigpu-once-basic-defer-mmap:
- shard-dg2-set2: [SKIP][567] ([Intel XE#1392]) -> [SKIP][568] ([Intel XE#1130]) +2 other tests skip
[567]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
[568]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind:
- shard-bmg: [SKIP][569] ([Intel XE#1130]) -> [SKIP][570] ([Intel XE#2322]) +8 other tests skip
[569]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html
[570]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html
- shard-dg2-set2: [SKIP][571] ([Intel XE#1130]) -> [SKIP][572] ([Intel XE#1392]) +2 other tests skip
[571]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html
[572]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html
* igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-prefetch:
- shard-bmg: [SKIP][573] ([Intel XE#1130]) -> [DMESG-WARN][574] ([Intel XE#4172]) +2 other tests dmesg-warn
[573]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-prefetch.html
[574]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-prefetch.html
* igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind-prefetch:
- shard-dg2-set2: [SKIP][575] ([Intel XE#288]) -> [SKIP][576] ([Intel XE#1130]) +23 other tests skip
[575]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind-prefetch.html
[576]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind-prefetch.html
* igt@xe_exec_fault_mode@twice-userptr-invalidate-race:
- shard-dg2-set2: [SKIP][577] ([Intel XE#1130]) -> [SKIP][578] ([Intel XE#288]) +24 other tests skip
[577]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@xe_exec_fault_mode@twice-userptr-invalidate-race.html
[578]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@xe_exec_fault_mode@twice-userptr-invalidate-race.html
* igt@xe_live_ktest@xe_eudebug:
- shard-bmg: [SKIP][579] ([Intel XE#1192]) -> [SKIP][580] ([Intel XE#2833])
[579]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-2/igt@xe_live_ktest@xe_eudebug.html
[580]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-4/igt@xe_live_ktest@xe_eudebug.html
* igt@xe_media_fill@media-fill:
- shard-bmg: [SKIP][581] ([Intel XE#2459] / [Intel XE#2596]) -> [SKIP][582] ([Intel XE#1130])
[581]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@xe_media_fill@media-fill.html
[582]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@xe_media_fill@media-fill.html
* igt@xe_oa@closed-fd-and-unmapped-access:
- shard-dg2-set2: [SKIP][583] ([Intel XE#2541] / [Intel XE#3573]) -> [SKIP][584] ([Intel XE#1130]) +6 other tests skip
[583]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@xe_oa@closed-fd-and-unmapped-access.html
[584]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@xe_oa@closed-fd-and-unmapped-access.html
* igt@xe_oa@non-privileged-access-vaddr:
- shard-dg2-set2: [SKIP][585] ([Intel XE#1130]) -> [SKIP][586] ([Intel XE#2541] / [Intel XE#3573]) +6 other tests skip
[585]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@xe_oa@non-privileged-access-vaddr.html
[586]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-466/igt@xe_oa@non-privileged-access-vaddr.html
* igt@xe_oa@oa-tlb-invalidate:
- shard-bmg: [SKIP][587] ([Intel XE#1130]) -> [SKIP][588] ([Intel XE#2248])
[587]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@xe_oa@oa-tlb-invalidate.html
[588]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@xe_oa@oa-tlb-invalidate.html
* igt@xe_oa@unprivileged-single-ctx-counters:
- shard-bmg: [SKIP][589] ([Intel XE#2248]) -> [SKIP][590] ([Intel XE#1130])
[589]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-1/igt@xe_oa@unprivileged-single-ctx-counters.html
[590]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@xe_oa@unprivileged-single-ctx-counters.html
* igt@xe_pat@display-vs-wb-transient:
- shard-dg2-set2: [SKIP][591] ([Intel XE#1130]) -> [SKIP][592] ([Intel XE#1337])
[591]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@xe_pat@display-vs-wb-transient.html
[592]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-466/igt@xe_pat@display-vs-wb-transient.html
* igt@xe_peer2peer@write:
- shard-dg2-set2: [SKIP][593] ([Intel XE#1061]) -> [FAIL][594] ([Intel XE#1173])
[593]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@xe_peer2peer@write.html
[594]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@xe_peer2peer@write.html
* igt@xe_pm@d3cold-basic:
- shard-dg2-set2: [SKIP][595] ([Intel XE#2284] / [Intel XE#366]) -> [SKIP][596] ([Intel XE#1130]) +1 other test skip
[595]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-436/igt@xe_pm@d3cold-basic.html
[596]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@xe_pm@d3cold-basic.html
* igt@xe_pm@d3cold-mocs:
- shard-dg2-set2: [SKIP][597] ([Intel XE#1130]) -> [SKIP][598] ([Intel XE#2284])
[597]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@xe_pm@d3cold-mocs.html
[598]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@xe_pm@d3cold-mocs.html
* igt@xe_pm@d3cold-multiple-execs:
- shard-bmg: [SKIP][599] ([Intel XE#2284]) -> [SKIP][600] ([Intel XE#1130]) +2 other tests skip
[599]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-7/igt@xe_pm@d3cold-multiple-execs.html
[600]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@xe_pm@d3cold-multiple-execs.html
* igt@xe_pm@s3-multiple-execs:
- shard-dg2-set2: [SKIP][601] ([Intel XE#1130]) -> [ABORT][602] ([Intel XE#1358] / [Intel XE#1794])
[601]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@xe_pm@s3-multiple-execs.html
[602]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-432/igt@xe_pm@s3-multiple-execs.html
* igt@xe_pm@s3-vm-bind-unbind-all:
- shard-dg2-set2: [ABORT][603] ([Intel XE#1358] / [Intel XE#1794]) -> [SKIP][604] ([Intel XE#1130])
[603]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@xe_pm@s3-vm-bind-unbind-all.html
[604]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@xe_pm@s3-vm-bind-unbind-all.html
* igt@xe_pm@s3-vm-bind-userptr:
- shard-bmg: [SKIP][605] ([Intel XE#1130]) -> [DMESG-WARN][606] ([Intel XE#4172] / [Intel XE#569])
[605]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@xe_pm@s3-vm-bind-userptr.html
[606]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@xe_pm@s3-vm-bind-userptr.html
* igt@xe_pm@vram-d3cold-threshold:
- shard-bmg: [SKIP][607] ([Intel XE#1130]) -> [SKIP][608] ([Intel XE#579])
[607]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@xe_pm@vram-d3cold-threshold.html
[608]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@xe_pm@vram-d3cold-threshold.html
* igt@xe_query@multigpu-query-engines:
- shard-dg2-set2: [SKIP][609] ([Intel XE#1130]) -> [SKIP][610] ([Intel XE#944]) +1 other test skip
[609]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@xe_query@multigpu-query-engines.html
[610]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-436/igt@xe_query@multigpu-query-engines.html
* igt@xe_query@multigpu-query-hwconfig:
- shard-bmg: [SKIP][611] ([Intel XE#1130]) -> [SKIP][612] ([Intel XE#944]) +3 other tests skip
[611]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@xe_query@multigpu-query-hwconfig.html
[612]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-5/igt@xe_query@multigpu-query-hwconfig.html
* igt@xe_query@multigpu-query-invalid-cs-cycles:
- shard-dg2-set2: [SKIP][613] ([Intel XE#944]) -> [SKIP][614] ([Intel XE#1130]) +1 other test skip
[613]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@xe_query@multigpu-query-invalid-cs-cycles.html
[614]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@xe_query@multigpu-query-invalid-cs-cycles.html
* igt@xe_query@multigpu-query-uc-fw-version-huc:
- shard-bmg: [SKIP][615] ([Intel XE#944]) -> [SKIP][616] ([Intel XE#1130]) +1 other test skip
[615]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-7/igt@xe_query@multigpu-query-uc-fw-version-huc.html
[616]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-3/igt@xe_query@multigpu-query-uc-fw-version-huc.html
* igt@xe_sriov_auto_provisioning@exclusive-ranges:
- shard-dg2-set2: [SKIP][617] ([Intel XE#1130]) -> [SKIP][618] ([Intel XE#4130])
[617]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-433/igt@xe_sriov_auto_provisioning@exclusive-ranges.html
[618]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-432/igt@xe_sriov_auto_provisioning@exclusive-ranges.html
* igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling:
- shard-bmg: [SKIP][619] ([Intel XE#1130]) -> [SKIP][620] ([Intel XE#4130])
[619]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-bmg-3/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html
[620]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-bmg-6/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html
* igt@xe_sriov_flr@flr-vf1-clear:
- shard-dg2-set2: [SKIP][621] ([Intel XE#3342]) -> [SKIP][622] ([Intel XE#1130])
[621]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3/shard-dg2-432/igt@xe_sriov_flr@flr-vf1-clear.html
[622]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/shard-dg2-433/igt@xe_sriov_flr@flr-vf1-clear.html
[Intel XE#1033]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1033
[Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
[Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130
[Intel XE#1137]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1137
[Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
[Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
[Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337
[Intel XE#1358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1358
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
[Intel XE#1607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1607
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
[Intel XE#1999]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1999
[Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
[Intel XE#2136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2136
[Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2248]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2248
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
[Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
[Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
[Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
[Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
[Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
[Intel XE#2423]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2423
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2446]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2446
[Intel XE#2450]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2450
[Intel XE#2459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2459
[Intel XE#2486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2486
[Intel XE#2493]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2493
[Intel XE#2499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2499
[Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
[Intel XE#2596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2596
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#2625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2625
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
[Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
[Intel XE#2833]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2833
[Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2853]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2853
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
[Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
[Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
[Intel XE#2934]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2934
[Intel XE#2939]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2939
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/314
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#3226]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3226
[Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
[Intel XE#3249]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3249
[Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
[Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
[Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#3440]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3440
[Intel XE#3442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3442
[Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
[Intel XE#3546]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3546
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3768]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3768
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#379]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/379
[Intel XE#3889]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3889
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4080]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4080
[Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4156]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4156
[Intel XE#4172]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4172
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#560]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/560
[Intel XE#569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/569
[Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
[Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
[Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
[Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703
[Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756
[Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/873
[Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
[Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
Build changes
-------------
* Linux: xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3 -> xe-pw-143138v2
IGT_8214: 7a8a3744466fbb89127201077f030033c72df948 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-2569-683350734da38bc7332a3b87c9f2faf6bbeeb5a3: 683350734da38bc7332a3b87c9f2faf6bbeeb5a3
xe-pw-143138v2: 143138v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-143138v2/index.html
[-- Attachment #2: Type: text/html, Size: 191093 bytes --]
^ permalink raw reply [flat|nested] 45+ messages in thread* Re: [PATCH v4 0/8] PMU Support for per-engine-class activity
2025-01-29 10:16 [PATCH v4 0/8] PMU Support for per-engine-class activity Riana Tauro
` (15 preceding siblings ...)
2025-01-29 21:35 ` ✗ Xe.CI.Full: " Patchwork
@ 2025-01-30 0:06 ` Umesh Nerlige Ramappa
16 siblings, 0 replies; 45+ messages in thread
From: Umesh Nerlige Ramappa @ 2025-01-30 0:06 UTC (permalink / raw)
To: Riana Tauro
Cc: intel-xe, anshuman.gupta, lucas.demarchi, vinay.belgaumkar,
soham.purkait
On Wed, Jan 29, 2025 at 03:46:43PM +0530, Riana Tauro wrote:
>This series adds support for per-engine-class activity for native
>and PF and VF's
A general comment applicable to entire series:
I am wondering why you are referring to the granularity of engine
activity as "per-engine-class"? The interface supports per-engine (class
and instance) level activity.
Maybe you could just use per-engine everywhere instead because
per-engine-class means something else and that's what we export with the
fdinfo interface.
Thanks,
Umesh
>
>PMU provides two counters (engine-active-ticks, engine-total-ticks)
>to calculate engine activity. When querying this, user must group
>these 2 counters using the perf_event group mechanism to ensure
>both counters are sampled together.
>
>To list the events
>
> ./perf list
> xe_0000_03_00.0/engine-active-ticks/ [Kernel PMU event]
> xe_0000_03_00.0/engine-total-ticks/ [Kernel PMU event]
>
>The formats to be used with the above are
>
> function - config:59-44
> engine_class - config:20-27
> engine_instance - config:12-19
> gt - config:60-63
>
>The events can then be read using perf tool
>
> ./perf stat -e xe_<bdf>/engine-active-ticks,gt=<n>,engine_class=<n>,
> engine_instance=<n>,function=<n>/,
> xe_<bdf>/engine-total-ticks,gt=<n>,engine_class=<n>,
> engine_instance=<n>,function<n>/
> -I 1000
>
>Engine activity can then be calculated as below
>engine activity % = (engine active ticks/engine total ticks) * 100
>
>
>Rev2: Add trace functions
> fix cosmetic review comments
>
>Rev3: add engine class and instance as parameters
> bump minimum guc to 70.36.0
> replace busyness with engine activity
>
>Rev4: add per-function per-engine-class activity
> fix review comments
>
>Riana Tauro (8):
> drm/xe: Add per-engine-class activity support
> drm/xe/trace: Add trace for engine activity
> drm/xe/guc: Expose engine activity only for supported GuC version
> drm/xe/xe_pmu: Add PMU support for per-engine-class activity
> drm/xe/guc: Bump minimum required GuC version to v70.36.0
> drm/xe: Add support for per-function engine activity
> drm/xe/xe_pmu: Add pmu support for per-function engine activity stats
> drm/xe/pf: Enable per-function per-engine-class activity stats
>
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/abi/guc_actions_abi.h | 2 +
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
> drivers/gpu/drm/xe/xe_guc.c | 5 +
> drivers/gpu/drm/xe/xe_guc_engine_activity.c | 500 ++++++++++++++++++
> drivers/gpu/drm/xe/xe_guc_engine_activity.h | 20 +
> .../gpu/drm/xe/xe_guc_engine_activity_types.h | 95 ++++
> drivers/gpu/drm/xe/xe_guc_fwif.h | 19 +
> drivers/gpu/drm/xe/xe_guc_types.h | 4 +
> drivers/gpu/drm/xe/xe_pci_sriov.c | 23 +
> drivers/gpu/drm/xe/xe_pmu.c | 158 +++++-
> drivers/gpu/drm/xe/xe_trace_guc.h | 49 ++
> drivers/gpu/drm/xe/xe_uc.c | 3 +
> drivers/gpu/drm/xe/xe_uc_fw.c | 28 +-
> 14 files changed, 886 insertions(+), 23 deletions(-)
> create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.c
> create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity.h
> create mode 100644 drivers/gpu/drm/xe/xe_guc_engine_activity_types.h
>
>--
>2.47.1
>
^ permalink raw reply [flat|nested] 45+ messages in thread