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From: Gustavo Sousa <gustavo.sousa@intel.com>
To: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>,
	<intel-xe@lists.freedesktop.org>
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Subject: Re: [PATCH] drm/xe/xe2hpg: Performance tuning changes
Date: Fri, 9 Jan 2026 16:37:11 -0300	[thread overview]
Message-ID: <176798743165.16319.15130481848588509084@intel.com> (raw)
In-Reply-To: <20260109164250.237044-2-balasubramani.vivekanandan@intel.com>

Quoting Balasubramani Vivekanandan (2026-01-09 13:42:51-03:00)
>Further updates to performance tuning for Xe2_HPG

Maybe worth noting that this is specific for version 20.02 of the IP.

>
>Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 +++
> drivers/gpu/drm/xe/xe_tuning.c       | 5 +++++
> 2 files changed, 8 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>index 93643da57428..cc18ddfb7cc0 100644
>--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>@@ -135,6 +135,9 @@
> 
> #define XEHPG_INSTDONE_GEOM_SVGUNIT                XE_REG_MCR(0x666c)
> 
>+#define CACHE_MODE_0                                XE_REG_MCR(0x7000, XE_REG_OPTION_MASKED)
>+#define   MSAA_FAST_CLEAR_ENABLED                REG_BIT(5)
>+
> #define CACHE_MODE_1                                XE_REG(0x7004, XE_REG_OPTION_MASKED)

Huh. A bit unrelated to this patch, but I find it weird that
CACHE_MODE_1 is not defined as multicast.

The current users of CACHE_MODE_1 are DG2 and MTL and that register is
multicast for both (Bspec 66534 and 67788).  We probably need a separate
patch to fix this.

Anyway,

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

> #define   MSAA_OPTIMIZATION_REDUC_DISABLE        REG_BIT(11)
> 
>diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
>index 5766fa7742d3..122829c8d14e 100644
>--- a/drivers/gpu/drm/xe/xe_tuning.c
>+++ b/drivers/gpu/drm/xe/xe_tuning.c
>@@ -144,6 +144,11 @@ static const struct xe_rtp_entry_sr lrc_tunings[] = {
>           XE_RTP_ACTIONS(FIELD_SET(FF_MODE, VS_HIT_MAX_VALUE_MASK,
>                                    REG_FIELD_PREP(VS_HIT_MAX_VALUE_MASK, 0x3f)))
>         },
>+
>+        { XE_RTP_NAME("Tuning: MSAA fast clear"),
>+          XE_RTP_RULES(GRAPHICS_VERSION(2002), ENGINE_CLASS(RENDER)),
>+          XE_RTP_ACTIONS(SET(CACHE_MODE_0, MSAA_FAST_CLEAR_ENABLED))
>+        },
> };
> 
> /**
>-- 
>2.43.0
>

  parent reply	other threads:[~2026-01-09 19:37 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-09 16:42 [PATCH] drm/xe/xe2hpg: Performance tuning changes Balasubramani Vivekanandan
2026-01-09 17:07 ` ✓ CI.KUnit: success for " Patchwork
2026-01-09 17:40 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-09 19:37 ` Gustavo Sousa [this message]
2026-01-09 22:45 ` ✗ Xe.CI.Full: failure " Patchwork
2026-01-12  7:04 ` ✓ CI.KUnit: success for drm/xe/xe2hpg: Performance tuning changes (rev2) Patchwork
2026-01-12  7:40 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-12  8:45 ` ✗ Xe.CI.Full: failure " Patchwork
2026-01-13 15:34 ` [PATCH] drm/xe/xe2hpg: Performance tuning changes Matt Roper
2026-01-16  8:07   ` Vivekanandan, Balasubramani

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