* [PATCH v10 0/4] drm/xe/vf: Post-migration recovery of GGTT nodes and CTB
@ 2025-04-15 22:20 Tomasz Lis
2025-04-15 22:20 ` [PATCH v10 1/4] drm/xe/vf: Divide GGTT ballooning into allocation and insertion Tomasz Lis
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: Tomasz Lis @ 2025-04-15 22:20 UTC (permalink / raw)
To: intel-xe
Cc: Michał Winiarski, Michał Wajdeczko,
Piotr Piórkowski, Matthew Brost, Lucas De Marchi
To support VF Migration, it is necessary to do fixups to any
non-virtualized resources. These fixups need to be applied within
VM, on the KMD working with VF.
This series adds two fixup functions to the recovery worker:
* for fixing drm_mm nodes which represent GGTT allocations
* for fixing content of outgoing CTB buffer
v2: Fixed missing include, made checkpatch happy
v3: Moved some functs to xe_ggtt.c; moved shift computation to just
after querying; improved documentation; switched some warns to asserts;
skipping fixups when GGTT shift eq 0; iterating through tiles rather
than gts; fixes in log messages
v4: Updated kerneldocs, removed unused funct, properly allocate
balloning nodes if non existent, removed inline keywords, enums for
offsets in CTB messages, less error messages, if return unused then
made functs void
v5: Removed drm_mm change, but added VF init modifications. These then
allowed to re-use ballooning functions during ggtt node fixing.
v6: Minor update - fixed some misplaced funct declarations; sent to
a different list by mistake:
https://patchwork.freedesktop.org/series/146977/#rev2
v7: Altered, rephrased, added or promoted several kerneldocs; added
_locked versions of some functs; improved lockdep tagging; altered
error handling; renamed or moved some functions; defined few macros;
prepared CTB fixups for future changes of CTB handling; renamed and
introduced enums; did many minor changes to adjust for xe-specific
coding practices
v8: renamed several functions, reused helpers, separated switch cases,
documented more functs, shortened asserts, added `_locked` suffixes,
fixed a leak in error path
v9: More helpers, fixed coding style, renamed and moved functions,
improved kerneldoc, added asserts, avoided null dereference
v10: More xe_map*() functs to macros, added asserts and debug print,
changed params of two functions
Tomasz Lis (4):
drm/xe/vf: Divide GGTT ballooning into allocation and insertion
drm/xe/vf: Shifting GGTT area post migration
drm/xe/guc: Introduce enum with offsets for context register H2Gs
drm/xe/vf: Fixup CTB send buffer messages after migration
drivers/gpu/drm/xe/abi/guc_actions_abi.h | 31 ++++
drivers/gpu/drm/xe/xe_ggtt.c | 83 +++++++--
drivers/gpu/drm/xe/xe_ggtt.h | 7 +-
drivers/gpu/drm/xe/xe_gt_sriov_vf.c | 216 +++++++++++++++++++---
drivers/gpu/drm/xe/xe_gt_sriov_vf.h | 4 +
drivers/gpu/drm/xe/xe_gt_sriov_vf_types.h | 2 +
drivers/gpu/drm/xe/xe_guc_ct.c | 172 +++++++++++++++++
drivers/gpu/drm/xe/xe_guc_ct.h | 2 +
drivers/gpu/drm/xe/xe_guc_submit.c | 17 ++
drivers/gpu/drm/xe/xe_map.h | 18 ++
drivers/gpu/drm/xe/xe_sriov_vf.c | 40 ++++
11 files changed, 543 insertions(+), 49 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v10 1/4] drm/xe/vf: Divide GGTT ballooning into allocation and insertion
2025-04-15 22:20 [PATCH v10 0/4] drm/xe/vf: Post-migration recovery of GGTT nodes and CTB Tomasz Lis
@ 2025-04-15 22:20 ` Tomasz Lis
2025-04-17 18:10 ` Michal Wajdeczko
2025-04-15 22:20 ` [PATCH v10 2/4] drm/xe/vf: Shifting GGTT area post migration Tomasz Lis
` (4 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Tomasz Lis @ 2025-04-15 22:20 UTC (permalink / raw)
To: intel-xe
Cc: Michał Winiarski, Michał Wajdeczko,
Piotr Piórkowski, Matthew Brost, Lucas De Marchi
The balloon nodes, which are used to fill areas of GGTT inaccessible
for a specific VF, were allocated and inserted into GGTT within one
function. To be able to re-use that insertion code during VF
migration recovery, we need to split it.
This patch separates allocation (init/fini functs) from the insertion
of balloons (balloon/deballoon functs). Locks are also moved to ensure
calls from post-migration recovery worker will not cause a deadlock.
v2: Moved declarations to proper header
v3: Rephrased description, introduced "_locked" versions of some
functs, more lockdep checks, some functions renamed, altered error
handling, added missing kerneldocs.
v4: Suffixed more functs with `_locked`, moved lockdep asserts,
fixed finalization in error path, added asserts
v5: Renamed another few functs, used xe_ggtt_node_allocated(),
moved lockdep back again to avoid null dereference, added
asserts, improved comments
v6: Changed params of cleanup_ggtt()
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/xe/xe_ggtt.c | 35 ++++-----
drivers/gpu/drm/xe/xe_ggtt.h | 6 +-
drivers/gpu/drm/xe/xe_gt_sriov_vf.c | 114 +++++++++++++++++++++-------
drivers/gpu/drm/xe/xe_gt_sriov_vf.h | 2 +
4 files changed, 107 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 7062115909f2..5a37233f2420 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -429,16 +429,17 @@ static void xe_ggtt_dump_node(struct xe_ggtt *ggtt,
}
/**
- * xe_ggtt_node_insert_balloon - prevent allocation of specified GGTT addresses
+ * xe_ggtt_node_insert_balloon_locked - prevent allocation of specified GGTT addresses
* @node: the &xe_ggtt_node to hold reserved GGTT node
* @start: the starting GGTT address of the reserved region
* @end: then end GGTT address of the reserved region
*
- * Use xe_ggtt_node_remove_balloon() to release a reserved GGTT node.
+ * To be used in cases where ggtt->lock is already taken.
+ * Use xe_ggtt_node_remove_balloon_locked() to release a reserved GGTT node.
*
* Return: 0 on success or a negative error code on failure.
*/
-int xe_ggtt_node_insert_balloon(struct xe_ggtt_node *node, u64 start, u64 end)
+int xe_ggtt_node_insert_balloon_locked(struct xe_ggtt_node *node, u64 start, u64 end)
{
struct xe_ggtt *ggtt = node->ggtt;
int err;
@@ -447,14 +448,13 @@ int xe_ggtt_node_insert_balloon(struct xe_ggtt_node *node, u64 start, u64 end)
xe_tile_assert(ggtt->tile, IS_ALIGNED(start, XE_PAGE_SIZE));
xe_tile_assert(ggtt->tile, IS_ALIGNED(end, XE_PAGE_SIZE));
xe_tile_assert(ggtt->tile, !drm_mm_node_allocated(&node->base));
+ lockdep_assert_held(&ggtt->lock);
node->base.color = 0;
node->base.start = start;
node->base.size = end - start;
- mutex_lock(&ggtt->lock);
err = drm_mm_reserve_node(&ggtt->mm, &node->base);
- mutex_unlock(&ggtt->lock);
if (xe_gt_WARN(ggtt->tile->primary_gt, err,
"Failed to balloon GGTT %#llx-%#llx (%pe)\n",
@@ -466,27 +466,22 @@ int xe_ggtt_node_insert_balloon(struct xe_ggtt_node *node, u64 start, u64 end)
}
/**
- * xe_ggtt_node_remove_balloon - release a reserved GGTT region
+ * xe_ggtt_node_remove_balloon_locked - release a reserved GGTT region
* @node: the &xe_ggtt_node with reserved GGTT region
*
- * See xe_ggtt_node_insert_balloon() for details.
+ * To be used in cases where ggtt->lock is already taken.
+ * See xe_ggtt_node_insert_balloon_locked() for details.
*/
-void xe_ggtt_node_remove_balloon(struct xe_ggtt_node *node)
+void xe_ggtt_node_remove_balloon_locked(struct xe_ggtt_node *node)
{
- if (!node || !node->ggtt)
+ if (!xe_ggtt_node_allocated(node))
return;
- if (!drm_mm_node_allocated(&node->base))
- goto free_node;
+ lockdep_assert_held(&node->ggtt->lock);
xe_ggtt_dump_node(node->ggtt, &node->base, "remove-balloon");
- mutex_lock(&node->ggtt->lock);
drm_mm_remove_node(&node->base);
- mutex_unlock(&node->ggtt->lock);
-
-free_node:
- xe_ggtt_node_fini(node);
}
/**
@@ -537,12 +532,12 @@ int xe_ggtt_node_insert(struct xe_ggtt_node *node, u32 size, u32 align)
* xe_ggtt_node_init - Initialize %xe_ggtt_node struct
* @ggtt: the &xe_ggtt where the new node will later be inserted/reserved.
*
- * This function will allocated the struct %xe_ggtt_node and return it's pointer.
+ * This function will allocate the struct %xe_ggtt_node and return its pointer.
* This struct will then be freed after the node removal upon xe_ggtt_node_remove()
- * or xe_ggtt_node_remove_balloon().
+ * or xe_ggtt_node_remove_balloon_locked().
* Having %xe_ggtt_node struct allocated doesn't mean that the node is already allocated
* in GGTT. Only the xe_ggtt_node_insert(), xe_ggtt_node_insert_locked(),
- * xe_ggtt_node_insert_balloon() will ensure the node is inserted or reserved in GGTT.
+ * xe_ggtt_node_insert_balloon_locked() will ensure the node is inserted or reserved in GGTT.
*
* Return: A pointer to %xe_ggtt_node struct on success. An ERR_PTR otherwise.
**/
@@ -564,7 +559,7 @@ struct xe_ggtt_node *xe_ggtt_node_init(struct xe_ggtt *ggtt)
* @node: the &xe_ggtt_node to be freed
*
* If anything went wrong with either xe_ggtt_node_insert(), xe_ggtt_node_insert_locked(),
- * or xe_ggtt_node_insert_balloon(); and this @node is not going to be reused, then,
+ * or xe_ggtt_node_insert_balloon_locked(); and this @node is not going to be reused, then,
* this function needs to be called to free the %xe_ggtt_node struct
**/
void xe_ggtt_node_fini(struct xe_ggtt_node *node)
diff --git a/drivers/gpu/drm/xe/xe_ggtt.h b/drivers/gpu/drm/xe/xe_ggtt.h
index 27e7d67de004..d468af96b465 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.h
+++ b/drivers/gpu/drm/xe/xe_ggtt.h
@@ -15,9 +15,9 @@ int xe_ggtt_init(struct xe_ggtt *ggtt);
struct xe_ggtt_node *xe_ggtt_node_init(struct xe_ggtt *ggtt);
void xe_ggtt_node_fini(struct xe_ggtt_node *node);
-int xe_ggtt_node_insert_balloon(struct xe_ggtt_node *node,
- u64 start, u64 size);
-void xe_ggtt_node_remove_balloon(struct xe_ggtt_node *node);
+int xe_ggtt_node_insert_balloon_locked(struct xe_ggtt_node *node,
+ u64 start, u64 size);
+void xe_ggtt_node_remove_balloon_locked(struct xe_ggtt_node *node);
int xe_ggtt_node_insert(struct xe_ggtt_node *node, u32 size, u32 align);
int xe_ggtt_node_insert_locked(struct xe_ggtt_node *node,
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
index a439261bf4d7..f82ddff79b3b 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
@@ -560,35 +560,43 @@ u64 xe_gt_sriov_vf_lmem(struct xe_gt *gt)
return gt->sriov.vf.self_config.lmem_size;
}
-static struct xe_ggtt_node *
-vf_balloon_ggtt_node(struct xe_ggtt *ggtt, u64 start, u64 end)
+static int vf_init_ggtt_balloons(struct xe_gt *gt)
{
- struct xe_ggtt_node *node;
- int err;
+ struct xe_tile *tile = gt_to_tile(gt);
+ struct xe_ggtt *ggtt = tile->mem.ggtt;
- node = xe_ggtt_node_init(ggtt);
- if (IS_ERR(node))
- return node;
+ xe_gt_assert(gt, IS_SRIOV_VF(gt_to_xe(gt)));
+ xe_gt_assert(gt, !xe_gt_is_media_type(gt));
- err = xe_ggtt_node_insert_balloon(node, start, end);
- if (err) {
- xe_ggtt_node_fini(node);
- return ERR_PTR(err);
+ tile->sriov.vf.ggtt_balloon[0] = xe_ggtt_node_init(ggtt);
+ if (IS_ERR(tile->sriov.vf.ggtt_balloon[0]))
+ return PTR_ERR(tile->sriov.vf.ggtt_balloon[0]);
+
+ tile->sriov.vf.ggtt_balloon[1] = xe_ggtt_node_init(ggtt);
+ if (IS_ERR(tile->sriov.vf.ggtt_balloon[1])) {
+ xe_ggtt_node_fini(tile->sriov.vf.ggtt_balloon[0]);
+ return PTR_ERR(tile->sriov.vf.ggtt_balloon[1]);
}
- return node;
+ return 0;
}
-static int vf_balloon_ggtt(struct xe_gt *gt)
+/**
+ * xe_gt_sriov_vf_balloon_ggtt_locked - Insert balloon nodes to limit used GGTT address range.
+ * @gt: the &xe_gt struct instance
+ * Return: 0 on success or a negative error code on failure.
+ */
+int xe_gt_sriov_vf_balloon_ggtt_locked(struct xe_gt *gt)
{
struct xe_gt_sriov_vf_selfconfig *config = >->sriov.vf.self_config;
struct xe_tile *tile = gt_to_tile(gt);
- struct xe_ggtt *ggtt = tile->mem.ggtt;
struct xe_device *xe = gt_to_xe(gt);
u64 start, end;
+ int err;
xe_gt_assert(gt, IS_SRIOV_VF(xe));
xe_gt_assert(gt, !xe_gt_is_media_type(gt));
+ lockdep_assert_held(&tile->mem.ggtt->lock);
if (!config->ggtt_size)
return -ENODATA;
@@ -611,31 +619,77 @@ static int vf_balloon_ggtt(struct xe_gt *gt)
start = xe_wopcm_size(xe);
end = config->ggtt_base;
if (end != start) {
- tile->sriov.vf.ggtt_balloon[0] = vf_balloon_ggtt_node(ggtt, start, end);
- if (IS_ERR(tile->sriov.vf.ggtt_balloon[0]))
- return PTR_ERR(tile->sriov.vf.ggtt_balloon[0]);
+ err = xe_ggtt_node_insert_balloon_locked(tile->sriov.vf.ggtt_balloon[0],
+ start, end);
+ if (err)
+ return err;
}
start = config->ggtt_base + config->ggtt_size;
end = GUC_GGTT_TOP;
if (end != start) {
- tile->sriov.vf.ggtt_balloon[1] = vf_balloon_ggtt_node(ggtt, start, end);
- if (IS_ERR(tile->sriov.vf.ggtt_balloon[1])) {
- xe_ggtt_node_remove_balloon(tile->sriov.vf.ggtt_balloon[0]);
- return PTR_ERR(tile->sriov.vf.ggtt_balloon[1]);
+ err = xe_ggtt_node_insert_balloon_locked(tile->sriov.vf.ggtt_balloon[1],
+ start, end);
+ if (err) {
+ xe_ggtt_node_remove_balloon_locked(tile->sriov.vf.ggtt_balloon[0]);
+ return err;
}
}
return 0;
}
-static void deballoon_ggtt(struct drm_device *drm, void *arg)
+static int vf_balloon_ggtt(struct xe_gt *gt)
+{
+ struct xe_ggtt *ggtt = gt_to_tile(gt)->mem.ggtt;
+ int err;
+
+ mutex_lock(&ggtt->lock);
+ err = xe_gt_sriov_vf_balloon_ggtt_locked(gt);
+ mutex_unlock(&ggtt->lock);
+
+ return err;
+}
+
+/**
+ * xe_gt_sriov_vf_deballoon_ggtt_locked - Remove balloon nodes.
+ * @gt: the &xe_gt struct instance
+ */
+void xe_gt_sriov_vf_deballoon_ggtt_locked(struct xe_gt *gt)
{
- struct xe_tile *tile = arg;
+ struct xe_tile *tile = gt_to_tile(gt);
xe_tile_assert(tile, IS_SRIOV_VF(tile_to_xe(tile)));
- xe_ggtt_node_remove_balloon(tile->sriov.vf.ggtt_balloon[1]);
- xe_ggtt_node_remove_balloon(tile->sriov.vf.ggtt_balloon[0]);
+ xe_ggtt_node_remove_balloon_locked(tile->sriov.vf.ggtt_balloon[1]);
+ xe_ggtt_node_remove_balloon_locked(tile->sriov.vf.ggtt_balloon[0]);
+}
+
+static void vf_deballoon_ggtt(struct xe_gt *gt)
+{
+ struct xe_tile *tile = gt_to_tile(gt);
+
+ mutex_lock(&tile->mem.ggtt->lock);
+ xe_gt_sriov_vf_deballoon_ggtt_locked(gt);
+ mutex_unlock(&tile->mem.ggtt->lock);
+}
+
+static void vf_fini_ggtt_balloons(struct xe_gt *gt)
+{
+ struct xe_tile *tile = gt_to_tile(gt);
+
+ xe_gt_assert(gt, IS_SRIOV_VF(gt_to_xe(gt)));
+ xe_gt_assert(gt, !xe_gt_is_media_type(gt));
+
+ xe_ggtt_node_fini(tile->sriov.vf.ggtt_balloon[1]);
+ xe_ggtt_node_fini(tile->sriov.vf.ggtt_balloon[0]);
+}
+
+static void cleanup_ggtt(struct drm_device *drm, void *arg)
+{
+ struct xe_gt *gt = arg;
+
+ vf_deballoon_ggtt(gt);
+ vf_fini_ggtt_balloons(gt);
}
/**
@@ -655,11 +709,17 @@ int xe_gt_sriov_vf_prepare_ggtt(struct xe_gt *gt)
if (xe_gt_is_media_type(gt))
return 0;
- err = vf_balloon_ggtt(gt);
+ err = vf_init_ggtt_balloons(gt);
if (err)
return err;
- return drmm_add_action_or_reset(&xe->drm, deballoon_ggtt, tile);
+ err = vf_balloon_ggtt(gt);
+ if (err) {
+ vf_fini_ggtt_balloons(gt);
+ return err;
+ }
+
+ return drmm_add_action_or_reset(&xe->drm, cleanup_ggtt, gt);
}
static int relay_action_handshake(struct xe_gt *gt, u32 *major, u32 *minor)
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_vf.h b/drivers/gpu/drm/xe/xe_gt_sriov_vf.h
index ba6c5d74e326..d717deb8af91 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_vf.h
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_vf.h
@@ -18,6 +18,8 @@ int xe_gt_sriov_vf_query_config(struct xe_gt *gt);
int xe_gt_sriov_vf_connect(struct xe_gt *gt);
int xe_gt_sriov_vf_query_runtime(struct xe_gt *gt);
int xe_gt_sriov_vf_prepare_ggtt(struct xe_gt *gt);
+int xe_gt_sriov_vf_balloon_ggtt_locked(struct xe_gt *gt);
+void xe_gt_sriov_vf_deballoon_ggtt_locked(struct xe_gt *gt);
int xe_gt_sriov_vf_notify_resfix_done(struct xe_gt *gt);
void xe_gt_sriov_vf_migrated_event_handler(struct xe_gt *gt);
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v10 2/4] drm/xe/vf: Shifting GGTT area post migration
2025-04-15 22:20 [PATCH v10 0/4] drm/xe/vf: Post-migration recovery of GGTT nodes and CTB Tomasz Lis
2025-04-15 22:20 ` [PATCH v10 1/4] drm/xe/vf: Divide GGTT ballooning into allocation and insertion Tomasz Lis
@ 2025-04-15 22:20 ` Tomasz Lis
2025-04-15 22:20 ` [PATCH v10 3/4] drm/xe/guc: Introduce enum with offsets for context register H2Gs Tomasz Lis
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Tomasz Lis @ 2025-04-15 22:20 UTC (permalink / raw)
To: intel-xe
Cc: Michał Winiarski, Michał Wajdeczko,
Piotr Piórkowski, Matthew Brost, Lucas De Marchi
We have only one GGTT for all IOV functions, with each VF having assigned
a range of addresses for its use. After migration, a VF can receive a
different range of addresses than it had initially.
This implements shifting GGTT addresses within drm_mm nodes, so that
VMAs stay valid after migration. This will make the driver use new
addresses when accessing GGTT from the moment the shifting ends.
By taking the ggtt->lock for the period of VMA fixups, this change
also adds constraint on that mutex. Any locks used during the recovery
cannot ever wait for hardware response - because after migration,
the hardware will not do anything until fixups are finished.
v2: Moved some functs to xe_ggtt.c; moved shift computation to just
after querying; improved documentation; switched some warns to asserts;
skipping fixups when GGTT shift eq 0; iterating through tiles (Michal)
v3: Updated kerneldocs, removed unused funct, properly allocate
balloning nodes if non existent
v4: Re-used ballooning functions from VF init, used bool in place of
standard error codes
v5: Renamed one function
v6: Subject tag change, several kerneldocs updated, some functions
renamed, some moved, added several asserts, shuffled declarations
of variables, revealed more detail in high level functions
v7: Fixed typos, added `_locked` suffix to some functs, improved
readability of asserts, removed unneeded conditional
v8: Moved one function, removed implementation detail from kerneldoc,
added asserts
v9: Code shuffling without much change, and one param rename
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/xe/xe_ggtt.c | 50 +++++++++++
drivers/gpu/drm/xe/xe_ggtt.h | 1 +
drivers/gpu/drm/xe/xe_gt_sriov_vf.c | 102 ++++++++++++++++++++++
drivers/gpu/drm/xe/xe_gt_sriov_vf.h | 2 +
drivers/gpu/drm/xe/xe_gt_sriov_vf_types.h | 2 +
drivers/gpu/drm/xe/xe_sriov_vf.c | 22 +++++
6 files changed, 179 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 5a37233f2420..fe299b9683c7 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -484,6 +484,56 @@ void xe_ggtt_node_remove_balloon_locked(struct xe_ggtt_node *node)
drm_mm_remove_node(&node->base);
}
+static void xe_ggtt_assert_fit(struct xe_ggtt *ggtt, u64 start, u64 size)
+{
+ struct xe_tile *tile = ggtt->tile;
+ struct xe_device *xe = tile_to_xe(tile);
+ u64 __maybe_unused wopcm = xe_wopcm_size(xe);
+
+ xe_tile_assert(tile, start >= wopcm);
+ xe_tile_assert(tile, start + size < ggtt->size - wopcm);
+}
+
+/**
+ * xe_ggtt_shift_nodes_locked - Shift GGTT nodes to adjust for a change in usable address range.
+ * @ggtt: the &xe_ggtt struct instance
+ * @shift: change to the location of area provisioned for current VF
+ *
+ * This function moves all nodes from the GGTT VM, to a temp list. These nodes are expected
+ * to represent allocations in range formerly assigned to current VF, before the range changed.
+ * When the GGTT VM is completely clear of any nodes, they are re-added with shifted offsets.
+ *
+ * The function has no ability of failing - because it shifts existing nodes, without
+ * any additional processing. If the nodes were successfully existing at the old address,
+ * they will do the same at the new one. A fail inside this function would indicate that
+ * the list of nodes was either already damaged, or that the shift brings the address range
+ * outside of valid bounds. Both cases justify an assert rather than error code.
+ */
+void xe_ggtt_shift_nodes_locked(struct xe_ggtt *ggtt, s64 shift)
+{
+ struct xe_tile *tile __maybe_unused = ggtt->tile;
+ struct drm_mm_node *node, *tmpn;
+ LIST_HEAD(temp_list_head);
+ int err;
+
+ lockdep_assert_held(&ggtt->lock);
+
+ drm_mm_for_each_node_safe(node, tmpn, &ggtt->mm)
+ xe_ggtt_assert_fit(ggtt, node->start + shift, node->size);
+
+ drm_mm_for_each_node_safe(node, tmpn, &ggtt->mm) {
+ drm_mm_remove_node(node);
+ list_add(&node->node_list, &temp_list_head);
+ }
+
+ list_for_each_entry_safe(node, tmpn, &temp_list_head, node_list) {
+ list_del(&node->node_list);
+ node->start += shift;
+ err = drm_mm_reserve_node(&ggtt->mm, node);
+ xe_tile_assert(tile, !err);
+ }
+}
+
/**
* xe_ggtt_node_insert_locked - Locked version to insert a &xe_ggtt_node into the GGTT
* @node: the &xe_ggtt_node to be inserted
diff --git a/drivers/gpu/drm/xe/xe_ggtt.h b/drivers/gpu/drm/xe/xe_ggtt.h
index d468af96b465..4337a279ff3b 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.h
+++ b/drivers/gpu/drm/xe/xe_ggtt.h
@@ -18,6 +18,7 @@ void xe_ggtt_node_fini(struct xe_ggtt_node *node);
int xe_ggtt_node_insert_balloon_locked(struct xe_ggtt_node *node,
u64 start, u64 size);
void xe_ggtt_node_remove_balloon_locked(struct xe_ggtt_node *node);
+void xe_ggtt_shift_nodes_locked(struct xe_ggtt *ggtt, s64 shift);
int xe_ggtt_node_insert(struct xe_ggtt_node *node, u32 size, u32 align);
int xe_ggtt_node_insert_locked(struct xe_ggtt_node *node,
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
index f82ddff79b3b..613537b90554 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_vf.c
@@ -415,6 +415,7 @@ static int vf_get_ggtt_info(struct xe_gt *gt)
xe_gt_sriov_dbg_verbose(gt, "GGTT %#llx-%#llx = %lluK\n",
start, start + size - 1, size / SZ_1K);
+ config->ggtt_shift = start - (s64)config->ggtt_base;
config->ggtt_base = start;
config->ggtt_size = size;
@@ -560,6 +561,24 @@ u64 xe_gt_sriov_vf_lmem(struct xe_gt *gt)
return gt->sriov.vf.self_config.lmem_size;
}
+/**
+ * xe_gt_sriov_vf_ggtt_shift - Return shift in GGTT range due to VF migration
+ * @gt: the &xe_gt struct instance
+ *
+ * This function is for VF use only.
+ *
+ * Return: The shift value; could be negative
+ */
+s64 xe_gt_sriov_vf_ggtt_shift(struct xe_gt *gt)
+{
+ struct xe_gt_sriov_vf_selfconfig *config = >->sriov.vf.self_config;
+
+ xe_gt_assert(gt, IS_SRIOV_VF(gt_to_xe(gt)));
+ xe_gt_assert(gt, !xe_gt_is_media_type(gt));
+
+ return config->ggtt_shift;
+}
+
static int vf_init_ggtt_balloons(struct xe_gt *gt)
{
struct xe_tile *tile = gt_to_tile(gt);
@@ -817,6 +836,89 @@ int xe_gt_sriov_vf_connect(struct xe_gt *gt)
return err;
}
+/**
+ * DOC: GGTT nodes shifting during VF post-migration recovery
+ *
+ * The first fixup applied to the VF KMD structures as part of post-migration
+ * recovery is shifting nodes within &xe_ggtt instance. The nodes are moved
+ * from range previously assigned to this VF, into newly provisioned area.
+ * The changes include balloons, which are resized accordingly.
+ *
+ * The balloon nodes are there to eliminate unavailable ranges from use: one
+ * reserves the GGTT area below the range for current VF, and another one
+ * reserves area above.
+ *
+ * Below is a GGTT layout of example VF, with a certain address range assigned to
+ * said VF, and inaccessible areas above and below:
+ *
+ * 0 4GiB
+ * |<--------------------------- Total GGTT size ----------------------------->|
+ * WOPCM GUC_TOP
+ * |<-------------- Area mappable by xe_ggtt instance ---------------->|
+ *
+ * +---+---------------------------------+----------+----------------------+---+
+ * |\\\|/////////////////////////////////| VF mem |//////////////////////|\\\|
+ * +---+---------------------------------+----------+----------------------+---+
+ *
+ * Hardware enforced access rules before migration:
+ *
+ * |<------- inaccessible for VF ------->|<VF owned>|<-- inaccessible for VF ->|
+ *
+ * GGTT nodes used for tracking allocations:
+ *
+ * |<---------- balloon ------------>|<- nodes->|<----- balloon ------>|
+ *
+ * After the migration, GGTT area assigned to the VF might have shifted, either
+ * to lower or to higher address. But we expect the total size and extra areas to
+ * be identical, as migration can only happen between matching platforms.
+ * Below is an example of GGTT layout of the VF after migration. Content of the
+ * GGTT for VF has been moved to a new area, and we receive its address from GuC:
+ *
+ * +---+----------------------+----------+---------------------------------+---+
+ * |\\\|//////////////////////| VF mem |/////////////////////////////////|\\\|
+ * +---+----------------------+----------+---------------------------------+---+
+ *
+ * Hardware enforced access rules after migration:
+ *
+ * |<- inaccessible for VF -->|<VF owned>|<------- inaccessible for VF ------->|
+ *
+ * So the VF has a new slice of GGTT assigned, and during migration process, the
+ * memory content was copied to that new area. But the &xe_ggtt nodes are still
+ * tracking allocations using the old addresses. The nodes within VF owned area
+ * have to be shifted, and balloon nodes need to be resized to properly mask out
+ * areas not owned by the VF.
+ *
+ * Fixed &xe_ggtt nodes used for tracking allocations:
+ *
+ * |<------ balloon ------>|<- nodes->|<----------- balloon ----------->|
+ *
+ * Due to use of GPU profiles, we do not expect the old and new GGTT ares to
+ * overlap; but our node shifting will fix addresses properly regardless.
+ */
+
+/**
+ * xe_gt_sriov_vf_fixup_ggtt_nodes - Shift GGTT allocations to match assigned range.
+ * @gt: the &xe_gt struct instance
+ * @shift: the shift value
+ *
+ * Since Global GTT is not virtualized, each VF has an assigned range
+ * within the global space. This range might have changed during migration,
+ * which requires all memory addresses pointing to GGTT to be shifted.
+ */
+void xe_gt_sriov_vf_fixup_ggtt_nodes(struct xe_gt *gt, s64 shift)
+{
+ struct xe_tile *tile = gt_to_tile(gt);
+ struct xe_ggtt *ggtt = tile->mem.ggtt;
+
+ xe_gt_assert(gt, !xe_gt_is_media_type(gt));
+
+ mutex_lock(&ggtt->lock);
+ xe_gt_sriov_vf_deballoon_ggtt_locked(gt);
+ xe_ggtt_shift_nodes_locked(ggtt, shift);
+ xe_gt_sriov_vf_balloon_ggtt_locked(gt);
+ mutex_unlock(&ggtt->lock);
+}
+
/**
* xe_gt_sriov_vf_migrated_event_handler - Start a VF migration recovery,
* or just mark that a GuC is ready for it.
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_vf.h b/drivers/gpu/drm/xe/xe_gt_sriov_vf.h
index d717deb8af91..9db41afddd5a 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_vf.h
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_vf.h
@@ -20,6 +20,8 @@ int xe_gt_sriov_vf_query_runtime(struct xe_gt *gt);
int xe_gt_sriov_vf_prepare_ggtt(struct xe_gt *gt);
int xe_gt_sriov_vf_balloon_ggtt_locked(struct xe_gt *gt);
void xe_gt_sriov_vf_deballoon_ggtt_locked(struct xe_gt *gt);
+s64 xe_gt_sriov_vf_ggtt_shift(struct xe_gt *gt);
+void xe_gt_sriov_vf_fixup_ggtt_nodes(struct xe_gt *gt, s64 shift);
int xe_gt_sriov_vf_notify_resfix_done(struct xe_gt *gt);
void xe_gt_sriov_vf_migrated_event_handler(struct xe_gt *gt);
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_vf_types.h b/drivers/gpu/drm/xe/xe_gt_sriov_vf_types.h
index a57f13b5afcd..5ccbdf8d08b6 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_vf_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_vf_types.h
@@ -40,6 +40,8 @@ struct xe_gt_sriov_vf_selfconfig {
u64 ggtt_base;
/** @ggtt_size: assigned size of the GGTT region. */
u64 ggtt_size;
+ /** @ggtt_shift: difference in ggtt_base on last migration */
+ s64 ggtt_shift;
/** @lmem_size: assigned size of the LMEM. */
u64 lmem_size;
/** @num_ctxs: assigned number of GuC submission context IDs. */
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf.c b/drivers/gpu/drm/xe/xe_sriov_vf.c
index c1275e64aa9c..e70f1ceabbb3 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf.c
+++ b/drivers/gpu/drm/xe/xe_sriov_vf.c
@@ -7,6 +7,7 @@
#include "xe_assert.h"
#include "xe_device.h"
+#include "xe_gt.h"
#include "xe_gt_sriov_printk.h"
#include "xe_gt_sriov_vf.h"
#include "xe_pm.h"
@@ -170,6 +171,25 @@ static bool vf_post_migration_imminent(struct xe_device *xe)
work_pending(&xe->sriov.vf.migration.worker);
}
+static bool vf_post_migration_fixup_ggtt_nodes(struct xe_device *xe)
+{
+ bool need_fixups = false;
+ struct xe_tile *tile;
+ unsigned int id;
+
+ for_each_tile(tile, xe, id) {
+ struct xe_gt *gt = tile->primary_gt;
+ s64 shift;
+
+ shift = xe_gt_sriov_vf_ggtt_shift(gt);
+ if (shift) {
+ need_fixups = true;
+ xe_gt_sriov_vf_fixup_ggtt_nodes(gt, shift);
+ }
+ }
+ return need_fixups;
+}
+
/*
* Notify all GuCs about resource fixups apply finished.
*/
@@ -191,6 +211,7 @@ static void vf_post_migration_notify_resfix_done(struct xe_device *xe)
static void vf_post_migration_recovery(struct xe_device *xe)
{
+ bool need_fixups;
int err;
drm_dbg(&xe->drm, "migration recovery in progress\n");
@@ -201,6 +222,7 @@ static void vf_post_migration_recovery(struct xe_device *xe)
if (unlikely(err))
goto fail;
+ need_fixups = vf_post_migration_fixup_ggtt_nodes(xe);
/* FIXME: add the recovery steps */
vf_post_migration_notify_resfix_done(xe);
xe_pm_runtime_put(xe);
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v10 3/4] drm/xe/guc: Introduce enum with offsets for context register H2Gs
2025-04-15 22:20 [PATCH v10 0/4] drm/xe/vf: Post-migration recovery of GGTT nodes and CTB Tomasz Lis
2025-04-15 22:20 ` [PATCH v10 1/4] drm/xe/vf: Divide GGTT ballooning into allocation and insertion Tomasz Lis
2025-04-15 22:20 ` [PATCH v10 2/4] drm/xe/vf: Shifting GGTT area post migration Tomasz Lis
@ 2025-04-15 22:20 ` Tomasz Lis
2025-04-15 22:20 ` [PATCH v10 4/4] drm/xe/vf: Fixup CTB send buffer messages after migration Tomasz Lis
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Tomasz Lis @ 2025-04-15 22:20 UTC (permalink / raw)
To: intel-xe
Cc: Michał Winiarski, Michał Wajdeczko,
Piotr Piórkowski, Matthew Brost, Lucas De Marchi
Some GuC messages are constructed with incrementing dword counter
rather than referencing specific DWORDs, as described in GuC interface
specification.
This change introduces the definitions of DWORD numbers for parameters
which will need to be referenced in a CTB parser to be added in a
following patch. To ensure correctness of these DWORDs, verification
in form of asserts was added to the message construction code.
v2: Renamed enum members, added ones for single context registration,
modified asserts to check values rather than indexes.
v3: Reordered assert args to take less lines
v4: Added lengths
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Suggested-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> (v3)
---
drivers/gpu/drm/xe/abi/guc_actions_abi.h | 31 ++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_guc_submit.c | 17 +++++++++++++
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
index 448afb86e05c..3c2808fabc6a 100644
--- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h
@@ -161,6 +161,37 @@ enum xe_guc_preempt_options {
XE_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8,
};
+enum xe_guc_register_context_param_offsets {
+ XE_GUC_REGISTER_CONTEXT_DATA_0_MBZ = 0,
+ XE_GUC_REGISTER_CONTEXT_DATA_1_FLAGS,
+ XE_GUC_REGISTER_CONTEXT_DATA_2_CONTEXT_INDEX,
+ XE_GUC_REGISTER_CONTEXT_DATA_3_ENGINE_CLASS,
+ XE_GUC_REGISTER_CONTEXT_DATA_4_ENGINE_SUBMIT_MASK,
+ XE_GUC_REGISTER_CONTEXT_DATA_5_WQ_DESC_ADDR_LOWER,
+ XE_GUC_REGISTER_CONTEXT_DATA_6_WQ_DESC_ADDR_UPPER,
+ XE_GUC_REGISTER_CONTEXT_DATA_7_WQ_BUF_BASE_LOWER,
+ XE_GUC_REGISTER_CONTEXT_DATA_8_WQ_BUF_BASE_UPPER,
+ XE_GUC_REGISTER_CONTEXT_DATA_9_WQ_BUF_SIZE,
+ XE_GUC_REGISTER_CONTEXT_DATA_10_HW_LRC_ADDR,
+ XE_GUC_REGISTER_CONTEXT_MSG_LEN,
+};
+
+enum xe_guc_register_context_multi_lrc_param_offsets {
+ XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_0_MBZ = 0,
+ XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_1_FLAGS,
+ XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_2_PARENT_CONTEXT,
+ XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_3_ENGINE_CLASS,
+ XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_4_ENGINE_SUBMIT_MASK,
+ XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_5_WQ_DESC_ADDR_LOWER,
+ XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_6_WQ_DESC_ADDR_UPPER,
+ XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_7_WQ_BUF_BASE_LOWER,
+ XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_8_WQ_BUF_BASE_UPPER,
+ XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_9_WQ_BUF_SIZE,
+ XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_10_NUM_CTXS,
+ XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_11_HW_LRC_ADDR,
+ XE_GUC_REGISTER_CONTEXT_MULTI_LRC_MSG_LEN = 11,
+};
+
enum xe_guc_report_status {
XE_GUC_REPORT_STATUS_UNKNOWN = 0x0,
XE_GUC_REPORT_STATUS_ACKED = 0x1,
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 813c3c0bb250..cfc65f21b2f7 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -487,6 +487,15 @@ static void __register_mlrc_exec_queue(struct xe_guc *guc,
action[len++] = upper_32_bits(xe_lrc_descriptor(lrc));
}
+ /* explicitly checks some fields that we might fixup later */
+ xe_gt_assert(guc_to_gt(guc), info->wq_desc_lo ==
+ action[XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_5_WQ_DESC_ADDR_LOWER]);
+ xe_gt_assert(guc_to_gt(guc), info->wq_base_lo ==
+ action[XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_7_WQ_BUF_BASE_LOWER]);
+ xe_gt_assert(guc_to_gt(guc), q->width ==
+ action[XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_10_NUM_CTXS]);
+ xe_gt_assert(guc_to_gt(guc), info->hwlrca_lo ==
+ action[XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_11_HW_LRC_ADDR]);
xe_gt_assert(guc_to_gt(guc), len <= MAX_MLRC_REG_SIZE);
#undef MAX_MLRC_REG_SIZE
@@ -511,6 +520,14 @@ static void __register_exec_queue(struct xe_guc *guc,
info->hwlrca_hi,
};
+ /* explicitly checks some fields that we might fixup later */
+ xe_gt_assert(guc_to_gt(guc), info->wq_desc_lo ==
+ action[XE_GUC_REGISTER_CONTEXT_DATA_5_WQ_DESC_ADDR_LOWER]);
+ xe_gt_assert(guc_to_gt(guc), info->wq_base_lo ==
+ action[XE_GUC_REGISTER_CONTEXT_DATA_7_WQ_BUF_BASE_LOWER]);
+ xe_gt_assert(guc_to_gt(guc), info->hwlrca_lo ==
+ action[XE_GUC_REGISTER_CONTEXT_DATA_10_HW_LRC_ADDR]);
+
xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v10 4/4] drm/xe/vf: Fixup CTB send buffer messages after migration
2025-04-15 22:20 [PATCH v10 0/4] drm/xe/vf: Post-migration recovery of GGTT nodes and CTB Tomasz Lis
` (2 preceding siblings ...)
2025-04-15 22:20 ` [PATCH v10 3/4] drm/xe/guc: Introduce enum with offsets for context register H2Gs Tomasz Lis
@ 2025-04-15 22:20 ` Tomasz Lis
2025-04-17 19:06 ` Michal Wajdeczko
2025-04-15 23:15 ` ✓ Xe.CI.BAT: success for drm/xe/vf: Post-migration recovery of GGTT nodes and CTB Patchwork
2025-04-16 8:05 ` ✗ Xe.CI.Full: failure " Patchwork
5 siblings, 1 reply; 10+ messages in thread
From: Tomasz Lis @ 2025-04-15 22:20 UTC (permalink / raw)
To: intel-xe
Cc: Michał Winiarski, Michał Wajdeczko,
Piotr Piórkowski, Matthew Brost, Lucas De Marchi
During post-migration recovery of a VF, it is necessary to update
GGTT references included in messages which are going to be sent
to GuC. GuC will start consuming messages after VF KMD will inform
it about fixups being done; before that, the VF KMD is expected
to update any H2G messages which are already in send buffer but
were not consumed by GuC.
Only a small subset of messages allowed for VFs have GGTT references
in them. This patch adds the functionality to parse the CTB send
ring buffer and shift addresses contained within.
While fixing the CTB content, ct->lock is not taken. This means
the only barrier taken remains GGTT address lock - which is ok,
because only requests with GGTT addresses matter, but it also means
tail changes can happen during the CTB fixups execution (which may
be ignored as any new messages will not have anything to fix).
The GGTT address locking will be introduced in a future series.
v2: removed storing shift as that's now done in VMA nodes patch;
macros to inlines; warns to asserts; log messages fixes (Michal)
v3: removed inline keywords, enums for offsets in CTB messages,
less error messages, if return unused then made functs void (Michal)
v4: update the cached head before starting fixups
v5: removed/updated comments, wrapped lines, converted assert into
error, enums for offsets to separate patch, reused xe_map_rd
v6: define xe_map_*_array() macros, support CTB wrap which divides
a message, updated comments, moved one function to an earlier patch
v7: renamed few functions, wider use on previously introduced helper,
separate cases in parsing messges, documented a static funct
v8: Introduced more helpers, fixed coding style mistakes
v9: Move xe_map*() functs to macros, add asserts, add debug print
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
drivers/gpu/drm/xe/xe_guc_ct.c | 172 +++++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_guc_ct.h | 2 +
drivers/gpu/drm/xe/xe_map.h | 18 ++++
drivers/gpu/drm/xe/xe_sriov_vf.c | 18 ++++
4 files changed, 210 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index 0a4fef7d7225..b0fd05550af8 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -25,6 +25,7 @@
#include "xe_gt_printk.h"
#include "xe_gt_sriov_pf_control.h"
#include "xe_gt_sriov_pf_monitor.h"
+#include "xe_gt_sriov_printk.h"
#include "xe_gt_tlb_invalidation.h"
#include "xe_guc.h"
#include "xe_guc_log.h"
@@ -84,6 +85,8 @@ struct g2h_fence {
bool done;
};
+#define make_u64(hi, lo) ((u64)((u64)(u32)(hi) << 32 | (u32)(lo)))
+
static void g2h_fence_init(struct g2h_fence *g2h_fence, u32 *response_buffer)
{
g2h_fence->response_buffer = response_buffer;
@@ -1623,6 +1626,175 @@ static void g2h_worker_func(struct work_struct *w)
receive_g2h(ct);
}
+static void xe_fixup_u64_in_cmds(struct xe_device *xe, struct iosys_map *cmds,
+ u32 size, u32 idx, s64 shift)
+{
+ u32 hi, lo;
+ u64 offset;
+
+ lo = xe_map_rd_ring_u32(xe, cmds, idx, size);
+ hi = xe_map_rd_ring_u32(xe, cmds, idx + 1, size);
+ offset = make_u64(hi, lo);
+ offset += shift;
+ lo = lower_32_bits(offset);
+ hi = upper_32_bits(offset);
+ xe_map_wr_ring_u32(xe, cmds, idx, size, lo);
+ xe_map_wr_ring_u32(xe, cmds, idx + 1, size, hi);
+}
+
+/*
+ * Shift any GGTT addresses within a single message left within CTB from
+ * before post-migration recovery.
+ * @ct: pointer to CT struct of the target GuC
+ * @cmds: iomap buffer containing CT messages
+ * @head: start of the target message within the buffer
+ * @len: length of the target message
+ * @size: size of the commands buffer
+ * @shift: the address shift to be added to each GGTT reference
+ */
+static void ct_fixup_ggtt_in_message(struct xe_guc_ct *ct,
+ struct iosys_map *cmds, u32 head,
+ u32 len, u32 size, s64 shift)
+{
+ struct xe_gt *gt __maybe_unused = ct_to_gt(ct);
+ struct xe_device *xe = ct_to_xe(ct);
+ u32 msg[GUC_HXG_MSG_MIN_LEN];
+ u32 action, i, n;
+
+ xe_gt_assert(gt, len >= GUC_HXG_MSG_MIN_LEN);
+
+ msg[0] = xe_map_rd_ring_u32(xe, cmds, head, size);
+ action = FIELD_GET(GUC_HXG_REQUEST_MSG_0_ACTION, msg[0]);
+
+ xe_gt_sriov_dbg_verbose(gt, "fixing H2G %#x\n", action);
+
+ switch (action) {
+ case XE_GUC_ACTION_REGISTER_CONTEXT:
+ xe_gt_assert(gt, len >= XE_GUC_REGISTER_CONTEXT_MSG_LEN);
+ xe_fixup_u64_in_cmds(xe, cmds, size, head +
+ XE_GUC_REGISTER_CONTEXT_DATA_5_WQ_DESC_ADDR_LOWER,
+ shift);
+ xe_fixup_u64_in_cmds(xe, cmds, size, head +
+ XE_GUC_REGISTER_CONTEXT_DATA_7_WQ_BUF_BASE_LOWER,
+ shift);
+ xe_fixup_u64_in_cmds(xe, cmds, size, head +
+ XE_GUC_REGISTER_CONTEXT_DATA_10_HW_LRC_ADDR, shift);
+ break;
+ case XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC:
+ xe_gt_assert(gt, len >= XE_GUC_REGISTER_CONTEXT_MULTI_LRC_MSG_LEN);
+ xe_fixup_u64_in_cmds(xe, cmds, size, head +
+ XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_5_WQ_DESC_ADDR_LOWER,
+ shift);
+ xe_fixup_u64_in_cmds(xe, cmds, size, head +
+ XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_7_WQ_BUF_BASE_LOWER,
+ shift);
+ n = xe_map_rd_ring_u32(xe, cmds, head +
+ XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_10_NUM_CTXS, size);
+ xe_gt_assert(gt, len >= XE_GUC_REGISTER_CONTEXT_MULTI_LRC_MSG_LEN + 2 * n);
+ for (i = 0; i < n; i++)
+ xe_fixup_u64_in_cmds(xe, cmds, size, head +
+ XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_11_HW_LRC_ADDR
+ + 2 * i, shift);
+ break;
+ default:
+ break;
+ }
+}
+
+/*
+ * Apply fixups to the next outgoing CT message within given CTB
+ * @ct: the &xe_guc_ct struct instance representing the target GuC
+ * @h2g: the &guc_ctb struct instance of the target buffer
+ * @shift: shift to be added to all GGTT addresses within the CTB
+ * @mhead: pointer to an integer storing message start position; the
+ * position is changed to next message before this function return
+ * @avail: size of the area available for parsing, that is length
+ * of all remaining messages stored within the CTB
+ * Return: size of the area available for parsing after one message
+ * has been parsed, that is length remaining from the updated mhead
+ */
+static int ct_fixup_ggtt_in_buffer(struct xe_guc_ct *ct, struct guc_ctb *h2g,
+ s64 shift, u32 *mhead, s32 avail)
+{
+ struct xe_device *xe = ct_to_xe(ct);
+ u32 msg[GUC_HXG_MSG_MIN_LEN];
+ u32 size = h2g->info.size;
+ u32 head = *mhead;
+ u32 len;
+
+ xe_gt_assert(ct_to_gt(ct), avail >= (s32)GUC_CTB_MSG_MIN_LEN);
+
+ /* Read header */
+ msg[0] = xe_map_rd_ring_u32(xe, &h2g->cmds, head, size);
+ len = FIELD_GET(GUC_CTB_MSG_0_NUM_DWORDS, msg[0]) + GUC_CTB_MSG_MIN_LEN;
+
+ if (unlikely(len > (u32)avail)) {
+ xe_gt_err(ct_to_gt(ct), "H2G channel broken on read, avail=%d, len=%d, fixups skipped\n",
+ avail, len);
+ return 0;
+ }
+
+ head = (head + GUC_CTB_MSG_MIN_LEN) % size;
+ ct_fixup_ggtt_in_message(ct, &h2g->cmds, head, msg_len_to_hxg_len(len), size, shift);
+ *mhead = (head + msg_len_to_hxg_len(len)) % size;
+
+ return avail - len;
+}
+
+/**
+ * xe_guc_ct_fixup_messages_with_ggtt - Fixup any pending H2G CTB messages
+ * @ct: pointer to CT struct of the target GuC
+ * @ggtt_shift: shift to be added to all GGTT addresses within the CTB
+ *
+ * Messages in GuC to Host CTB are owned by GuC and any fixups in them
+ * are made by GuC. But content of the Host to GuC CTB is owned by the
+ * KMD, so fixups to GGTT references in any pending messages need to be
+ * applied here.
+ * This function updates GGTT offsets in payloads of pending H2G CTB
+ * messages (messages which were not consumed by GuC before the VF got
+ * paused).
+ */
+void xe_guc_ct_fixup_messages_with_ggtt(struct xe_guc_ct *ct, s64 ggtt_shift)
+{
+ struct guc_ctb *h2g = &ct->ctbs.h2g;
+ struct xe_guc *guc = ct_to_guc(ct);
+ struct xe_gt *gt = guc_to_gt(guc);
+ u32 head, tail, size;
+ s32 avail;
+
+ if (unlikely(h2g->info.broken))
+ return;
+
+ h2g->info.head = desc_read(ct_to_xe(ct), h2g, head);
+ head = h2g->info.head;
+ tail = READ_ONCE(h2g->info.tail);
+ size = h2g->info.size;
+
+ if (unlikely(head > size))
+ goto corrupted;
+
+ if (unlikely(tail >= size))
+ goto corrupted;
+
+ avail = tail - head;
+
+ /* beware of buffer wrap case */
+ if (unlikely(avail < 0))
+ avail += size;
+ xe_gt_dbg(gt, "available %d (%u:%u:%u)\n", avail, head, tail, size);
+ xe_gt_assert(gt, avail >= 0);
+
+ while (avail > 0)
+ avail = ct_fixup_ggtt_in_buffer(ct, h2g, ggtt_shift, &head, avail);
+
+ return;
+
+corrupted:
+ xe_gt_err(gt, "Corrupted H2G descriptor head=%u tail=%u size=%u, fixups not applied\n",
+ head, tail, size);
+ h2g->info.broken = true;
+}
+
static struct xe_guc_ct_snapshot *guc_ct_snapshot_alloc(struct xe_guc_ct *ct, bool atomic,
bool want_ctb)
{
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.h b/drivers/gpu/drm/xe/xe_guc_ct.h
index 82c4ae458dda..5649bda82823 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.h
+++ b/drivers/gpu/drm/xe/xe_guc_ct.h
@@ -22,6 +22,8 @@ void xe_guc_ct_snapshot_print(struct xe_guc_ct_snapshot *snapshot, struct drm_pr
void xe_guc_ct_snapshot_free(struct xe_guc_ct_snapshot *snapshot);
void xe_guc_ct_print(struct xe_guc_ct *ct, struct drm_printer *p, bool want_ctb);
+void xe_guc_ct_fixup_messages_with_ggtt(struct xe_guc_ct *ct, s64 ggtt_shift);
+
static inline bool xe_guc_ct_enabled(struct xe_guc_ct *ct)
{
return ct->state == XE_GUC_CT_STATE_ENABLED;
diff --git a/drivers/gpu/drm/xe/xe_map.h b/drivers/gpu/drm/xe/xe_map.h
index f62e0c8b67ab..fa65e6c908fa 100644
--- a/drivers/gpu/drm/xe/xe_map.h
+++ b/drivers/gpu/drm/xe/xe_map.h
@@ -78,6 +78,24 @@ static inline void xe_map_write32(struct xe_device *xe, struct iosys_map *map,
iosys_map_wr(map__, offset__, type__, val__); \
})
+#define xe_map_rd_array(xe__, map__, index__, type__) \
+ xe_map_rd(xe__, map__, (index__) * sizeof(type__), type__)
+
+#define xe_map_wr_array(xe__, map__, index__, type__, val__) \
+ xe_map_wr(xe__, map__, (index__) * sizeof(type__), type__, val__)
+
+#define xe_map_rd_array_u32(xe__, map__, index__) \
+ xe_map_rd_array(xe__, map__, index__, u32)
+
+#define xe_map_wr_array_u32(xe__, map__, index__, val__) \
+ xe_map_wr_array(xe__, map__, index__, u32, val__)
+
+#define xe_map_rd_ring_u32(xe__, map__, index__, size__) \
+ xe_map_rd_array_u32(xe__, map__, (index__) % (size__))
+
+#define xe_map_wr_ring_u32(xe__, map__, index__, size__, val__) \
+ xe_map_wr_array_u32(xe__, map__, (index__) % (size__), val__)
+
#define xe_map_rd_field(xe__, map__, struct_offset__, struct_type__, field__) ({ \
struct xe_device *__xe = xe__; \
xe_device_assert_mem_access(__xe); \
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf.c b/drivers/gpu/drm/xe/xe_sriov_vf.c
index e70f1ceabbb3..2674fa948fda 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf.c
+++ b/drivers/gpu/drm/xe/xe_sriov_vf.c
@@ -10,6 +10,7 @@
#include "xe_gt.h"
#include "xe_gt_sriov_printk.h"
#include "xe_gt_sriov_vf.h"
+#include "xe_guc_ct.h"
#include "xe_pm.h"
#include "xe_sriov.h"
#include "xe_sriov_printk.h"
@@ -158,6 +159,20 @@ static int vf_post_migration_requery_guc(struct xe_device *xe)
return ret;
}
+static void vf_post_migration_fixup_ctb(struct xe_device *xe)
+{
+ struct xe_gt *gt;
+ unsigned int id;
+
+ xe_assert(xe, IS_SRIOV_VF(xe));
+
+ for_each_gt(gt, xe, id) {
+ s32 shift = xe_gt_sriov_vf_ggtt_shift(gt);
+
+ xe_guc_ct_fixup_messages_with_ggtt(>->uc.guc.ct, shift);
+ }
+}
+
/*
* vf_post_migration_imminent - Check if post-restore recovery is coming.
* @xe: the &xe_device struct instance
@@ -224,6 +239,9 @@ static void vf_post_migration_recovery(struct xe_device *xe)
need_fixups = vf_post_migration_fixup_ggtt_nodes(xe);
/* FIXME: add the recovery steps */
+ if (need_fixups)
+ vf_post_migration_fixup_ctb(xe);
+
vf_post_migration_notify_resfix_done(xe);
xe_pm_runtime_put(xe);
drm_notice(&xe->drm, "migration recovery ended\n");
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* ✓ Xe.CI.BAT: success for drm/xe/vf: Post-migration recovery of GGTT nodes and CTB
2025-04-15 22:20 [PATCH v10 0/4] drm/xe/vf: Post-migration recovery of GGTT nodes and CTB Tomasz Lis
` (3 preceding siblings ...)
2025-04-15 22:20 ` [PATCH v10 4/4] drm/xe/vf: Fixup CTB send buffer messages after migration Tomasz Lis
@ 2025-04-15 23:15 ` Patchwork
2025-04-16 8:05 ` ✗ Xe.CI.Full: failure " Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2025-04-15 23:15 UTC (permalink / raw)
To: Tomasz Lis; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 963 bytes --]
== Series Details ==
Series: drm/xe/vf: Post-migration recovery of GGTT nodes and CTB
URL : https://patchwork.freedesktop.org/series/147786/
State : success
== Summary ==
CI Bug Log - changes from xe-2956-b61f5de7570012cb79e72624a97b216d395f7380_BAT -> xe-pw-147786v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 8)
------------------------------
Missing (1): bat-adlp-vm
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-2956-b61f5de7570012cb79e72624a97b216d395f7380 -> xe-pw-147786v1
IGT_8320: cd3b5612be3cef838f16e074bf1bc421399d584d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-2956-b61f5de7570012cb79e72624a97b216d395f7380: b61f5de7570012cb79e72624a97b216d395f7380
xe-pw-147786v1: 147786v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/index.html
[-- Attachment #2: Type: text/html, Size: 1511 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✗ Xe.CI.Full: failure for drm/xe/vf: Post-migration recovery of GGTT nodes and CTB
2025-04-15 22:20 [PATCH v10 0/4] drm/xe/vf: Post-migration recovery of GGTT nodes and CTB Tomasz Lis
` (4 preceding siblings ...)
2025-04-15 23:15 ` ✓ Xe.CI.BAT: success for drm/xe/vf: Post-migration recovery of GGTT nodes and CTB Patchwork
@ 2025-04-16 8:05 ` Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2025-04-16 8:05 UTC (permalink / raw)
To: Tomasz Lis; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 78560 bytes --]
== Series Details ==
Series: drm/xe/vf: Post-migration recovery of GGTT nodes and CTB
URL : https://patchwork.freedesktop.org/series/147786/
State : failure
== Summary ==
CI Bug Log - changes from xe-2956-b61f5de7570012cb79e72624a97b216d395f7380_FULL -> xe-pw-147786v1_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-147786v1_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-147786v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-147786v1_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_plane_alpha_blend@constant-alpha-min:
- shard-bmg: [PASS][1] -> [SKIP][2] +2 other tests skip
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-2/igt@kms_plane_alpha_blend@constant-alpha-min.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-6/igt@kms_plane_alpha_blend@constant-alpha-min.html
* igt@kms_vblank@wait-forked:
- shard-bmg: [PASS][3] -> [FAIL][4] +5 other tests fail
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-8/igt@kms_vblank@wait-forked.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-6/igt@kms_vblank@wait-forked.html
* igt@xe_exec_sip_eudebug@breakpoint-writesip-nodebug@drm_xe_engine_class_compute0:
- shard-lnl: NOTRUN -> [DMESG-FAIL][5]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-5/igt@xe_exec_sip_eudebug@breakpoint-writesip-nodebug@drm_xe_engine_class_compute0.html
#### Warnings ####
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-bmg: [SKIP][6] ([Intel XE#2321]) -> [SKIP][7] +1 other test skip
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-8/igt@kms_cursor_crc@cursor-sliding-512x512.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-6/igt@kms_cursor_crc@cursor-sliding-512x512.html
New tests
---------
New tests have been introduced between xe-2956-b61f5de7570012cb79e72624a97b216d395f7380_FULL and xe-pw-147786v1_FULL:
### New IGT tests (2) ###
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-c-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [19.09] s
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing@pipe-d-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [19.09] s
Known issues
------------
Here are the changes found in xe-pw-147786v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_addfb_basic@bad-pitch-1024:
- shard-adlp: [PASS][8] -> [DMESG-WARN][9] ([Intel XE#4173]) +2 other tests dmesg-warn
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-adlp-3/igt@kms_addfb_basic@bad-pitch-1024.html
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-adlp-6/igt@kms_addfb_basic@bad-pitch-1024.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-bmg: [PASS][10] -> [FAIL][11] ([Intel XE#827])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-4/igt@kms_async_flips@alternate-sync-async-flip.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-7/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][12] ([Intel XE#827])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-7/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-2.html
* igt@kms_async_flips@async-flip-with-page-flip-events-atomic:
- shard-bmg: [PASS][13] -> [FAIL][14] ([Intel XE#4781]) +3 other tests fail
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-2/igt@kms_async_flips@async-flip-with-page-flip-events-atomic.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-6/igt@kms_async_flips@async-flip-with-page-flip-events-atomic.html
* igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-dp-2-linear:
- shard-bmg: [PASS][15] -> [FAIL][16] ([Intel XE#4782])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-2/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-dp-2-linear.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-6/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-dp-2-linear.html
* igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-b-hdmi-a-6-4-mc-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][17] ([Intel XE#3767]) +7 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-b-hdmi-a-6-4-mc-ccs.html
* igt@kms_async_flips@crc:
- shard-adlp: [PASS][18] -> [DMESG-FAIL][19] ([Intel XE#4543]) +2 other tests dmesg-fail
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-adlp-9/igt@kms_async_flips@crc.html
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-adlp-1/igt@kms_async_flips@crc.html
* igt@kms_async_flips@invalid-async-flip-atomic:
- shard-lnl: NOTRUN -> [SKIP][20] ([Intel XE#3768])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-5/igt@kms_async_flips@invalid-async-flip-atomic.html
- shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#3768])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_async_flips@invalid-async-flip-atomic.html
* igt@kms_async_flips@overlay-atomic:
- shard-lnl: NOTRUN -> [SKIP][22] ([Intel XE#4761])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_async_flips@overlay-atomic.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-270:
- shard-lnl: NOTRUN -> [SKIP][23] ([Intel XE#1407])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][24] ([Intel XE#316]) +1 other test skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-432/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#2327])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-0:
- shard-lnl: NOTRUN -> [SKIP][26] ([Intel XE#1124]) +2 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-dg2-set2: NOTRUN -> [SKIP][27] ([Intel XE#1124]) +3 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-432/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-bmg: NOTRUN -> [SKIP][28] ([Intel XE#1124])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#2328])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-adlp: NOTRUN -> [SKIP][30] ([Intel XE#607])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-adlp-3/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
- shard-lnl: NOTRUN -> [SKIP][31] ([Intel XE#2191])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
* igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p:
- shard-dg2-set2: NOTRUN -> [SKIP][32] ([Intel XE#2191]) +1 other test skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-432/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html
* igt@kms_bw@linear-tiling-2-displays-1920x1080p:
- shard-dg2-set2: NOTRUN -> [SKIP][33] ([Intel XE#367])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html
* igt@kms_bw@linear-tiling-4-displays-1920x1080p:
- shard-lnl: NOTRUN -> [SKIP][34] ([Intel XE#1512])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_bw@linear-tiling-4-displays-1920x1080p.html
* igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][35] ([Intel XE#787]) +103 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-436/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-6.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs:
- shard-lnl: NOTRUN -> [SKIP][36] ([Intel XE#2887]) +3 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [SKIP][37] ([Intel XE#2652] / [Intel XE#787]) +7 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-dp-2.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-a-edp-1:
- shard-lnl: NOTRUN -> [SKIP][38] ([Intel XE#2669]) +3 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-a-edp-1.html
* igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][39] ([Intel XE#2887]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][40] ([Intel XE#455] / [Intel XE#787]) +22 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4:
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][41] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html
* igt@kms_chamelium_color@ctm-negative:
- shard-lnl: NOTRUN -> [SKIP][42] ([Intel XE#306])
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-5/igt@kms_chamelium_color@ctm-negative.html
- shard-bmg: NOTRUN -> [SKIP][43] ([Intel XE#2325])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_frames@vga-frame-dump:
- shard-lnl: NOTRUN -> [SKIP][44] ([Intel XE#373])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_chamelium_frames@vga-frame-dump.html
* igt@kms_chamelium_hpd@dp-hpd-after-suspend:
- shard-dg2-set2: NOTRUN -> [SKIP][45] ([Intel XE#373]) +1 other test skip
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-463/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
* igt@kms_content_protection@lic-type-0:
- shard-lnl: NOTRUN -> [SKIP][46] ([Intel XE#3278])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-5/igt@kms_content_protection@lic-type-0.html
- shard-bmg: NOTRUN -> [SKIP][47] ([Intel XE#2341])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@lic-type-0@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [FAIL][48] ([Intel XE#3304])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-433/igt@kms_content_protection@lic-type-0@pipe-a-dp-4.html
* igt@kms_content_protection@srm@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][49] ([Intel XE#1178]) +1 other test fail
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-1/igt@kms_content_protection@srm@pipe-a-dp-2.html
* igt@kms_content_protection@uevent:
- shard-dg2-set2: NOTRUN -> [FAIL][50] ([Intel XE#1188]) +1 other test fail
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-432/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-dg2-set2: NOTRUN -> [SKIP][51] ([Intel XE#308])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-sliding-256x85:
- shard-bmg: NOTRUN -> [SKIP][52] ([Intel XE#2320])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_cursor_crc@cursor-sliding-256x85.html
- shard-lnl: NOTRUN -> [SKIP][53] ([Intel XE#1424])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-5/igt@kms_cursor_crc@cursor-sliding-256x85.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy:
- shard-lnl: NOTRUN -> [SKIP][54] ([Intel XE#309]) +1 other test skip
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_cursor_legacy@2x-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
- shard-bmg: [PASS][55] -> [SKIP][56] ([Intel XE#2291]) +5 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-3/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-dg2-set2: NOTRUN -> [SKIP][57] ([Intel XE#309])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-dg2-set2: [PASS][58] -> [SKIP][59] ([Intel XE#309])
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-436/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
- shard-bmg: NOTRUN -> [SKIP][60] ([Intel XE#2291])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-adlp: NOTRUN -> [SKIP][61] ([Intel XE#309])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-adlp-3/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_dp_link_training@non-uhbr-sst:
- shard-bmg: [PASS][62] -> [SKIP][63] ([Intel XE#4354])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-1/igt@kms_dp_link_training@non-uhbr-sst.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_dp_link_training@non-uhbr-sst.html
- shard-dg2-set2: [PASS][64] -> [SKIP][65] ([Intel XE#4354])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-434/igt@kms_dp_link_training@non-uhbr-sst.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_dp_link_training@non-uhbr-sst.html
* igt@kms_dp_linktrain_fallback@dsc-fallback:
- shard-dg2-set2: NOTRUN -> [SKIP][66] ([Intel XE#4331])
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_dp_linktrain_fallback@dsc-fallback.html
* igt@kms_dsc@dsc-basic:
- shard-bmg: NOTRUN -> [SKIP][67] ([Intel XE#2244])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_dsc@dsc-basic.html
- shard-lnl: NOTRUN -> [SKIP][68] ([Intel XE#2244])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-5/igt@kms_dsc@dsc-basic.html
* igt@kms_feature_discovery@display-2x:
- shard-lnl: NOTRUN -> [SKIP][69] ([Intel XE#702])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_feature_discovery@display-2x.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-bmg: NOTRUN -> [SKIP][70] ([Intel XE#2316])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_flip@2x-absolute-wf_vblank.html
- shard-lnl: NOTRUN -> [SKIP][71] ([Intel XE#1421])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-5/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-blocking-wf_vblank:
- shard-bmg: [PASS][72] -> [DMESG-FAIL][73] ([Intel XE#3428]) +1 other test dmesg-fail
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-2/igt@kms_flip@2x-blocking-wf_vblank.html
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-6/igt@kms_flip@2x-blocking-wf_vblank.html
- shard-dg2-set2: NOTRUN -> [SKIP][74] ([Intel XE#310])
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_flip@2x-blocking-wf_vblank.html
* igt@kms_flip@2x-blocking-wf_vblank@ac-dp2-hdmi-a3:
- shard-bmg: [PASS][75] -> [FAIL][76] ([Intel XE#2882]) +11 other tests fail
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-2/igt@kms_flip@2x-blocking-wf_vblank@ac-dp2-hdmi-a3.html
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-6/igt@kms_flip@2x-blocking-wf_vblank@ac-dp2-hdmi-a3.html
* igt@kms_flip@2x-dpms-vs-vblank-race:
- shard-adlp: NOTRUN -> [SKIP][77] ([Intel XE#310])
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-adlp-3/igt@kms_flip@2x-dpms-vs-vblank-race.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a2-dp2:
- shard-dg2-set2: [PASS][78] -> [FAIL][79] ([Intel XE#301])
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-432/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a2-dp2.html
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-432/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a2-dp2.html
* igt@kms_flip@2x-nonexisting-fb:
- shard-bmg: [PASS][80] -> [SKIP][81] ([Intel XE#2316]) +6 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-7/igt@kms_flip@2x-nonexisting-fb.html
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_flip@2x-nonexisting-fb.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-dg2-set2: [PASS][82] -> [SKIP][83] ([Intel XE#310]) +3 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-434/igt@kms_flip@2x-plain-flip-fb-recreate.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_flip@2x-plain-flip-fb-recreate.html
* igt@kms_flip@flip-vs-expired-vblank@c-dp4:
- shard-dg2-set2: [PASS][84] -> [FAIL][85] ([Intel XE#301] / [Intel XE#3321])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-433/igt@kms_flip@flip-vs-expired-vblank@c-dp4.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-463/igt@kms_flip@flip-vs-expired-vblank@c-dp4.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a3:
- shard-bmg: [PASS][86] -> [FAIL][87] ([Intel XE#3321]) +1 other test fail
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-6/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a3.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-7/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a3.html
* igt@kms_flip@flip-vs-suspend@d-hdmi-a1:
- shard-adlp: [PASS][88] -> [DMESG-WARN][89] ([Intel XE#2953] / [Intel XE#4173]) +1 other test dmesg-warn
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-adlp-6/igt@kms_flip@flip-vs-suspend@d-hdmi-a1.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-adlp-4/igt@kms_flip@flip-vs-suspend@d-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend@d-hdmi-a3:
- shard-bmg: NOTRUN -> [INCOMPLETE][90] ([Intel XE#2049] / [Intel XE#2597])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-7/igt@kms_flip@flip-vs-suspend@d-hdmi-a3.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
- shard-lnl: NOTRUN -> [SKIP][91] ([Intel XE#1401] / [Intel XE#1745])
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-default-mode:
- shard-lnl: NOTRUN -> [SKIP][92] ([Intel XE#1401])
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][93] ([Intel XE#2311]) +3 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff:
- shard-adlp: NOTRUN -> [SKIP][94] ([Intel XE#651])
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-adlp-3/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw:
- shard-adlp: NOTRUN -> [SKIP][95] ([Intel XE#656]) +1 other test skip
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-adlp-3/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-plflip-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][96] ([Intel XE#656]) +5 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-render:
- shard-lnl: NOTRUN -> [SKIP][97] ([Intel XE#656]) +10 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][98] ([Intel XE#4141]) +1 other test skip
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt:
- shard-dg2-set2: [PASS][99] -> [SKIP][100] ([Intel XE#656]) +5 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-434/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-bmg: NOTRUN -> [SKIP][101] ([Intel XE#2312]) +6 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render:
- shard-lnl: NOTRUN -> [SKIP][102] ([Intel XE#651]) +4 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff:
- shard-dg2-set2: NOTRUN -> [SKIP][103] ([Intel XE#651]) +7 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- shard-bmg: NOTRUN -> [SKIP][104] ([Intel XE#2313]) +2 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][105] ([Intel XE#653]) +9 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-pgflip-blt.html
* igt@kms_hdr@invalid-hdr:
- shard-dg2-set2: NOTRUN -> [SKIP][106] ([Intel XE#455]) +4 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_hdr@invalid-hdr.html
* igt@kms_hdr@static-swap:
- shard-bmg: [PASS][107] -> [SKIP][108] ([Intel XE#1503]) +1 other test skip
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-3/igt@kms_hdr@static-swap.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_hdr@static-swap.html
* igt@kms_joiner@basic-big-joiner:
- shard-dg2-set2: NOTRUN -> [SKIP][109] ([Intel XE#346])
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-463/igt@kms_joiner@basic-big-joiner.html
* igt@kms_joiner@basic-force-ultra-joiner:
- shard-bmg: NOTRUN -> [SKIP][110] ([Intel XE#2934])
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_joiner@basic-force-ultra-joiner.html
* igt@kms_joiner@basic-max-non-joiner:
- shard-adlp: NOTRUN -> [SKIP][111] ([Intel XE#4298])
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-adlp-3/igt@kms_joiner@basic-max-non-joiner.html
* igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256:
- shard-dg2-set2: NOTRUN -> [FAIL][112] ([Intel XE#616]) +2 other tests fail
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-436/igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256.html
* igt@kms_plane_multiple@tiling-x@pipe-b-edp-1:
- shard-lnl: NOTRUN -> [FAIL][113] ([Intel XE#4658]) +3 other tests fail
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-5/igt@kms_plane_multiple@tiling-x@pipe-b-edp-1.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-lnl: NOTRUN -> [SKIP][114] ([Intel XE#3307])
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-dg2-set2: NOTRUN -> [SKIP][115] ([Intel XE#836])
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-dg2-set2: [PASS][116] -> [SKIP][117] ([Intel XE#836])
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-434/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area:
- shard-dg2-set2: NOTRUN -> [SKIP][118] ([Intel XE#1489]) +2 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-432/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr@fbc-pr-cursor-plane-onoff:
- shard-lnl: NOTRUN -> [SKIP][119] ([Intel XE#1406]) +1 other test skip
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_psr@fbc-pr-cursor-plane-onoff.html
* igt@kms_psr@fbc-psr-sprite-render:
- shard-dg2-set2: NOTRUN -> [SKIP][120] ([Intel XE#2850] / [Intel XE#929]) +2 other tests skip
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-463/igt@kms_psr@fbc-psr-sprite-render.html
* igt@kms_psr@fbc-psr2-cursor-render@edp-1:
- shard-lnl: NOTRUN -> [SKIP][121] ([Intel XE#4609])
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_psr@fbc-psr2-cursor-render@edp-1.html
* igt@kms_psr@psr2-cursor-plane-move:
- shard-bmg: NOTRUN -> [SKIP][122] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_psr@psr2-cursor-plane-move.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-adlp: NOTRUN -> [SKIP][123] ([Intel XE#2939])
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-adlp-3/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-dg2-set2: NOTRUN -> [SKIP][124] ([Intel XE#3414])
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@primary-rotation-90:
- shard-bmg: NOTRUN -> [SKIP][125] ([Intel XE#3414] / [Intel XE#3904])
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_rotation_crc@primary-rotation-90.html
- shard-lnl: NOTRUN -> [SKIP][126] ([Intel XE#3414] / [Intel XE#3904])
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-5/igt@kms_rotation_crc@primary-rotation-90.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-lnl: NOTRUN -> [SKIP][127] ([Intel XE#1127])
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_vrr@negative-basic:
- shard-bmg: [PASS][128] -> [SKIP][129] ([Intel XE#1499])
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-1/igt@kms_vrr@negative-basic.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_vrr@negative-basic.html
- shard-dg2-set2: [PASS][130] -> [SKIP][131] ([Intel XE#455])
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-434/igt@kms_vrr@negative-basic.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_vrr@negative-basic.html
* igt@xe_copy_basic@mem-copy-linear-0xfffe:
- shard-dg2-set2: NOTRUN -> [SKIP][132] ([Intel XE#1123])
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-432/igt@xe_copy_basic@mem-copy-linear-0xfffe.html
* igt@xe_create@create-big-vram:
- shard-lnl: NOTRUN -> [SKIP][133] ([Intel XE#1062])
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@xe_create@create-big-vram.html
* igt@xe_eudebug@basic-close:
- shard-lnl: NOTRUN -> [SKIP][134] ([Intel XE#2905]) +4 other tests skip
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@xe_eudebug@basic-close.html
* igt@xe_eudebug@basic-vm-bind-ufence-reconnect:
- shard-adlp: NOTRUN -> [SKIP][135] ([Intel XE#2905] / [Intel XE#3889])
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-adlp-3/igt@xe_eudebug@basic-vm-bind-ufence-reconnect.html
* igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-sram:
- shard-dg2-set2: NOTRUN -> [SKIP][136] ([Intel XE#2905]) +3 other tests skip
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-sram.html
* igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram:
- shard-bmg: NOTRUN -> [SKIP][137] ([Intel XE#2905]) +2 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-vram.html
* igt@xe_evict@evict-small-external:
- shard-lnl: NOTRUN -> [SKIP][138] ([Intel XE#688])
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-5/igt@xe_evict@evict-small-external.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind:
- shard-dg2-set2: [PASS][139] -> [SKIP][140] ([Intel XE#1392]) +2 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-436/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind.html
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind.html
* igt@xe_exec_basic@multigpu-once-basic-defer-mmap:
- shard-lnl: NOTRUN -> [SKIP][141] ([Intel XE#1392]) +2 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-5/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
- shard-bmg: NOTRUN -> [SKIP][142] ([Intel XE#2322])
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
* igt@xe_exec_basic@multigpu-once-null-rebind:
- shard-dg2-set2: NOTRUN -> [SKIP][143] ([Intel XE#1392])
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-432/igt@xe_exec_basic@multigpu-once-null-rebind.html
* igt@xe_exec_fault_mode@many-basic:
- shard-adlp: NOTRUN -> [SKIP][144] ([Intel XE#288]) +1 other test skip
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-adlp-3/igt@xe_exec_fault_mode@many-basic.html
* igt@xe_exec_fault_mode@many-execqueues-basic-imm:
- shard-dg2-set2: NOTRUN -> [SKIP][145] ([Intel XE#288]) +7 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-432/igt@xe_exec_fault_mode@many-execqueues-basic-imm.html
* igt@xe_exec_reset@cm-close-fd:
- shard-adlp: [PASS][146] -> [DMESG-WARN][147] ([Intel XE#3868])
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-adlp-4/igt@xe_exec_reset@cm-close-fd.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-adlp-3/igt@xe_exec_reset@cm-close-fd.html
* igt@xe_exec_sip_eudebug@breakpoint-writesip-nodebug:
- shard-lnl: NOTRUN -> [ABORT][148] ([Intel XE#4624]) +1 other test abort
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-5/igt@xe_exec_sip_eudebug@breakpoint-writesip-nodebug.html
* igt@xe_exec_threads@threads-bal-mixed-fd-rebind:
- shard-bmg: [PASS][149] -> [DMESG-WARN][150] ([Intel XE#3428]) +10 other tests dmesg-warn
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-2/igt@xe_exec_threads@threads-bal-mixed-fd-rebind.html
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-6/igt@xe_exec_threads@threads-bal-mixed-fd-rebind.html
* igt@xe_exec_threads@threads-hang-rebind-err:
- shard-lnl: [PASS][151] -> [DMESG-WARN][152] ([Intel XE#3876])
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-lnl-6/igt@xe_exec_threads@threads-hang-rebind-err.html
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@xe_exec_threads@threads-hang-rebind-err.html
* igt@xe_oa@enable-disable:
- shard-dg2-set2: NOTRUN -> [SKIP][153] ([Intel XE#2541] / [Intel XE#3573]) +1 other test skip
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@xe_oa@enable-disable.html
* igt@xe_oa@enable-disable@ccs-0:
- shard-bmg: NOTRUN -> [FAIL][154] ([Intel XE#4804])
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-6/igt@xe_oa@enable-disable@ccs-0.html
* igt@xe_oa@polling-small-buf:
- shard-lnl: NOTRUN -> [FAIL][155] ([Intel XE#4810])
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-5/igt@xe_oa@polling-small-buf.html
- shard-bmg: NOTRUN -> [FAIL][156] ([Intel XE#4810])
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@xe_oa@polling-small-buf.html
* igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p:
- shard-dg2-set2: NOTRUN -> [FAIL][157] ([Intel XE#1173])
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-436/igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p.html
* igt@xe_pm@d3cold-mmap-system:
- shard-dg2-set2: NOTRUN -> [SKIP][158] ([Intel XE#2284] / [Intel XE#366])
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-432/igt@xe_pm@d3cold-mmap-system.html
* igt@xe_pm@s3-mocs:
- shard-lnl: NOTRUN -> [SKIP][159] ([Intel XE#584])
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@xe_pm@s3-mocs.html
* igt@xe_pm@s4-basic:
- shard-lnl: [PASS][160] -> [ABORT][161] ([Intel XE#1794])
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-lnl-5/igt@xe_pm@s4-basic.html
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-2/igt@xe_pm@s4-basic.html
* igt@xe_pxp@pxp-termination-key-update-post-termination-irq:
- shard-dg2-set2: NOTRUN -> [SKIP][162] ([Intel XE#4733])
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@xe_pxp@pxp-termination-key-update-post-termination-irq.html
* igt@xe_pxp@regular-src-to-pxp-dest-rendercopy:
- shard-bmg: NOTRUN -> [SKIP][163] ([Intel XE#4733])
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@xe_pxp@regular-src-to-pxp-dest-rendercopy.html
* igt@xe_query@multigpu-query-invalid-extension:
- shard-dg2-set2: NOTRUN -> [SKIP][164] ([Intel XE#944]) +1 other test skip
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@xe_query@multigpu-query-invalid-extension.html
* igt@xe_query@multigpu-query-topology-l3-bank-mask:
- shard-lnl: NOTRUN -> [SKIP][165] ([Intel XE#944]) +2 other tests skip
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-5/igt@xe_query@multigpu-query-topology-l3-bank-mask.html
- shard-bmg: NOTRUN -> [SKIP][166] ([Intel XE#944])
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@xe_query@multigpu-query-topology-l3-bank-mask.html
* igt@xe_sriov_auto_provisioning@exclusive-ranges:
- shard-lnl: NOTRUN -> [SKIP][167] ([Intel XE#4130])
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@xe_sriov_auto_provisioning@exclusive-ranges.html
#### Possible fixes ####
* igt@intel_sysfs_debugfs@xe-debugfs-read-all-entries:
- shard-lnl: [ABORT][168] ([Intel XE#4624]) -> [PASS][169]
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-lnl-1/igt@intel_sysfs_debugfs@xe-debugfs-read-all-entries.html
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-5/igt@intel_sysfs_debugfs@xe-debugfs-read-all-entries.html
* igt@kms_addfb_basic@bad-pitch-256:
- shard-adlp: [DMESG-WARN][170] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][171] +1 other test pass
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-adlp-1/igt@kms_addfb_basic@bad-pitch-256.html
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-adlp-9/igt@kms_addfb_basic@bad-pitch-256.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-adlp: [DMESG-FAIL][172] ([Intel XE#4543]) -> [PASS][173]
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-adlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-adlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-bmg: [INCOMPLETE][174] ([Intel XE#3862]) -> [PASS][175]
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6:
- shard-dg2-set2: [INCOMPLETE][176] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124]) -> [PASS][177] +1 other test pass
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-dg2-set2: [SKIP][178] ([Intel XE#309]) -> [PASS][179] +2 other tests pass
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-464/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-463/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-bmg: [SKIP][180] ([Intel XE#2291]) -> [PASS][181] +3 other tests pass
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-4/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-2/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
* igt@kms_dp_aux_dev:
- shard-bmg: [SKIP][182] ([Intel XE#3009]) -> [PASS][183]
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-4/igt@kms_dp_aux_dev.html
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-1/igt@kms_dp_aux_dev.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop:
- shard-bmg: [SKIP][184] ([Intel XE#2316]) -> [PASS][185] +8 other tests pass
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-4/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-1/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a2-dp2:
- shard-dg2-set2: [FAIL][186] ([Intel XE#301]) -> [PASS][187] +5 other tests pass
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-432/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a2-dp2.html
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-432/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a2-dp2.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3:
- shard-bmg: [FAIL][188] ([Intel XE#3321]) -> [PASS][189] +1 other test pass
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3.html
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3.html
* igt@kms_flip@2x-modeset-vs-vblank-race:
- shard-dg2-set2: [SKIP][190] ([Intel XE#310]) -> [PASS][191] +3 other tests pass
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-464/igt@kms_flip@2x-modeset-vs-vblank-race.html
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-463/igt@kms_flip@2x-modeset-vs-vblank-race.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-lnl: [FAIL][192] ([Intel XE#301]) -> [PASS][193] +1 other test pass
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@d-dp4:
- shard-dg2-set2: [FAIL][194] ([Intel XE#301] / [Intel XE#3321]) -> [PASS][195]
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-433/igt@kms_flip@flip-vs-expired-vblank@d-dp4.html
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-463/igt@kms_flip@flip-vs-expired-vblank@d-dp4.html
* igt@kms_flip@flip-vs-suspend@c-dp2:
- shard-bmg: [INCOMPLETE][196] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][197]
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-6/igt@kms_flip@flip-vs-suspend@c-dp2.html
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-7/igt@kms_flip@flip-vs-suspend@c-dp2.html
* igt@kms_flip@flip-vs-suspend@c-dp4:
- shard-dg2-set2: [INCOMPLETE][198] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][199] +1 other test pass
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-433/igt@kms_flip@flip-vs-suspend@c-dp4.html
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-463/igt@kms_flip@flip-vs-suspend@c-dp4.html
* igt@kms_flip@plain-flip-ts-check:
- shard-bmg: [FAIL][200] ([Intel XE#2882]) -> [PASS][201] +2 other tests pass
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-3/igt@kms_flip@plain-flip-ts-check.html
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-1/igt@kms_flip@plain-flip-ts-check.html
* igt@kms_flip@plain-flip-ts-check@a-edp1:
- shard-lnl: [FAIL][202] ([Intel XE#886]) -> [PASS][203] +1 other test pass
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-lnl-1/igt@kms_flip@plain-flip-ts-check@a-edp1.html
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-8/igt@kms_flip@plain-flip-ts-check@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt:
- shard-dg2-set2: [SKIP][204] ([Intel XE#656]) -> [PASS][205] +4 other tests pass
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt.html
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-lnl: [ABORT][206] -> [PASS][207]
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-lnl-8/igt@kms_frontbuffer_tracking@psr-suspend.html
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-7/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_hdr@static-toggle-suspend:
- shard-bmg: [SKIP][208] ([Intel XE#1503]) -> [PASS][209]
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-4/igt@kms_hdr@static-toggle-suspend.html
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-1/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_pm_rpm@dpms-non-lpsp:
- shard-dg2-set2: [SKIP][210] ([Intel XE#836]) -> [PASS][211]
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-464/igt@kms_pm_rpm@dpms-non-lpsp.html
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-463/igt@kms_pm_rpm@dpms-non-lpsp.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic:
- shard-dg2-set2: [SKIP][212] ([Intel XE#1392]) -> [PASS][213] +2 other tests pass
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic.html
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-436/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic.html
* igt@xe_fault_injection@inject-fault-probe-function-xe_guc_relay_init:
- shard-adlp: [DMESG-WARN][214] ([Intel XE#4173]) -> [PASS][215] +2 other tests pass
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-adlp-1/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_relay_init.html
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-adlp-9/igt@xe_fault_injection@inject-fault-probe-function-xe_guc_relay_init.html
* igt@xe_pm@s4-d3hot-basic-exec:
- shard-adlp: [ABORT][216] ([Intel XE#1794]) -> [PASS][217]
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-adlp-9/igt@xe_pm@s4-d3hot-basic-exec.html
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-adlp-3/igt@xe_pm@s4-d3hot-basic-exec.html
* igt@xe_pm@s4-multiple-execs:
- shard-lnl: [ABORT][218] ([Intel XE#1794]) -> [PASS][219]
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-lnl-2/igt@xe_pm@s4-multiple-execs.html
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-5/igt@xe_pm@s4-multiple-execs.html
* igt@xe_pmu@gt-frequency:
- shard-lnl: [FAIL][220] -> [PASS][221] +1 other test pass
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-lnl-1/igt@xe_pmu@gt-frequency.html
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-lnl-8/igt@xe_pmu@gt-frequency.html
#### Warnings ####
* igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-6:
- shard-dg2-set2: [SKIP][222] ([Intel XE#787]) -> [SKIP][223] ([Intel XE#455] / [Intel XE#787]) +9 other tests skip
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-434/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-6.html
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs@pipe-d-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
- shard-dg2-set2: [INCOMPLETE][224] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124]) -> [INCOMPLETE][225] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522])
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-6:
- shard-dg2-set2: [SKIP][226] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][227] ([Intel XE#787]) +6 other tests skip
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-464/igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-6.html
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-433/igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-6.html
* igt@kms_content_protection@atomic:
- shard-bmg: [FAIL][228] ([Intel XE#1178]) -> [SKIP][229] ([Intel XE#2341])
[228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-1/igt@kms_content_protection@atomic.html
[229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg2-set2: [FAIL][230] ([Intel XE#1178]) -> [SKIP][231] ([Intel XE#455]) +1 other test skip
[230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-436/igt@kms_content_protection@atomic-dpms.html
[231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@lic-type-0:
- shard-dg2-set2: [SKIP][232] ([Intel XE#455]) -> [FAIL][233] ([Intel XE#1178])
[232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-464/igt@kms_content_protection@lic-type-0.html
[233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-433/igt@kms_content_protection@lic-type-0.html
* igt@kms_content_protection@srm:
- shard-bmg: [SKIP][234] ([Intel XE#2341]) -> [FAIL][235] ([Intel XE#1178]) +1 other test fail
[234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-4/igt@kms_content_protection@srm.html
[235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-1/igt@kms_content_protection@srm.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff:
- shard-dg2-set2: [SKIP][236] ([Intel XE#656]) -> [SKIP][237] ([Intel XE#651]) +8 other tests skip
[236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff.html
[237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render:
- shard-bmg: [SKIP][238] ([Intel XE#2311]) -> [SKIP][239] ([Intel XE#2312]) +20 other tests skip
[238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html
[239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][240] ([Intel XE#2312]) -> [SKIP][241] ([Intel XE#2311]) +13 other tests skip
[240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][242] ([Intel XE#4141]) -> [SKIP][243] ([Intel XE#2312]) +6 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
[243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
- shard-bmg: [SKIP][244] ([Intel XE#2312]) -> [SKIP][245] ([Intel XE#4141]) +9 other tests skip
[244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
[245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt:
- shard-dg2-set2: [SKIP][246] ([Intel XE#651]) -> [SKIP][247] ([Intel XE#656]) +12 other tests skip
[246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt.html
[247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw:
- shard-bmg: [SKIP][248] ([Intel XE#2313]) -> [SKIP][249] ([Intel XE#2312]) +25 other tests skip
[248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html
[249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff:
- shard-dg2-set2: [SKIP][250] ([Intel XE#656]) -> [SKIP][251] ([Intel XE#653]) +8 other tests skip
[250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html
[251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt:
- shard-dg2-set2: [SKIP][252] ([Intel XE#653]) -> [SKIP][253] ([Intel XE#656]) +9 other tests skip
[252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-436/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt.html
[253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen:
- shard-bmg: [SKIP][254] ([Intel XE#2312]) -> [SKIP][255] ([Intel XE#2313]) +13 other tests skip
[254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
[255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][256] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][257] ([Intel XE#3544])
[256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-3/igt@kms_hdr@brightness-with-hdr.html
[257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html
* igt@xe_module_load@load:
- shard-bmg: ([PASS][258], [PASS][259], [PASS][260], [PASS][261], [PASS][262], [PASS][263], [PASS][264], [PASS][265], [PASS][266], [PASS][267], [PASS][268], [PASS][269], [PASS][270], [PASS][271], [PASS][272], [SKIP][273], [PASS][274], [PASS][275], [PASS][276], [PASS][277], [PASS][278], [PASS][279], [PASS][280], [PASS][281], [PASS][282], [PASS][283]) ([Intel XE#2457]) -> ([PASS][284], [PASS][285], [DMESG-WARN][286], [PASS][287], [PASS][288], [PASS][289], [SKIP][290], [PASS][291], [PASS][292], [PASS][293], [DMESG-WARN][294], [PASS][295], [PASS][296], [PASS][297], [PASS][298], [PASS][299], [PASS][300], [PASS][301], [PASS][302], [PASS][303], [PASS][304], [PASS][305], [PASS][306], [PASS][307], [PASS][308], [PASS][309]) ([Intel XE#2457] / [Intel XE#3428])
[258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-8/igt@xe_module_load@load.html
[259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-8/igt@xe_module_load@load.html
[260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-6/igt@xe_module_load@load.html
[261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-6/igt@xe_module_load@load.html
[262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-6/igt@xe_module_load@load.html
[263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-4/igt@xe_module_load@load.html
[264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-4/igt@xe_module_load@load.html
[265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-2/igt@xe_module_load@load.html
[266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-2/igt@xe_module_load@load.html
[267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-3/igt@xe_module_load@load.html
[268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-3/igt@xe_module_load@load.html
[269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-1/igt@xe_module_load@load.html
[270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-1/igt@xe_module_load@load.html
[271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-1/igt@xe_module_load@load.html
[272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-1/igt@xe_module_load@load.html
[273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-3/igt@xe_module_load@load.html
[274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-8/igt@xe_module_load@load.html
[275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-2/igt@xe_module_load@load.html
[276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-7/igt@xe_module_load@load.html
[277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-7/igt@xe_module_load@load.html
[278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-7/igt@xe_module_load@load.html
[279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-3/igt@xe_module_load@load.html
[280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-7/igt@xe_module_load@load.html
[281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-3/igt@xe_module_load@load.html
[282]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-4/igt@xe_module_load@load.html
[283]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-bmg-4/igt@xe_module_load@load.html
[284]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-3/igt@xe_module_load@load.html
[285]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-2/igt@xe_module_load@load.html
[286]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-6/igt@xe_module_load@load.html
[287]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@xe_module_load@load.html
[288]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@xe_module_load@load.html
[289]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@xe_module_load@load.html
[290]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@xe_module_load@load.html
[291]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-1/igt@xe_module_load@load.html
[292]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-1/igt@xe_module_load@load.html
[293]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@xe_module_load@load.html
[294]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-6/igt@xe_module_load@load.html
[295]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-3/igt@xe_module_load@load.html
[296]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-6/igt@xe_module_load@load.html
[297]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-6/igt@xe_module_load@load.html
[298]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-3/igt@xe_module_load@load.html
[299]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-8/igt@xe_module_load@load.html
[300]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-8/igt@xe_module_load@load.html
[301]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-7/igt@xe_module_load@load.html
[302]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-7/igt@xe_module_load@load.html
[303]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-7/igt@xe_module_load@load.html
[304]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-4/igt@xe_module_load@load.html
[305]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-2/igt@xe_module_load@load.html
[306]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-2/igt@xe_module_load@load.html
[307]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-1/igt@xe_module_load@load.html
[308]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-8/igt@xe_module_load@load.html
[309]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-bmg-8/igt@xe_module_load@load.html
* igt@xe_peer2peer@read:
- shard-dg2-set2: [SKIP][310] ([Intel XE#1061]) -> [FAIL][311] ([Intel XE#1173])
[310]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2956-b61f5de7570012cb79e72624a97b216d395f7380/shard-dg2-432/igt@xe_peer2peer@read.html
[311]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/shard-dg2-436/igt@xe_peer2peer@read.html
[Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
[Intel XE#1062]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1062
[Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1512
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
[Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
[Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
[Intel XE#2934]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2934
[Intel XE#2939]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2939
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#3278]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3278
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#3307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3307
[Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3428
[Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3767]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3767
[Intel XE#3768]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3768
[Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
[Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
[Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
[Intel XE#3889]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3889
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
[Intel XE#4298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4298
[Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
[Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
[Intel XE#4624]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4624
[Intel XE#4658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4658
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4761]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4761
[Intel XE#4781]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4781
[Intel XE#4782]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4782
[Intel XE#4804]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4804
[Intel XE#4810]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4810
[Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#702]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/702
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#827]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/827
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-2956-b61f5de7570012cb79e72624a97b216d395f7380 -> xe-pw-147786v1
IGT_8320: cd3b5612be3cef838f16e074bf1bc421399d584d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-2956-b61f5de7570012cb79e72624a97b216d395f7380: b61f5de7570012cb79e72624a97b216d395f7380
xe-pw-147786v1: 147786v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-147786v1/index.html
[-- Attachment #2: Type: text/html, Size: 92074 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v10 1/4] drm/xe/vf: Divide GGTT ballooning into allocation and insertion
2025-04-15 22:20 ` [PATCH v10 1/4] drm/xe/vf: Divide GGTT ballooning into allocation and insertion Tomasz Lis
@ 2025-04-17 18:10 ` Michal Wajdeczko
0 siblings, 0 replies; 10+ messages in thread
From: Michal Wajdeczko @ 2025-04-17 18:10 UTC (permalink / raw)
To: Tomasz Lis, intel-xe
Cc: Michał Winiarski, Piotr Piórkowski, Matthew Brost,
Lucas De Marchi
On 16.04.2025 00:20, Tomasz Lis wrote:
> The balloon nodes, which are used to fill areas of GGTT inaccessible
> for a specific VF, were allocated and inserted into GGTT within one
> function. To be able to re-use that insertion code during VF
> migration recovery, we need to split it.
>
> This patch separates allocation (init/fini functs) from the insertion
> of balloons (balloon/deballoon functs). Locks are also moved to ensure
> calls from post-migration recovery worker will not cause a deadlock.
>
> v2: Moved declarations to proper header
> v3: Rephrased description, introduced "_locked" versions of some
> functs, more lockdep checks, some functions renamed, altered error
> handling, added missing kerneldocs.
> v4: Suffixed more functs with `_locked`, moved lockdep asserts,
> fixed finalization in error path, added asserts
> v5: Renamed another few functs, used xe_ggtt_node_allocated(),
> moved lockdep back again to avoid null dereference, added
> asserts, improved comments
> v6: Changed params of cleanup_ggtt()
>
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
hmm, still not 100% happy with all this gt<->tile dance that seems to be
unavoidable right now, likely we need to do little refactor and move
some stuff to xe_tile_sriov_vf.* files, but that's really not your
fault, so let this is in as-is and try to cleanup later,
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v10 4/4] drm/xe/vf: Fixup CTB send buffer messages after migration
2025-04-15 22:20 ` [PATCH v10 4/4] drm/xe/vf: Fixup CTB send buffer messages after migration Tomasz Lis
@ 2025-04-17 19:06 ` Michal Wajdeczko
2025-04-17 23:25 ` Lis, Tomasz
0 siblings, 1 reply; 10+ messages in thread
From: Michal Wajdeczko @ 2025-04-17 19:06 UTC (permalink / raw)
To: Tomasz Lis, intel-xe
Cc: Michał Winiarski, Piotr Piórkowski, Matthew Brost,
Lucas De Marchi
On 16.04.2025 00:20, Tomasz Lis wrote:
> During post-migration recovery of a VF, it is necessary to update
> GGTT references included in messages which are going to be sent
> to GuC. GuC will start consuming messages after VF KMD will inform
> it about fixups being done; before that, the VF KMD is expected
> to update any H2G messages which are already in send buffer but
> were not consumed by GuC.
>
> Only a small subset of messages allowed for VFs have GGTT references
> in them. This patch adds the functionality to parse the CTB send
> ring buffer and shift addresses contained within.
>
> While fixing the CTB content, ct->lock is not taken. This means
> the only barrier taken remains GGTT address lock - which is ok,
> because only requests with GGTT addresses matter, but it also means
> tail changes can happen during the CTB fixups execution (which may
> be ignored as any new messages will not have anything to fix).
>
> The GGTT address locking will be introduced in a future series.
>
> v2: removed storing shift as that's now done in VMA nodes patch;
> macros to inlines; warns to asserts; log messages fixes (Michal)
> v3: removed inline keywords, enums for offsets in CTB messages,
> less error messages, if return unused then made functs void (Michal)
> v4: update the cached head before starting fixups
> v5: removed/updated comments, wrapped lines, converted assert into
> error, enums for offsets to separate patch, reused xe_map_rd
> v6: define xe_map_*_array() macros, support CTB wrap which divides
> a message, updated comments, moved one function to an earlier patch
> v7: renamed few functions, wider use on previously introduced helper,
> separate cases in parsing messges, documented a static funct
> v8: Introduced more helpers, fixed coding style mistakes
> v9: Move xe_map*() functs to macros, add asserts, add debug print
>
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc_ct.c | 172 +++++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_guc_ct.h | 2 +
> drivers/gpu/drm/xe/xe_map.h | 18 ++++
> drivers/gpu/drm/xe/xe_sriov_vf.c | 18 ++++
> 4 files changed, 210 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
> index 0a4fef7d7225..b0fd05550af8 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> @@ -25,6 +25,7 @@
> #include "xe_gt_printk.h"
> #include "xe_gt_sriov_pf_control.h"
> #include "xe_gt_sriov_pf_monitor.h"
> +#include "xe_gt_sriov_printk.h"
> #include "xe_gt_tlb_invalidation.h"
> #include "xe_guc.h"
> #include "xe_guc_log.h"
> @@ -84,6 +85,8 @@ struct g2h_fence {
> bool done;
> };
>
> +#define make_u64(hi, lo) ((u64)((u64)(u32)(hi) << 32 | (u32)(lo)))
> +
> static void g2h_fence_init(struct g2h_fence *g2h_fence, u32 *response_buffer)
> {
> g2h_fence->response_buffer = response_buffer;
> @@ -1623,6 +1626,175 @@ static void g2h_worker_func(struct work_struct *w)
> receive_g2h(ct);
> }
>
> +static void xe_fixup_u64_in_cmds(struct xe_device *xe, struct iosys_map *cmds,
> + u32 size, u32 idx, s64 shift)
> +{
> + u32 hi, lo;
> + u64 offset;
> +
> + lo = xe_map_rd_ring_u32(xe, cmds, idx, size);
> + hi = xe_map_rd_ring_u32(xe, cmds, idx + 1, size);
> + offset = make_u64(hi, lo);
> + offset += shift;
> + lo = lower_32_bits(offset);
> + hi = upper_32_bits(offset);
> + xe_map_wr_ring_u32(xe, cmds, idx, size, lo);
> + xe_map_wr_ring_u32(xe, cmds, idx + 1, size, hi);
> +}
> +
> +/*
> + * Shift any GGTT addresses within a single message left within CTB from
> + * before post-migration recovery.
> + * @ct: pointer to CT struct of the target GuC
> + * @cmds: iomap buffer containing CT messages
> + * @head: start of the target message within the buffer
> + * @len: length of the target message
> + * @size: size of the commands buffer
> + * @shift: the address shift to be added to each GGTT reference
> + */
> +static void ct_fixup_ggtt_in_message(struct xe_guc_ct *ct,
> + struct iosys_map *cmds, u32 head,
> + u32 len, u32 size, s64 shift)
> +{
> + struct xe_gt *gt __maybe_unused = ct_to_gt(ct);
> + struct xe_device *xe = ct_to_xe(ct);
> + u32 msg[GUC_HXG_MSG_MIN_LEN];
> + u32 action, i, n;
> +
> + xe_gt_assert(gt, len >= GUC_HXG_MSG_MIN_LEN);
> +
> + msg[0] = xe_map_rd_ring_u32(xe, cmds, head, size);
> + action = FIELD_GET(GUC_HXG_REQUEST_MSG_0_ACTION, msg[0]);
> +
> + xe_gt_sriov_dbg_verbose(gt, "fixing H2G %#x\n", action);
> +
> + switch (action) {
> + case XE_GUC_ACTION_REGISTER_CONTEXT:
> + xe_gt_assert(gt, len >= XE_GUC_REGISTER_CONTEXT_MSG_LEN);
I'm not sure assert is a good choice here, as this is different check
than above where GUC_HXG_MSG_MIN_LEN is used to verify your code only
here you are fixing specific action written to CTB and at this point you
must be sure that 'len' is actually equal to MSG_LEN as only then you
could be sure CTB is not broken and there is whole message available and
you can continue with fixups at those offsets
if you would read my comments for rev9 more carefully then you would
notice that I was saying about 'missing check' not 'missing assert'
> + xe_fixup_u64_in_cmds(xe, cmds, size, head +
> + XE_GUC_REGISTER_CONTEXT_DATA_5_WQ_DESC_ADDR_LOWER,
> + shift);
> + xe_fixup_u64_in_cmds(xe, cmds, size, head +
> + XE_GUC_REGISTER_CONTEXT_DATA_7_WQ_BUF_BASE_LOWER,
> + shift);
> + xe_fixup_u64_in_cmds(xe, cmds, size, head +
> + XE_GUC_REGISTER_CONTEXT_DATA_10_HW_LRC_ADDR, shift);
> + break;
> + case XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC:
> + xe_gt_assert(gt, len >= XE_GUC_REGISTER_CONTEXT_MULTI_LRC_MSG_LEN);
this needs to be more than assert
> + xe_fixup_u64_in_cmds(xe, cmds, size, head +
> + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_5_WQ_DESC_ADDR_LOWER,
> + shift);
> + xe_fixup_u64_in_cmds(xe, cmds, size, head +
> + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_7_WQ_BUF_BASE_LOWER,
> + shift);
> + n = xe_map_rd_ring_u32(xe, cmds, head +
> + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_10_NUM_CTXS, size);
> + xe_gt_assert(gt, len >= XE_GUC_REGISTER_CONTEXT_MULTI_LRC_MSG_LEN + 2 * n);
and here
> + for (i = 0; i < n; i++)
> + xe_fixup_u64_in_cmds(xe, cmds, size, head +
> + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_11_HW_LRC_ADDR
> + + 2 * i, shift);
and maybe all fixups should be done *after* checking that the whole
message is not truncated, so
// check min size (to make sure DATA10 is there)
// read DATA_10_NUM_CTXS
// check full size
// fixups
> + break;
> + default:
> + break;
> + }
> +}
> +
> +/*
> + * Apply fixups to the next outgoing CT message within given CTB
> + * @ct: the &xe_guc_ct struct instance representing the target GuC
> + * @h2g: the &guc_ctb struct instance of the target buffer
> + * @shift: shift to be added to all GGTT addresses within the CTB
> + * @mhead: pointer to an integer storing message start position; the
> + * position is changed to next message before this function return
> + * @avail: size of the area available for parsing, that is length
> + * of all remaining messages stored within the CTB
> + * Return: size of the area available for parsing after one message
> + * has been parsed, that is length remaining from the updated mhead
> + */
> +static int ct_fixup_ggtt_in_buffer(struct xe_guc_ct *ct, struct guc_ctb *h2g,
> + s64 shift, u32 *mhead, s32 avail)
> +{
> + struct xe_device *xe = ct_to_xe(ct);
> + u32 msg[GUC_HXG_MSG_MIN_LEN];
> + u32 size = h2g->info.size;
> + u32 head = *mhead;
> + u32 len;
> +
> + xe_gt_assert(ct_to_gt(ct), avail >= (s32)GUC_CTB_MSG_MIN_LEN);
> +
> + /* Read header */
> + msg[0] = xe_map_rd_ring_u32(xe, &h2g->cmds, head, size);
> + len = FIELD_GET(GUC_CTB_MSG_0_NUM_DWORDS, msg[0]) + GUC_CTB_MSG_MIN_LEN;
> +
> + if (unlikely(len > (u32)avail)) {
> + xe_gt_err(ct_to_gt(ct), "H2G channel broken on read, avail=%d, len=%d, fixups skipped\n",
> + avail, len);
> + return 0;
> + }
> +
> + head = (head + GUC_CTB_MSG_MIN_LEN) % size;
> + ct_fixup_ggtt_in_message(ct, &h2g->cmds, head, msg_len_to_hxg_len(len), size, shift);
> + *mhead = (head + msg_len_to_hxg_len(len)) % size;
> +
> + return avail - len;
> +}
> +
> +/**
> + * xe_guc_ct_fixup_messages_with_ggtt - Fixup any pending H2G CTB messages
> + * @ct: pointer to CT struct of the target GuC
> + * @ggtt_shift: shift to be added to all GGTT addresses within the CTB
> + *
> + * Messages in GuC to Host CTB are owned by GuC and any fixups in them
> + * are made by GuC. But content of the Host to GuC CTB is owned by the
> + * KMD, so fixups to GGTT references in any pending messages need to be
> + * applied here.
> + * This function updates GGTT offsets in payloads of pending H2G CTB
> + * messages (messages which were not consumed by GuC before the VF got
> + * paused).
> + */
> +void xe_guc_ct_fixup_messages_with_ggtt(struct xe_guc_ct *ct, s64 ggtt_shift)
> +{
> + struct guc_ctb *h2g = &ct->ctbs.h2g;
> + struct xe_guc *guc = ct_to_guc(ct);
> + struct xe_gt *gt = guc_to_gt(guc);
> + u32 head, tail, size;
> + s32 avail;
> +
> + if (unlikely(h2g->info.broken))
> + return;
> +
> + h2g->info.head = desc_read(ct_to_xe(ct), h2g, head);
> + head = h2g->info.head;
> + tail = READ_ONCE(h2g->info.tail);
> + size = h2g->info.size;
> +
> + if (unlikely(head > size))
> + goto corrupted;
> +
> + if (unlikely(tail >= size))
> + goto corrupted;
> +
> + avail = tail - head;
> +
> + /* beware of buffer wrap case */
> + if (unlikely(avail < 0))
> + avail += size;
> + xe_gt_dbg(gt, "available %d (%u:%u:%u)\n", avail, head, tail, size);
> + xe_gt_assert(gt, avail >= 0);
> +
> + while (avail > 0)
> + avail = ct_fixup_ggtt_in_buffer(ct, h2g, ggtt_shift, &head, avail);
> +
> + return;
> +
> +corrupted:
> + xe_gt_err(gt, "Corrupted H2G descriptor head=%u tail=%u size=%u, fixups not applied\n",
> + head, tail, size);
> + h2g->info.broken = true;
> +}
> +
> static struct xe_guc_ct_snapshot *guc_ct_snapshot_alloc(struct xe_guc_ct *ct, bool atomic,
> bool want_ctb)
> {
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct.h b/drivers/gpu/drm/xe/xe_guc_ct.h
> index 82c4ae458dda..5649bda82823 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct.h
> +++ b/drivers/gpu/drm/xe/xe_guc_ct.h
> @@ -22,6 +22,8 @@ void xe_guc_ct_snapshot_print(struct xe_guc_ct_snapshot *snapshot, struct drm_pr
> void xe_guc_ct_snapshot_free(struct xe_guc_ct_snapshot *snapshot);
> void xe_guc_ct_print(struct xe_guc_ct *ct, struct drm_printer *p, bool want_ctb);
>
> +void xe_guc_ct_fixup_messages_with_ggtt(struct xe_guc_ct *ct, s64 ggtt_shift);
> +
> static inline bool xe_guc_ct_enabled(struct xe_guc_ct *ct)
> {
> return ct->state == XE_GUC_CT_STATE_ENABLED;
> diff --git a/drivers/gpu/drm/xe/xe_map.h b/drivers/gpu/drm/xe/xe_map.h
> index f62e0c8b67ab..fa65e6c908fa 100644
> --- a/drivers/gpu/drm/xe/xe_map.h
> +++ b/drivers/gpu/drm/xe/xe_map.h
> @@ -78,6 +78,24 @@ static inline void xe_map_write32(struct xe_device *xe, struct iosys_map *map,
> iosys_map_wr(map__, offset__, type__, val__); \
> })
>
> +#define xe_map_rd_array(xe__, map__, index__, type__) \
> + xe_map_rd(xe__, map__, (index__) * sizeof(type__), type__)
> +
> +#define xe_map_wr_array(xe__, map__, index__, type__, val__) \
> + xe_map_wr(xe__, map__, (index__) * sizeof(type__), type__, val__)
> +
> +#define xe_map_rd_array_u32(xe__, map__, index__) \
> + xe_map_rd_array(xe__, map__, index__, u32)
> +
> +#define xe_map_wr_array_u32(xe__, map__, index__, val__) \
> + xe_map_wr_array(xe__, map__, index__, u32, val__)
> +
> +#define xe_map_rd_ring_u32(xe__, map__, index__, size__) \
> + xe_map_rd_array_u32(xe__, map__, (index__) % (size__))
> +
> +#define xe_map_wr_ring_u32(xe__, map__, index__, size__, val__) \
> + xe_map_wr_array_u32(xe__, map__, (index__) % (size__), val__)
> +
nit: for simple line split no need to align \ to the far right
instead
#define xe_map_wr_ring_u32(...) \
xe_map_wr_array_u32(...)
just
#define xe_map_wr_ring_u32(...) \
xe_map_wr_array_u32(...)
> #define xe_map_rd_field(xe__, map__, struct_offset__, struct_type__, field__) ({ \
> struct xe_device *__xe = xe__; \
> xe_device_assert_mem_access(__xe); \
> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf.c b/drivers/gpu/drm/xe/xe_sriov_vf.c
> index e70f1ceabbb3..2674fa948fda 100644
> --- a/drivers/gpu/drm/xe/xe_sriov_vf.c
> +++ b/drivers/gpu/drm/xe/xe_sriov_vf.c
> @@ -10,6 +10,7 @@
> #include "xe_gt.h"
> #include "xe_gt_sriov_printk.h"
> #include "xe_gt_sriov_vf.h"
> +#include "xe_guc_ct.h"
> #include "xe_pm.h"
> #include "xe_sriov.h"
> #include "xe_sriov_printk.h"
> @@ -158,6 +159,20 @@ static int vf_post_migration_requery_guc(struct xe_device *xe)
> return ret;
> }
>
> +static void vf_post_migration_fixup_ctb(struct xe_device *xe)
> +{
> + struct xe_gt *gt;
> + unsigned int id;
> +
> + xe_assert(xe, IS_SRIOV_VF(xe));
> +
> + for_each_gt(gt, xe, id) {
> + s32 shift = xe_gt_sriov_vf_ggtt_shift(gt);
> +
> + xe_guc_ct_fixup_messages_with_ggtt(>->uc.guc.ct, shift);
> + }
> +}
> +
> /*
> * vf_post_migration_imminent - Check if post-restore recovery is coming.
> * @xe: the &xe_device struct instance
> @@ -224,6 +239,9 @@ static void vf_post_migration_recovery(struct xe_device *xe)
>
> need_fixups = vf_post_migration_fixup_ggtt_nodes(xe);
> /* FIXME: add the recovery steps */
> + if (need_fixups)
> + vf_post_migration_fixup_ctb(xe);
> +
> vf_post_migration_notify_resfix_done(xe);
> xe_pm_runtime_put(xe);
> drm_notice(&xe->drm, "migration recovery ended\n");
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v10 4/4] drm/xe/vf: Fixup CTB send buffer messages after migration
2025-04-17 19:06 ` Michal Wajdeczko
@ 2025-04-17 23:25 ` Lis, Tomasz
0 siblings, 0 replies; 10+ messages in thread
From: Lis, Tomasz @ 2025-04-17 23:25 UTC (permalink / raw)
To: Michal Wajdeczko, intel-xe
Cc: Michał Winiarski, Piotr Piórkowski, Matthew Brost,
Lucas De Marchi
On 17.04.2025 21:06, Michal Wajdeczko wrote:
>
> On 16.04.2025 00:20, Tomasz Lis wrote:
>> During post-migration recovery of a VF, it is necessary to update
>> GGTT references included in messages which are going to be sent
>> to GuC. GuC will start consuming messages after VF KMD will inform
>> it about fixups being done; before that, the VF KMD is expected
>> to update any H2G messages which are already in send buffer but
>> were not consumed by GuC.
>>
>> Only a small subset of messages allowed for VFs have GGTT references
>> in them. This patch adds the functionality to parse the CTB send
>> ring buffer and shift addresses contained within.
>>
>> While fixing the CTB content, ct->lock is not taken. This means
>> the only barrier taken remains GGTT address lock - which is ok,
>> because only requests with GGTT addresses matter, but it also means
>> tail changes can happen during the CTB fixups execution (which may
>> be ignored as any new messages will not have anything to fix).
>>
>> The GGTT address locking will be introduced in a future series.
>>
>> v2: removed storing shift as that's now done in VMA nodes patch;
>> macros to inlines; warns to asserts; log messages fixes (Michal)
>> v3: removed inline keywords, enums for offsets in CTB messages,
>> less error messages, if return unused then made functs void (Michal)
>> v4: update the cached head before starting fixups
>> v5: removed/updated comments, wrapped lines, converted assert into
>> error, enums for offsets to separate patch, reused xe_map_rd
>> v6: define xe_map_*_array() macros, support CTB wrap which divides
>> a message, updated comments, moved one function to an earlier patch
>> v7: renamed few functions, wider use on previously introduced helper,
>> separate cases in parsing messges, documented a static funct
>> v8: Introduced more helpers, fixed coding style mistakes
>> v9: Move xe_map*() functs to macros, add asserts, add debug print
>>
>> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_guc_ct.c | 172 +++++++++++++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_guc_ct.h | 2 +
>> drivers/gpu/drm/xe/xe_map.h | 18 ++++
>> drivers/gpu/drm/xe/xe_sriov_vf.c | 18 ++++
>> 4 files changed, 210 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
>> index 0a4fef7d7225..b0fd05550af8 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_ct.c
>> +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
>> @@ -25,6 +25,7 @@
>> #include "xe_gt_printk.h"
>> #include "xe_gt_sriov_pf_control.h"
>> #include "xe_gt_sriov_pf_monitor.h"
>> +#include "xe_gt_sriov_printk.h"
>> #include "xe_gt_tlb_invalidation.h"
>> #include "xe_guc.h"
>> #include "xe_guc_log.h"
>> @@ -84,6 +85,8 @@ struct g2h_fence {
>> bool done;
>> };
>>
>> +#define make_u64(hi, lo) ((u64)((u64)(u32)(hi) << 32 | (u32)(lo)))
>> +
>> static void g2h_fence_init(struct g2h_fence *g2h_fence, u32 *response_buffer)
>> {
>> g2h_fence->response_buffer = response_buffer;
>> @@ -1623,6 +1626,175 @@ static void g2h_worker_func(struct work_struct *w)
>> receive_g2h(ct);
>> }
>>
>> +static void xe_fixup_u64_in_cmds(struct xe_device *xe, struct iosys_map *cmds,
>> + u32 size, u32 idx, s64 shift)
>> +{
>> + u32 hi, lo;
>> + u64 offset;
>> +
>> + lo = xe_map_rd_ring_u32(xe, cmds, idx, size);
>> + hi = xe_map_rd_ring_u32(xe, cmds, idx + 1, size);
>> + offset = make_u64(hi, lo);
>> + offset += shift;
>> + lo = lower_32_bits(offset);
>> + hi = upper_32_bits(offset);
>> + xe_map_wr_ring_u32(xe, cmds, idx, size, lo);
>> + xe_map_wr_ring_u32(xe, cmds, idx + 1, size, hi);
>> +}
>> +
>> +/*
>> + * Shift any GGTT addresses within a single message left within CTB from
>> + * before post-migration recovery.
>> + * @ct: pointer to CT struct of the target GuC
>> + * @cmds: iomap buffer containing CT messages
>> + * @head: start of the target message within the buffer
>> + * @len: length of the target message
>> + * @size: size of the commands buffer
>> + * @shift: the address shift to be added to each GGTT reference
>> + */
>> +static void ct_fixup_ggtt_in_message(struct xe_guc_ct *ct,
>> + struct iosys_map *cmds, u32 head,
>> + u32 len, u32 size, s64 shift)
>> +{
>> + struct xe_gt *gt __maybe_unused = ct_to_gt(ct);
>> + struct xe_device *xe = ct_to_xe(ct);
>> + u32 msg[GUC_HXG_MSG_MIN_LEN];
>> + u32 action, i, n;
>> +
>> + xe_gt_assert(gt, len >= GUC_HXG_MSG_MIN_LEN);
>> +
>> + msg[0] = xe_map_rd_ring_u32(xe, cmds, head, size);
>> + action = FIELD_GET(GUC_HXG_REQUEST_MSG_0_ACTION, msg[0]);
>> +
>> + xe_gt_sriov_dbg_verbose(gt, "fixing H2G %#x\n", action);
>> +
>> + switch (action) {
>> + case XE_GUC_ACTION_REGISTER_CONTEXT:
>> + xe_gt_assert(gt, len >= XE_GUC_REGISTER_CONTEXT_MSG_LEN);
> I'm not sure assert is a good choice here, as this is different check
> than above where GUC_HXG_MSG_MIN_LEN is used to verify your code only
>
> here you are fixing specific action written to CTB and at this point you
> must be sure that 'len' is actually equal to MSG_LEN as only then you
> could be sure CTB is not broken and there is whole message available and
> you can continue with fixups at those offsets
>
> if you would read my comments for rev9 more carefully then you would
> notice that I was saying about 'missing check' not 'missing assert'
Only the KMD is writing the messages to that buffer. If messages are
invalid, then either ctb writer de-synced from our parser, or
LMEM/SYSMEM was restored incorrectly. Both situations justify an assert.
Additionally, in place where we assert we already know that the message
in CTB is something that does need fixups. In most cases the CTB parser
issues wouldn't affect migration, as only two messages are affected, and
these specific messages have below average use frequency. But in place
of these asserts - we already know that we do have one of those
problematic messages.
Well.. this is a simplistic view, as it leaves out consideration of
concurrency. The bad message could be also an effect of concurrency
issues within KMD, if it turns out our locking isn't perfect. Also there
is that improbable but not impossible situation where GuC is still
running during recovery (due to double migration), so both head and tail
may change, before and after we've copied them.. in these cases the CTB
fixups should just be skipped, maybe with a warning.
ok, will change.
>> + xe_fixup_u64_in_cmds(xe, cmds, size, head +
>> + XE_GUC_REGISTER_CONTEXT_DATA_5_WQ_DESC_ADDR_LOWER,
>> + shift);
>> + xe_fixup_u64_in_cmds(xe, cmds, size, head +
>> + XE_GUC_REGISTER_CONTEXT_DATA_7_WQ_BUF_BASE_LOWER,
>> + shift);
>> + xe_fixup_u64_in_cmds(xe, cmds, size, head +
>> + XE_GUC_REGISTER_CONTEXT_DATA_10_HW_LRC_ADDR, shift);
>> + break;
>> + case XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC:
>> + xe_gt_assert(gt, len >= XE_GUC_REGISTER_CONTEXT_MULTI_LRC_MSG_LEN);
> this needs to be more than assert
>
>> + xe_fixup_u64_in_cmds(xe, cmds, size, head +
>> + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_5_WQ_DESC_ADDR_LOWER,
>> + shift);
>> + xe_fixup_u64_in_cmds(xe, cmds, size, head +
>> + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_7_WQ_BUF_BASE_LOWER,
>> + shift);
>> + n = xe_map_rd_ring_u32(xe, cmds, head +
>> + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_10_NUM_CTXS, size);
>> + xe_gt_assert(gt, len >= XE_GUC_REGISTER_CONTEXT_MULTI_LRC_MSG_LEN + 2 * n);
> and here
>
>> + for (i = 0; i < n; i++)
>> + xe_fixup_u64_in_cmds(xe, cmds, size, head +
>> + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_11_HW_LRC_ADDR
>> + + 2 * i, shift);
> and maybe all fixups should be done *after* checking that the whole
> message is not truncated, so
>
> // check min size (to make sure DATA10 is there)
> // read DATA_10_NUM_CTXS
> // check full size
> // fixups
That's true. For it to have any influence, the extremely rare case would
have to occur. But yeah, that's how it should be done.
will fix.
>
>> + break;
>> + default:
>> + break;
>> + }
>> +}
>> +
>> +/*
>> + * Apply fixups to the next outgoing CT message within given CTB
>> + * @ct: the &xe_guc_ct struct instance representing the target GuC
>> + * @h2g: the &guc_ctb struct instance of the target buffer
>> + * @shift: shift to be added to all GGTT addresses within the CTB
>> + * @mhead: pointer to an integer storing message start position; the
>> + * position is changed to next message before this function return
>> + * @avail: size of the area available for parsing, that is length
>> + * of all remaining messages stored within the CTB
>> + * Return: size of the area available for parsing after one message
>> + * has been parsed, that is length remaining from the updated mhead
>> + */
>> +static int ct_fixup_ggtt_in_buffer(struct xe_guc_ct *ct, struct guc_ctb *h2g,
>> + s64 shift, u32 *mhead, s32 avail)
>> +{
>> + struct xe_device *xe = ct_to_xe(ct);
>> + u32 msg[GUC_HXG_MSG_MIN_LEN];
>> + u32 size = h2g->info.size;
>> + u32 head = *mhead;
>> + u32 len;
>> +
>> + xe_gt_assert(ct_to_gt(ct), avail >= (s32)GUC_CTB_MSG_MIN_LEN);
>> +
>> + /* Read header */
>> + msg[0] = xe_map_rd_ring_u32(xe, &h2g->cmds, head, size);
>> + len = FIELD_GET(GUC_CTB_MSG_0_NUM_DWORDS, msg[0]) + GUC_CTB_MSG_MIN_LEN;
>> +
>> + if (unlikely(len > (u32)avail)) {
>> + xe_gt_err(ct_to_gt(ct), "H2G channel broken on read, avail=%d, len=%d, fixups skipped\n",
>> + avail, len);
>> + return 0;
>> + }
>> +
>> + head = (head + GUC_CTB_MSG_MIN_LEN) % size;
>> + ct_fixup_ggtt_in_message(ct, &h2g->cmds, head, msg_len_to_hxg_len(len), size, shift);
>> + *mhead = (head + msg_len_to_hxg_len(len)) % size;
>> +
>> + return avail - len;
>> +}
>> +
>> +/**
>> + * xe_guc_ct_fixup_messages_with_ggtt - Fixup any pending H2G CTB messages
>> + * @ct: pointer to CT struct of the target GuC
>> + * @ggtt_shift: shift to be added to all GGTT addresses within the CTB
>> + *
>> + * Messages in GuC to Host CTB are owned by GuC and any fixups in them
>> + * are made by GuC. But content of the Host to GuC CTB is owned by the
>> + * KMD, so fixups to GGTT references in any pending messages need to be
>> + * applied here.
>> + * This function updates GGTT offsets in payloads of pending H2G CTB
>> + * messages (messages which were not consumed by GuC before the VF got
>> + * paused).
>> + */
>> +void xe_guc_ct_fixup_messages_with_ggtt(struct xe_guc_ct *ct, s64 ggtt_shift)
>> +{
>> + struct guc_ctb *h2g = &ct->ctbs.h2g;
>> + struct xe_guc *guc = ct_to_guc(ct);
>> + struct xe_gt *gt = guc_to_gt(guc);
>> + u32 head, tail, size;
>> + s32 avail;
>> +
>> + if (unlikely(h2g->info.broken))
>> + return;
>> +
>> + h2g->info.head = desc_read(ct_to_xe(ct), h2g, head);
>> + head = h2g->info.head;
>> + tail = READ_ONCE(h2g->info.tail);
>> + size = h2g->info.size;
>> +
>> + if (unlikely(head > size))
>> + goto corrupted;
>> +
>> + if (unlikely(tail >= size))
>> + goto corrupted;
>> +
>> + avail = tail - head;
>> +
>> + /* beware of buffer wrap case */
>> + if (unlikely(avail < 0))
>> + avail += size;
>> + xe_gt_dbg(gt, "available %d (%u:%u:%u)\n", avail, head, tail, size);
>> + xe_gt_assert(gt, avail >= 0);
>> +
>> + while (avail > 0)
>> + avail = ct_fixup_ggtt_in_buffer(ct, h2g, ggtt_shift, &head, avail);
>> +
>> + return;
>> +
>> +corrupted:
>> + xe_gt_err(gt, "Corrupted H2G descriptor head=%u tail=%u size=%u, fixups not applied\n",
>> + head, tail, size);
>> + h2g->info.broken = true;
>> +}
>> +
>> static struct xe_guc_ct_snapshot *guc_ct_snapshot_alloc(struct xe_guc_ct *ct, bool atomic,
>> bool want_ctb)
>> {
>> diff --git a/drivers/gpu/drm/xe/xe_guc_ct.h b/drivers/gpu/drm/xe/xe_guc_ct.h
>> index 82c4ae458dda..5649bda82823 100644
>> --- a/drivers/gpu/drm/xe/xe_guc_ct.h
>> +++ b/drivers/gpu/drm/xe/xe_guc_ct.h
>> @@ -22,6 +22,8 @@ void xe_guc_ct_snapshot_print(struct xe_guc_ct_snapshot *snapshot, struct drm_pr
>> void xe_guc_ct_snapshot_free(struct xe_guc_ct_snapshot *snapshot);
>> void xe_guc_ct_print(struct xe_guc_ct *ct, struct drm_printer *p, bool want_ctb);
>>
>> +void xe_guc_ct_fixup_messages_with_ggtt(struct xe_guc_ct *ct, s64 ggtt_shift);
>> +
>> static inline bool xe_guc_ct_enabled(struct xe_guc_ct *ct)
>> {
>> return ct->state == XE_GUC_CT_STATE_ENABLED;
>> diff --git a/drivers/gpu/drm/xe/xe_map.h b/drivers/gpu/drm/xe/xe_map.h
>> index f62e0c8b67ab..fa65e6c908fa 100644
>> --- a/drivers/gpu/drm/xe/xe_map.h
>> +++ b/drivers/gpu/drm/xe/xe_map.h
>> @@ -78,6 +78,24 @@ static inline void xe_map_write32(struct xe_device *xe, struct iosys_map *map,
>> iosys_map_wr(map__, offset__, type__, val__); \
>> })
>>
>> +#define xe_map_rd_array(xe__, map__, index__, type__) \
>> + xe_map_rd(xe__, map__, (index__) * sizeof(type__), type__)
>> +
>> +#define xe_map_wr_array(xe__, map__, index__, type__, val__) \
>> + xe_map_wr(xe__, map__, (index__) * sizeof(type__), type__, val__)
>> +
>> +#define xe_map_rd_array_u32(xe__, map__, index__) \
>> + xe_map_rd_array(xe__, map__, index__, u32)
>> +
>> +#define xe_map_wr_array_u32(xe__, map__, index__, val__) \
>> + xe_map_wr_array(xe__, map__, index__, u32, val__)
>> +
>> +#define xe_map_rd_ring_u32(xe__, map__, index__, size__) \
>> + xe_map_rd_array_u32(xe__, map__, (index__) % (size__))
>> +
>> +#define xe_map_wr_ring_u32(xe__, map__, index__, size__, val__) \
>> + xe_map_wr_array_u32(xe__, map__, (index__) % (size__), val__)
>> +
> nit: for simple line split no need to align \ to the far right
>
> instead
>
> #define xe_map_wr_ring_u32(...) \
> xe_map_wr_array_u32(...)
>
> just
>
> #define xe_map_wr_ring_u32(...) \
> xe_map_wr_array_u32(...)
ok
-Tomasz
>> #define xe_map_rd_field(xe__, map__, struct_offset__, struct_type__, field__) ({ \
>> struct xe_device *__xe = xe__; \
>> xe_device_assert_mem_access(__xe); \
>> diff --git a/drivers/gpu/drm/xe/xe_sriov_vf.c b/drivers/gpu/drm/xe/xe_sriov_vf.c
>> index e70f1ceabbb3..2674fa948fda 100644
>> --- a/drivers/gpu/drm/xe/xe_sriov_vf.c
>> +++ b/drivers/gpu/drm/xe/xe_sriov_vf.c
>> @@ -10,6 +10,7 @@
>> #include "xe_gt.h"
>> #include "xe_gt_sriov_printk.h"
>> #include "xe_gt_sriov_vf.h"
>> +#include "xe_guc_ct.h"
>> #include "xe_pm.h"
>> #include "xe_sriov.h"
>> #include "xe_sriov_printk.h"
>> @@ -158,6 +159,20 @@ static int vf_post_migration_requery_guc(struct xe_device *xe)
>> return ret;
>> }
>>
>> +static void vf_post_migration_fixup_ctb(struct xe_device *xe)
>> +{
>> + struct xe_gt *gt;
>> + unsigned int id;
>> +
>> + xe_assert(xe, IS_SRIOV_VF(xe));
>> +
>> + for_each_gt(gt, xe, id) {
>> + s32 shift = xe_gt_sriov_vf_ggtt_shift(gt);
>> +
>> + xe_guc_ct_fixup_messages_with_ggtt(>->uc.guc.ct, shift);
>> + }
>> +}
>> +
>> /*
>> * vf_post_migration_imminent - Check if post-restore recovery is coming.
>> * @xe: the &xe_device struct instance
>> @@ -224,6 +239,9 @@ static void vf_post_migration_recovery(struct xe_device *xe)
>>
>> need_fixups = vf_post_migration_fixup_ggtt_nodes(xe);
>> /* FIXME: add the recovery steps */
>> + if (need_fixups)
>> + vf_post_migration_fixup_ctb(xe);
>> +
>> vf_post_migration_notify_resfix_done(xe);
>> xe_pm_runtime_put(xe);
>> drm_notice(&xe->drm, "migration recovery ended\n");
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2025-04-17 23:25 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-04-15 22:20 [PATCH v10 0/4] drm/xe/vf: Post-migration recovery of GGTT nodes and CTB Tomasz Lis
2025-04-15 22:20 ` [PATCH v10 1/4] drm/xe/vf: Divide GGTT ballooning into allocation and insertion Tomasz Lis
2025-04-17 18:10 ` Michal Wajdeczko
2025-04-15 22:20 ` [PATCH v10 2/4] drm/xe/vf: Shifting GGTT area post migration Tomasz Lis
2025-04-15 22:20 ` [PATCH v10 3/4] drm/xe/guc: Introduce enum with offsets for context register H2Gs Tomasz Lis
2025-04-15 22:20 ` [PATCH v10 4/4] drm/xe/vf: Fixup CTB send buffer messages after migration Tomasz Lis
2025-04-17 19:06 ` Michal Wajdeczko
2025-04-17 23:25 ` Lis, Tomasz
2025-04-15 23:15 ` ✓ Xe.CI.BAT: success for drm/xe/vf: Post-migration recovery of GGTT nodes and CTB Patchwork
2025-04-16 8:05 ` ✗ Xe.CI.Full: failure " Patchwork
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