From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: <intel-xe@lists.freedesktop.org>
Cc: dri-devel@lists.freedesktop.org, Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [Intel-xe] [PATCH 07/14] drm/xe: Introduce guc_submit_types.h with relevant structs.
Date: Wed, 26 Apr 2023 16:57:06 -0400 [thread overview]
Message-ID: <20230426205713.512695-8-rodrigo.vivi@intel.com> (raw)
In-Reply-To: <20230426205713.512695-1-rodrigo.vivi@intel.com>
These structs and definitions are only used for the guc_submit
and they were added specifically for the parallel submission.
While doing that also delete the unused struct guc_wq_item.
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/xe/xe_guc_fwif.h | 29 -----------
drivers/gpu/drm/xe/xe_guc_submit.c | 40 ++++-----------
drivers/gpu/drm/xe/xe_guc_submit_types.h | 64 ++++++++++++++++++++++++
3 files changed, 75 insertions(+), 58 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_guc_submit_types.h
diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
index 20155ba4ef07..27d132ce2087 100644
--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
@@ -46,35 +46,6 @@
#define GUC_MAX_ENGINE_CLASSES 16
#define GUC_MAX_INSTANCES_PER_CLASS 32
-/* Work item for submitting workloads into work queue of GuC. */
-#define WQ_STATUS_ACTIVE 1
-#define WQ_STATUS_SUSPENDED 2
-#define WQ_STATUS_CMD_ERROR 3
-#define WQ_STATUS_ENGINE_ID_NOT_USED 4
-#define WQ_STATUS_SUSPENDED_FROM_RESET 5
-#define WQ_TYPE_NOOP 0x4
-#define WQ_TYPE_MULTI_LRC 0x5
-#define WQ_TYPE_MASK GENMASK(7, 0)
-#define WQ_LEN_MASK GENMASK(26, 16)
-
-#define WQ_GUC_ID_MASK GENMASK(15, 0)
-#define WQ_RING_TAIL_MASK GENMASK(28, 18)
-
-struct guc_wq_item {
- u32 header;
- u32 context_desc;
- u32 submit_element_info;
- u32 fence_id;
-} __packed;
-
-struct guc_sched_wq_desc {
- u32 head;
- u32 tail;
- u32 error_offset;
- u32 wq_status;
- u32 reserved[28];
-} __packed;
-
/* Helper for context registration H2G */
struct guc_ctxt_registration_info {
u32 flags;
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 231fb4145297..a5fe7755ce4c 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -22,6 +22,7 @@
#include "xe_guc.h"
#include "xe_guc_ct.h"
#include "xe_guc_engine_types.h"
+#include "xe_guc_submit_types.h"
#include "xe_hw_engine.h"
#include "xe_hw_fence.h"
#include "xe_lrc.h"
@@ -378,32 +379,12 @@ static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_engine *e)
__guc_engine_policy_action_size(&policy), 0, 0);
}
-#define PARALLEL_SCRATCH_SIZE 2048
-#define WQ_SIZE (PARALLEL_SCRATCH_SIZE / 2)
-#define WQ_OFFSET (PARALLEL_SCRATCH_SIZE - WQ_SIZE)
-#define CACHELINE_BYTES 64
-
-struct sync_semaphore {
- u32 semaphore;
- u8 unused[CACHELINE_BYTES - sizeof(u32)];
-};
-
-struct parallel_scratch {
- struct guc_sched_wq_desc wq_desc;
-
- struct sync_semaphore go;
- struct sync_semaphore join[XE_HW_ENGINE_MAX_INSTANCE];
-
- u8 unused[WQ_OFFSET - sizeof(struct guc_sched_wq_desc) -
- sizeof(struct sync_semaphore) * (XE_HW_ENGINE_MAX_INSTANCE + 1)];
-
- u32 wq[WQ_SIZE / sizeof(u32)];
-};
-
#define parallel_read(xe_, map_, field_) \
- xe_map_rd_field(xe_, &map_, 0, struct parallel_scratch, field_)
+ xe_map_rd_field(xe_, &map_, 0, struct guc_submit_parallel_scratch, \
+ field_)
#define parallel_write(xe_, map_, field_, val_) \
- xe_map_wr_field(xe_, &map_, 0, struct parallel_scratch, field_, val_)
+ xe_map_wr_field(xe_, &map_, 0, struct guc_submit_parallel_scratch, \
+ field_, val_)
static void __register_mlrc_engine(struct xe_guc *guc,
struct xe_engine *e,
@@ -486,13 +467,13 @@ static void register_engine(struct xe_engine *e)
struct iosys_map map = xe_lrc_parallel_map(lrc);
info.wq_desc_lo = lower_32_bits(ggtt_addr +
- offsetof(struct parallel_scratch, wq_desc));
+ offsetof(struct guc_submit_parallel_scratch, wq_desc));
info.wq_desc_hi = upper_32_bits(ggtt_addr +
- offsetof(struct parallel_scratch, wq_desc));
+ offsetof(struct guc_submit_parallel_scratch, wq_desc));
info.wq_base_lo = lower_32_bits(ggtt_addr +
- offsetof(struct parallel_scratch, wq[0]));
+ offsetof(struct guc_submit_parallel_scratch, wq[0]));
info.wq_base_hi = upper_32_bits(ggtt_addr +
- offsetof(struct parallel_scratch, wq[0]));
+ offsetof(struct guc_submit_parallel_scratch, wq[0]));
info.wq_size = WQ_SIZE;
e->guc->wqi_head = 0;
@@ -594,7 +575,7 @@ static void wq_item_append(struct xe_engine *e)
XE_BUG_ON(i != wqi_size / sizeof(u32));
- iosys_map_incr(&map, offsetof(struct parallel_scratch,
+ iosys_map_incr(&map, offsetof(struct guc_submit_parallel_scratch,
wq[e->guc->wqi_tail / sizeof(u32)]));
xe_map_memcpy_to(xe, &map, 0, wqi, wqi_size);
e->guc->wqi_tail += wqi_size;
@@ -1674,6 +1655,7 @@ static void guc_engine_print(struct xe_engine *e, struct drm_printer *p)
guc_engine_wq_print(e, p);
spin_lock(&sched->job_list_lock);
+
list_for_each_entry(job, &sched->pending_list, drm.list)
drm_printf(p, "\tJob: seqno=%d, fence=%d, finished=%d\n",
xe_sched_job_seqno(job),
diff --git a/drivers/gpu/drm/xe/xe_guc_submit_types.h b/drivers/gpu/drm/xe/xe_guc_submit_types.h
new file mode 100644
index 000000000000..d369ea0bad60
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_guc_submit_types.h
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _XE_GUC_SUBMIT_TYPES_H_
+#define _XE_GUC_SUBMIT_TYPES_H_
+
+#include "xe_hw_engine_types.h"
+
+/* Work item for submitting workloads into work queue of GuC. */
+#define WQ_STATUS_ACTIVE 1
+#define WQ_STATUS_SUSPENDED 2
+#define WQ_STATUS_CMD_ERROR 3
+#define WQ_STATUS_ENGINE_ID_NOT_USED 4
+#define WQ_STATUS_SUSPENDED_FROM_RESET 5
+#define WQ_TYPE_NOOP 0x4
+#define WQ_TYPE_MULTI_LRC 0x5
+#define WQ_TYPE_MASK GENMASK(7, 0)
+#define WQ_LEN_MASK GENMASK(26, 16)
+
+#define WQ_GUC_ID_MASK GENMASK(15, 0)
+#define WQ_RING_TAIL_MASK GENMASK(28, 18)
+
+#define PARALLEL_SCRATCH_SIZE 2048
+#define WQ_SIZE (PARALLEL_SCRATCH_SIZE / 2)
+#define WQ_OFFSET (PARALLEL_SCRATCH_SIZE - WQ_SIZE)
+#define CACHELINE_BYTES 64
+
+struct guc_sched_wq_desc {
+ u32 head;
+ u32 tail;
+ u32 error_offset;
+ u32 wq_status;
+ u32 reserved[28];
+} __packed;
+
+struct sync_semaphore {
+ u32 semaphore;
+ u8 unused[CACHELINE_BYTES - sizeof(u32)];
+};
+
+/**
+ * Struct guc_submit_parallel_scratch - A scratch shared mapped buffer.
+ */
+struct guc_submit_parallel_scratch {
+ /** @wq_desc: Guc scheduler workqueue descriptor */
+ struct guc_sched_wq_desc wq_desc;
+
+ /** @go: Go Semaphore */
+ struct sync_semaphore go;
+ /** @join: Joined semaphore for the relevant hw engine instances */
+ struct sync_semaphore join[XE_HW_ENGINE_MAX_INSTANCE];
+
+ /** @unused: Unused/Reserved memory space */
+ u8 unused[WQ_OFFSET - sizeof(struct guc_sched_wq_desc) -
+ sizeof(struct sync_semaphore) *
+ (XE_HW_ENGINE_MAX_INSTANCE + 1)];
+
+ /** @wq: Workqueue info */
+ u32 wq[WQ_SIZE / sizeof(u32)];
+};
+
+#endif
--
2.39.2
next prev parent reply other threads:[~2023-04-26 20:57 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-26 20:56 [Intel-xe] [PATCH 00/14] Introduce xe_devcoredump Rodrigo Vivi
2023-04-26 20:57 ` [Intel-xe] [PATCH 01/14] drm/xe: Fix print of RING_EXECLIST_SQ_CONTENTS_HI Rodrigo Vivi
2023-04-26 21:40 ` Lucas De Marchi
2023-04-26 21:59 ` Rodrigo Vivi
2023-04-26 20:57 ` [Intel-xe] [PATCH 02/14] drm/xe: Introduce the dev_coredump infrastructure Rodrigo Vivi
2023-04-27 8:28 ` Thomas Hellström
2023-05-02 7:57 ` Matthew Brost
2023-05-02 18:06 ` Rodrigo Vivi
2023-05-02 20:29 ` Matthew Brost
2023-05-02 7:55 ` Jani Nikula
2023-05-02 17:25 ` Rodrigo Vivi
2023-04-26 20:57 ` [Intel-xe] [PATCH 03/14] drm/xe: Do not take any action if our device was removed Rodrigo Vivi
2023-05-02 15:40 ` Matthew Brost
2023-05-02 17:21 ` Rodrigo Vivi
2023-05-02 23:06 ` Matthew Brost
2023-04-26 20:57 ` [Intel-xe] [PATCH 04/14] drm/xe: Extract non mapped regions out of GuC CTB into its own struct Rodrigo Vivi
2023-05-02 5:12 ` Matthew Brost
2023-04-26 20:57 ` [Intel-xe] [PATCH 05/14] drm/xe: Convert GuC CT print to snapshot capture and print Rodrigo Vivi
2023-05-02 5:27 ` Matthew Brost
2023-04-26 20:57 ` [Intel-xe] [PATCH 06/14] drm/xe: Add GuC CT snapshot to xe_devcoredump Rodrigo Vivi
2023-05-02 14:55 ` Matthew Brost
2023-04-26 20:57 ` Rodrigo Vivi [this message]
2023-05-02 7:44 ` [Intel-xe] [PATCH 07/14] drm/xe: Introduce guc_submit_types.h with relevant structs Matthew Brost
2023-04-26 20:57 ` [Intel-xe] [PATCH 08/14] drm/xe: Convert GuC Engine print to snapshot capture and print Rodrigo Vivi
2023-05-02 15:01 ` Matthew Brost
2023-04-26 20:57 ` [Intel-xe] [PATCH 09/14] drm/xe: Add GuC Submit Engine snapshot to xe_devcoredump Rodrigo Vivi
2023-05-02 15:03 ` Matthew Brost
2023-04-26 20:57 ` [Intel-xe] [PATCH 10/14] drm/xe: Convert Xe HW Engine print to snapshot capture and print Rodrigo Vivi
2023-05-02 15:20 ` Matthew Brost
2023-04-26 20:57 ` [Intel-xe] [PATCH 11/14] drm/xe: Add HW Engine snapshot to xe_devcoredump Rodrigo Vivi
2023-05-02 15:30 ` Matthew Brost
2023-04-26 20:57 ` [Intel-xe] [PATCH 12/14] drm/xe: Limit CONFIG_DRM_XE_SIMPLE_ERROR_CAPTURE to itself Rodrigo Vivi
2023-05-02 15:35 ` Matthew Brost
2023-04-26 20:57 ` [Intel-xe] [PATCH 13/14] drm/xe: Convert VM print to snapshot capture and print Rodrigo Vivi
2023-05-02 7:50 ` Matthew Brost
2023-05-02 8:07 ` Matthew Brost
2023-04-26 20:57 ` [Intel-xe] [PATCH 14/14] drm/xe: Add VM snapshot to xe_devcoredump Rodrigo Vivi
2023-05-02 15:38 ` Matthew Brost
2023-04-26 21:01 ` [Intel-xe] ✓ CI.Patch_applied: success for Introduce xe_devcoredump Patchwork
2023-04-26 21:02 ` [Intel-xe] ✓ CI.KUnit: " Patchwork
2023-04-26 21:06 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-04-26 21:29 ` [Intel-xe] ○ CI.BAT: info " Patchwork
2023-05-02 8:11 ` [Intel-xe] [PATCH 00/14] " Matthew Brost
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