From: Matthew Auld <matthew.auld@intel.com>
To: intel-xe@lists.freedesktop.org
Subject: [Intel-xe] [PATCH v3 0/5] Try to handle TLB invalidations from CT fast-path
Date: Tue, 4 Jul 2023 14:45:25 +0100 [thread overview]
Message-ID: <20230704134524.138377-7-matthew.auld@intel.com> (raw)
In various test cases and workloads that put the system under a heavy load, we
can sometimes see errors with missed TLB invalidations. If we handle the TLB
completions directly from IRQ we can see a big improvement.
--
2.41.0
next reply other threads:[~2023-07-04 13:46 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 13:45 Matthew Auld [this message]
2023-07-04 13:45 ` [Intel-xe] [PATCH v3 1/5] drm/xe: hold mem_access.ref for CT fast-path Matthew Auld
2023-07-04 13:45 ` [Intel-xe] [PATCH v3 2/5] drm/xe/ct: serialise fast_lock during CT disable Matthew Auld
2023-07-04 13:45 ` [Intel-xe] [PATCH v3 3/5] drm/xe/gt: tweak placement for signalling TLB fences after GT reset Matthew Auld
2023-07-04 13:45 ` [Intel-xe] [PATCH v3 4/5] drm/xe/tlb: also update seqno_recv during reset Matthew Auld
2023-07-04 13:45 ` [Intel-xe] [PATCH v3 5/5] drm/xe: handle TLB invalidations from CT fast-path Matthew Auld
2023-07-04 13:48 ` [Intel-xe] ✓ CI.Patch_applied: success for Try to " Patchwork
2023-07-04 13:49 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-07-04 13:50 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-07-04 13:54 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-07-04 13:54 ` [Intel-xe] ✓ CI.Hooks: " Patchwork
2023-07-04 13:55 ` [Intel-xe] ✓ CI.checksparse: " Patchwork
2023-07-04 14:42 ` [Intel-xe] ○ CI.BAT: info " Patchwork
2023-07-04 18:19 ` [Intel-xe] [PATCH v3 0/5] " Souza, Jose
2023-07-04 18:42 ` Souza, Jose
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