From: Matthew Auld <matthew.auld@intel.com>
To: intel-xe@lists.freedesktop.org
Subject: [Intel-xe] [PATCH v5 05/10] drm/xe/tlb: increment next seqno after successful CT send
Date: Thu, 6 Jul 2023 17:20:09 +0100 [thread overview]
Message-ID: <20230706162003.427026-17-matthew.auld@intel.com> (raw)
In-Reply-To: <20230706162003.427026-12-matthew.auld@intel.com>
If we are in the middle of a GT reset or similar the CT might be
disabled, such that the CT send fails. However we already incremented
gt->tlb_invalidation.seqno which might lead to warnings, since we
effectively just skipped a seqno:
0000:00:02.0: drm_WARN_ON(expected_seqno != msg[0])
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
index c67abc67d9fc..de65b0b69679 100644
--- a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
+++ b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
@@ -124,10 +124,6 @@ static int send_tlb_invalidation(struct xe_guc *guc,
trace_xe_gt_tlb_invalidation_fence_send(fence);
}
action[1] = seqno;
- gt->tlb_invalidation.seqno = (gt->tlb_invalidation.seqno + 1) %
- TLB_INVALIDATION_SEQNO_MAX;
- if (!gt->tlb_invalidation.seqno)
- gt->tlb_invalidation.seqno = 1;
ret = xe_guc_ct_send_locked(&guc->ct, action, len,
G2H_LEN_DW_TLB_INVALIDATE, 1);
if (!ret && fence) {
@@ -137,8 +133,13 @@ static int send_tlb_invalidation(struct xe_guc *guc,
>->tlb_invalidation.fence_tdr,
TLB_TIMEOUT);
}
- if (!ret)
+ if (!ret) {
+ gt->tlb_invalidation.seqno = (gt->tlb_invalidation.seqno + 1) %
+ TLB_INVALIDATION_SEQNO_MAX;
+ if (!gt->tlb_invalidation.seqno)
+ gt->tlb_invalidation.seqno = 1;
ret = seqno;
+ }
if (ret < 0 && fence)
invalidation_fence_signal(fence);
mutex_unlock(&guc->ct.lock);
--
2.41.0
next prev parent reply other threads:[~2023-07-06 16:20 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-06 16:20 [Intel-xe] [PATCH v5 00/10] Try to handle TLB invalidations from CT fast-path Matthew Auld
2023-07-06 16:20 ` [Intel-xe] [PATCH v5 01/10] drm/xe/tlb: drop unnecessary smp_wmb() Matthew Auld
2023-07-06 18:44 ` Matthew Brost
2023-07-06 16:20 ` [Intel-xe] [PATCH v5 02/10] drm/xe/tlb: ensure we access seqno_recv once Matthew Auld
2023-07-06 18:53 ` Matthew Brost
2023-07-06 16:20 ` [Intel-xe] [PATCH v5 03/10] drm/xe: hold mem_access.ref for CT fast-path Matthew Auld
2023-07-06 16:20 ` [Intel-xe] [PATCH v5 04/10] drm/xe/ct: hold fast_lock when reserving space for g2h Matthew Auld
2023-07-06 16:20 ` Matthew Auld [this message]
2023-07-06 16:20 ` [Intel-xe] [PATCH v5 06/10] drm/xe/ct: serialise fast_lock during CT disable Matthew Auld
2023-07-06 16:20 ` [Intel-xe] [PATCH v5 07/10] drm/xe/gt: tweak placement for signalling TLB fences after GT reset Matthew Auld
2023-07-06 16:20 ` [Intel-xe] [PATCH v5 08/10] drm/xe/tlb: also update seqno_recv during reset Matthew Auld
2023-07-06 16:20 ` [Intel-xe] [PATCH v5 09/10] drm/xe: handle TLB invalidations from CT fast-path Matthew Auld
2023-07-06 16:20 ` [Intel-xe] [PATCH v5 10/10] drm/xe/tlb: print seqno_recv on fence TLB timeout Matthew Auld
2023-07-06 18:54 ` Matthew Brost
2023-07-06 18:43 ` [Intel-xe] ✓ CI.Patch_applied: success for Try to handle TLB invalidations from CT fast-path (rev3) Patchwork
2023-07-06 18:43 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-07-07 13:47 ` [Intel-xe] [PATCH v5 00/10] Try to handle TLB invalidations from CT fast-path Souza, Jose
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