From: Ashutosh Dixit <ashutosh.dixit@intel.com>
To: intel-xe@lists.freedesktop.org
Subject: [Intel-xe] [PATCH 06/21] drm/xe/oa: Start implementing OA stream open ioctl
Date: Tue, 19 Sep 2023 09:10:34 -0700 [thread overview]
Message-ID: <20230919161049.2307855-7-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <20230919161049.2307855-1-ashutosh.dixit@intel.com>
Start implementing OA stream open ioctl and parse properties passed in as
part of OA stream open. The remaining operations associated with OA stream
open continue in subsequent patches.
v2: Include PVC in xe_oa_timestamp_frequency
Remove forcewake_get from reading RPM_CONFIG0
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/xe/xe_device.c | 1 +
drivers/gpu/drm/xe/xe_oa.c | 239 +++++++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_oa.h | 2 +
3 files changed, 242 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index aacca14e52b11..7a179c4515633 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -115,6 +115,7 @@ static const struct drm_ioctl_desc xe_ioctls[] = {
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(XE_VM_MADVISE, xe_vm_madvise_ioctl, DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(XE_OA_OPEN, xe_oa_stream_open_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(XE_OA_ADD_CONFIG, xe_oa_add_config_ioctl, DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(XE_OA_REMOVE_CONFIG, xe_oa_remove_config_ioctl, DRM_RENDER_ALLOW),
diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index 1963bc6fad10e..c0ff8c2319ac0 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -11,11 +11,16 @@
#include <drm/xe_drm.h>
#include <drm/drm_drv.h>
+#include "regs/xe_gt_regs.h"
#include "regs/xe_oa_regs.h"
#include "xe_device.h"
#include "xe_gt.h"
+#include "xe_mmio.h"
#include "xe_oa.h"
+#define DEFAULT_POLL_FREQUENCY_HZ 200
+#define DEFAULT_POLL_PERIOD_NS (NSEC_PER_SEC / DEFAULT_POLL_FREQUENCY_HZ)
+
static u32 xe_oa_stream_paranoid = true;
static int xe_oa_sample_rate_hard_limit;
static u32 xe_oa_max_sample_rate = 100000;
@@ -31,6 +36,21 @@ static const struct xe_oa_format oa_formats[] = {
[XE_OAM_FORMAT_MPEC8u32_B8_C8] = { 2, 128, TYPE_OAM, HDR_64_BIT },
};
+struct xe_oa_open_properties {
+ bool sample;
+ bool single_exec_q;
+ u64 exec_q_id;
+
+ int metrics_set;
+ int oa_format;
+ bool oa_periodic;
+ int oa_period_exponent;
+
+ struct xe_hw_engine *hwe;
+
+ u64 poll_oa_period;
+};
+
static struct ctl_table_header *sysctl_header;
static void xe_oa_config_release(struct kref *ref)
@@ -53,6 +73,225 @@ static void xe_oa_config_put(struct xe_oa_config *oa_config)
kref_put(&oa_config->ref, xe_oa_config_release);
}
+/*
+ * OA timestamp frequency = CS timestamp frequency in most platforms. On some
+ * platforms OA unit ignores the CTC_SHIFT and the 2 timestamps differ. In such
+ * cases, return the adjusted CS timestamp frequency to the user.
+ */
+u32 xe_oa_timestamp_frequency(struct xe_device *xe)
+{
+ u32 reg, shift;
+
+ /*
+ * Wa_18013179988:dg2
+ * Wa_14015568240:pvc
+ * Wa_14015846243:mtl
+ */
+ switch (xe->info.platform) {
+ case XE_DG2:
+ case XE_PVC:
+ case XE_METEORLAKE:
+ xe_device_mem_access_get(xe);
+ reg = xe_mmio_read32(xe_root_mmio_gt(xe), RPM_CONFIG0);
+ xe_device_mem_access_put(xe);
+
+ shift = REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
+ return xe_root_mmio_gt(xe)->info.clock_freq << (3 - shift);
+
+ default:
+ return xe_root_mmio_gt(xe)->info.clock_freq;
+ }
+}
+
+static u64 oa_exponent_to_ns(struct xe_oa *oa, int exponent)
+{
+ u64 nom = (2ULL << exponent) * NSEC_PER_SEC;
+ u32 den = xe_oa_timestamp_frequency(oa->xe);
+
+ return div_u64(nom + den - 1, den);
+}
+
+static bool oa_format_valid(struct xe_oa *oa, u64 format)
+{
+ if (format >= XE_OA_FORMAT_MAX)
+ return false;
+ return test_bit(format, oa->format_mask);
+}
+
+static bool engine_supports_oa(const struct xe_hw_engine *hwe)
+{
+ return hwe->oa_group;
+}
+
+static bool engine_supports_oa_format(const struct xe_hw_engine *hwe, int type)
+{
+ return hwe->oa_group && hwe->oa_group->type == type;
+}
+
+#define OA_EXPONENT_MAX 31
+
+static int xe_oa_read_properties_unlocked(struct xe_oa *oa, u64 __user *uprops,
+ u32 n_props,
+ struct xe_oa_open_properties *props)
+{
+ const struct xe_oa_format *f;
+ u64 __user *uprop = uprops;
+ bool config_instance = false;
+ bool config_class = false;
+ u8 class, instance;
+ struct xe_gt *gt;
+ u32 i;
+ int ret;
+
+ if (!n_props || n_props >= DRM_XE_OA_PROP_MAX) {
+ drm_dbg(&oa->xe->drm, "Invalid number of xe perf properties given\n");
+ return -EINVAL;
+ }
+
+ props->poll_oa_period = DEFAULT_POLL_PERIOD_NS;
+
+ /* Defaults when class:instance is not passed */
+ class = XE_ENGINE_CLASS_RENDER;
+ instance = 0;
+
+ for (i = 0; i < n_props; i++) {
+ u64 oa_period, oa_freq_hz;
+ u64 id, value;
+
+ ret = get_user(id, uprop);
+ if (ret)
+ return ret;
+
+ ret = get_user(value, uprop + 1);
+ if (ret)
+ return ret;
+
+ switch ((enum drm_xe_oa_property_id)id) {
+ case DRM_XE_OA_PROP_EXEC_QUEUE_ID:
+ props->single_exec_q = true;
+ props->exec_q_id = value;
+ break;
+ case DRM_XE_OA_PROP_SAMPLE_OA:
+ props->sample = value;
+ break;
+ case DRM_XE_OA_PROP_OA_METRICS_SET:
+ if (!value) {
+ drm_dbg(&oa->xe->drm, "Unknown OA metric set ID\n");
+ return -EINVAL;
+ }
+ props->metrics_set = value;
+ break;
+ case DRM_XE_OA_PROP_OA_FORMAT:
+ if (!oa_format_valid(oa, value)) {
+ drm_dbg(&oa->xe->drm, "Unsupported OA report format %llu\n",
+ value);
+ return -EINVAL;
+ }
+ props->oa_format = value;
+ break;
+ case DRM_XE_OA_PROP_OA_EXPONENT:
+ if (value > OA_EXPONENT_MAX) {
+ drm_dbg(&oa->xe->drm, "OA timer exponent too high (> %u)\n",
+ OA_EXPONENT_MAX);
+ return -EINVAL;
+ }
+
+ BUILD_BUG_ON(sizeof(oa_period) != 8);
+ oa_period = oa_exponent_to_ns(oa, value);
+
+ oa_freq_hz = div64_u64(NSEC_PER_SEC, oa_period);
+ if (oa_freq_hz > xe_oa_max_sample_rate && !perfmon_capable()) {
+ drm_dbg(&oa->xe->drm,
+ "OA exponent would exceed the max sampling frequency (sysctl dev.xe.oa_max_sample_rate) %uHz without CAP_PERFMON or CAP_SYS_ADMIN privileges\n",
+ xe_oa_max_sample_rate);
+ return -EACCES;
+ }
+
+ props->oa_periodic = true;
+ props->oa_period_exponent = value;
+ break;
+ case DRM_XE_OA_PROP_POLL_OA_PERIOD:
+ if (value < 100000 /* 100us */) {
+ drm_dbg(&oa->xe->drm, "OA timer too small (%lluns < 100us)\n",
+ value);
+ return -EINVAL;
+ }
+ props->poll_oa_period = value;
+ break;
+ case DRM_XE_OA_PROP_OA_ENGINE_CLASS:
+ class = (u8)value;
+ config_class = true;
+ break;
+ case DRM_XE_OA_PROP_OA_ENGINE_INSTANCE:
+ instance = (u8)value;
+ config_instance = true;
+ break;
+ default:
+ drm_dbg(&oa->xe->drm, "Unknown xe oa property ID %lld\n", id);
+ return -EINVAL;
+ }
+
+ uprop += 2;
+ }
+
+ if ((config_class && !config_instance) ||
+ (config_instance && !config_class)) {
+ drm_dbg(&oa->xe->drm, "OA engine class/instance parameters must be passed together\n");
+ return -EINVAL;
+ }
+
+ for_each_gt(gt, oa->xe, i) {
+ props->hwe = xe_gt_hw_engine(gt, class, instance, false);
+ if (props->hwe)
+ break;
+ }
+ if (!props->hwe) {
+ drm_dbg(&oa->xe->drm, "OA engine class and instance invalid %d:%d\n",
+ class, instance);
+ return -EINVAL;
+ }
+
+ if (!engine_supports_oa(props->hwe)) {
+ drm_dbg(&oa->xe->drm, "Engine not supported by OA %d:%d\n",
+ class, instance);
+ return -EINVAL;
+ }
+
+ f = &oa->oa_formats[props->oa_format];
+ if (!props->oa_format || !f->size ||
+ !engine_supports_oa_format(props->hwe, f->type)) {
+ drm_dbg(&oa->xe->drm, "Invalid OA format %d type %d size %d for class %d\n",
+ props->oa_format, f->type, f->size, props->hwe->class);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int xe_oa_stream_open_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file)
+{
+ struct xe_oa *oa = &to_xe_device(dev)->oa;
+ struct drm_xe_oa_open_param *param = data;
+ struct xe_oa_open_properties props = {};
+ u32 known_open_flags;
+
+ if (!oa->xe) {
+ drm_dbg(&oa->xe->drm, "xe oa interface not available for this system\n");
+ return -ENODEV;
+ }
+
+ known_open_flags = XE_OA_FLAG_FD_CLOEXEC | XE_OA_FLAG_FD_NONBLOCK | XE_OA_FLAG_DISABLED;
+ if (param->flags & ~known_open_flags) {
+ drm_dbg(&oa->xe->drm, "Unknown drm_xe_oa_open_param flag\n");
+ return -EINVAL;
+ }
+
+ return xe_oa_read_properties_unlocked(oa, u64_to_user_ptr(param->properties_ptr),
+ param->num_properties,
+ &props);
+}
+
static bool xe_oa_is_valid_flex_addr(struct xe_oa *oa, u32 addr)
{
static const struct xe_reg flex_eu_regs[] = {
diff --git a/drivers/gpu/drm/xe/xe_oa.h b/drivers/gpu/drm/xe/xe_oa.h
index 79f77f445deb0..fd6caf652047a 100644
--- a/drivers/gpu/drm/xe/xe_oa.h
+++ b/drivers/gpu/drm/xe/xe_oa.h
@@ -16,6 +16,8 @@ int xe_oa_ioctl_version(struct xe_device *xe);
int xe_oa_sysctl_register(void);
void xe_oa_sysctl_unregister(void);
+int xe_oa_stream_open_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file);
int xe_oa_add_config_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
int xe_oa_remove_config_ioctl(struct drm_device *dev, void *data,
--
2.41.0
next prev parent reply other threads:[~2023-09-19 16:16 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-19 16:10 [Intel-xe] [PATCH 00/21] Add OA functionality to Xe Ashutosh Dixit
2023-09-19 16:10 ` [Intel-xe] [PATCH 01/21] drm/xe/uapi: Introduce OA (observability architecture) uapi Ashutosh Dixit
2023-10-04 0:26 ` Umesh Nerlige Ramappa
2023-10-04 0:36 ` Dixit, Ashutosh
2023-11-04 1:23 ` Dixit, Ashutosh
2023-09-19 16:10 ` [Intel-xe] [PATCH 02/21] drm/xe/oa: Add OA types Ashutosh Dixit
2023-10-13 17:05 ` Umesh Nerlige Ramappa
2023-09-19 16:10 ` [Intel-xe] [PATCH 03/21] drm/xe/oa: Add registers and GPU commands used by OA Ashutosh Dixit
2023-10-13 17:06 ` Umesh Nerlige Ramappa
2023-11-17 22:52 ` Dixit, Ashutosh
2023-09-19 16:10 ` [Intel-xe] [PATCH 04/21] drm/xe/oa: Module init/exit and probe/remove Ashutosh Dixit
2023-10-13 17:50 ` Umesh Nerlige Ramappa
2023-10-20 7:08 ` [Intel-xe] [04/21] " Lionel Landwerlin
2023-10-27 20:28 ` Dixit, Ashutosh
2023-09-19 16:10 ` [Intel-xe] [PATCH 05/21] drm/xe/oa: Add/remove config ioctl's Ashutosh Dixit
2023-10-13 17:59 ` Umesh Nerlige Ramappa
2023-09-19 16:10 ` Ashutosh Dixit [this message]
2023-10-13 18:09 ` [Intel-xe] [PATCH 06/21] drm/xe/oa: Start implementing OA stream open ioctl Umesh Nerlige Ramappa
2023-09-19 16:10 ` [Intel-xe] [PATCH 07/21] drm/xe/oa: OA stream initialization Ashutosh Dixit
2023-10-04 15:22 ` Dixit, Ashutosh
2023-09-19 16:10 ` [Intel-xe] [PATCH 08/21] drm/xe/oa: Expose OA stream fd Ashutosh Dixit
2023-10-13 18:17 ` Umesh Nerlige Ramappa
2023-09-19 16:10 ` [Intel-xe] [PATCH 09/21] drm/xe/oa: Read file_operation Ashutosh Dixit
2023-10-14 0:56 ` Umesh Nerlige Ramappa
2023-09-19 16:10 ` [Intel-xe] [PATCH 10/21] drm/xe/oa: Implement queries Ashutosh Dixit
2023-10-14 0:58 ` Umesh Nerlige Ramappa
2023-09-19 16:10 ` [Intel-xe] [PATCH 11/21] drm/xe/oa: Override GuC RC with OA on PVC Ashutosh Dixit
2023-10-16 17:43 ` Umesh Nerlige Ramappa
2023-09-19 16:10 ` [Intel-xe] [PATCH 12/21] drm/xe/uapi: "Perf" layer to support multiple perf counter stream types Ashutosh Dixit
2023-10-04 2:13 ` Umesh Nerlige Ramappa
2023-10-05 4:33 ` Dixit, Ashutosh
2023-09-19 16:10 ` [Intel-xe] [PATCH 13/21] drm/xe/uapi: Multiplex PERF ops through a single PERF ioctl Ashutosh Dixit
2023-10-04 2:23 ` Umesh Nerlige Ramappa
2023-10-05 5:27 ` Dixit, Ashutosh
2023-10-05 15:22 ` Dixit, Ashutosh
2023-10-05 18:27 ` Umesh Nerlige Ramappa
2023-10-05 23:18 ` Dixit, Ashutosh
2023-09-19 16:10 ` [Intel-xe] [PATCH 14/21] drm/xe/uapi: Simplify OA configs in uapi Ashutosh Dixit
2023-10-04 2:26 ` Umesh Nerlige Ramappa
2023-10-04 15:44 ` Dixit, Ashutosh
2023-10-04 16:13 ` Rodrigo Vivi
2023-09-19 16:10 ` [Intel-xe] [PATCH 15/21] drm/xe/uapi: Remove OA format names from OA uapi Ashutosh Dixit
2023-10-04 2:33 ` Umesh Nerlige Ramappa
2023-10-05 6:13 ` Dixit, Ashutosh
2023-09-19 16:10 ` [Intel-xe] [PATCH 16/21] drm/xe/oa: Make xe_oa_timestamp_frequency per gt Ashutosh Dixit
2023-09-21 20:45 ` Rodrigo Vivi
2023-09-21 21:58 ` Dixit, Ashutosh
2023-09-22 19:10 ` Rodrigo Vivi
2023-09-19 16:10 ` [Intel-xe] [PATCH 17/21] drm/xe/oa: Remove filtering reports on context id Ashutosh Dixit
2023-10-14 1:01 ` Umesh Nerlige Ramappa
2023-10-20 7:30 ` [Intel-xe] [17/21] " Lionel Landwerlin
2023-10-20 17:00 ` Umesh Nerlige Ramappa
2023-09-19 16:10 ` [Intel-xe] [PATCH 18/21] drm/xe/uapi: More OA uapi fixes/additions Ashutosh Dixit
2023-10-04 0:23 ` Dixit, Ashutosh
2023-10-05 22:33 ` Dixit, Ashutosh
2023-10-12 3:14 ` Umesh Nerlige Ramappa
2023-10-20 7:28 ` [Intel-xe] [18/21] " Lionel Landwerlin
2023-10-27 20:28 ` Dixit, Ashutosh
2023-10-30 10:06 ` Lionel Landwerlin
2023-10-31 2:08 ` Dixit, Ashutosh
2023-09-19 16:10 ` [Intel-xe] [PATCH 19/21] drm/xe/uapi: Drop OA_IOCTL_VERSION Ashutosh Dixit
2023-09-19 17:02 ` Dixit, Ashutosh
2023-10-04 2:37 ` Umesh Nerlige Ramappa
2023-10-05 3:28 ` Dixit, Ashutosh
2023-10-05 19:35 ` Umesh Nerlige Ramappa
2023-10-20 7:36 ` [Intel-xe] [19/21] " Lionel Landwerlin
2023-10-23 23:02 ` Umesh Nerlige Ramappa
2023-10-24 4:08 ` Dixit, Ashutosh
2023-10-24 15:54 ` Dixit, Ashutosh
2023-09-19 16:10 ` [Intel-xe] [PATCH 20/21] drm/xe/uapi: Use OA unit id to identify OA unit Ashutosh Dixit
2023-10-04 22:37 ` Umesh Nerlige Ramappa
2023-10-05 3:04 ` Dixit, Ashutosh
2023-10-05 3:09 ` Dixit, Ashutosh
2023-09-19 16:10 ` [Intel-xe] [PATCH 21/21] drm/xe/uapi: Convert OA property key/value pairs to a struct Ashutosh Dixit
2023-09-21 23:53 ` Dixit, Ashutosh
2023-10-05 5:37 ` Dixit, Ashutosh
2023-10-05 19:26 ` Umesh Nerlige Ramappa
2023-09-19 16:19 ` [Intel-xe] ✓ CI.Patch_applied: success for Add OA functionality to Xe (rev6) Patchwork
2023-09-19 16:19 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-09-19 16:21 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-09-19 16:28 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-09-19 16:28 ` [Intel-xe] ✗ CI.Hooks: failure " Patchwork
2023-09-19 16:29 ` [Intel-xe] ✓ CI.checksparse: success " Patchwork
2023-09-19 17:04 ` [Intel-xe] ✗ CI.BAT: failure " Patchwork
2023-10-14 1:05 ` [Intel-xe] [PATCH 00/21] Add OA functionality to Xe Umesh Nerlige Ramappa
2023-10-20 7:44 ` Lionel Landwerlin
2023-10-20 7:52 ` Lionel Landwerlin
2023-10-31 6:51 ` Dixit, Ashutosh
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230919161049.2307855-7-ashutosh.dixit@intel.com \
--to=ashutosh.dixit@intel.com \
--cc=intel-xe@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox