Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Matthew Auld <matthew.auld@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>,
	Matt Roper <matthew.d.roper@intel.com>
Subject: [Intel-xe] [PATCH v4 1/5] drm/xe/pat: trim the xelp PAT table
Date: Wed, 27 Sep 2023 12:00:07 +0100	[thread overview]
Message-ID: <20230927110005.291917-8-matthew.auld@intel.com> (raw)
In-Reply-To: <20230927110005.291917-7-matthew.auld@intel.com>

We don't seem to use the 4-7 pat indexes, even though they are defined
by the HW. In the next patch userspace will be able to directly set the
pat_index as part of vm_bind and we don't want to allow setting 4-7.
Simplest is to just ignore them here.

Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Pallavi Mishra <pallavi.mishra@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/xe_pat.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 6efa44556689..2c759ffa35ef 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -42,10 +42,6 @@ static const u32 xelp_pat_table[] = {
 	[1] = XELP_PAT_WC,
 	[2] = XELP_PAT_WT,
 	[3] = XELP_PAT_UC,
-	[4] = XELP_PAT_WB,
-	[5] = XELP_PAT_WB,
-	[6] = XELP_PAT_WB,
-	[7] = XELP_PAT_WB,
 };
 
 static const u32 xehpc_pat_table[] = {
-- 
2.41.0


  reply	other threads:[~2023-09-27 11:00 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-27 11:00 [Intel-xe] [PATCH v4 0/5] PAT and cache coherency support Matthew Auld
2023-09-27 11:00 ` Matthew Auld [this message]
2023-09-27 11:00 ` [Intel-xe] [PATCH v4 2/5] drm/xe: directly use pat_index for pte_encode Matthew Auld
2023-09-28  4:41   ` Niranjana Vishwanathapura
2023-09-28  7:25     ` Matthew Auld
2023-09-27 11:00 ` [Intel-xe] [PATCH v4 3/5] drm/xe/uapi: Add support for cache and coherency mode Matthew Auld
2023-09-27 11:00 ` [Intel-xe] [PATCH v4 4/5] drm/xe/pat: annotate pat_index with " Matthew Auld
2023-09-27 11:00 ` [Intel-xe] [PATCH v4 5/5] drm/xe/uapi: support pat_index selection with vm_bind Matthew Auld
2023-09-27 11:31 ` [Intel-xe] ✗ CI.Patch_applied: failure for PAT and cache coherency support (rev5) Patchwork
2023-09-27 16:21 ` [Intel-xe] [PATCH v4 0/5] PAT and cache coherency support Souza, Jose
2023-09-28  7:53   ` Matthew Auld

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230927110005.291917-8-matthew.auld@intel.com \
    --to=matthew.auld@intel.com \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=lucas.demarchi@intel.com \
    --cc=matthew.d.roper@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox