* [Intel-xe] [PATCH v7 0/5] PAT and cache coherency support
@ 2023-10-05 15:46 Matthew Auld
2023-10-05 15:46 ` [Intel-xe] [PATCH v7 1/5] drm/xe/pat: trim the xelp PAT table Matthew Auld
` (7 more replies)
0 siblings, 8 replies; 9+ messages in thread
From: Matthew Auld @ 2023-10-05 15:46 UTC (permalink / raw)
To: intel-xe
Branch available here:
https://gitlab.freedesktop.org/mwa/kernel/-/tree/xe-pat-index?ref_type=heads
IGT changes:
https://patchwork.freedesktop.org/series/124667/
Mesa:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25462
Goal here is to allow userspace to directly control the pat_index when mapping
memory via the ppGTT, in addtion to the CPU caching mode. This is very much
needed on newer igpu platforms which allow incoherent GT access, where the
choice over the cache level and expected coherency is best left to userspace
depending on their usecase. In the future there may also be other stuff encoded
in the pat_index, so giving userspace direct control will also be needed there.
To support this we added new gem_create uAPI for selecting the CPU cache
mode to use for system memory, including the expected GPU coherency mode. There
are various restrictions here for the selected coherency mode and compatible CPU
cache modes. With that in place the actual pat_index can now be provided as
part of vm_bind. The only restriction is that the coherency mode of the
pat_index must be at least as coherent as the gem_create coherency mode. There
are also some special cases like with userptr and dma-buf.
v2:
- Loads of improvements/tweaks. Main changes are to now allow
gem_create.coh_mode <= coh_mode(pat_index), rather than it needing to match
exactly. This simplifies the dma-buf policy from userspace pov. Also we now
only consider COH_NONE and COH_AT_LEAST_1WAY.
v3:
- Rebase. Split the pte_encode() refactoring, plus various smaller tweaks and
fixes.
v4:
- Rebase on Lucas' new series.
- Drop UC cache mode.
- s/smem_cpu_caching/cpu_caching/. Idea is to make VRAM WC explicit in the
uapi, plus make it more future proof.
v5:
- Rebase, plus some small tweaks and fixes.
v6:
- CI hooks fixes + checkpatch.
v7:
- Some small tweaks
--
2.41.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-xe] [PATCH v7 1/5] drm/xe/pat: trim the xelp PAT table
2023-10-05 15:46 [Intel-xe] [PATCH v7 0/5] PAT and cache coherency support Matthew Auld
@ 2023-10-05 15:46 ` Matthew Auld
2023-10-05 15:46 ` [Intel-xe] [PATCH v7 2/5] drm/xe: directly use pat_index for pte_encode Matthew Auld
` (6 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Matthew Auld @ 2023-10-05 15:46 UTC (permalink / raw)
To: intel-xe; +Cc: Lucas De Marchi, Matt Roper
We don't seem to use the 4-7 pat indexes, even though they are defined
by the HW. In the next patch userspace will be able to directly set the
pat_index as part of vm_bind and we don't want to allow setting 4-7.
Simplest is to just ignore them here.
Suggested-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Pallavi Mishra <pallavi.mishra@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/xe/xe_pat.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 869aee64641f..36b79d675e54 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -42,10 +42,6 @@ static const u32 xelp_pat_table[] = {
[1] = XELP_PAT_WC,
[2] = XELP_PAT_WT,
[3] = XELP_PAT_UC,
- [4] = XELP_PAT_WB,
- [5] = XELP_PAT_WB,
- [6] = XELP_PAT_WB,
- [7] = XELP_PAT_WB,
};
static const u32 xehpc_pat_table[] = {
--
2.41.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-xe] [PATCH v7 2/5] drm/xe: directly use pat_index for pte_encode
2023-10-05 15:46 [Intel-xe] [PATCH v7 0/5] PAT and cache coherency support Matthew Auld
2023-10-05 15:46 ` [Intel-xe] [PATCH v7 1/5] drm/xe/pat: trim the xelp PAT table Matthew Auld
@ 2023-10-05 15:46 ` Matthew Auld
2023-10-05 15:46 ` [Intel-xe] [PATCH v7 3/5] drm/xe/uapi: Add support for cache and coherency mode Matthew Auld
` (5 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Matthew Auld @ 2023-10-05 15:46 UTC (permalink / raw)
To: intel-xe; +Cc: Matt Roper, Lucas De Marchi
In the next patch userspace will be able to directly set the pat_index
as part of vm_bind. To support this we need to get away from using
xe_cache_level in the low level routines and rather just use the
pat_index directly.
v2: Rebase
v3: Some missed conversions, also prefer tile_to_xe() (Niranjana)
v4: remove leftover const (Lucas)
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Pallavi Mishra <pallavi.mishra@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Pallavi Mishra <pallavi.mishra@intel.com>
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 10 ++++++----
drivers/gpu/drm/xe/tests/xe_migrate.c | 2 +-
drivers/gpu/drm/xe/xe_ggtt.c | 16 +++++++++-------
drivers/gpu/drm/xe/xe_ggtt_types.h | 3 +--
drivers/gpu/drm/xe/xe_migrate.c | 19 +++++++++++--------
drivers/gpu/drm/xe/xe_pt.c | 11 ++++++-----
drivers/gpu/drm/xe/xe_pt_types.h | 8 ++++----
drivers/gpu/drm/xe/xe_vm.c | 24 +++++++++++-------------
8 files changed, 49 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index b7a04fba3585..2c36e5032433 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -30,7 +30,7 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32 bo_
for (row = 0; row < height; row++) {
u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
- XE_CACHE_WB);
+ xe->pat.idx[XE_CACHE_WB]);
iosys_map_wr(map, *dpt_ofs, u64, pte);
*dpt_ofs += 8;
@@ -84,7 +84,7 @@ static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
for (x = 0; x < size / XE_PAGE_SIZE; x++) {
u64 pte = ggtt->pt_ops->pte_encode_bo(bo, x * XE_PAGE_SIZE,
- XE_CACHE_WB);
+ xe->pat.idx[XE_CACHE_WB]);
iosys_map_wr(&dpt->vmap, x * 8, u64, pte);
}
@@ -110,6 +110,7 @@ static void
write_ggtt_rotated(struct xe_bo *bo, struct xe_ggtt *ggtt, u32 *ggtt_ofs, u32 bo_ofs,
u32 width, u32 height, u32 src_stride, u32 dst_stride)
{
+ struct xe_device *xe = xe_bo_device(bo);
u32 column, row;
for (column = 0; column < width; column++) {
@@ -117,7 +118,7 @@ write_ggtt_rotated(struct xe_bo *bo, struct xe_ggtt *ggtt, u32 *ggtt_ofs, u32 bo
for (row = 0; row < height; row++) {
u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
- XE_CACHE_WB);
+ xe->pat.idx[XE_CACHE_WB]);
xe_ggtt_set_pte(ggtt, *ggtt_ofs, pte);
*ggtt_ofs += XE_PAGE_SIZE;
@@ -162,7 +163,8 @@ static int __xe_pin_fb_vma_ggtt(struct intel_framebuffer *fb,
goto out_unlock;
for (x = 0; x < size; x += XE_PAGE_SIZE) {
- u64 pte = ggtt->pt_ops->pte_encode_bo(bo, x, XE_CACHE_WB);
+ u64 pte = ggtt->pt_ops->pte_encode_bo(bo, x,
+ xe->pat.idx[XE_CACHE_WB]);
xe_ggtt_set_pte(ggtt, vma->node.start + x, pte);
}
diff --git a/drivers/gpu/drm/xe/tests/xe_migrate.c b/drivers/gpu/drm/xe/tests/xe_migrate.c
index 6906ff9d9c31..4c8526af06ce 100644
--- a/drivers/gpu/drm/xe/tests/xe_migrate.c
+++ b/drivers/gpu/drm/xe/tests/xe_migrate.c
@@ -301,7 +301,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test)
/* First part of the test, are we updating our pagetable bo with a new entry? */
xe_map_wr(xe, &bo->vmap, XE_PAGE_SIZE * (NUM_KERNEL_PDE - 1), u64,
0xdeaddeadbeefbeef);
- expected = m->q->vm->pt_ops->pte_encode_bo(pt, 0, XE_CACHE_WB, 0);
+ expected = m->q->vm->pt_ops->pte_encode_bo(pt, 0, xe->pat.idx[XE_CACHE_WB], 0);
if (m->q->vm->flags & XE_VM_FLAG_64K)
expected |= XE_PTE_PS64;
if (xe_bo_is_vram(pt))
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 99b54794917e..354871a6b371 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -27,7 +27,7 @@
#define GUC_GGTT_TOP 0xFEE00000
static u64 xelp_ggtt_pte_encode_bo(struct xe_bo *bo, u64 bo_offset,
- enum xe_cache_level cache)
+ u16 pat_index)
{
u64 pte;
@@ -41,13 +41,12 @@ static u64 xelp_ggtt_pte_encode_bo(struct xe_bo *bo, u64 bo_offset,
}
static u64 xelpg_ggtt_pte_encode_bo(struct xe_bo *bo, u64 bo_offset,
- enum xe_cache_level cache)
+ u16 pat_index)
{
struct xe_device *xe = xe_bo_device(bo);
- u32 pat_index = xe->pat.idx[cache];
u64 pte;
- pte = xelp_ggtt_pte_encode_bo(bo, bo_offset, cache);
+ pte = xelp_ggtt_pte_encode_bo(bo, bo_offset, pat_index);
xe_assert(xe, pat_index <= 3);
@@ -79,6 +78,7 @@ void xe_ggtt_set_pte(struct xe_ggtt *ggtt, u64 addr, u64 pte)
static void xe_ggtt_clear(struct xe_ggtt *ggtt, u64 start, u64 size)
{
+ u16 pat_index = tile_to_xe(ggtt->tile)->pat.idx[XE_CACHE_WB];
u64 end = start + size - 1;
u64 scratch_pte;
@@ -86,7 +86,7 @@ static void xe_ggtt_clear(struct xe_ggtt *ggtt, u64 start, u64 size)
if (ggtt->scratch)
scratch_pte = ggtt->pt_ops->pte_encode_bo(ggtt->scratch, 0,
- XE_CACHE_WB);
+ pat_index);
else
scratch_pte = 0;
@@ -285,9 +285,10 @@ void xe_ggtt_invalidate(struct xe_ggtt *ggtt)
void xe_ggtt_printk(struct xe_ggtt *ggtt, const char *prefix)
{
+ u16 pat_index = tile_to_xe(ggtt->tile)->pat.idx[XE_CACHE_WB];
u64 addr, scratch_pte;
- scratch_pte = ggtt->pt_ops->pte_encode_bo(ggtt->scratch, 0, XE_CACHE_WB);
+ scratch_pte = ggtt->pt_ops->pte_encode_bo(ggtt->scratch, 0, pat_index);
printk("%sGlobal GTT:", prefix);
for (addr = 0; addr < ggtt->size; addr += XE_PAGE_SIZE) {
@@ -324,11 +325,12 @@ int xe_ggtt_insert_special_node(struct xe_ggtt *ggtt, struct drm_mm_node *node,
void xe_ggtt_map_bo(struct xe_ggtt *ggtt, struct xe_bo *bo)
{
+ u16 pat_index = tile_to_xe(ggtt->tile)->pat.idx[XE_CACHE_WB];
u64 start = bo->ggtt_node.start;
u64 offset, pte;
for (offset = 0; offset < bo->size; offset += XE_PAGE_SIZE) {
- pte = ggtt->pt_ops->pte_encode_bo(bo, offset, XE_CACHE_WB);
+ pte = ggtt->pt_ops->pte_encode_bo(bo, offset, pat_index);
xe_ggtt_set_pte(ggtt, start + offset, pte);
}
diff --git a/drivers/gpu/drm/xe/xe_ggtt_types.h b/drivers/gpu/drm/xe/xe_ggtt_types.h
index 486016ea5b67..d8c584d9a8c3 100644
--- a/drivers/gpu/drm/xe/xe_ggtt_types.h
+++ b/drivers/gpu/drm/xe/xe_ggtt_types.h
@@ -14,8 +14,7 @@ struct xe_bo;
struct xe_gt;
struct xe_ggtt_pt_ops {
- u64 (*pte_encode_bo)(struct xe_bo *bo, u64 bo_offset,
- enum xe_cache_level cache);
+ u64 (*pte_encode_bo)(struct xe_bo *bo, u64 bo_offset, u16 pat_index);
};
struct xe_ggtt {
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 15f091a7bba3..70c4ff70779e 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -158,6 +158,7 @@ static int xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
struct xe_vm *vm)
{
struct xe_device *xe = tile_to_xe(tile);
+ u16 pat_index = xe->pat.idx[XE_CACHE_WB];
u8 id = tile->id;
u32 num_entries = NUM_PT_SLOTS, num_level = vm->pt_root[id]->level;
u32 map_ofs, level, i;
@@ -189,7 +190,7 @@ static int xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
return ret;
}
- entry = vm->pt_ops->pde_encode_bo(bo, bo->size - XE_PAGE_SIZE, XE_CACHE_WB);
+ entry = vm->pt_ops->pde_encode_bo(bo, bo->size - XE_PAGE_SIZE, pat_index);
xe_pt_write(xe, &vm->pt_root[id]->bo->vmap, 0, entry);
map_ofs = (num_entries - num_level) * XE_PAGE_SIZE;
@@ -197,7 +198,7 @@ static int xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
/* Map the entire BO in our level 0 pt */
for (i = 0, level = 0; i < num_entries; level++) {
entry = vm->pt_ops->pte_encode_bo(bo, i * XE_PAGE_SIZE,
- XE_CACHE_WB, 0);
+ pat_index, 0);
xe_map_wr(xe, &bo->vmap, map_ofs + level * 8, u64, entry);
@@ -216,7 +217,7 @@ static int xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
i += vm->flags & XE_VM_FLAG_64K ? XE_64K_PAGE_SIZE :
XE_PAGE_SIZE) {
entry = vm->pt_ops->pte_encode_bo(batch, i,
- XE_CACHE_WB, 0);
+ pat_index, 0);
xe_map_wr(xe, &bo->vmap, map_ofs + level * 8, u64,
entry);
@@ -241,7 +242,7 @@ static int xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
flags = XE_PDE_64K;
entry = vm->pt_ops->pde_encode_bo(bo, map_ofs + (level - 1) *
- XE_PAGE_SIZE, XE_CACHE_WB);
+ XE_PAGE_SIZE, pat_index);
xe_map_wr(xe, &bo->vmap, map_ofs + XE_PAGE_SIZE * level, u64,
entry | flags);
}
@@ -249,7 +250,7 @@ static int xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
/* Write PDE's that point to our BO. */
for (i = 0; i < num_entries - num_level; i++) {
entry = vm->pt_ops->pde_encode_bo(bo, i * XE_PAGE_SIZE,
- XE_CACHE_WB);
+ pat_index);
xe_map_wr(xe, &bo->vmap, map_ofs + XE_PAGE_SIZE +
(i + 1) * 8, u64, entry);
@@ -261,7 +262,7 @@ static int xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
level = 2;
ofs = map_ofs + XE_PAGE_SIZE * level + 256 * 8;
- flags = vm->pt_ops->pte_encode_addr(xe, 0, XE_CACHE_WB, level,
+ flags = vm->pt_ops->pte_encode_addr(xe, 0, pat_index, level,
true, 0);
/*
@@ -457,6 +458,7 @@ static void emit_pte(struct xe_migrate *m,
struct xe_res_cursor *cur,
u32 size, struct xe_bo *bo)
{
+ u16 pat_index = tile_to_xe(m->tile)->pat.idx[XE_CACHE_WB];
u32 ptes;
u64 ofs = at_pt * XE_PAGE_SIZE;
u64 cur_ofs;
@@ -500,7 +502,7 @@ static void emit_pte(struct xe_migrate *m,
}
addr = m->q->vm->pt_ops->pte_encode_addr(m->tile->xe,
- addr, XE_CACHE_WB,
+ addr, pat_index,
0, devmem, flags);
bb->cs[bb->len++] = lower_32_bits(addr);
bb->cs[bb->len++] = upper_32_bits(addr);
@@ -1219,6 +1221,7 @@ xe_migrate_update_pgtables(struct xe_migrate *m,
bool first_munmap_rebind = vma &&
vma->gpuva.flags & XE_VMA_FIRST_REBIND;
struct xe_exec_queue *q_override = !q ? m->q : q;
+ u16 pat_index = xe->pat.idx[XE_CACHE_WB];
/* Use the CPU if no in syncs and engine is idle */
if (no_in_syncs(syncs, num_syncs) && xe_exec_queue_is_idle(q_override)) {
@@ -1290,7 +1293,7 @@ xe_migrate_update_pgtables(struct xe_migrate *m,
xe_tile_assert(tile, pt_bo->size == SZ_4K);
- addr = vm->pt_ops->pte_encode_bo(pt_bo, 0, XE_CACHE_WB, 0);
+ addr = vm->pt_ops->pte_encode_bo(pt_bo, 0, pat_index, 0);
bb->cs[bb->len++] = lower_32_bits(addr);
bb->cs[bb->len++] = upper_32_bits(addr);
}
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 70a8bd3558c2..f7553a2415ac 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -50,6 +50,7 @@ static struct xe_pt *xe_pt_entry(struct xe_pt_dir *pt_dir, unsigned int index)
static u64 __xe_pt_empty_pte(struct xe_tile *tile, struct xe_vm *vm,
unsigned int level)
{
+ u16 pat_index = tile_to_xe(tile)->pat.idx[XE_CACHE_WB];
u8 id = tile->id;
if (!vm->scratch_bo[id])
@@ -57,9 +58,9 @@ static u64 __xe_pt_empty_pte(struct xe_tile *tile, struct xe_vm *vm,
if (level > 0)
return vm->pt_ops->pde_encode_bo(vm->scratch_pt[id][level - 1]->bo,
- 0, XE_CACHE_WB);
+ 0, pat_index);
- return vm->pt_ops->pte_encode_bo(vm->scratch_bo[id], 0, XE_CACHE_WB, 0);
+ return vm->pt_ops->pte_encode_bo(vm->scratch_bo[id], 0, pat_index, 0);
}
/**
@@ -510,6 +511,7 @@ xe_pt_stage_bind_entry(struct xe_ptw *parent, pgoff_t offset,
{
struct xe_pt_stage_bind_walk *xe_walk =
container_of(walk, typeof(*xe_walk), base);
+ u16 pat_index = tile_to_xe(xe_walk->tile)->pat.idx[xe_walk->cache];
struct xe_pt *xe_parent = container_of(parent, typeof(*xe_parent), base);
struct xe_vm *vm = xe_walk->vm;
struct xe_pt *xe_child;
@@ -526,7 +528,7 @@ xe_pt_stage_bind_entry(struct xe_ptw *parent, pgoff_t offset,
pte = vm->pt_ops->pte_encode_vma(is_null ? 0 :
xe_res_dma(curs) + xe_walk->dma_offset,
- xe_walk->vma, xe_walk->cache, level);
+ xe_walk->vma, pat_index, level);
pte |= xe_walk->default_pte;
/*
@@ -591,8 +593,7 @@ xe_pt_stage_bind_entry(struct xe_ptw *parent, pgoff_t offset,
xe_child->is_compact = true;
}
- pte = vm->pt_ops->pde_encode_bo(xe_child->bo, 0,
- xe_walk->cache) | flags;
+ pte = vm->pt_ops->pde_encode_bo(xe_child->bo, 0, pat_index) | flags;
ret = xe_pt_insert_entry(xe_walk, xe_parent, offset, xe_child,
pte);
}
diff --git a/drivers/gpu/drm/xe/xe_pt_types.h b/drivers/gpu/drm/xe/xe_pt_types.h
index bd6645295fe6..82cbf1ef8e57 100644
--- a/drivers/gpu/drm/xe/xe_pt_types.h
+++ b/drivers/gpu/drm/xe/xe_pt_types.h
@@ -38,14 +38,14 @@ struct xe_pt {
struct xe_pt_ops {
u64 (*pte_encode_bo)(struct xe_bo *bo, u64 bo_offset,
- enum xe_cache_level cache, u32 pt_level);
+ u16 pat_index, u32 pt_level);
u64 (*pte_encode_vma)(u64 pte, struct xe_vma *vma,
- enum xe_cache_level cache, u32 pt_level);
+ u16 pat_index, u32 pt_level);
u64 (*pte_encode_addr)(struct xe_device *xe, u64 addr,
- enum xe_cache_level cache,
+ u16 pat_index,
u32 pt_level, bool devmem, u64 flags);
u64 (*pde_encode_bo)(struct xe_bo *bo, u64 bo_offset,
- const enum xe_cache_level cache);
+ u16 pat_index);
};
struct xe_pt_entry {
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index ea17d026546c..d1ff9fadac53 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -1191,9 +1191,8 @@ static struct drm_gpuvm_ops gpuvm_ops = {
.op_alloc = xe_vm_op_alloc,
};
-static u64 pde_encode_cache(struct xe_device *xe, enum xe_cache_level cache)
+static u64 pde_encode_pat_index(struct xe_device *xe, u16 pat_index)
{
- u32 pat_index = xe->pat.idx[cache];
u64 pte = 0;
if (pat_index & BIT(0))
@@ -1205,9 +1204,8 @@ static u64 pde_encode_cache(struct xe_device *xe, enum xe_cache_level cache)
return pte;
}
-static u64 pte_encode_cache(struct xe_device *xe, enum xe_cache_level cache)
+static u64 pte_encode_pat_index(struct xe_device *xe, u16 pat_index)
{
- u32 pat_index = xe->pat.idx[cache];
u64 pte = 0;
if (pat_index & BIT(0))
@@ -1238,27 +1236,27 @@ static u64 pte_encode_ps(u32 pt_level)
}
static u64 xelp_pde_encode_bo(struct xe_bo *bo, u64 bo_offset,
- const enum xe_cache_level cache)
+ const u16 pat_index)
{
struct xe_device *xe = xe_bo_device(bo);
u64 pde;
pde = xe_bo_addr(bo, bo_offset, XE_PAGE_SIZE);
pde |= XE_PAGE_PRESENT | XE_PAGE_RW;
- pde |= pde_encode_cache(xe, cache);
+ pde |= pde_encode_pat_index(xe, pat_index);
return pde;
}
static u64 xelp_pte_encode_bo(struct xe_bo *bo, u64 bo_offset,
- enum xe_cache_level cache, u32 pt_level)
+ u16 pat_index, u32 pt_level)
{
struct xe_device *xe = xe_bo_device(bo);
u64 pte;
pte = xe_bo_addr(bo, bo_offset, XE_PAGE_SIZE);
pte |= XE_PAGE_PRESENT | XE_PAGE_RW;
- pte |= pte_encode_cache(xe, cache);
+ pte |= pte_encode_pat_index(xe, pat_index);
pte |= pte_encode_ps(pt_level);
if (xe_bo_is_vram(bo) || xe_bo_is_stolen_devmem(bo))
@@ -1268,7 +1266,7 @@ static u64 xelp_pte_encode_bo(struct xe_bo *bo, u64 bo_offset,
}
static u64 xelp_pte_encode_vma(u64 pte, struct xe_vma *vma,
- enum xe_cache_level cache, u32 pt_level)
+ u16 pat_index, u32 pt_level)
{
struct xe_device *xe = xe_vma_vm(vma)->xe;
@@ -1277,7 +1275,7 @@ static u64 xelp_pte_encode_vma(u64 pte, struct xe_vma *vma,
if (likely(!xe_vma_read_only(vma)))
pte |= XE_PAGE_RW;
- pte |= pte_encode_cache(xe, cache);
+ pte |= pte_encode_pat_index(xe, pat_index);
pte |= pte_encode_ps(pt_level);
if (unlikely(xe_vma_is_null(vma)))
@@ -1287,7 +1285,7 @@ static u64 xelp_pte_encode_vma(u64 pte, struct xe_vma *vma,
}
static u64 xelp_pte_encode_addr(struct xe_device *xe, u64 addr,
- enum xe_cache_level cache,
+ u16 pat_index,
u32 pt_level, bool devmem, u64 flags)
{
u64 pte;
@@ -1297,7 +1295,7 @@ static u64 xelp_pte_encode_addr(struct xe_device *xe, u64 addr,
pte = addr;
pte |= XE_PAGE_PRESENT | XE_PAGE_RW;
- pte |= pte_encode_cache(xe, cache);
+ pte |= pte_encode_pat_index(xe, pat_index);
pte |= pte_encode_ps(pt_level);
if (devmem)
@@ -1701,7 +1699,7 @@ struct xe_vm *xe_vm_lookup(struct xe_file *xef, u32 id)
u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_tile *tile)
{
return vm->pt_ops->pde_encode_bo(vm->pt_root[tile->id]->bo, 0,
- XE_CACHE_WB);
+ tile_to_xe(tile)->pat.idx[XE_CACHE_WB]);
}
static struct dma_fence *
--
2.41.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-xe] [PATCH v7 3/5] drm/xe/uapi: Add support for cache and coherency mode
2023-10-05 15:46 [Intel-xe] [PATCH v7 0/5] PAT and cache coherency support Matthew Auld
2023-10-05 15:46 ` [Intel-xe] [PATCH v7 1/5] drm/xe/pat: trim the xelp PAT table Matthew Auld
2023-10-05 15:46 ` [Intel-xe] [PATCH v7 2/5] drm/xe: directly use pat_index for pte_encode Matthew Auld
@ 2023-10-05 15:46 ` Matthew Auld
2023-10-05 15:46 ` [Intel-xe] [PATCH v7 4/5] drm/xe/pat: annotate pat_index with " Matthew Auld
` (4 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Matthew Auld @ 2023-10-05 15:46 UTC (permalink / raw)
To: intel-xe
Cc: Filip Hazubski, Lucas De Marchi, Carl Zhang, Effie Yu, Matt Roper
From: Pallavi Mishra <pallavi.mishra@intel.com>
Allow userspace to specify the CPU caching mode to use in addition to
coherency modes during object creation. Modify gem create handler and
introduce xe_bo_create_user to replace xe_bo_create. In a later patch we
will support setting the pat_index as part of vm_bind, where expectation
is that the coherency mode extracted from the pat_index must match the
one set at object creation.
v2
- s/smem_caching/smem_cpu_caching/ and
s/XE_GEM_CACHING/XE_GEM_CPU_CACHING/. (Matt Roper)
- Drop COH_2WAY and just use COH_NONE + COH_AT_LEAST_1WAY; KMD mostly
just cares that zeroing/swap-in can't be bypassed with the given
smem_caching mode. (Matt Roper)
- Fix broken range check for coh_mode and smem_cpu_caching and also
don't use constant value, but the already defined macros. (José)
- Prefer switch statement for smem_cpu_caching -> ttm_caching. (José)
- Add note in kernel-doc for dgpu and coherency modes for system
memory. (José)
v3 (José):
- Make sure to reject coh_mode == 0 for VRAM-only.
- Also make sure to actually pass along the (start, end) for
__xe_bo_create_locked.
v4
- Drop UC caching mode. Can be added back if we need it. (Matt Roper)
- s/smem_cpu_caching/cpu_caching. Idea is that VRAM is always WC, but
that is currently implicit and KMD controlled. Make it explicit in
the uapi with the limitation that it currently must be WC. For VRAM
+ SYS objects userspace must now select WC. (José)
- Make sure to initialize bo_flags. (José)
v5
- Make to align with the other uapi and prefix uapi constants with
DRM_ (José)
v6:
- Make it clear that zero cpu_caching is only allowed for kernel
objects. (José)
Testcase: igt@xe_mmap@cpu-caching-coh
Signed-off-by: Pallavi Mishra <pallavi.mishra@intel.com>
Co-developed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Filip Hazubski <filip.hazubski@intel.com>
Cc: Carl Zhang <carl.zhang@intel.com>
Cc: Effie Yu <effie.yu@intel.com>
Tested-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/xe/xe_bo.c | 115 ++++++++++++++++++++++++-------
drivers/gpu/drm/xe/xe_bo.h | 9 +--
drivers/gpu/drm/xe/xe_bo_types.h | 10 +++
drivers/gpu/drm/xe/xe_dma_buf.c | 5 +-
include/uapi/drm/xe_drm.h | 50 +++++++++++++-
5 files changed, 156 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index 61789c0e88fb..8ce7d16c918a 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -326,7 +326,7 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo,
struct xe_device *xe = xe_bo_device(bo);
struct xe_ttm_tt *tt;
unsigned long extra_pages;
- enum ttm_caching caching = ttm_cached;
+ enum ttm_caching caching;
int err;
tt = kzalloc(sizeof(*tt), GFP_KERNEL);
@@ -340,13 +340,24 @@ static struct ttm_tt *xe_ttm_tt_create(struct ttm_buffer_object *ttm_bo,
extra_pages = DIV_ROUND_UP(xe_device_ccs_bytes(xe, bo->size),
PAGE_SIZE);
+ switch (bo->cpu_caching) {
+ case DRM_XE_GEM_CPU_CACHING_WC:
+ caching = ttm_write_combined;
+ break;
+ default:
+ caching = ttm_cached;
+ break;
+ }
+
+ WARN_ON((bo->flags & XE_BO_CREATE_USER_BIT) && !bo->cpu_caching);
+
/*
* Display scanout is always non-coherent with the CPU cache.
*
* For Xe_LPG and beyond, PPGTT PTE lookups are also non-coherent and
* require a CPU:WC mapping.
*/
- if (bo->flags & XE_BO_SCANOUT_BIT ||
+ if ((!bo->cpu_caching && bo->flags & XE_BO_SCANOUT_BIT) ||
(xe->info.graphics_verx100 >= 1270 && bo->flags & XE_BO_PAGETABLE))
caching = ttm_write_combined;
@@ -1190,10 +1201,11 @@ void xe_bo_free(struct xe_bo *bo)
kfree(bo);
}
-struct xe_bo *__xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo,
- struct xe_tile *tile, struct dma_resv *resv,
- struct ttm_lru_bulk_move *bulk, size_t size,
- enum ttm_bo_type type, u32 flags)
+struct xe_bo *___xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo,
+ struct xe_tile *tile, struct dma_resv *resv,
+ struct ttm_lru_bulk_move *bulk, size_t size,
+ u16 cpu_caching, u16 coh_mode,
+ enum ttm_bo_type type, u32 flags)
{
struct ttm_operation_ctx ctx = {
.interruptible = true,
@@ -1231,6 +1243,8 @@ struct xe_bo *__xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo,
bo->tile = tile;
bo->size = size;
bo->flags = flags;
+ bo->cpu_caching = cpu_caching;
+ bo->coh_mode = coh_mode;
bo->ttm.base.funcs = &xe_gem_object_funcs;
bo->props.preferred_mem_class = XE_BO_PROPS_INVALID;
bo->props.preferred_gt = XE_BO_PROPS_INVALID;
@@ -1315,11 +1329,12 @@ static int __xe_bo_fixed_placement(struct xe_device *xe,
return 0;
}
-struct xe_bo *
-xe_bo_create_locked_range(struct xe_device *xe,
- struct xe_tile *tile, struct xe_vm *vm,
- size_t size, u64 start, u64 end,
- enum ttm_bo_type type, u32 flags)
+static struct xe_bo *
+__xe_bo_create_locked(struct xe_device *xe,
+ struct xe_tile *tile, struct xe_vm *vm,
+ size_t size, u64 start, u64 end,
+ u16 cpu_caching, u16 coh_mode,
+ enum ttm_bo_type type, u32 flags)
{
struct xe_bo *bo = NULL;
int err;
@@ -1340,11 +1355,12 @@ xe_bo_create_locked_range(struct xe_device *xe,
}
}
- bo = __xe_bo_create_locked(xe, bo, tile, vm ? &vm->resv : NULL,
- vm && !xe_vm_in_fault_mode(vm) &&
- flags & XE_BO_CREATE_USER_BIT ?
- &vm->lru_bulk_move : NULL, size,
- type, flags);
+ bo = ___xe_bo_create_locked(xe, bo, tile, vm ? &vm->resv : NULL,
+ vm && !xe_vm_in_fault_mode(vm) &&
+ flags & XE_BO_CREATE_USER_BIT ?
+ &vm->lru_bulk_move : NULL, size,
+ cpu_caching, coh_mode,
+ type, flags);
if (IS_ERR(bo))
return bo;
@@ -1377,11 +1393,35 @@ xe_bo_create_locked_range(struct xe_device *xe,
return ERR_PTR(err);
}
+struct xe_bo *
+xe_bo_create_locked_range(struct xe_device *xe,
+ struct xe_tile *tile, struct xe_vm *vm,
+ size_t size, u64 start, u64 end,
+ enum ttm_bo_type type, u32 flags)
+{
+ return __xe_bo_create_locked(xe, tile, vm, size, start, end, 0, 0, type, flags);
+}
+
struct xe_bo *xe_bo_create_locked(struct xe_device *xe, struct xe_tile *tile,
struct xe_vm *vm, size_t size,
enum ttm_bo_type type, u32 flags)
{
- return xe_bo_create_locked_range(xe, tile, vm, size, 0, ~0ULL, type, flags);
+ return __xe_bo_create_locked(xe, tile, vm, size, 0, ~0ULL, 0, 0, type, flags);
+}
+
+static struct xe_bo *xe_bo_create_user(struct xe_device *xe, struct xe_tile *tile,
+ struct xe_vm *vm, size_t size,
+ u16 cpu_caching, u16 coh_mode,
+ enum ttm_bo_type type,
+ u32 flags)
+{
+ struct xe_bo *bo = __xe_bo_create_locked(xe, tile, vm, size, 0, ~0ULL,
+ cpu_caching, coh_mode, type,
+ flags | XE_BO_CREATE_USER_BIT);
+ if (!IS_ERR(bo))
+ xe_bo_unlock_vm_held(bo);
+
+ return bo;
}
struct xe_bo *xe_bo_create(struct xe_device *xe, struct xe_tile *tile,
@@ -1764,11 +1804,11 @@ int xe_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_xe_gem_create *args = data;
struct xe_vm *vm = NULL;
struct xe_bo *bo;
- unsigned int bo_flags = XE_BO_CREATE_USER_BIT;
+ unsigned int bo_flags;
u32 handle;
int err;
- if (XE_IOCTL_DBG(xe, args->extensions) || XE_IOCTL_DBG(xe, args->pad) ||
+ if (XE_IOCTL_DBG(xe, args->extensions) ||
XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
return -EINVAL;
@@ -1795,6 +1835,7 @@ int xe_gem_create_ioctl(struct drm_device *dev, void *data,
if (XE_IOCTL_DBG(xe, args->size & ~PAGE_MASK))
return -EINVAL;
+ bo_flags = 0;
if (args->flags & XE_GEM_CREATE_FLAG_DEFER_BACKING)
bo_flags |= XE_BO_DEFER_BACKING;
@@ -1810,6 +1851,26 @@ int xe_gem_create_ioctl(struct drm_device *dev, void *data,
bo_flags |= XE_BO_NEEDS_CPU_ACCESS;
}
+ if (XE_IOCTL_DBG(xe, !args->coh_mode ||
+ args->coh_mode > DRM_XE_GEM_COH_AT_LEAST_1WAY))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, !args->cpu_caching ||
+ args->cpu_caching > DRM_XE_GEM_CPU_CACHING_WC))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, bo_flags & XE_BO_CREATE_VRAM_MASK &&
+ args->cpu_caching != DRM_XE_GEM_CPU_CACHING_WC))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, bo_flags & XE_BO_SCANOUT_BIT &&
+ args->cpu_caching == DRM_XE_GEM_CPU_CACHING_WB))
+ return -EINVAL;
+
+ if (XE_IOCTL_DBG(xe, args->coh_mode == DRM_XE_GEM_COH_NONE &&
+ args->cpu_caching == DRM_XE_GEM_CPU_CACHING_WB))
+ return -EINVAL;
+
if (args->vm_id) {
vm = xe_vm_lookup(xef, args->vm_id);
if (XE_IOCTL_DBG(xe, !vm))
@@ -1821,8 +1882,10 @@ int xe_gem_create_ioctl(struct drm_device *dev, void *data,
}
}
- bo = xe_bo_create(xe, NULL, vm, args->size, ttm_bo_type_device,
- bo_flags);
+ bo = xe_bo_create_user(xe, NULL, vm, args->size,
+ args->cpu_caching, args->coh_mode,
+ ttm_bo_type_device,
+ bo_flags);
if (IS_ERR(bo)) {
err = PTR_ERR(bo);
goto out_vm;
@@ -2114,10 +2177,12 @@ int xe_bo_dumb_create(struct drm_file *file_priv,
args->size = ALIGN(mul_u32_u32(args->pitch, args->height),
page_size);
- bo = xe_bo_create(xe, NULL, NULL, args->size, ttm_bo_type_device,
- XE_BO_CREATE_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) |
- XE_BO_CREATE_USER_BIT | XE_BO_SCANOUT_BIT |
- XE_BO_NEEDS_CPU_ACCESS);
+ bo = xe_bo_create_user(xe, NULL, NULL, args->size,
+ DRM_XE_GEM_CPU_CACHING_WC, DRM_XE_GEM_COH_NONE,
+ ttm_bo_type_device,
+ XE_BO_CREATE_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) |
+ XE_BO_CREATE_USER_BIT | XE_BO_SCANOUT_BIT |
+ XE_BO_NEEDS_CPU_ACCESS);
if (IS_ERR(bo))
return PTR_ERR(bo);
diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
index e5e8173433c3..41e91b5ae2d9 100644
--- a/drivers/gpu/drm/xe/xe_bo.h
+++ b/drivers/gpu/drm/xe/xe_bo.h
@@ -83,10 +83,11 @@ struct sg_table;
struct xe_bo *xe_bo_alloc(void);
void xe_bo_free(struct xe_bo *bo);
-struct xe_bo *__xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo,
- struct xe_tile *tile, struct dma_resv *resv,
- struct ttm_lru_bulk_move *bulk, size_t size,
- enum ttm_bo_type type, u32 flags);
+struct xe_bo *___xe_bo_create_locked(struct xe_device *xe, struct xe_bo *bo,
+ struct xe_tile *tile, struct dma_resv *resv,
+ struct ttm_lru_bulk_move *bulk, size_t size,
+ u16 cpu_caching, u16 coh_mode,
+ enum ttm_bo_type type, u32 flags);
struct xe_bo *
xe_bo_create_locked_range(struct xe_device *xe,
struct xe_tile *tile, struct xe_vm *vm,
diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h
index 051fe990c133..56f7f9a4975f 100644
--- a/drivers/gpu/drm/xe/xe_bo_types.h
+++ b/drivers/gpu/drm/xe/xe_bo_types.h
@@ -76,6 +76,16 @@ struct xe_bo {
struct llist_node freed;
/** @created: Whether the bo has passed initial creation */
bool created;
+ /**
+ * @coh_mode: Coherency setting. Currently only used for userspace
+ * objects.
+ */
+ u16 coh_mode;
+ /**
+ * @cpu_caching: CPU caching mode. Currently only used for userspace
+ * objects.
+ */
+ u16 cpu_caching;
};
#define intel_bo_to_drm_bo(bo) (&(bo)->ttm.base)
diff --git a/drivers/gpu/drm/xe/xe_dma_buf.c b/drivers/gpu/drm/xe/xe_dma_buf.c
index cfde3be3b0dc..9da5cffeef13 100644
--- a/drivers/gpu/drm/xe/xe_dma_buf.c
+++ b/drivers/gpu/drm/xe/xe_dma_buf.c
@@ -214,8 +214,9 @@ xe_dma_buf_init_obj(struct drm_device *dev, struct xe_bo *storage,
int ret;
dma_resv_lock(resv, NULL);
- bo = __xe_bo_create_locked(xe, storage, NULL, resv, NULL, dma_buf->size,
- ttm_bo_type_sg, XE_BO_CREATE_SYSTEM_BIT);
+ bo = ___xe_bo_create_locked(xe, storage, NULL, resv, NULL, dma_buf->size,
+ 0, 0, /* Will require 1way or 2way for vm_bind */
+ ttm_bo_type_sg, XE_BO_CREATE_SYSTEM_BIT);
if (IS_ERR(bo)) {
ret = PTR_ERR(bo);
goto error;
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index d48d8e3c898c..ec4cdbc8d2bd 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -456,8 +456,54 @@ struct drm_xe_gem_create {
*/
__u32 handle;
- /** @pad: MBZ */
- __u32 pad;
+ /**
+ * @coh_mode: The coherency mode for this object. This will limit the
+ * possible @cpu_caching values.
+ *
+ * Supported values:
+ *
+ * DRM_XE_GEM_COH_NONE: GPU access is assumed to be not coherent with
+ * CPU. CPU caches are not snooped.
+ *
+ * DRM_XE_GEM_COH_AT_LEAST_1WAY:
+ *
+ * CPU-GPU coherency must be at least 1WAY.
+ *
+ * If 1WAY then GPU access is coherent with CPU (CPU caches are snooped)
+ * until GPU acquires. The acquire by the GPU is not tracked by CPU
+ * caches.
+ *
+ * If 2WAY then should be fully coherent between GPU and CPU. Fully
+ * tracked by CPU caches. Both CPU and GPU caches are snooped.
+ *
+ * Note: On dgpu the GPU device never caches system memory. The device
+ * should be thought of as always 1WAY coherent, with the addition that
+ * the GPU never caches system memory. At least on current dgpu HW there
+ * is no way to turn off snooping so likely the different coherency
+ * modes of the pat_index make no difference for system memory.
+ */
+#define DRM_XE_GEM_COH_NONE 1
+#define DRM_XE_GEM_COH_AT_LEAST_1WAY 2
+ __u16 coh_mode;
+
+ /**
+ * @cpu_caching: The CPU caching mode to select for this object. If
+ * mmaping the object the mode selected here will also be used.
+ *
+ * Supported values:
+ *
+ * DRM_XE_GEM_CPU_CACHING_WB: Allocate the pages with write-back caching.
+ * On iGPU this can't be used for scanout surfaces. The @coh_mode must
+ * be DRM_XE_GEM_COH_AT_LEAST_1WAY. Currently not allowed for objects placed
+ * in VRAM.
+ *
+ * DRM_XE_GEM_CPU_CACHING_WC: Allocate the pages as write-combined. This is
+ * uncached. Any @coh_mode is permitted. Scanout surfaces should likely
+ * use this. All objects that can be placed in VRAM must use this.
+ */
+#define DRM_XE_GEM_CPU_CACHING_WB 1
+#define DRM_XE_GEM_CPU_CACHING_WC 2
+ __u16 cpu_caching;
/** @reserved: Reserved */
__u64 reserved[2];
--
2.41.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-xe] [PATCH v7 4/5] drm/xe/pat: annotate pat_index with coherency mode
2023-10-05 15:46 [Intel-xe] [PATCH v7 0/5] PAT and cache coherency support Matthew Auld
` (2 preceding siblings ...)
2023-10-05 15:46 ` [Intel-xe] [PATCH v7 3/5] drm/xe/uapi: Add support for cache and coherency mode Matthew Auld
@ 2023-10-05 15:46 ` Matthew Auld
2023-10-05 15:46 ` [Intel-xe] [PATCH v7 5/5] drm/xe/uapi: support pat_index selection with vm_bind Matthew Auld
` (3 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Matthew Auld @ 2023-10-05 15:46 UTC (permalink / raw)
To: intel-xe
Cc: Filip Hazubski, Lucas De Marchi, Carl Zhang, Effie Yu, Matt Roper
Future uapi needs to give userspace the ability to select the pat_index
for a given vm_bind. However we need to be able to extract the coherency
mode from the provided pat_index to ensure it matches the coherency mode
set at object creation. There are various security reasons for why this
matters. However the pat_index itself is very platform specific, so
seems reasonable to annotate each platform definition of the pat table.
On some older platforms there is no explicit coherency mode, so we just
pick whatever makes sense.
v2:
- Simplify with COH_AT_LEAST_1_WAY
- Add some kernel-doc
v3 (Matt Roper):
- Some small tweaks
v4:
- Rebase
Bspec: 45101, 44235 #xe
Bspec: 70552, 71582, 59400 #xe2
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Pallavi Mishra <pallavi.mishra@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Filip Hazubski <filip.hazubski@intel.com>
Cc: Carl Zhang <carl.zhang@intel.com>
Cc: Effie Yu <effie.yu@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Pallavi Mishra <pallavi.mishra@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 2 +-
drivers/gpu/drm/xe/xe_pat.c | 64 +++++++++++++++++-----------
drivers/gpu/drm/xe/xe_pat.h | 28 ++++++++++++
3 files changed, 67 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index fd87fbb6306f..11214c274394 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -338,7 +338,7 @@ struct xe_device {
/** Internal operations to abstract platforms */
const struct xe_pat_ops *ops;
/** PAT table to program in the HW */
- const u32 *table;
+ const struct xe_pat_table_entry *table;
/** Number of PAT entries */
int n_entries;
u32 idx[__XE_CACHE_LEVEL_COUNT];
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 36b79d675e54..3e9d253ac1ff 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -5,6 +5,8 @@
#include "xe_pat.h"
+#include <drm/xe_drm.h>
+
#include "regs/xe_reg_defs.h"
#include "xe_gt.h"
#include "xe_gt_mcr.h"
@@ -33,51 +35,60 @@
#define XELP_PAT_UC REG_FIELD_PREP(XELP_MEM_TYPE_MASK, 0)
struct xe_pat_ops {
- void (*program_graphics)(struct xe_gt *gt, const u32 table[], int n_entries);
- void (*program_media)(struct xe_gt *gt, const u32 table[], int n_entries);
+ void (*program_graphics)(struct xe_gt *gt, const struct xe_pat_table_entry table[],
+ int n_entries);
+ void (*program_media)(struct xe_gt *gt, const struct xe_pat_table_entry table[],
+ int n_entries);
};
-static const u32 xelp_pat_table[] = {
- [0] = XELP_PAT_WB,
- [1] = XELP_PAT_WC,
- [2] = XELP_PAT_WT,
- [3] = XELP_PAT_UC,
+static const struct xe_pat_table_entry xelp_pat_table[] = {
+ [0] = { XELP_PAT_WB, DRM_XE_GEM_COH_AT_LEAST_1WAY },
+ [1] = { XELP_PAT_WC, DRM_XE_GEM_COH_NONE },
+ [2] = { XELP_PAT_WT, DRM_XE_GEM_COH_NONE },
+ [3] = { XELP_PAT_UC, DRM_XE_GEM_COH_NONE },
};
-static const u32 xehpc_pat_table[] = {
- [0] = XELP_PAT_UC,
- [1] = XELP_PAT_WC,
- [2] = XELP_PAT_WT,
- [3] = XELP_PAT_WB,
- [4] = XEHPC_PAT_CLOS(1) | XELP_PAT_WT,
- [5] = XEHPC_PAT_CLOS(1) | XELP_PAT_WB,
- [6] = XEHPC_PAT_CLOS(2) | XELP_PAT_WT,
- [7] = XEHPC_PAT_CLOS(2) | XELP_PAT_WB,
+static const struct xe_pat_table_entry xehpc_pat_table[] = {
+ [0] = { XELP_PAT_UC, DRM_XE_GEM_COH_NONE },
+ [1] = { XELP_PAT_WC, DRM_XE_GEM_COH_NONE },
+ [2] = { XELP_PAT_WT, DRM_XE_GEM_COH_NONE },
+ [3] = { XELP_PAT_WB, DRM_XE_GEM_COH_AT_LEAST_1WAY },
+ [4] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WT, DRM_XE_GEM_COH_NONE },
+ [5] = { XEHPC_PAT_CLOS(1) | XELP_PAT_WB, DRM_XE_GEM_COH_AT_LEAST_1WAY },
+ [6] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WT, DRM_XE_GEM_COH_NONE },
+ [7] = { XEHPC_PAT_CLOS(2) | XELP_PAT_WB, DRM_XE_GEM_COH_AT_LEAST_1WAY },
};
-static const u32 xelpg_pat_table[] = {
- [0] = XELPG_PAT_0_WB,
- [1] = XELPG_PAT_1_WT,
- [2] = XELPG_PAT_3_UC,
- [3] = XELPG_PAT_0_WB | XELPG_2_COH_1W,
- [4] = XELPG_PAT_0_WB | XELPG_3_COH_2W,
+static const struct xe_pat_table_entry xelpg_pat_table[] = {
+ [0] = { XELPG_PAT_0_WB, DRM_XE_GEM_COH_NONE },
+ [1] = { XELPG_PAT_1_WT, DRM_XE_GEM_COH_NONE },
+ [2] = { XELPG_PAT_3_UC, DRM_XE_GEM_COH_NONE },
+ [3] = { XELPG_PAT_0_WB | XELPG_2_COH_1W, DRM_XE_GEM_COH_AT_LEAST_1WAY },
+ [4] = { XELPG_PAT_0_WB | XELPG_3_COH_2W, DRM_XE_GEM_COH_AT_LEAST_1WAY },
};
-static void program_pat(struct xe_gt *gt, const u32 table[], int n_entries)
+u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index)
+{
+ WARN_ON(pat_index >= xe->pat.n_entries);
+ return xe->pat.table[pat_index].coh_mode;
+}
+
+static void program_pat(struct xe_gt *gt, const struct xe_pat_table_entry table[], int n_entries)
{
for (int i = 0; i < n_entries; i++) {
struct xe_reg reg = XE_REG(_PAT_INDEX(i));
- xe_mmio_write32(gt, reg, table[i]);
+ xe_mmio_write32(gt, reg, table[i].value);
}
}
-static void program_pat_mcr(struct xe_gt *gt, const u32 table[], int n_entries)
+static void program_pat_mcr(struct xe_gt *gt, const struct xe_pat_table_entry table[],
+ int n_entries)
{
for (int i = 0; i < n_entries; i++) {
struct xe_reg_mcr reg_mcr = XE_REG_MCR(_PAT_INDEX(i));
- xe_gt_mcr_multicast_write(gt, reg_mcr, table[i]);
+ xe_gt_mcr_multicast_write(gt, reg_mcr, table[i].value);
}
}
@@ -126,6 +137,7 @@ void xe_pat_init_early(struct xe_device *xe)
xe->pat.idx[XE_CACHE_WT] = 2;
xe->pat.idx[XE_CACHE_WB] = 0;
} else if (GRAPHICS_VERx100(xe) <= 1210) {
+ WARN_ON_ONCE(!IS_DGFX(xe) && !xe->info.has_llc);
xe->pat.ops = &xelp_pat_ops;
xe->pat.table = xelp_pat_table;
xe->pat.n_entries = ARRAY_SIZE(xelp_pat_table);
diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h
index 168e80e63809..a4fe9d5466bc 100644
--- a/drivers/gpu/drm/xe/xe_pat.h
+++ b/drivers/gpu/drm/xe/xe_pat.h
@@ -6,9 +6,29 @@
#ifndef _XE_PAT_H_
#define _XE_PAT_H_
+#include <linux/types.h>
+
struct xe_gt;
struct xe_device;
+/**
+ * struct xe_pat_table_entry - The pat_index encoding and other meta information.
+ */
+struct xe_pat_table_entry {
+ /**
+ * @value: The platform specific value encoding the various memory
+ * attributes (this maps to some fixed pat_index). So things like
+ * caching, coherency, compression etc can be encoded here.
+ */
+ u32 value;
+
+ /**
+ * @coh_mode: The GPU coherency mode that @value maps to. Either
+ * DRM_XE_GEM_COH_NONE or DRM_XE_GEM_COH_AT_LEAST_1WAY.
+ */
+ u16 coh_mode;
+};
+
/**
* xe_pat_init_early - SW initialization, setting up data based on device
* @xe: xe device
@@ -21,4 +41,12 @@ void xe_pat_init_early(struct xe_device *xe);
*/
void xe_pat_init(struct xe_gt *gt);
+/**
+ * xe_pat_index_get_coh_mode - Extract the coherency mode for the given
+ * pat_index.
+ * @xe: xe device
+ * @pat_index: The pat_index to query
+ */
+u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index);
+
#endif
--
2.41.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-xe] [PATCH v7 5/5] drm/xe/uapi: support pat_index selection with vm_bind
2023-10-05 15:46 [Intel-xe] [PATCH v7 0/5] PAT and cache coherency support Matthew Auld
` (3 preceding siblings ...)
2023-10-05 15:46 ` [Intel-xe] [PATCH v7 4/5] drm/xe/pat: annotate pat_index with " Matthew Auld
@ 2023-10-05 15:46 ` Matthew Auld
2023-10-05 19:34 ` [Intel-xe] ✓ CI.Patch_applied: success for PAT and cache coherency support (rev9) Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 9+ messages in thread
From: Matthew Auld @ 2023-10-05 15:46 UTC (permalink / raw)
To: intel-xe
Cc: Filip Hazubski, Lucas De Marchi, Carl Zhang, Effie Yu, Matt Roper
Allow userspace to directly control the pat_index for a given vm
binding. This should allow directly controlling the coherency, caching
and potentially other stuff in the future for the ppGTT binding.
The exact meaning behind the pat_index is very platform specific (see
BSpec or PRMs) but effectively maps to some predefined memory
attributes. From the KMD pov we only care about the coherency that is
provided by the pat_index, which falls into either NONE, 1WAY or 2WAY.
The vm_bind coherency mode for the given pat_index needs to be at least
as coherent as the coh_mode that was set at object creation. For
platforms that lack the explicit coherency mode, we treat UC/WT/WC as
NONE and WB as AT_LEAST_1WAY.
For userptr mappings we lack a corresponding gem object, so the expected
coherency mode is instead implicit and must fall into either 1WAY or
2WAY. Trying to use NONE will be rejected by the kernel. For imported
dma-buf (from a different device) the coherency mode is also implicit
and must also be either 1WAY or 2WAY i.e AT_LEAST_1WAY.
v2:
- Undefined coh_mode(pat_index) can now be treated as programmer
error. (Matt Roper)
- We now allow gem_create.coh_mode <= coh_mode(pat_index), rather than
having to match exactly. This ensures imported dma-buf can always
just use 1way (or even 2way), now that we also bundle 1way/2way into
at_least_1way. We still require 1way/2way for external dma-buf, but
the policy can now be the same for self-import, if desired.
- Use u16 for pat_index in uapi. u32 is massive overkill. (José)
- Move as much of the pat_index validation as we can into
vm_bind_ioctl_check_args. (José)
v3 (Matt Roper):
- Split the pte_encode() refactoring into separate patch.
v4:
- Rebase
Testcase: igt@xe_pat
Bspec: 45101, 44235 #xe
Bspec: 70552, 71582, 59400 #xe2
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Pallavi Mishra <pallavi.mishra@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Filip Hazubski <filip.hazubski@intel.com>
Cc: Carl Zhang <carl.zhang@intel.com>
Cc: Effie Yu <effie.yu@intel.com>
Tested-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/xe/xe_pt.c | 11 ++----
drivers/gpu/drm/xe/xe_vm.c | 61 +++++++++++++++++++++++++++-----
drivers/gpu/drm/xe/xe_vm_types.h | 7 ++++
include/uapi/drm/xe_drm.h | 43 +++++++++++++++++++++-
4 files changed, 104 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index f7553a2415ac..a8a3e91414a2 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -290,8 +290,6 @@ struct xe_pt_stage_bind_walk {
struct xe_vm *vm;
/** @tile: The tile we're building for. */
struct xe_tile *tile;
- /** @cache: Desired cache level for the ptes */
- enum xe_cache_level cache;
/** @default_pte: PTE flag only template. No address is associated */
u64 default_pte;
/** @dma_offset: DMA offset to add to the PTE. */
@@ -511,7 +509,7 @@ xe_pt_stage_bind_entry(struct xe_ptw *parent, pgoff_t offset,
{
struct xe_pt_stage_bind_walk *xe_walk =
container_of(walk, typeof(*xe_walk), base);
- u16 pat_index = tile_to_xe(xe_walk->tile)->pat.idx[xe_walk->cache];
+ u16 pat_index = xe_walk->vma->pat_index;
struct xe_pt *xe_parent = container_of(parent, typeof(*xe_parent), base);
struct xe_vm *vm = xe_walk->vm;
struct xe_pt *xe_child;
@@ -654,13 +652,8 @@ xe_pt_stage_bind(struct xe_tile *tile, struct xe_vma *vma,
if (vma && vma->gpuva.flags & XE_VMA_ATOMIC_PTE_BIT)
xe_walk.default_pte |= XE_USM_PPGTT_PTE_AE;
xe_walk.dma_offset = vram_region_gpu_offset(bo->ttm.resource);
- xe_walk.cache = XE_CACHE_WB;
- } else {
- if (!xe_vma_has_no_bo(vma) && bo->flags & XE_BO_SCANOUT_BIT)
- xe_walk.cache = XE_CACHE_WT;
- else
- xe_walk.cache = XE_CACHE_WB;
}
+
if (!xe_vma_has_no_bo(vma) && xe_bo_is_stolen(bo))
xe_walk.dma_offset = xe_ttm_stolen_gpu_offset(xe_bo_device(bo));
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index d1ff9fadac53..3c40a9a6763c 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -6,6 +6,7 @@
#include "xe_vm.h"
#include <linux/dma-fence-array.h>
+#include <linux/nospec.h>
#include <drm/drm_exec.h>
#include <drm/drm_print.h>
@@ -25,6 +26,7 @@
#include "xe_gt_pagefault.h"
#include "xe_gt_tlb_invalidation.h"
#include "xe_migrate.h"
+#include "xe_pat.h"
#include "xe_pm.h"
#include "xe_preempt_fence.h"
#include "xe_pt.h"
@@ -858,7 +860,8 @@ static struct xe_vma *xe_vma_create(struct xe_vm *vm,
u64 start, u64 end,
bool read_only,
bool is_null,
- u8 tile_mask)
+ u8 tile_mask,
+ u16 pat_index)
{
struct xe_vma *vma;
struct xe_tile *tile;
@@ -900,6 +903,8 @@ static struct xe_vma *xe_vma_create(struct xe_vm *vm,
if (GRAPHICS_VER(vm->xe) >= 20 || vm->xe->info.platform == XE_PVC)
vma->gpuva.flags |= XE_VMA_ATOMIC_PTE_BIT;
+ vma->pat_index = pat_index;
+
if (bo) {
xe_bo_assert_held(bo);
@@ -2390,7 +2395,7 @@ static void print_op(struct xe_device *xe, struct drm_gpuva_op *op)
static struct drm_gpuva_ops *
vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_bo *bo,
u64 bo_offset_or_userptr, u64 addr, u64 range,
- u32 operation, u8 tile_mask, u32 region)
+ u32 operation, u8 tile_mask, u32 region, u16 pat_index)
{
struct drm_gem_object *obj = bo ? &bo->ttm.base : NULL;
struct drm_gpuva_ops *ops;
@@ -2417,6 +2422,7 @@ vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_bo *bo,
struct xe_vma_op *op = gpuva_op_to_vma_op(__op);
op->tile_mask = tile_mask;
+ op->pat_index = pat_index;
op->map.immediate =
operation & XE_VM_BIND_FLAG_IMMEDIATE;
op->map.read_only =
@@ -2444,6 +2450,7 @@ vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_bo *bo,
struct xe_vma_op *op = gpuva_op_to_vma_op(__op);
op->tile_mask = tile_mask;
+ op->pat_index = pat_index;
op->prefetch.region = region;
}
break;
@@ -2486,7 +2493,8 @@ vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_bo *bo,
}
static struct xe_vma *new_vma(struct xe_vm *vm, struct drm_gpuva_op_map *op,
- u8 tile_mask, bool read_only, bool is_null)
+ u8 tile_mask, bool read_only, bool is_null,
+ u16 pat_index)
{
struct xe_bo *bo = op->gem.obj ? gem_to_xe_bo(op->gem.obj) : NULL;
struct xe_vma *vma;
@@ -2502,7 +2510,7 @@ static struct xe_vma *new_vma(struct xe_vm *vm, struct drm_gpuva_op_map *op,
vma = xe_vma_create(vm, bo, op->gem.offset,
op->va.addr, op->va.addr +
op->va.range - 1, read_only, is_null,
- tile_mask);
+ tile_mask, pat_index);
if (bo)
xe_bo_unlock(bo);
@@ -2659,7 +2667,7 @@ static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_exec_queue *q,
vma = new_vma(vm, &op->base.map,
op->tile_mask, op->map.read_only,
- op->map.is_null);
+ op->map.is_null, op->pat_index);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
goto free_fence;
@@ -2687,7 +2695,7 @@ static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_exec_queue *q,
vma = new_vma(vm, op->base.remap.prev,
op->tile_mask, read_only,
- is_null);
+ is_null, op->pat_index);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
goto free_fence;
@@ -2723,7 +2731,7 @@ static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_exec_queue *q,
vma = new_vma(vm, op->base.remap.next,
op->tile_mask, read_only,
- is_null);
+ is_null, op->pat_index);
if (IS_ERR(vma)) {
err = PTR_ERR(vma);
goto free_fence;
@@ -3235,7 +3243,22 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe,
u32 obj = (*bind_ops)[i].obj;
u64 obj_offset = (*bind_ops)[i].obj_offset;
u32 region = (*bind_ops)[i].region;
+ u16 pat_index = (*bind_ops)[i].pat_index;
bool is_null = op & XE_VM_BIND_FLAG_NULL;
+ u16 coh_mode;
+
+ if (XE_IOCTL_DBG(xe, pat_index >= xe->pat.n_entries)) {
+ err = -EINVAL;
+ goto free_bind_ops;
+ }
+
+ pat_index = array_index_nospec(pat_index, xe->pat.n_entries);
+ (*bind_ops)[i].pat_index = pat_index;
+ coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
+ if (XE_WARN_ON(!coh_mode || coh_mode > DRM_XE_GEM_COH_AT_LEAST_1WAY)) {
+ err = -EINVAL;
+ goto free_bind_ops;
+ }
if (i == 0) {
*async = !!(op & XE_VM_BIND_FLAG_ASYNC);
@@ -3277,6 +3300,8 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe,
VM_BIND_OP(op) == XE_VM_BIND_OP_UNMAP_ALL) ||
XE_IOCTL_DBG(xe, obj &&
VM_BIND_OP(op) == XE_VM_BIND_OP_MAP_USERPTR) ||
+ XE_IOCTL_DBG(xe, coh_mode == DRM_XE_GEM_COH_NONE &&
+ VM_BIND_OP(op) == XE_VM_BIND_OP_MAP_USERPTR) ||
XE_IOCTL_DBG(xe, obj &&
VM_BIND_OP(op) == XE_VM_BIND_OP_PREFETCH) ||
XE_IOCTL_DBG(xe, region &&
@@ -3425,6 +3450,8 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
u64 addr = bind_ops[i].addr;
u32 obj = bind_ops[i].obj;
u64 obj_offset = bind_ops[i].obj_offset;
+ u16 pat_index = bind_ops[i].pat_index;
+ u16 coh_mode;
if (!obj)
continue;
@@ -3452,6 +3479,23 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
goto put_obj;
}
}
+
+ coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
+ if (bos[i]->coh_mode) {
+ if (XE_IOCTL_DBG(xe, coh_mode < bos[i]->coh_mode)) {
+ err = -EINVAL;
+ goto put_obj;
+ }
+ } else if (XE_IOCTL_DBG(xe, coh_mode == DRM_XE_GEM_COH_NONE)) {
+ /*
+ * Imported dma-buf from a different device should
+ * require 1way or 2way coherency since we don't know
+ * how it was mapped on the CPU. Just assume is it
+ * potentially cached on CPU side.
+ */
+ err = -EINVAL;
+ goto put_obj;
+ }
}
if (args->num_syncs) {
@@ -3489,10 +3533,11 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
u64 obj_offset = bind_ops[i].obj_offset;
u8 tile_mask = bind_ops[i].tile_mask;
u32 region = bind_ops[i].region;
+ u16 pat_index = bind_ops[i].pat_index;
ops[i] = vm_bind_ioctl_ops_create(vm, bos[i], obj_offset,
addr, range, op, tile_mask,
- region);
+ region, pat_index);
if (IS_ERR(ops[i])) {
err = PTR_ERR(ops[i]);
ops[i] = NULL;
diff --git a/drivers/gpu/drm/xe/xe_vm_types.h b/drivers/gpu/drm/xe/xe_vm_types.h
index da5e6cb6f094..734585200701 100644
--- a/drivers/gpu/drm/xe/xe_vm_types.h
+++ b/drivers/gpu/drm/xe/xe_vm_types.h
@@ -111,6 +111,11 @@ struct xe_vma {
*/
u8 tile_present;
+ /**
+ * @pat_index: The pat index to use when encoding the PTEs for this vma.
+ */
+ u16 pat_index;
+
struct {
struct list_head rebind_link;
} notifier;
@@ -418,6 +423,8 @@ struct xe_vma_op {
struct async_op_fence *fence;
/** @tile_mask: gt mask for this operation */
u8 tile_mask;
+ /** @pat_index: The pat index to use for this operation. */
+ u16 pat_index;
/** @flags: operation flags */
enum xe_vma_op_flags flags;
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index ec4cdbc8d2bd..ef71007c244b 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -598,8 +598,49 @@ struct drm_xe_vm_bind_op {
*/
__u32 obj;
+ /**
+ * @pat_index: The platform defined @pat_index to use for this mapping.
+ * The index basically maps to some predefined memory attributes,
+ * including things like caching, coherency, compression etc. The exact
+ * meaning of the pat_index is platform specific and defined in the
+ * Bspec and PRMs. When the KMD sets up the binding the index here is
+ * encoded into the ppGTT PTE.
+ *
+ * For coherency the @pat_index needs to be least as coherent as
+ * drm_xe_gem_create.coh_mode. i.e coh_mode(pat_index) >=
+ * drm_xe_gem_create.coh_mode. The KMD will extract the coherency mode
+ * from the @pat_index and reject if there is a mismatch (see note below
+ * for pre-MTL platforms).
+ *
+ * Note: On pre-MTL platforms there is only a caching mode and no
+ * explicit coherency mode, but on such hardware there is always a
+ * shared-LLC (or is dgpu) so all GT memory accesses are coherent with
+ * CPU caches even with the caching mode set as uncached. It's only the
+ * display engine that is incoherent (on dgpu it must be in VRAM which
+ * is always mapped as WC on the CPU). However to keep the uapi somewhat
+ * consistent with newer platforms the KMD groups the different cache
+ * levels into the following coherency buckets on all pre-MTL platforms:
+ *
+ * ppGTT UC -> DRM_XE_GEM_COH_NONE
+ * ppGTT WC -> DRM_XE_GEM_COH_NONE
+ * ppGTT WT -> DRM_XE_GEM_COH_NONE
+ * ppGTT WB -> DRM_XE_GEM_COH_AT_LEAST_1WAY
+ *
+ * In practice UC/WC/WT should only ever used for scanout surfaces on
+ * such platforms (or perhaps in general for dma-buf if shared with
+ * another device) since it is only the display engine that is actually
+ * incoherent. Everything else should typically use WB given that we
+ * have a shared-LLC. On MTL+ this completely changes and the HW
+ * defines the coherency mode as part of the @pat_index, where
+ * incoherent GT access is possible.
+ *
+ * Note: For userptr and externally imported dma-buf the kernel expects
+ * either 1WAY or 2WAY for the @pat_index.
+ */
+ __u16 pat_index;
+
/** @pad: MBZ */
- __u32 pad;
+ __u16 pad;
union {
/**
--
2.41.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-xe] ✓ CI.Patch_applied: success for PAT and cache coherency support (rev9)
2023-10-05 15:46 [Intel-xe] [PATCH v7 0/5] PAT and cache coherency support Matthew Auld
` (4 preceding siblings ...)
2023-10-05 15:46 ` [Intel-xe] [PATCH v7 5/5] drm/xe/uapi: support pat_index selection with vm_bind Matthew Auld
@ 2023-10-05 19:34 ` Patchwork
2023-10-05 19:34 ` [Intel-xe] ✓ CI.checkpatch: " Patchwork
2023-10-05 19:35 ` [Intel-xe] ✓ CI.KUnit: " Patchwork
7 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2023-10-05 19:34 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-xe
== Series Details ==
Series: PAT and cache coherency support (rev9)
URL : https://patchwork.freedesktop.org/series/123027/
State : success
== Summary ==
=== Applying kernel patches on branch 'drm-xe-next' with base: ===
Base commit: be79dc250 fixup! drm/xe/hwmon: Expose power attributes
=== git am output follows ===
Applying: drm/xe/pat: trim the xelp PAT table
Applying: drm/xe: directly use pat_index for pte_encode
Applying: drm/xe/uapi: Add support for cache and coherency mode
Applying: drm/xe/pat: annotate pat_index with coherency mode
Applying: drm/xe/uapi: support pat_index selection with vm_bind
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-xe] ✓ CI.checkpatch: success for PAT and cache coherency support (rev9)
2023-10-05 15:46 [Intel-xe] [PATCH v7 0/5] PAT and cache coherency support Matthew Auld
` (5 preceding siblings ...)
2023-10-05 19:34 ` [Intel-xe] ✓ CI.Patch_applied: success for PAT and cache coherency support (rev9) Patchwork
@ 2023-10-05 19:34 ` Patchwork
2023-10-05 19:35 ` [Intel-xe] ✓ CI.KUnit: " Patchwork
7 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2023-10-05 19:34 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-xe
== Series Details ==
Series: PAT and cache coherency support (rev9)
URL : https://patchwork.freedesktop.org/series/123027/
State : success
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
63c2b6b160bca2df6efc7bc4cea6f442097d7854
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit f036fc8a6f6b176c7f642e3dae8c30ebf35101b3
Author: Matthew Auld <matthew.auld@intel.com>
Date: Thu Oct 5 16:46:59 2023 +0100
drm/xe/uapi: support pat_index selection with vm_bind
Allow userspace to directly control the pat_index for a given vm
binding. This should allow directly controlling the coherency, caching
and potentially other stuff in the future for the ppGTT binding.
The exact meaning behind the pat_index is very platform specific (see
BSpec or PRMs) but effectively maps to some predefined memory
attributes. From the KMD pov we only care about the coherency that is
provided by the pat_index, which falls into either NONE, 1WAY or 2WAY.
The vm_bind coherency mode for the given pat_index needs to be at least
as coherent as the coh_mode that was set at object creation. For
platforms that lack the explicit coherency mode, we treat UC/WT/WC as
NONE and WB as AT_LEAST_1WAY.
For userptr mappings we lack a corresponding gem object, so the expected
coherency mode is instead implicit and must fall into either 1WAY or
2WAY. Trying to use NONE will be rejected by the kernel. For imported
dma-buf (from a different device) the coherency mode is also implicit
and must also be either 1WAY or 2WAY i.e AT_LEAST_1WAY.
v2:
- Undefined coh_mode(pat_index) can now be treated as programmer
error. (Matt Roper)
- We now allow gem_create.coh_mode <= coh_mode(pat_index), rather than
having to match exactly. This ensures imported dma-buf can always
just use 1way (or even 2way), now that we also bundle 1way/2way into
at_least_1way. We still require 1way/2way for external dma-buf, but
the policy can now be the same for self-import, if desired.
- Use u16 for pat_index in uapi. u32 is massive overkill. (José)
- Move as much of the pat_index validation as we can into
vm_bind_ioctl_check_args. (José)
v3 (Matt Roper):
- Split the pte_encode() refactoring into separate patch.
v4:
- Rebase
Testcase: igt@xe_pat
Bspec: 45101, 44235 #xe
Bspec: 70552, 71582, 59400 #xe2
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Pallavi Mishra <pallavi.mishra@intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Filip Hazubski <filip.hazubski@intel.com>
Cc: Carl Zhang <carl.zhang@intel.com>
Cc: Effie Yu <effie.yu@intel.com>
Tested-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
+ /mt/dim checkpatch be79dc2504eef9a437df54ca9aac316755e475cf drm-intel
d39862e75 drm/xe/pat: trim the xelp PAT table
88527fba7 drm/xe: directly use pat_index for pte_encode
d36be8933 drm/xe/uapi: Add support for cache and coherency mode
04821607f drm/xe/pat: annotate pat_index with coherency mode
f036fc8a6 drm/xe/uapi: support pat_index selection with vm_bind
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-xe] ✓ CI.KUnit: success for PAT and cache coherency support (rev9)
2023-10-05 15:46 [Intel-xe] [PATCH v7 0/5] PAT and cache coherency support Matthew Auld
` (6 preceding siblings ...)
2023-10-05 19:34 ` [Intel-xe] ✓ CI.checkpatch: " Patchwork
@ 2023-10-05 19:35 ` Patchwork
7 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2023-10-05 19:35 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-xe
== Series Details ==
Series: PAT and cache coherency support (rev9)
URL : https://patchwork.freedesktop.org/series/123027/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
stty: 'standard input': Inappropriate ioctl for device
[19:34:26] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:34:30] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[19:34:51] Starting KUnit Kernel (1/1)...
[19:34:51] ============================================================
[19:34:51] ========================== xe_bo ==========================
[19:34:51] [SKIPPED] xe_ccs_migrate_kunit
[19:34:51] [SKIPPED] xe_bo_evict_kunit
[19:34:51] ===================== [SKIPPED] xe_bo ======================
[19:34:51] ======================= xe_dma_buf ========================
[19:34:51] [SKIPPED] xe_dma_buf_kunit
[19:34:51] =================== [SKIPPED] xe_dma_buf ===================
[19:34:51] ======================= xe_migrate ========================
[19:34:51] [SKIPPED] xe_migrate_sanity_kunit
[19:34:51] =================== [SKIPPED] xe_migrate ===================
[19:34:51] ========================= xe_pci ==========================
[19:34:51] [PASSED] xe_gmdid_graphics_ip
[19:34:51] [PASSED] xe_gmdid_media_ip
[19:34:51] ===================== [PASSED] xe_pci ======================
[19:34:51] ========================= xe_rtp ==========================
[19:34:51] ================== xe_rtp_process_tests ===================
[19:34:51] [PASSED] coalesce-same-reg
[19:34:51] [PASSED] no-match-no-add
[19:34:51] [PASSED] no-match-no-add-multiple-rules
[19:34:51] [PASSED] two-regs-two-entries
[19:34:51] [PASSED] clr-one-set-other
[19:34:51] [PASSED] set-field
[19:34:51] [PASSED] conflict-duplicate
[19:34:51] [PASSED] conflict-not-disjoint
[19:34:51] [PASSED] conflict-reg-type
[19:34:51] ============== [PASSED] xe_rtp_process_tests ===============
[19:34:51] ===================== [PASSED] xe_rtp ======================
[19:34:51] ========================== xe_wa ==========================
[19:34:51] ======================== xe_wa_gt =========================
[19:34:51] [PASSED] TIGERLAKE (B0)
[19:34:51] [PASSED] DG1 (A0)
[19:34:51] [PASSED] DG1 (B0)
[19:34:51] [PASSED] ALDERLAKE_S (A0)
[19:34:51] [PASSED] ALDERLAKE_S (B0)
[19:34:51] [PASSED] ALDERLAKE_S (C0)
[19:34:51] [PASSED] ALDERLAKE_S (D0)
[19:34:51] [PASSED] ALDERLAKE_P (A0)
[19:34:51] [PASSED] ALDERLAKE_P (B0)
[19:34:51] [PASSED] ALDERLAKE_P (C0)
[19:34:51] [PASSED] DG2_G10 (A0)
[19:34:51] [PASSED] DG2_G10 (A1)
[19:34:51] [PASSED] DG2_G10 (B0)
[19:34:51] [PASSED] DG2_G10 (C0)
[19:34:51] [PASSED] DG2_G11 (A0)
[19:34:51] [PASSED] DG2_G11 (B0)
[19:34:51] [PASSED] DG2_G11 (B1)
[19:34:51] [PASSED] DG2_G12 (A0)
[19:34:51] [PASSED] DG2_G12 (A1)
[19:34:51] [PASSED] PVC (B0)
[19:34:51] [PASSED] PVC (B1)
[19:34:51] [PASSED] PVC (C0)
[19:34:51] ==================== [PASSED] xe_wa_gt =====================
[19:34:51] ====================== [PASSED] xe_wa ======================
[19:34:51] ============================================================
[19:34:51] Testing complete. Ran 37 tests: passed: 33, skipped: 4
[19:34:51] Elapsed time: 24.634s total, 4.180s configuring, 20.335s building, 0.101s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[19:34:51] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[19:34:52] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[19:35:12] Starting KUnit Kernel (1/1)...
[19:35:12] ============================================================
[19:35:12] ================== drm_test_pick_cmdline ==================
[19:35:12] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[19:35:12] =============== drm_test_pick_cmdline_named ===============
[19:35:12] [PASSED] NTSC
[19:35:12] [PASSED] NTSC-J
[19:35:12] [PASSED] PAL
[19:35:12] [PASSED] PAL-M
[19:35:12] =========== [PASSED] drm_test_pick_cmdline_named ===========
[19:35:12] ============== [PASSED] drm_test_pick_cmdline ==============
[19:35:12] ======================== drm_buddy ========================
[19:35:12] [PASSED] drm_test_buddy_alloc_limit
[19:35:12] [PASSED] drm_test_buddy_alloc_range
[19:35:12] [PASSED] drm_test_buddy_alloc_optimistic
[19:35:12] [PASSED] drm_test_buddy_alloc_pessimistic
[19:35:12] [PASSED] drm_test_buddy_alloc_smoke
[19:35:12] [PASSED] drm_test_buddy_alloc_pathological
[19:35:12] ==================== [PASSED] drm_buddy ====================
[19:35:12] =================== drm_cmdline_parser ====================
[19:35:12] [PASSED] drm_test_cmdline_force_d_only
[19:35:12] [PASSED] drm_test_cmdline_force_D_only_dvi
[19:35:12] [PASSED] drm_test_cmdline_force_D_only_hdmi
[19:35:12] [PASSED] drm_test_cmdline_force_D_only_not_digital
[19:35:12] [PASSED] drm_test_cmdline_force_e_only
[19:35:12] [PASSED] drm_test_cmdline_res
[19:35:12] [PASSED] drm_test_cmdline_res_vesa
[19:35:12] [PASSED] drm_test_cmdline_res_vesa_rblank
[19:35:12] [PASSED] drm_test_cmdline_res_rblank
[19:35:12] [PASSED] drm_test_cmdline_res_bpp
[19:35:12] [PASSED] drm_test_cmdline_res_refresh
[19:35:12] [PASSED] drm_test_cmdline_res_bpp_refresh
[19:35:12] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[19:35:12] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[19:35:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[19:35:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[19:35:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[19:35:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[19:35:12] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[19:35:12] [PASSED] drm_test_cmdline_res_margins_force_on
[19:35:12] [PASSED] drm_test_cmdline_res_vesa_margins
[19:35:12] [PASSED] drm_test_cmdline_name
[19:35:12] [PASSED] drm_test_cmdline_name_bpp
[19:35:12] [PASSED] drm_test_cmdline_name_option
[19:35:12] [PASSED] drm_test_cmdline_name_bpp_option
[19:35:12] [PASSED] drm_test_cmdline_rotate_0
[19:35:12] [PASSED] drm_test_cmdline_rotate_90
[19:35:12] [PASSED] drm_test_cmdline_rotate_180
[19:35:12] [PASSED] drm_test_cmdline_rotate_270
[19:35:12] [PASSED] drm_test_cmdline_hmirror
[19:35:12] [PASSED] drm_test_cmdline_vmirror
[19:35:12] [PASSED] drm_test_cmdline_margin_options
[19:35:12] [PASSED] drm_test_cmdline_multiple_options
[19:35:12] [PASSED] drm_test_cmdline_bpp_extra_and_option
[19:35:12] [PASSED] drm_test_cmdline_extra_and_option
[19:35:12] [PASSED] drm_test_cmdline_freestanding_options
[19:35:12] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[19:35:12] [PASSED] drm_test_cmdline_panel_orientation
[19:35:12] ================ drm_test_cmdline_invalid =================
[19:35:12] [PASSED] margin_only
[19:35:12] [PASSED] interlace_only
[19:35:12] [PASSED] res_missing_x
[19:35:12] [PASSED] res_missing_y
[19:35:12] [PASSED] res_bad_y
[19:35:12] [PASSED] res_missing_y_bpp
[19:35:12] [PASSED] res_bad_bpp
[19:35:12] [PASSED] res_bad_refresh
[19:35:12] [PASSED] res_bpp_refresh_force_on_off
[19:35:12] [PASSED] res_invalid_mode
[19:35:12] [PASSED] res_bpp_wrong_place_mode
[19:35:12] [PASSED] name_bpp_refresh
[19:35:12] [PASSED] name_refresh
[19:35:12] [PASSED] name_refresh_wrong_mode
[19:35:12] [PASSED] name_refresh_invalid_mode
[19:35:12] [PASSED] rotate_multiple
[19:35:12] [PASSED] rotate_invalid_val
[19:35:12] [PASSED] rotate_truncated
[19:35:12] [PASSED] invalid_option
[19:35:12] [PASSED] invalid_tv_option
[19:35:12] [PASSED] truncated_tv_option
[19:35:12] ============ [PASSED] drm_test_cmdline_invalid =============
[19:35:12] =============== drm_test_cmdline_tv_options ===============
[19:35:12] [PASSED] NTSC
[19:35:12] [PASSED] NTSC_443
[19:35:12] [PASSED] NTSC_J
[19:35:12] [PASSED] PAL
[19:35:12] [PASSED] PAL_M
[19:35:12] [PASSED] PAL_N
[19:35:12] [PASSED] SECAM
[19:35:12] =========== [PASSED] drm_test_cmdline_tv_options ===========
[19:35:12] =============== [PASSED] drm_cmdline_parser ================
[19:35:12] ================ drm_get_tv_mode_from_name ================
[19:35:12] ========== drm_test_get_tv_mode_from_name_valid ===========
[19:35:12] [PASSED] NTSC
[19:35:12] [PASSED] NTSC-443
[19:35:12] [PASSED] NTSC-J
[19:35:12] [PASSED] PAL
[19:35:12] [PASSED] PAL-M
[19:35:12] [PASSED] PAL-N
[19:35:12] [PASSED] SECAM
[19:35:12] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[19:35:12] [PASSED] drm_test_get_tv_mode_from_name_truncated
[19:35:12] ============ [PASSED] drm_get_tv_mode_from_name ============
[19:35:12] ==================== drm_damage_helper ====================
[19:35:12] [PASSED] drm_test_damage_iter_no_damage
[19:35:12] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[19:35:12] [PASSED] drm_test_damage_iter_no_damage_src_moved
[19:35:12] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[19:35:12] [PASSED] drm_test_damage_iter_no_damage_not_visible
[19:35:12] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[19:35:12] [PASSED] drm_test_damage_iter_no_damage_no_fb
[19:35:12] [PASSED] drm_test_damage_iter_simple_damage
[19:35:12] [PASSED] drm_test_damage_iter_single_damage
[19:35:12] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[19:35:12] [PASSED] drm_test_damage_iter_single_damage_outside_src
[19:35:12] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[19:35:12] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[19:35:12] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[19:35:12] [PASSED] drm_test_damage_iter_single_damage_src_moved
[19:35:12] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[19:35:12] [PASSED] drm_test_damage_iter_damage
[19:35:12] [PASSED] drm_test_damage_iter_damage_one_intersect
[19:35:12] [PASSED] drm_test_damage_iter_damage_one_outside
[19:35:12] [PASSED] drm_test_damage_iter_damage_src_moved
[19:35:12] [PASSED] drm_test_damage_iter_damage_not_visible
[19:35:12] ================ [PASSED] drm_damage_helper ================
[19:35:12] ==================== drm_dp_mst_helper ====================
[19:35:12] ============== drm_test_dp_mst_calc_pbn_mode ==============
[19:35:12] [PASSED] Clock 154000 BPP 30 DSC disabled
[19:35:12] [PASSED] Clock 234000 BPP 30 DSC disabled
[19:35:12] [PASSED] Clock 297000 BPP 24 DSC disabled
[19:35:12] [PASSED] Clock 332880 BPP 24 DSC enabled
[19:35:12] [PASSED] Clock 324540 BPP 24 DSC enabled
[19:35:12] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[19:35:12] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[19:35:12] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[19:35:12] [PASSED] DP_POWER_UP_PHY with port number
[19:35:12] [PASSED] DP_POWER_DOWN_PHY with port number
[19:35:12] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[19:35:12] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[19:35:12] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[19:35:12] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[19:35:12] [PASSED] DP_QUERY_PAYLOAD with port number
[19:35:12] [PASSED] DP_QUERY_PAYLOAD with VCPI
[19:35:12] [PASSED] DP_REMOTE_DPCD_READ with port number
[19:35:12] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[19:35:12] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[19:35:12] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[19:35:12] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[19:35:12] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[19:35:12] [PASSED] DP_REMOTE_I2C_READ with port number
[19:35:12] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[19:35:12] [PASSED] DP_REMOTE_I2C_READ with transactions array
[19:35:12] [PASSED] DP_REMOTE_I2C_WRITE with port number
[19:35:12] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[19:35:12] [PASSED] DP_REMOTE_I2C_WRITE with data array
[19:35:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[19:35:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[19:35:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[19:35:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[19:35:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[19:35:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[19:35:12] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[19:35:12] ================ [PASSED] drm_dp_mst_helper ================
[19:35:12] ================= drm_format_helper_test ==================
[19:35:12] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[19:35:12] [PASSED] single_pixel_source_buffer
[19:35:12] [PASSED] single_pixel_clip_rectangle
[19:35:12] [PASSED] well_known_colors
[19:35:12] [PASSED] destination_pitch
[19:35:12] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[19:35:12] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[19:35:12] [PASSED] single_pixel_source_buffer
[19:35:12] [PASSED] single_pixel_clip_rectangle
[19:35:12] [PASSED] well_known_colors
[19:35:12] [PASSED] destination_pitch
[19:35:12] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[19:35:12] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[19:35:12] [PASSED] single_pixel_source_buffer
[19:35:12] [PASSED] single_pixel_clip_rectangle
[19:35:12] [PASSED] well_known_colors
[19:35:12] [PASSED] destination_pitch
[19:35:12] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[19:35:12] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[19:35:12] [PASSED] single_pixel_source_buffer
[19:35:12] [PASSED] single_pixel_clip_rectangle
[19:35:12] [PASSED] well_known_colors
[19:35:12] [PASSED] destination_pitch
[19:35:12] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[19:35:12] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[19:35:12] [PASSED] single_pixel_source_buffer
[19:35:12] [PASSED] single_pixel_clip_rectangle
[19:35:12] [PASSED] well_known_colors
[19:35:12] [PASSED] destination_pitch
[19:35:12] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[19:35:12] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[19:35:12] [PASSED] single_pixel_source_buffer
[19:35:12] [PASSED] single_pixel_clip_rectangle
[19:35:12] [PASSED] well_known_colors
[19:35:12] [PASSED] destination_pitch
[19:35:12] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[19:35:12] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[19:35:12] [PASSED] single_pixel_source_buffer
[19:35:12] [PASSED] single_pixel_clip_rectangle
[19:35:12] [PASSED] well_known_colors
[19:35:12] [PASSED] destination_pitch
[19:35:12] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[19:35:12] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[19:35:12] [PASSED] single_pixel_source_buffer
[19:35:12] [PASSED] single_pixel_clip_rectangle
[19:35:12] [PASSED] well_known_colors
[19:35:12] [PASSED] destination_pitch
[19:35:12] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[19:35:12] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[19:35:12] [PASSED] single_pixel_source_buffer
[19:35:12] [PASSED] single_pixel_clip_rectangle
[19:35:12] [PASSED] well_known_colors
[19:35:12] [PASSED] destination_pitch
[19:35:12] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[19:35:12] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[19:35:12] [PASSED] single_pixel_source_buffer
[19:35:12] [PASSED] single_pixel_clip_rectangle
[19:35:12] [PASSED] well_known_colors
[19:35:12] [PASSED] destination_pitch
[19:35:12] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[19:35:12] ============== drm_test_fb_xrgb8888_to_mono ===============
[19:35:12] [PASSED] single_pixel_source_buffer
[19:35:12] [PASSED] single_pixel_clip_rectangle
[19:35:12] [PASSED] well_known_colors
[19:35:12] [PASSED] destination_pitch
[19:35:12] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[19:35:12] ==================== drm_test_fb_swab =====================
[19:35:12] [PASSED] single_pixel_source_buffer
[19:35:12] [PASSED] single_pixel_clip_rectangle
[19:35:12] [PASSED] well_known_colors
[19:35:12] [PASSED] destination_pitch
[19:35:12] ================ [PASSED] drm_test_fb_swab =================
[19:35:12] ================= drm_test_fb_clip_offset =================
[19:35:12] [PASSED] pass through
[19:35:12] [PASSED] horizontal offset
[19:35:12] [PASSED] vertical offset
[19:35:12] [PASSED] horizontal and vertical offset
[19:35:12] [PASSED] horizontal offset (custom pitch)
[19:35:12] [PASSED] vertical offset (custom pitch)
[19:35:12] [PASSED] horizontal and vertical offset (custom pitch)
[19:35:12] ============= [PASSED] drm_test_fb_clip_offset =============
[19:35:12] ============== drm_test_fb_build_fourcc_list ==============
[19:35:12] [PASSED] no native formats
[19:35:12] [PASSED] XRGB8888 as native format
[19:35:12] [PASSED] remove duplicates
[19:35:12] [PASSED] convert alpha formats
[19:35:12] [PASSED] random formats
[19:35:12] ========== [PASSED] drm_test_fb_build_fourcc_list ==========
[19:35:12] =================== drm_test_fb_memcpy ====================
[19:35:12] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[19:35:12] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[19:35:12] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[19:35:12] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[19:35:12] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[19:35:12] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[19:35:12] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[19:35:12] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[19:35:12] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[19:35:12] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[19:35:12] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[19:35:12] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[19:35:12] =============== [PASSED] drm_test_fb_memcpy ================
[19:35:12] ============= [PASSED] drm_format_helper_test ==============
[19:35:12] ======================= drm_format ========================
[19:35:12] [PASSED] drm_test_format_block_width_invalid
[19:35:12] [PASSED] drm_test_format_block_width_one_plane
[19:35:12] [PASSED] drm_test_format_block_width_two_plane
[19:35:12] [PASSED] drm_test_format_block_width_three_plane
[19:35:12] [PASSED] drm_test_format_block_width_tiled
[19:35:12] [PASSED] drm_test_format_block_height_invalid
[19:35:12] [PASSED] drm_test_format_block_height_one_plane
[19:35:12] [PASSED] drm_test_format_block_height_two_plane
[19:35:12] [PASSED] drm_test_format_block_height_three_plane
[19:35:12] [PASSED] drm_test_format_block_height_tiled
[19:35:12] [PASSED] drm_test_format_min_pitch_invalid
[19:35:12] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[19:35:12] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[19:35:12] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[19:35:12] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[19:35:12] [PASSED] drm_test_format_min_pitch_two_plane
[19:35:12] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[19:35:12] [PASSED] drm_test_format_min_pitch_tiled
[19:35:12] =================== [PASSED] drm_format ====================
[19:35:12] ===================== drm_framebuffer =====================
[19:35:12] =============== drm_test_framebuffer_create ===============
[19:35:12] [PASSED] ABGR8888 normal sizes
[19:35:12] [PASSED] ABGR8888 max sizes
[19:35:12] [PASSED] ABGR8888 pitch greater than min required
[19:35:12] [PASSED] ABGR8888 pitch less than min required
[19:35:12] [PASSED] ABGR8888 Invalid width
[19:35:12] [PASSED] ABGR8888 Invalid buffer handle
[19:35:12] [PASSED] No pixel format
[19:35:12] [PASSED] ABGR8888 Width 0
[19:35:12] [PASSED] ABGR8888 Height 0
[19:35:12] [PASSED] ABGR8888 Out of bound height * pitch combination
[19:35:12] [PASSED] ABGR8888 Large buffer offset
[19:35:12] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[19:35:12] [PASSED] ABGR8888 Valid buffer modifier
[19:35:12] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[19:35:12] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[19:35:12] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[19:35:12] [PASSED] NV12 Normal sizes
[19:35:12] [PASSED] NV12 Max sizes
[19:35:12] [PASSED] NV12 Invalid pitch
[19:35:12] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[19:35:12] [PASSED] NV12 different modifier per-plane
[19:35:12] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[19:35:12] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[19:35:12] [PASSED] NV12 Modifier for inexistent plane
[19:35:12] [PASSED] NV12 Handle for inexistent plane
[19:35:12] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[19:35:12] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[19:35:12] [PASSED] YVU420 Normal sizes
[19:35:12] [PASSED] YVU420 Max sizes
[19:35:12] [PASSED] YVU420 Invalid pitch
[19:35:12] [PASSED] YVU420 Different pitches
[19:35:12] [PASSED] YVU420 Different buffer offsets/pitches
[19:35:12] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[19:35:12] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[19:35:12] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[19:35:12] [PASSED] YVU420 Valid modifier
[19:35:12] [PASSED] YVU420 Different modifiers per plane
[19:35:12] [PASSED] YVU420 Modifier for inexistent plane
[19:35:12] [PASSED] X0L2 Normal sizes
[19:35:12] [PASSED] X0L2 Max sizes
[19:35:12] [PASSED] X0L2 Invalid pitch
[19:35:12] [PASSED] X0L2 Pitch greater than minimum required
[19:35:12] [PASSED] X0L2 Handle for inexistent plane
[19:35:12] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[19:35:12] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[19:35:12] [PASSED] X0L2 Valid modifier
[19:35:12] [PASSED] X0L2 Modifier for inexistent plane
[19:35:12] =========== [PASSED] drm_test_framebuffer_create ===========
[19:35:12] ================= [PASSED] drm_framebuffer =================
[19:35:12] ==================== drm-test-managed =====================
[19:35:12] [PASSED] drm_test_managed_run_action
[19:35:12] ================ [PASSED] drm-test-managed =================
[19:35:12] ========================= drm_mm ==========================
[19:35:12] [PASSED] drm_test_mm_init
[19:35:12] [PASSED] drm_test_mm_debug
[19:35:22] [PASSED] drm_test_mm_reserve
[19:35:32] [PASSED] drm_test_mm_insert
[19:35:33] [PASSED] drm_test_mm_replace
[19:35:33] [PASSED] drm_test_mm_insert_range
[19:35:33] [PASSED] drm_test_mm_frag
[19:35:33] [PASSED] drm_test_mm_align
[19:35:33] [PASSED] drm_test_mm_align32
[19:35:33] [PASSED] drm_test_mm_align64
[19:35:33] [PASSED] drm_test_mm_evict
[19:35:33] [PASSED] drm_test_mm_evict_range
[19:35:33] [PASSED] drm_test_mm_topdown
[19:35:33] [PASSED] drm_test_mm_bottomup
[19:35:33] [PASSED] drm_test_mm_lowest
[19:35:33] [PASSED] drm_test_mm_highest
[19:35:34] [PASSED] drm_test_mm_color
[19:35:35] [PASSED] drm_test_mm_color_evict
[19:35:35] [PASSED] drm_test_mm_color_evict_range
[19:35:35] ===================== [PASSED] drm_mm ======================
[19:35:35] =================== drm_modes_analog_tv ===================
[19:35:35] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[19:35:35] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[19:35:35] [PASSED] drm_test_modes_analog_tv_pal_576i
[19:35:35] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[19:35:35] =============== [PASSED] drm_modes_analog_tv ===============
[19:35:35] ==================== drm_plane_helper =====================
[19:35:35] =============== drm_test_check_plane_state ================
[19:35:35] [PASSED] clipping_simple
[19:35:35] [PASSED] clipping_rotate_reflect
[19:35:35] [PASSED] positioning_simple
[19:35:35] [PASSED] upscaling
[19:35:35] [PASSED] downscaling
[19:35:35] [PASSED] rounding1
[19:35:35] [PASSED] rounding2
[19:35:35] [PASSED] rounding3
[19:35:35] [PASSED] rounding4
[19:35:35] =========== [PASSED] drm_test_check_plane_state ============
[19:35:35] =========== drm_test_check_invalid_plane_state ============
[19:35:35] [PASSED] positioning_invalid
[19:35:35] [PASSED] upscaling_invalid
[19:35:35] [PASSED] downscaling_invalid
[19:35:35] ======= [PASSED] drm_test_check_invalid_plane_state ========
[19:35:35] ================ [PASSED] drm_plane_helper =================
[19:35:35] ============ drm_connector_helper_tv_get_modes ============
[19:35:35] ====== drm_test_connector_helper_tv_get_modes_check =======
[19:35:35] [PASSED] None
[19:35:35] [PASSED] PAL
[19:35:35] [PASSED] NTSC
[19:35:35] [PASSED] Both, NTSC Default
[19:35:35] [PASSED] Both, PAL Default
[19:35:35] [PASSED] Both, NTSC Default, with PAL on command-line
[19:35:35] [PASSED] Both, PAL Default, with NTSC on command-line
[19:35:35] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[19:35:35] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[19:35:35] ======================== drm_rect =========================
[19:35:35] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[19:35:35] [PASSED] drm_test_rect_clip_scaled_not_clipped
[19:35:35] [PASSED] drm_test_rect_clip_scaled_clipped
[19:35:35] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[19:35:35] ================= drm_test_rect_intersect =================
[19:35:35] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[19:35:35] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[19:35:35] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[19:35:35] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[19:35:35] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[19:35:35] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[19:35:35] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[19:35:35] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[19:35:35] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[19:35:35] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[19:35:35] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[19:35:35] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[19:35:35] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[19:35:35] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[19:35:35] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[19:35:35] ============= [PASSED] drm_test_rect_intersect =============
[19:35:35] ================ drm_test_rect_calc_hscale ================
[19:35:35] [PASSED] normal use
[19:35:35] [PASSED] out of max range
[19:35:35] [PASSED] out of min range
[19:35:35] [PASSED] zero dst
[19:35:35] [PASSED] negative src
[19:35:35] [PASSED] negative dst
[19:35:35] ============ [PASSED] drm_test_rect_calc_hscale ============
[19:35:35] ================ drm_test_rect_calc_vscale ================
[19:35:35] [PASSED] normal use
[19:35:35] [PASSED] out of max range
[19:35:35] [PASSED] out of min range
[19:35:35] [PASSED] zero dst
[19:35:35] [PASSED] negative src
[19:35:35] [PASSED] negative dst
[19:35:35] ============ [PASSED] drm_test_rect_calc_vscale ============
[19:35:35] ================== drm_test_rect_rotate ===================
[19:35:35] [PASSED] reflect-x
[19:35:35] [PASSED] reflect-y
[19:35:35] [PASSED] rotate-0
[19:35:35] [PASSED] rotate-90
[19:35:35] [PASSED] rotate-180
[19:35:35] [PASSED] rotate-270
[19:35:35] ============== [PASSED] drm_test_rect_rotate ===============
[19:35:35] ================ drm_test_rect_rotate_inv =================
[19:35:35] [PASSED] reflect-x
[19:35:35] [PASSED] reflect-y
[19:35:35] [PASSED] rotate-0
[19:35:35] [PASSED] rotate-90
[19:35:35] [PASSED] rotate-180
[19:35:35] [PASSED] rotate-270
[19:35:35] ============ [PASSED] drm_test_rect_rotate_inv =============
stty: 'standard input': Inappropriate ioctl for device
[19:35:35] ==================== [PASSED] drm_rect =====================
[19:35:35] ======================== drm_exec =========================
[19:35:35] [PASSED] sanitycheck
[19:35:35] [PASSED] test_lock
[19:35:35] [PASSED] test_lock_unlock
[19:35:35] [PASSED] test_duplicates
[19:35:35] [PASSED] test_prepare
[19:35:35] [PASSED] test_prepare_array
[19:35:35] [PASSED] test_multiple_loops
[19:35:35] ==================== [PASSED] drm_exec =====================
[19:35:35] ============================================================
[19:35:35] Testing complete. Ran 368 tests: passed: 368
[19:35:35] Elapsed time: 44.064s total, 1.673s configuring, 19.145s building, 23.244s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-10-05 19:35 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
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2023-10-05 15:46 [Intel-xe] [PATCH v7 0/5] PAT and cache coherency support Matthew Auld
2023-10-05 15:46 ` [Intel-xe] [PATCH v7 1/5] drm/xe/pat: trim the xelp PAT table Matthew Auld
2023-10-05 15:46 ` [Intel-xe] [PATCH v7 2/5] drm/xe: directly use pat_index for pte_encode Matthew Auld
2023-10-05 15:46 ` [Intel-xe] [PATCH v7 3/5] drm/xe/uapi: Add support for cache and coherency mode Matthew Auld
2023-10-05 15:46 ` [Intel-xe] [PATCH v7 4/5] drm/xe/pat: annotate pat_index with " Matthew Auld
2023-10-05 15:46 ` [Intel-xe] [PATCH v7 5/5] drm/xe/uapi: support pat_index selection with vm_bind Matthew Auld
2023-10-05 19:34 ` [Intel-xe] ✓ CI.Patch_applied: success for PAT and cache coherency support (rev9) Patchwork
2023-10-05 19:34 ` [Intel-xe] ✓ CI.checkpatch: " Patchwork
2023-10-05 19:35 ` [Intel-xe] ✓ CI.KUnit: " Patchwork
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