From: Ashutosh Dixit <ashutosh.dixit@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: ogabbay@habana.ai, gzadicario@habana.ai,
Harish Chegondi <harish.chegondi@intel.com>,
bdotan@habana.ai, talbo@habana.ai
Subject: [Intel-xe] [PATCH 1/2] drm/xe/uapi: "Perf" layer to support multiple perf counter stream types
Date: Mon, 9 Oct 2023 15:24:08 -0700 [thread overview]
Message-ID: <20231009222409.620443-2-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <20231009222409.620443-1-ashutosh.dixit@intel.com>
In XE, the plan is to support multiple types of perf counter streams (OA is
only one type of these streams). This requires addition of a PERF layer to
multiplex these different stream types through a single set of PERF
ioctl's.
v2: Add param_size to 'struct drm_xe_perf_param' (Umesh)
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_device.c | 4 +++
drivers/gpu/drm/xe/xe_perf.c | 47 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_perf.h | 18 +++++++++++++
include/uapi/drm/xe_drm.h | 49 ++++++++++++++++++++++++++++++++++
5 files changed, 119 insertions(+)
create mode 100644 drivers/gpu/drm/xe/xe_perf.c
create mode 100644 drivers/gpu/drm/xe/xe_perf.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index dff1386ee6b31..122498e24251c 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -88,6 +88,7 @@ xe-y += xe_bb.o \
xe_pat.o \
xe_pci.o \
xe_pcode.o \
+ xe_perf.o \
xe_pm.o \
xe_preempt_fence.o \
xe_pt.o \
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index ef42c33e30558..3c0c28c6f9fb8 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -28,6 +28,7 @@
#include "xe_module.h"
#include "xe_pat.h"
#include "xe_pcode.h"
+#include "xe_perf.h"
#include "xe_pm.h"
#include "xe_query.h"
#include "xe_tile.h"
@@ -128,6 +129,9 @@ static const struct drm_ioctl_desc xe_ioctls[] = {
DRM_IOCTL_DEF_DRV(XE_WAIT_USER_FENCE, xe_wait_user_fence_ioctl,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(XE_VM_MADVISE, xe_vm_madvise_ioctl, DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(XE_PERF_OPEN, xe_perf_open_ioctl, DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(XE_PERF_ADD_CONFIG, xe_perf_add_config_ioctl, DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(XE_PERF_REMOVE_CONFIG, xe_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
};
static const struct file_operations xe_driver_fops = {
diff --git a/drivers/gpu/drm/xe/xe_perf.c b/drivers/gpu/drm/xe/xe_perf.c
new file mode 100644
index 0000000000000..de430065e0d27
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_perf.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include <linux/errno.h>
+
+#include "xe_perf.h"
+
+int xe_perf_open_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+ struct drm_xe_perf_param *arg = data;
+
+ if (arg->extensions)
+ return -EINVAL;
+
+ switch (arg->perf_type) {
+ default:
+ return -EINVAL;
+ }
+}
+
+int xe_perf_add_config_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+ struct drm_xe_perf_param *arg = data;
+
+ if (arg->extensions)
+ return -EINVAL;
+
+ switch (arg->perf_type) {
+ default:
+ return -EINVAL;
+ }
+}
+
+int xe_perf_remove_config_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
+{
+ struct drm_xe_perf_param *arg = data;
+
+ if (arg->extensions)
+ return -EINVAL;
+
+ switch (arg->perf_type) {
+ default:
+ return -EINVAL;
+ }
+}
diff --git a/drivers/gpu/drm/xe/xe_perf.h b/drivers/gpu/drm/xe/xe_perf.h
new file mode 100644
index 0000000000000..7ee90491132a0
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_perf.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _XE_PERF_H_
+#define _XE_PERF_H_
+
+#include <drm/xe_drm.h>
+
+struct drm_device;
+struct drm_file;
+
+int xe_perf_open_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
+int xe_perf_add_config_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
+int xe_perf_remove_config_ioctl(struct drm_device *dev, void *data, struct drm_file *file);
+
+#endif
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index d48d8e3c898ce..a2b20335aacd7 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -111,6 +111,9 @@ struct xe_user_extension {
#define DRM_XE_WAIT_USER_FENCE 0x0b
#define DRM_XE_VM_MADVISE 0x0c
#define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x0d
+#define DRM_XE_PERF_OPEN 0x0e
+#define DRM_XE_PERF_ADD_CONFIG 0x0f
+#define DRM_XE_PERF_REMOVE_CONFIG 0x10
/* Must be kept compact -- no holes */
#define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query)
@@ -127,6 +130,9 @@ struct xe_user_extension {
#define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property)
#define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence)
#define DRM_IOCTL_XE_VM_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_MADVISE, struct drm_xe_vm_madvise)
+#define DRM_IOCTL_XE_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_XE_PERF_OPEN, struct drm_xe_perf_param)
+#define DRM_IOCTL_XE_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_XE_PERF_ADD_CONFIG, struct drm_xe_perf_param)
+#define DRM_IOCTL_XE_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_XE_PERF_REMOVE_CONFIG, struct drm_xe_perf_param)
/**
* enum drm_xe_memory_class - Supported memory classes.
@@ -1093,6 +1099,49 @@ struct drm_xe_vm_madvise {
#define XE_PMU_MEDIA_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 3)
#define XE_PMU_ANY_ENGINE_GROUP_BUSY(gt) ___XE_PMU_OTHER(gt, 4)
+/**
+ * enum drm_xe_perf_type - Perf stream types
+ */
+enum drm_xe_perf_type {
+ XE_PERF_TYPE_MAX,
+};
+
+/**
+ * struct drm_xe_perf_param - XE perf layer param
+ *
+ * The perf layer enables multiplexing perf counter streams of multiple
+ * types. The actual params for a particular stream operation are supplied
+ * via the @param pointer (use __copy_from_user to get these params).
+ */
+struct drm_xe_perf_param {
+ /** @extensions: Pointer to the first extension struct, if any */
+ __u64 extensions;
+ /** @perf_type: Type, of enum @drm_xe_perf_type, of perf stream */
+ __u64 perf_type;
+ /** @param_size: size of data struct pointed to by @param */
+ __u64 param_size;
+ /** @param: Pointer to actual stream params */
+ __u64 param;
+};
+
+/**
+ * enum drm_xe_perf_ops - Perf stream ops
+ */
+enum drm_xe_perf_ops {
+ /**
+ * @XE_PERF_IOCTL_ENABLE: Enable data capture for a stream that was
+ * e.g. either opened in a disabled state or was disabled via
+ * XE_PERF_IOCTL_DISABLE.
+ */
+ XE_PERF_IOCTL_ENABLE = _IO('i', 0x0),
+
+ /** @XE_PERF_IOCTL_DISABLE: Disable data capture for a stream */
+ XE_PERF_IOCTL_DISABLE = _IO('i', 0x1),
+
+ /** @XE_PERF_IOCTL_CONFIG: Change stream configuration */
+ XE_PERF_IOCTL_CONFIG = _IO('i', 0x2),
+};
+
#if defined(__cplusplus)
}
#endif
--
2.41.0
next prev parent reply other threads:[~2023-10-09 22:26 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-09 22:24 [Intel-xe] [PATCH 0/2] Xe PERF layer Ashutosh Dixit
2023-10-09 22:24 ` Ashutosh Dixit [this message]
2023-10-09 22:24 ` [Intel-xe] [PATCH 2/2] drm/xe/uapi: Multiplex PERF ops through a single PERF ioctl Ashutosh Dixit
[not found] ` <DB4PR02MB86074153DF64F83B00E66CAFDECCA@DB4PR02MB8607.eurprd02.prod.outlook.com>
2023-10-11 17:33 ` Dixit, Ashutosh
2023-10-09 22:29 ` [Intel-xe] ✓ CI.Patch_applied: success for Xe PERF layer Patchwork
2023-10-09 22:29 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-10-09 22:30 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-10-09 22:37 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-10-09 22:38 ` [Intel-xe] ✗ CI.Hooks: failure " Patchwork
2023-10-09 22:39 ` [Intel-xe] ✓ CI.checksparse: success " Patchwork
2023-10-09 23:11 ` [Intel-xe] ✓ CI.BAT: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2023-10-11 17:26 [Intel-xe] [PATCH v2 0/2] " Ashutosh Dixit
2023-10-11 17:26 ` [Intel-xe] [PATCH 1/2] drm/xe/uapi: "Perf" layer to support multiple perf counter stream types Ashutosh Dixit
2023-10-12 16:51 ` Umesh Nerlige Ramappa
2023-10-12 18:04 ` Dixit, Ashutosh
2023-10-13 2:05 ` Umesh Nerlige Ramappa
2023-10-28 3:44 ` Dixit, Ashutosh
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