From: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
To: intel-xe@lists.freedesktop.org
Subject: [Intel-xe] [PATCH v4 3/9] drm/xe/xe2: Updates on XY_CTRL_SURF_COPY_BLT
Date: Wed, 6 Dec 2023 10:01:20 +0530 [thread overview]
Message-ID: <20231206043126.984049-4-himal.prasad.ghimiray@intel.com> (raw)
In-Reply-To: <20231206043126.984049-1-himal.prasad.ghimiray@intel.com>
- The XY_CTRL_SURF_COPY_BLT instruction operationg on ccs data expects
size in pages of main memory for which CCS data should be copied.
- The bitfield representing copy size in XY_CTRL_SURF_COPY_BLT has
shifted one bit higher in the instruction.
v2:
- Fix the num_pages for ccs size calculation.
- Address nits (Thomas)
Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gpu_commands.h | 1 +
drivers/gpu/drm/xe/xe_migrate.c | 21 +++++++++++++++------
2 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
index 1f9c32e694c6..6ff6c7aaa648 100644
--- a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
+++ b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
@@ -13,6 +13,7 @@
#define DST_ACCESS_TYPE_SHIFT 20
#define CCS_SIZE_MASK 0x3FF
#define CCS_SIZE_SHIFT 8
+#define XE2_CCS_SIZE_SHIFT 9
#define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 26)
#define XE2_XY_CTRL_SURF_MOCS_INDEX_MASK GENMASK(31, 28)
#define NUM_CCS_BYTES_PER_BLOCK 256
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index e8b567708ac0..7ef068451b59 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -526,21 +526,30 @@ static void emit_copy_ccs(struct xe_gt *gt, struct xe_bb *bb,
struct xe_device *xe = gt_to_xe(gt);
u32 *cs = bb->cs + bb->len;
u32 num_ccs_blks;
+ u32 num_pages;
+ u32 ccs_copy_size;
u32 mocs;
- num_ccs_blks = DIV_ROUND_UP(xe_device_ccs_bytes(gt_to_xe(gt), size),
- NUM_CCS_BYTES_PER_BLOCK);
- xe_gt_assert(gt, num_ccs_blks <= NUM_CCS_BLKS_PER_XFER);
+ if (GRAPHICS_VERx100(xe) >= 2000) {
+ num_pages = DIV_ROUND_UP(size, XE_PAGE_SIZE);
+ xe_gt_assert(gt, num_pages <= 1024);
- if (GRAPHICS_VERx100(xe) >= 2000)
+ ccs_copy_size = ((num_pages - 1) & CCS_SIZE_MASK) << XE2_CCS_SIZE_SHIFT;
mocs = FIELD_PREP(XE2_XY_CTRL_SURF_MOCS_INDEX_MASK, gt->mocs.uc_index);
- else
+
+ } else {
+ num_ccs_blks = DIV_ROUND_UP(xe_device_ccs_bytes(gt_to_xe(gt), size),
+ NUM_CCS_BYTES_PER_BLOCK);
+ xe_gt_assert(gt, num_ccs_blks <= NUM_CCS_BLKS_PER_XFER);
+
+ ccs_copy_size = ((num_ccs_blks - 1) & CCS_SIZE_MASK) << CCS_SIZE_SHIFT;
mocs = FIELD_PREP(XY_CTRL_SURF_MOCS_MASK, gt->mocs.uc_index);
+ }
*cs++ = XY_CTRL_SURF_COPY_BLT |
(src_is_indirect ? 0x0 : 0x1) << SRC_ACCESS_TYPE_SHIFT |
(dst_is_indirect ? 0x0 : 0x1) << DST_ACCESS_TYPE_SHIFT |
- ((num_ccs_blks - 1) & CCS_SIZE_MASK) << CCS_SIZE_SHIFT;
+ ccs_copy_size;
*cs++ = lower_32_bits(src_ofs);
*cs++ = upper_32_bits(src_ofs) | mocs;
*cs++ = lower_32_bits(dst_ofs);
--
2.25.1
next prev parent reply other threads:[~2023-12-06 4:23 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-06 4:31 [Intel-xe] [PATCH v4 0/9] Enable compression handling on LNL Himal Prasad Ghimiray
2023-12-06 4:31 ` [Intel-xe] [PATCH v4 1/9] drm/xe/xe2: Determine bios enablement for flat ccs on igfx Himal Prasad Ghimiray
2023-12-06 22:14 ` Matt Roper
2023-12-06 4:31 ` [Intel-xe] [PATCH v4 2/9] drm/xe/xe2: Allocate extra pages for ccs during bo create Himal Prasad Ghimiray
2023-12-06 22:27 ` Matt Roper
2023-12-08 3:59 ` Ghimiray, Himal Prasad
2023-12-06 4:31 ` Himal Prasad Ghimiray [this message]
2023-12-06 23:22 ` [Intel-xe] [PATCH v4 3/9] drm/xe/xe2: Updates on XY_CTRL_SURF_COPY_BLT Matt Roper
2023-12-08 4:01 ` Ghimiray, Himal Prasad
2023-12-06 4:31 ` [Intel-xe] [PATCH v4 4/9] drm/xe/xe_migrate: Use NULL 1G PTE mapped at 255GiB VA for ccs clear Himal Prasad Ghimiray
2023-12-06 23:37 ` Matt Roper
2023-12-08 4:10 ` Ghimiray, Himal Prasad
2023-12-06 4:31 ` [Intel-xe] [PATCH v4 5/9] drm/xe/xe2: Update chunk size for each iteration of ccs copy Himal Prasad Ghimiray
2023-12-07 0:01 ` Matt Roper
2023-12-08 4:22 ` Ghimiray, Himal Prasad
2023-12-06 4:31 ` [Intel-xe] [PATCH v4 6/9] drm/xe/xe2: Update emit_pte to use compression enabled PAT index Himal Prasad Ghimiray
2023-12-07 0:14 ` Matt Roper
2023-12-08 5:01 ` Ghimiray, Himal Prasad
2023-12-06 4:31 ` [Intel-xe] [PATCH v4 7/9] drm/xe/xe2: Handle flat ccs move for igfx Himal Prasad Ghimiray
2023-12-07 0:17 ` Matt Roper
2023-12-08 4:32 ` Ghimiray, Himal Prasad
2023-12-06 4:31 ` [Intel-xe] [PATCH v4 8/9] drm/xe/xe2: Modify xe_bo_test for system memory Himal Prasad Ghimiray
2023-12-07 0:23 ` Matt Roper
2023-12-08 4:35 ` Ghimiray, Himal Prasad
2023-12-06 4:31 ` [Intel-xe] [PATCH v4 9/9] drm/xe/xe2: Support flat ccs Himal Prasad Ghimiray
2023-12-06 8:23 ` [Intel-xe] ✓ CI.Patch_applied: success for Enable compression handling on LNL. (rev5) Patchwork
2023-12-06 8:23 ` [Intel-xe] ✓ CI.checkpatch: " Patchwork
2023-12-06 8:24 ` [Intel-xe] ✓ CI.KUnit: " Patchwork
2023-12-06 8:32 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-12-06 8:32 ` [Intel-xe] ✓ CI.Hooks: " Patchwork
2023-12-06 8:33 ` [Intel-xe] ✓ CI.checksparse: " Patchwork
2023-12-06 9:07 ` [Intel-xe] ✗ CI.BAT: failure " Patchwork
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