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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: matthew.d.roper@intel.com
Subject: [PATCH 1/8] drm/xe: Drop "_REG" suffix from CSFE_CHICKEN1
Date: Thu, 14 Dec 2023 10:47:01 -0800	[thread overview]
Message-ID: <20231214184659.2249559-11-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20231214184659.2249559-10-matthew.d.roper@intel.com>

We don't use this suffix on any other registers, and it isn't part of
the register's official name either, so drop it for consistency.

While at it, move the register definition slightly so that it isn't
separating RING_CMD_CCTL's definition from its registers.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_engine_regs.h | 9 ++++-----
 drivers/gpu/drm/xe/xe_wa.c               | 2 +-
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index 1a857c4edcf5..67da19f9836f 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -46,11 +46,6 @@
 #define RING_ESR(base)				XE_REG((base) + 0xb8)
 
 #define RING_CMD_CCTL(base)			XE_REG((base) + 0xc4, XE_REG_OPTION_MASKED)
-
-#define CSFE_CHICKEN1_REG(base)			XE_REG((base) + 0xd4, XE_REG_OPTION_MASKED)
-#define   GHWSP_CSB_REPORT_DIS			REG_BIT(15)
-#define   PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS	REG_BIT(14)
-
 /*
  * CMD_CCTL read/write fields take a MOCS value and _not_ a table index.
  * The lsb of each can be considered a separate enabling bit for encryption.
@@ -61,6 +56,10 @@
 #define   CMD_CCTL_WRITE_OVERRIDE_MASK		REG_GENMASK(13, 8)
 #define   CMD_CCTL_READ_OVERRIDE_MASK		REG_GENMASK(6, 1)
 
+#define CSFE_CHICKEN1(base)			XE_REG((base) + 0xd4, XE_REG_OPTION_MASKED)
+#define   GHWSP_CSB_REPORT_DIS			REG_BIT(15)
+#define   PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS	REG_BIT(14)
+
 #define RING_BBADDR(base)			XE_REG((base) + 0x140)
 #define RING_BBADDR_UDW(base)			XE_REG((base) + 0x168)
 
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 23f1285135b8..12829748bb6c 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -605,7 +605,7 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 	 */
 	{ XE_RTP_NAME("18032095049, 16021639441"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(2004)),
-	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1_REG(0),
+	  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0),
 			     GHWSP_CSB_REPORT_DIS |
 			     PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS,
 			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
-- 
2.43.0


  reply	other threads:[~2023-12-14 18:47 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-14 18:47 [PATCH 0/8] Trivial register cleanups Matt Roper
2023-12-14 18:47 ` Matt Roper [this message]
2023-12-14 21:55   ` [PATCH 1/8] drm/xe: Drop "_REG" suffix from CSFE_CHICKEN1 Lucas De Marchi
2023-12-14 18:47 ` [PATCH 2/8] drm/xe: Move some per-engine register definitions to the engine header Matt Roper
2023-12-14 22:01   ` Lucas De Marchi
2023-12-14 18:47 ` [PATCH 3/8] drm/xe: Fix whitespace in register definitions Matt Roper
2023-12-14 22:09   ` Lucas De Marchi
2023-12-14 18:47 ` [PATCH 4/8] drm/xe: Move engine base offsets to engine register header Matt Roper
2023-12-14 22:08   ` Lucas De Marchi
2023-12-14 18:47 ` [PATCH 5/8] drm/xe: Move GSC HECI base offsets out of " Matt Roper
2023-12-14 22:06   ` Lucas De Marchi
2023-12-14 18:47 ` [PATCH 6/8] drm/xe: Define interrupt vector bits with the interrupt registers Matt Roper
2023-12-14 22:10   ` Lucas De Marchi
2023-12-14 18:47 ` [PATCH 7/8] drm/xe: Re-sort GT register header Matt Roper
2023-12-14 22:21   ` Lucas De Marchi
2023-12-14 23:11     ` Matt Roper
2023-12-14 23:38       ` Lucas De Marchi
2023-12-14 18:47 ` [PATCH 8/8] drm/xe: Drop some unnecessary header includes Matt Roper
2023-12-14 22:21   ` Lucas De Marchi
2023-12-14 19:41 ` ✓ CI.Patch_applied: success for Trivial register cleanups Patchwork
2023-12-14 19:42 ` ✓ CI.checkpatch: " Patchwork
2023-12-14 19:43 ` ✓ CI.KUnit: " Patchwork
2023-12-14 19:50 ` ✓ CI.Build: " Patchwork
2023-12-14 19:51 ` ✓ CI.Hooks: " Patchwork
2023-12-14 19:52 ` ✓ CI.checksparse: " Patchwork
2023-12-14 20:27 ` ✓ CI.BAT: " Patchwork
2023-12-15  0:07   ` Matt Roper

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