From: Matt Roper <matthew.d.roper@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: matthew.d.roper@intel.com
Subject: [PATCH 3/8] drm/xe: Fix whitespace in register definitions
Date: Thu, 14 Dec 2023 10:47:03 -0800 [thread overview]
Message-ID: <20231214184659.2249559-13-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20231214184659.2249559-10-matthew.d.roper@intel.com>
Our register headers use tabs to align the definition values. Convert a
few definitions that were using spaces instead.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/regs/xe_engine_regs.h | 4 ++--
drivers/gpu/drm/xe/regs/xe_regs.h | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index e109ef912706..7f82bef3a0db 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -136,8 +136,8 @@
#define PREEMPT_GPGPU_LEVEL_MASK PREEMPT_GPGPU_LEVEL(1, 1)
#define PREEMPT_3D_OBJECT_LEVEL REG_BIT(0)
-#define VDBOX_CGCTL3F08(base) XE_REG((base) + 0x3f08)
-#define CG3DDISHRS_CLKGATE_DIS REG_BIT(5)
+#define VDBOX_CGCTL3F08(base) XE_REG((base) + 0x3f08)
+#define CG3DDISHRS_CLKGATE_DIS REG_BIT(5)
#define VDBOX_CGCTL3F10(base) XE_REG((base) + 0x3f10)
#define IECPUNIT_CLKGATE_DIS REG_BIT(22)
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index 4ac71b605487..4b427ec8cbff 100644
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -34,9 +34,9 @@
#define XEHPC_BCS7_RING_BASE 0x3ec000
#define XEHPC_BCS8_RING_BASE 0x3ee000
-#define DG1_GSC_HECI2_BASE 0x00259000
-#define PVC_GSC_HECI2_BASE 0x00285000
-#define DG2_GSC_HECI2_BASE 0x00374000
+#define DG1_GSC_HECI2_BASE 0x00259000
+#define PVC_GSC_HECI2_BASE 0x00285000
+#define DG2_GSC_HECI2_BASE 0x00374000
#define GSCCS_RING_BASE 0x11a000
#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11)
--
2.43.0
next prev parent reply other threads:[~2023-12-14 18:47 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-14 18:47 [PATCH 0/8] Trivial register cleanups Matt Roper
2023-12-14 18:47 ` [PATCH 1/8] drm/xe: Drop "_REG" suffix from CSFE_CHICKEN1 Matt Roper
2023-12-14 21:55 ` Lucas De Marchi
2023-12-14 18:47 ` [PATCH 2/8] drm/xe: Move some per-engine register definitions to the engine header Matt Roper
2023-12-14 22:01 ` Lucas De Marchi
2023-12-14 18:47 ` Matt Roper [this message]
2023-12-14 22:09 ` [PATCH 3/8] drm/xe: Fix whitespace in register definitions Lucas De Marchi
2023-12-14 18:47 ` [PATCH 4/8] drm/xe: Move engine base offsets to engine register header Matt Roper
2023-12-14 22:08 ` Lucas De Marchi
2023-12-14 18:47 ` [PATCH 5/8] drm/xe: Move GSC HECI base offsets out of " Matt Roper
2023-12-14 22:06 ` Lucas De Marchi
2023-12-14 18:47 ` [PATCH 6/8] drm/xe: Define interrupt vector bits with the interrupt registers Matt Roper
2023-12-14 22:10 ` Lucas De Marchi
2023-12-14 18:47 ` [PATCH 7/8] drm/xe: Re-sort GT register header Matt Roper
2023-12-14 22:21 ` Lucas De Marchi
2023-12-14 23:11 ` Matt Roper
2023-12-14 23:38 ` Lucas De Marchi
2023-12-14 18:47 ` [PATCH 8/8] drm/xe: Drop some unnecessary header includes Matt Roper
2023-12-14 22:21 ` Lucas De Marchi
2023-12-14 19:41 ` ✓ CI.Patch_applied: success for Trivial register cleanups Patchwork
2023-12-14 19:42 ` ✓ CI.checkpatch: " Patchwork
2023-12-14 19:43 ` ✓ CI.KUnit: " Patchwork
2023-12-14 19:50 ` ✓ CI.Build: " Patchwork
2023-12-14 19:51 ` ✓ CI.Hooks: " Patchwork
2023-12-14 19:52 ` ✓ CI.checksparse: " Patchwork
2023-12-14 20:27 ` ✓ CI.BAT: " Patchwork
2023-12-15 0:07 ` Matt Roper
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