From: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>,
rodrigo.vivi@intel.com
Subject: [PATCH 3/3] [RFC] drm/xe: Add media rp0/rpn sysfs attributes
Date: Tue, 19 Dec 2023 15:37:11 +0530 [thread overview]
Message-ID: <20231219100711.645011-3-sujaritha.sundaresan@intel.com> (raw)
In-Reply-To: <20231219100711.645011-1-sujaritha.sundaresan@intel.com>
Add media frequency sysfs to the balance directory.
device/tile#/gt#/freq0/balance
|- media_rp0_freq
|- media_rpn_freq
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
---
drivers/gpu/drm/xe/xe_gt_balance_sysfs.c | 47 ++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_pcode_api.h | 1 +
2 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_gt_balance_sysfs.c b/drivers/gpu/drm/xe/xe_gt_balance_sysfs.c
index 054b90ca128d..e39629c211d0 100644
--- a/drivers/gpu/drm/xe/xe_gt_balance_sysfs.c
+++ b/drivers/gpu/drm/xe/xe_gt_balance_sysfs.c
@@ -137,11 +137,58 @@ static ssize_t base_rpn_freq_show(struct device *dev, struct device_attribute *a
}
static DEVICE_ATTR_RO(base_rpn_freq);
+static ssize_t media_rp0_freq_show(struct device *dev, struct device_attribute *attr,
+ char *buff)
+{
+ struct xe_gt *gt = dev_to_gt(dev);
+ u32 val, mbox;
+ int err;
+
+ mbox = REG_FIELD_PREP(PCODE_MB_COMMAND, PCODE_FREQUENCY_CONFIG)
+ | REG_FIELD_PREP(PCODE_MB_PARAM1, PCODE_MBOX_FC_SC_READ_FUSED_P0)
+ | REG_FIELD_PREP(PCODE_MB_PARAM2, PCODE_MBOX_DOMAIN_MEDIAFF);
+
+ err = xe_pcode_read(gt, mbox, &val, NULL);
+ if (err)
+ return err;
+
+ /* Fused media RP0 read from pcode is in units of 50 MHz */
+ val *= GT_FREQUENCY_MULTIPLIER;
+
+ return sysfs_emit(buff, "%u\n", val);
+}
+static DEVICE_ATTR_RO(media_rp0_freq);
+
+static ssize_t media_rpn_freq_show(struct device *dev, struct device_attribute *attr,
+ char *buff)
+{
+ struct xe_gt *gt = dev_to_gt(dev);
+ u32 val, mbox;
+ int err;
+
+ mbox = REG_FIELD_PREP(PCODE_MB_COMMAND, PCODE_FREQUENCY_CONFIG)
+ | REG_FIELD_PREP(PCODE_MB_PARAM1, PCODE_MBOX_FC_SC_READ_FUSED_PN)
+ | REG_FIELD_PREP(PCODE_MB_PARAM2, PCODE_MBOX_DOMAIN_MEDIAFF);
+
+ err = xe_pcode_read(gt, mbox, &val, NULL);
+
+ if (err)
+ return err;
+
+ /* Fused media RP0 read from pcode is in units of 50 MHz */
+ val *= GT_FREQUENCY_MULTIPLIER;
+
+ return sysfs_emit(buff, "%u\n", val);
+}
+static DEVICE_ATTR_RO(media_rpn_freq);
+
static struct attribute *balance_attrs[] = {
&dev_attr_base_freq_factor.attr,
&dev_attr_base_freq_factor_scale.attr,
&dev_attr_base_rp0_freq.attr,
&dev_attr_base_rpn_freq.attr,
+ &dev_attr_media_rp0_freq.attr,
+ &dev_attr_media_rpn_freq.attr,
NULL
};
diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
index 87213b52df4a..9fe42ef87730 100644
--- a/drivers/gpu/drm/xe/xe_pcode_api.h
+++ b/drivers/gpu/drm/xe/xe_pcode_api.h
@@ -49,6 +49,7 @@
/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
/* PCODE_FREQUENCY_CONFIG param2 */
#define PCODE_MBOX_DOMAIN_HBM 0x2
+#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
#define PCODE_MBOX_DOMAIN_CHIPLET 0x6
#define PCODE_MBOX_DOMAIN_BASE 0x8
#define PCODE_QOS_MULTIPLIER_SET 0x67
--
2.25.1
next prev parent reply other threads:[~2023-12-19 9:52 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-19 10:07 [v5 1/3] drm/xe: Add vram frequency sysfs attributes Sujaritha Sundaresan
2023-12-19 9:55 ` ✓ CI.Patch_applied: success for series starting with [v5,1/3] " Patchwork
2023-12-19 9:55 ` ✗ CI.checkpatch: warning " Patchwork
2023-12-19 9:56 ` ✓ CI.KUnit: success " Patchwork
2023-12-19 10:04 ` ✓ CI.Build: " Patchwork
2023-12-19 10:04 ` ✓ CI.Hooks: " Patchwork
2023-12-19 10:05 ` ✓ CI.checksparse: " Patchwork
2023-12-19 10:07 ` [PATCH 2/3] drm/xe: Add base balance " Sujaritha Sundaresan
2023-12-19 10:53 ` Jani Nikula
2023-12-19 11:04 ` Sundaresan, Sujaritha
2023-12-20 16:56 ` Rodrigo Vivi
2023-12-21 1:50 ` Sundaresan, Sujaritha
2023-12-19 10:07 ` Sujaritha Sundaresan [this message]
2023-12-19 10:41 ` ✓ CI.BAT: success for series starting with [v5,1/3] drm/xe: Add vram frequency " Patchwork
2023-12-20 14:56 ` [v5 1/3] " Gupta, Anshuman
2023-12-20 15:24 ` Rodrigo Vivi
2023-12-22 3:54 ` Gupta, Anshuman
2023-12-20 16:49 ` Rodrigo Vivi
2023-12-21 1:48 ` Sundaresan, Sujaritha
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