From: Badal Nilawar <badal.nilawar@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: anshuman.gupta@intel.com, lucas.demarchi@intel.com,
john.c.harrison@intel.com, matthew.d.roper@intel.com
Subject: [PATCH v2 1/2] drm/xe/guc: Add support for w/a KLVs
Date: Tue, 19 Mar 2024 21:38:58 +0530 [thread overview]
Message-ID: <20240319160859.2672825-2-badal.nilawar@intel.com> (raw)
In-Reply-To: <20240319160859.2672825-1-badal.nilawar@intel.com>
To prevent running out of bits, new w/a enable flags are being added
via a KLV system instead of a 32 bit flags word.
v2: GuC version check > 70.10 is not needed as xe will not be supporting
anything below < 70.19 (John Harrison)
Cc: John Harrison <John.C.Harrison@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
drivers/gpu/drm/xe/xe_guc_ads.c | 61 ++++++++++++++++++++++++++-
drivers/gpu/drm/xe/xe_guc_ads_types.h | 2 +
drivers/gpu/drm/xe/xe_guc_fwif.h | 5 ++-
3 files changed, 65 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 6ad4c1a90a78..506f0be35763 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -80,6 +80,10 @@ ads_to_map(struct xe_guc_ads *ads)
* +---------------------------------------+
* | padding |
* +---------------------------------------+ <== 4K aligned
+ * | w/a KLVs |
+ * +---------------------------------------+
+ * | padding |
+ * +---------------------------------------+ <== 4K aligned
* | capture lists |
* +---------------------------------------+
* | padding |
@@ -131,6 +135,11 @@ static size_t guc_ads_golden_lrc_size(struct xe_guc_ads *ads)
return PAGE_ALIGN(ads->golden_lrc_size);
}
+static u32 guc_ads_waklv_size(struct xe_guc_ads *ads)
+{
+ return PAGE_ALIGN(ads->ads_waklv_size);
+}
+
static size_t guc_ads_capture_size(struct xe_guc_ads *ads)
{
/* FIXME: Allocate a proper capture list */
@@ -167,12 +176,22 @@ static size_t guc_ads_golden_lrc_offset(struct xe_guc_ads *ads)
return PAGE_ALIGN(offset);
}
+static size_t guc_ads_waklv_offset(struct xe_guc_ads *ads)
+{
+ u32 offset;
+
+ offset = guc_ads_golden_lrc_offset(ads) +
+ guc_ads_golden_lrc_size(ads);
+
+ return PAGE_ALIGN(offset);
+}
+
static size_t guc_ads_capture_offset(struct xe_guc_ads *ads)
{
size_t offset;
- offset = guc_ads_golden_lrc_offset(ads) +
- guc_ads_golden_lrc_size(ads);
+ offset = guc_ads_waklv_offset(ads) +
+ guc_ads_waklv_size(ads);
return PAGE_ALIGN(offset);
}
@@ -260,6 +279,41 @@ static size_t calculate_golden_lrc_size(struct xe_guc_ads *ads)
return total_size;
}
+static void guc_waklv_init(struct xe_guc_ads *ads)
+{
+ u32 addr_ggtt, offset, remain, size;
+
+ offset = guc_ads_waklv_offset(ads);
+ remain = guc_ads_waklv_size(ads);
+
+ /*
+ * Add workarounds here:
+ *
+ * if (want_wa_<name>) {
+ * size = guc_waklv_<name>(guc, offset, remain);
+ * offset += size;
+ * remain -= size;
+ * }
+ */
+
+ size = guc_ads_waklv_size(ads) - remain;
+ if (!size)
+ return;
+
+ offset = guc_ads_waklv_offset(ads);
+ addr_ggtt = xe_bo_ggtt_addr(ads->bo) + offset;
+
+ ads_blob_write(ads, ads.wa_klv_addr_lo, addr_ggtt);
+ ads_blob_write(ads, ads.wa_klv_addr_hi, 0);
+ ads_blob_write(ads, ads.wa_klv_size, size);
+}
+
+static int calculate_waklv_size(struct xe_guc_ads *ads)
+{
+ /* Fudge something chunky for now: */
+ return PAGE_SIZE;
+}
+
#define MAX_GOLDEN_LRC_SIZE (SZ_4K * 64)
int xe_guc_ads_init(struct xe_guc_ads *ads)
@@ -271,6 +325,7 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
ads->golden_lrc_size = calculate_golden_lrc_size(ads);
ads->regset_size = calculate_regset_size(gt);
+ ads->ads_waklv_size = calculate_waklv_size(ads);
bo = xe_managed_bo_create_pin_map(xe, tile, guc_ads_size(ads) + MAX_GOLDEN_LRC_SIZE,
XE_BO_CREATE_SYSTEM_BIT |
@@ -597,6 +652,8 @@ void xe_guc_ads_populate(struct xe_guc_ads *ads)
guc_mapping_table_init(gt, &info_map);
guc_capture_list_init(ads);
guc_doorbell_init(ads);
+ /* Workaround KLV list */
+ guc_waklv_init(ads);
if (xe->info.has_usm) {
guc_um_init_params(ads);
diff --git a/drivers/gpu/drm/xe/xe_guc_ads_types.h b/drivers/gpu/drm/xe/xe_guc_ads_types.h
index 4afe44bece4b..62235b2a6fe3 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_ads_types.h
@@ -20,6 +20,8 @@ struct xe_guc_ads {
size_t golden_lrc_size;
/** @regset_size: size of register set passed to GuC for save/restore */
u32 regset_size;
+ /** @ads_waklv_size: waklv size */
+ u32 ads_waklv_size;
};
#endif
diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
index c281fdbfd2d6..52503719d2aa 100644
--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
@@ -207,7 +207,10 @@ struct guc_ads {
u32 capture_instance[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
u32 capture_class[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
u32 capture_global[GUC_CAPTURE_LIST_INDEX_MAX];
- u32 reserved[14];
+ u32 wa_klv_addr_lo;
+ u32 wa_klv_addr_hi;
+ u32 wa_klv_size;
+ u32 reserved[11];
} __packed;
/* Engine usage stats */
--
2.25.1
next prev parent reply other threads:[~2024-03-19 15:55 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-19 16:08 [PATCH 0/2] Add support for Wa KLVs Badal Nilawar
2024-03-19 15:59 ` ✓ CI.Patch_applied: success for Add support for Wa KLVs (rev2) Patchwork
2024-03-19 15:59 ` ✓ CI.checkpatch: " Patchwork
2024-03-19 16:00 ` ✓ CI.KUnit: " Patchwork
2024-03-19 16:08 ` Badal Nilawar [this message]
2024-03-20 20:40 ` [PATCH v2 1/2] drm/xe/guc: Add support for w/a KLVs John Harrison
2024-03-22 17:15 ` Daniele Ceraolo Spurio
2024-03-25 14:35 ` Nilawar, Badal
2024-03-19 16:08 ` [PATCH v2 2/2] drm/xe/lnl: Enable GuC Wa_14019882105 Badal Nilawar
2024-03-20 20:43 ` John Harrison
2024-03-19 16:11 ` ✓ CI.Build: success for Add support for Wa KLVs (rev2) Patchwork
2024-03-19 16:16 ` ✓ CI.Hooks: " Patchwork
2024-03-19 16:18 ` ✓ CI.checksparse: " Patchwork
2024-03-19 16:41 ` ✓ CI.BAT: " Patchwork
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