[PATCH v2 0/2] drm/xe: flush engine buffers before signalling user fence on all engines

[Andrzej Hajda <andrzej.hajda@intel.com>]

According to the discussion result on my previous patch I have prepared
new patchset, which reverts previous patch and adds barrier before
user fence signalling.
Remarks:
- I was not able to test it yet, hopefully CI will do it and me also after fixing LNL issue,
- I am not sure about MI_FLUSH_DW flags, bspec says:
  "After this command is completed with a Store DWord enabled, CPU access to graphics memory will be coherent"
  Shouldn't we use "Store DWord" then?

[1]: https://lore.kernel.org/intel-xe/Zl5DcuZeZiFgxVdJ@DUT025-TGLU.fm.intel.com/T/#m0b4420045908bac70426728d460108c0b2b65dca

Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
- Link to v1: https://lore.kernel.org/r/20240603-fix_user_fence_posted-v1-1-61c76ef69cea@intel.com

---
Andrzej Hajda (2):
      Revert "drm/xe: flush gtt before signalling user fence on all engines"
      drm/xe: flush engine buffers before signalling user fence on all engines

 drivers/gpu/drm/xe/xe_ring_ops.c | 26 ++++++++++++++++++++------
 1 file changed, 20 insertions(+), 6 deletions(-)
---
base-commit: fe3d637a9c72b22297da0c731fa5e217bd182d2d
change-id: 20240603-fix_user_fence_posted-ca56c79c0662

Best regards,
-- 
Andrzej Hajda <andrzej.hajda@intel.com>