From: Andrzej Hajda <andrzej.hajda@intel.com>
To: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
intel-xe@lists.freedesktop.org
Cc: Matthew Brost <matthew.brost@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Matthew Auld <matthew.auld@intel.com>
Subject: Re: [PATCH v2 0/2] drm/xe: flush engine buffers before signalling user fence on all engines
Date: Tue, 4 Jun 2024 16:58:39 +0200 [thread overview]
Message-ID: <8c51ae4e-dbd9-4ffe-ae42-17a67fec31d0@intel.com> (raw)
In-Reply-To: <ed6eb79e5942310650425f90e0d10f00fb704e36.camel@linux.intel.com>
On 04.06.2024 13:07, Thomas Hellström wrote:
> On Tue, 2024-06-04 at 11:38 +0200, Andrzej Hajda wrote:
>> According to the discussion result on my previous patch I have
>> prepared
>> new patchset, which reverts previous patch and adds barrier before
>> user fence signalling.
>> Remarks:
>> - I was not able to test it yet, hopefully CI will do it and me also
>> after fixing LNL issue,
Finally I can confirm that on LNL this patchset the barrier is enough,
at least on the igt tests I was fixing.
>> - I am not sure about MI_FLUSH_DW flags, bspec says:
>> "After this command is completed with a Store DWord enabled, CPU
>> access to graphics memory will be coherent"
>> Shouldn't we use "Store DWord" then?
> It's not impossible that "store dword" needs to be enabled to act as a
> write barrier. but it also says "The parser pauses on an internal flush
> until all drawing engines have completed any pending operations."
>
> If it turns out a store dword is indeed needed as a post sync
> operation, we could perhaps use the "store dword" functionality of this
> command to store the user-fence value and replace the posted write.
Yep this seems even more elegant solution for me, but as I stated above
the current solution works well.
Regards
Andrzej
>
> /Thomas
>
>> [1]:
>> https://lore.kernel.org/intel-xe/Zl5DcuZeZiFgxVdJ@DUT025-TGLU.fm.intel.com/T/#m0b4420045908bac70426728d460108c0b2b65dca
>>
>> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
>> ---
>> - Link to v1:
>> https://lore.kernel.org/r/20240603-fix_user_fence_posted-v1-1-61c76ef69cea@intel.com
>>
>> ---
>> Andrzej Hajda (2):
>> Revert "drm/xe: flush gtt before signalling user fence on all
>> engines"
>> drm/xe: flush engine buffers before signalling user fence on
>> all engines
>>
>> drivers/gpu/drm/xe/xe_ring_ops.c | 26 ++++++++++++++++++++------
>> 1 file changed, 20 insertions(+), 6 deletions(-)
>> ---
>> base-commit: fe3d637a9c72b22297da0c731fa5e217bd182d2d
>> change-id: 20240603-fix_user_fence_posted-ca56c79c0662
>>
>> Best regards,
next prev parent reply other threads:[~2024-06-04 14:58 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-04 9:38 [PATCH v2 0/2] drm/xe: flush engine buffers before signalling user fence on all engines Andrzej Hajda
2024-06-04 9:38 ` [PATCH v2 1/2] Revert "drm/xe: flush gtt before signalling user fence on all engines" Andrzej Hajda
2024-06-04 9:38 ` [PATCH v2 2/2] drm/xe: flush engine buffers before signalling user fence on all engines Andrzej Hajda
2024-06-04 11:07 ` [PATCH v2 0/2] " Thomas Hellström
2024-06-04 14:58 ` Andrzej Hajda [this message]
2024-06-04 15:39 ` Thomas Hellström
2024-06-04 23:33 ` ✓ CI.Patch_applied: success for " Patchwork
2024-06-04 23:33 ` ✓ CI.checkpatch: " Patchwork
2024-06-04 23:34 ` ✓ CI.KUnit: " Patchwork
2024-06-04 23:46 ` ✓ CI.Build: " Patchwork
2024-06-04 23:46 ` ✗ CI.Hooks: failure " Patchwork
2024-06-04 23:47 ` ✓ CI.checksparse: success " Patchwork
2024-06-05 0:15 ` ✓ CI.BAT: " Patchwork
2024-06-05 7:53 ` ✓ CI.FULL: " Patchwork
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