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* [Intel-xe] [PATCH v5] drm/xe/xe2: Enable Priority Mem Read
@ 2024-07-25 20:39 Pallavi Mishra
  2024-07-25 20:36 ` ✓ CI.Patch_applied: success for drm/xe/xe2: Enable Priority Mem Read (rev7) Patchwork
                   ` (7 more replies)
  0 siblings, 8 replies; 11+ messages in thread
From: Pallavi Mishra @ 2024-07-25 20:39 UTC (permalink / raw)
  To: intel-xe
  Cc: matthew.d.roper, jose.souza, carl.zhang, jonathan.cavitt,
	Pallavi Mishra

Enable feature to allow memory reads to take a priority memory path.
This will reduce latency on the read path, but may introduce read after
write (RAW) hazards as read and writes will no longer be ordered.

To avoid RAW hazards, SW can use the MI_MEM_FENCE command or any other
MI command that generates non posted memory writes.  This will ensure
data is coherent in memory prior to execution of commands which read
data from memory. RCS,BCS and CCS support this feature.

No pattern identified in KMD that could lead to a hazard.

v2: Modify commit message, enable priority mem read feature for media,
modify version range, modify bspec detail (Matt Roper)

v3: Rebase, fix cramped line-wrapping (jcavitt)

v4: Rebase

v5: Media does not support Priority Mem Read. Modify commit
to reflect the same.

Bspec: 60298, 60237, 60187, 60188

Signed-off-by: Pallavi Mishra <pallavi.mishra@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Acked-by: José Roberto de Souza <jose.souza@intel.com>
Acked-by: Carl Zhang <carl.zhang@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_engine_regs.h | 1 +
 drivers/gpu/drm/xe/xe_hw_engine.c        | 6 ++++++
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index c38db2a74614..81b71903675e 100644
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -104,6 +104,7 @@
 #define CSFE_CHICKEN1(base)			XE_REG((base) + 0xd4, XE_REG_OPTION_MASKED)
 #define   GHWSP_CSB_REPORT_DIS			REG_BIT(15)
 #define   PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS	REG_BIT(14)
+#define   CS_PRIORITY_MEM_READ			REG_BIT(7)
 
 #define FF_SLICE_CS_CHICKEN1(base)		XE_REG((base) + 0xe0, XE_REG_OPTION_MASKED)
 #define   FFSC_PERCTX_PREEMPT_CTRL		REG_BIT(14)
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 07ed9fd28f19..f8c9e439f2c6 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -425,6 +425,12 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
 					   0xA,
 					   XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 		},
+		/* Enable Priority Mem Read */
+		{ XE_RTP_NAME("Priority_Mem_Read"),
+		  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+		  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ,
+				     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
+		},
 		{}
 	};
 
-- 
2.25.1


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2024-07-25 20:39 [Intel-xe] [PATCH v5] drm/xe/xe2: Enable Priority Mem Read Pallavi Mishra
2024-07-25 20:36 ` ✓ CI.Patch_applied: success for drm/xe/xe2: Enable Priority Mem Read (rev7) Patchwork
2024-07-25 20:36 ` ✓ CI.checkpatch: " Patchwork
2024-07-25 20:37 ` ✓ CI.KUnit: " Patchwork
2024-07-25 20:49 ` ✓ CI.Build: " Patchwork
2024-07-25 20:51 ` ✓ CI.Hooks: " Patchwork
2024-07-25 20:53 ` ✓ CI.checksparse: " Patchwork
2024-07-25 21:13 ` ✗ CI.BAT: failure " Patchwork
2024-07-25 22:05   ` Mishra, Pallavi
2024-07-26  4:59 ` ✗ CI.FULL: " Patchwork
2024-07-26 14:37   ` Mishra, Pallavi

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