From: Tejas Upadhyay <tejas.upadhyay@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Matthew Auld <matthew.auld@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>,
Tejas Upadhyay <tejas.upadhyay@intel.com>
Subject: [PATCH 0/2] Shuffle enable_host_l2_vram order and use MCR reg
Date: Thu, 8 Aug 2024 14:58:24 +0530 [thread overview]
Message-ID: <20240808092826.585276-1-tejas.upadhyay@intel.com> (raw)
This series introduces,
1. Move enable_host_l2_vram after mcr_init
2. Use MCR regsiter as mcr reg and write to all slices
Tejas Upadhyay (2):
drm/xe: Init MCR before any mcr register read
drm/xe: Write all slices if its mcr register
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
drivers/gpu/drm/xe/xe_gt.c | 10 +++++-----
2 files changed, 6 insertions(+), 6 deletions(-)
--
2.25.1
next reply other threads:[~2024-08-08 9:26 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-08 9:28 Tejas Upadhyay [this message]
2024-08-08 9:28 ` [PATCH 1/2] drm/xe: Init MCR before any mcr register read Tejas Upadhyay
2024-08-08 19:51 ` Matt Roper
2024-08-09 8:55 ` Matthew Auld
2024-08-09 9:11 ` Upadhyay, Tejas
2024-08-09 9:21 ` Matthew Auld
2024-08-09 10:32 ` Upadhyay, Tejas
2024-08-14 6:15 ` Upadhyay, Tejas
2024-08-08 9:28 ` [PATCH 2/2] drm/xe: Write all slices if its mcr register Tejas Upadhyay
2024-08-08 9:46 ` ✓ CI.Patch_applied: success for Shuffle enable_host_l2_vram order and use MCR reg Patchwork
2024-08-08 9:46 ` ✓ CI.checkpatch: " Patchwork
2024-08-08 9:47 ` ✓ CI.KUnit: " Patchwork
2024-08-08 9:59 ` ✓ CI.Build: " Patchwork
2024-08-08 10:02 ` ✓ CI.Hooks: " Patchwork
2024-08-08 10:03 ` ✓ CI.checksparse: " Patchwork
2024-08-08 10:24 ` ✓ CI.BAT: " Patchwork
2024-08-08 13:23 ` ✓ CI.FULL: " Patchwork
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