From: Tejas Upadhyay <tejas.upadhyay@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Matthew Auld <matthew.auld@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>,
Tejas Upadhyay <tejas.upadhyay@intel.com>,
Matt Roper <matthew.d.roper@intel.com>
Subject: [PATCH 2/2] drm/xe: Write all slices if its mcr register
Date: Thu, 8 Aug 2024 14:58:26 +0530 [thread overview]
Message-ID: <20240808092826.585276-3-tejas.upadhyay@intel.com> (raw)
In-Reply-To: <20240808092826.585276-1-tejas.upadhyay@intel.com>
Register GAMREQSTRM_CTRL should be considered mcr register
which should write to all slices as per documentation.
Bspec: 71185
Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
drivers/gpu/drm/xe/xe_gt.c | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 2c8c4d4218db..41b70073e18d 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -83,7 +83,7 @@
#define STATELESS_COMPRESSION_CTRL XE_REG(0x4148)
#define UNIFIED_COMPRESSION_FORMAT REG_GENMASK(3, 0)
-#define XE2_GAMREQSTRM_CTRL XE_REG(0x4194)
+#define XE2_GAMREQSTRM_CTRL XE_REG_MCR(0x4194)
#define CG_DIS_CNTLBUS REG_BIT(6)
#define CCS_AUX_INV XE_REG(0x4208)
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 238c7d1053f0..224c137967c3 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -110,9 +110,9 @@ static void xe_gt_enable_host_l2_vram(struct xe_gt *gt)
if (!xe_gt_is_media_type(gt)) {
xe_mmio_write32(gt, SCRATCH1LPFC, EN_L3_RW_CCS_CACHE_FLUSH);
- reg = xe_mmio_read32(gt, XE2_GAMREQSTRM_CTRL);
+ reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL);
reg |= CG_DIS_CNTLBUS;
- xe_mmio_write32(gt, XE2_GAMREQSTRM_CTRL, reg);
+ xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg);
}
xe_gt_mcr_multicast_write(gt, XEHPC_L3CLOS_MASK(3), 0x3);
@@ -134,9 +134,9 @@ static void xe_gt_disable_host_l2_vram(struct xe_gt *gt)
if (WARN_ON(err))
return;
- reg = xe_mmio_read32(gt, XE2_GAMREQSTRM_CTRL);
+ reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL);
reg &= ~CG_DIS_CNTLBUS;
- xe_mmio_write32(gt, XE2_GAMREQSTRM_CTRL, reg);
+ xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg);
xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
}
--
2.25.1
next prev parent reply other threads:[~2024-08-08 9:26 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-08 9:28 [PATCH 0/2] Shuffle enable_host_l2_vram order and use MCR reg Tejas Upadhyay
2024-08-08 9:28 ` [PATCH 1/2] drm/xe: Init MCR before any mcr register read Tejas Upadhyay
2024-08-08 19:51 ` Matt Roper
2024-08-09 8:55 ` Matthew Auld
2024-08-09 9:11 ` Upadhyay, Tejas
2024-08-09 9:21 ` Matthew Auld
2024-08-09 10:32 ` Upadhyay, Tejas
2024-08-14 6:15 ` Upadhyay, Tejas
2024-08-08 9:28 ` Tejas Upadhyay [this message]
2024-08-08 9:46 ` ✓ CI.Patch_applied: success for Shuffle enable_host_l2_vram order and use MCR reg Patchwork
2024-08-08 9:46 ` ✓ CI.checkpatch: " Patchwork
2024-08-08 9:47 ` ✓ CI.KUnit: " Patchwork
2024-08-08 9:59 ` ✓ CI.Build: " Patchwork
2024-08-08 10:02 ` ✓ CI.Hooks: " Patchwork
2024-08-08 10:03 ` ✓ CI.checksparse: " Patchwork
2024-08-08 10:24 ` ✓ CI.BAT: " Patchwork
2024-08-08 13:23 ` ✓ CI.FULL: " Patchwork
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