From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: jani.nikula@linux.intel.com
Subject: [PATCH 3/5] drm/i915/cx0_phy_regs: Add C10 registers bits
Date: Tue, 13 Aug 2024 08:49:36 +0530 [thread overview]
Message-ID: <20240813031941.3553574-4-ankit.k.nautiyal@intel.com> (raw)
In-Reply-To: <20240813031941.3553574-1-ankit.k.nautiyal@intel.com>
Add C10 register bits to be used for computing HDMI PLLs with
algorithm.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index ab3ae110b68f..56443bf3e7cf 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -202,10 +202,34 @@
/* C10 Vendor Registers */
#define PHY_C10_VDR_PLL(idx) (0xC00 + (idx))
+#define C10_PLL0_SSC_EN REG_BIT8(0)
+#define C10_PLL0_DIVCLK_EN REG_BIT8(1)
+#define C10_PLL0_DIV5CLK_EN REG_BIT8(2)
+#define C10_PLL0_WORDDIV2_EN REG_BIT8(3)
#define C10_PLL0_FRACEN REG_BIT8(4)
+#define C10_PLL0_PMIX_EN REG_BIT8(5)
+#define C10_PLL0_ANA_FREQ_VCO_MASK REG_GENMASK8(7, 6)
+#define C10_PLL1_DIV_MULTIPLIER_MASK REG_GENMASK8(7, 0)
+#define C10_PLL2_MULTIPLIERL_MASK REG_GENMASK8(7, 0)
#define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
+#define C10_PLL8_SSC_UP_SPREAD REG_BIT(5)
+#define C10_PLL9_FRACN_DENL_MASK REG_GENMASK8(7, 0)
+#define C10_PLL10_FRACN_DENH_MASK REG_GENMASK8(7, 0)
+#define C10_PLL11_FRACN_QUOT_L_MASK REG_GENMASK8(7, 0)
+#define C10_PLL12_FRACN_QUOT_H_MASK REG_GENMASK8(7, 0)
+#define C10_PLL13_FRACN_REM_L_MASK REG_GENMASK8(7, 0)
+#define C10_PLL14_FRACN_REM_H_MASK REG_GENMASK8(7, 0)
#define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
#define C10_PLL15_HDMIDIV_MASK REG_GENMASK8(5, 3)
+#define C10_PLL15_PIXELCLKDIV_MASK REG_GENMASK8(7, 6)
+#define C10_PLL16_ANA_CPINT REG_GENMASK8(6, 0)
+#define C10_PLL16_ANA_CPINTGS_L REG_BIT(7)
+#define C10_PLL17_ANA_CPINTGS_H_MASK REG_GENMASK8(5, 0)
+#define C10_PLL17_ANA_CPPROP_L_MASK REG_GENMASK8(7, 6)
+#define C10_PLL18_ANA_CPPROP_H_MASK REG_GENMASK8(4, 0)
+#define C10_PLL18_ANA_CPPROPGS_L_MASK REG_GENMASK8(7, 5)
+#define C10_PLL19_ANA_CPPROPGS_H_MASK REG_GENMASK8(3, 0)
+#define C10_PLL19_ANA_V2I_MASK REG_GENMASK8(5, 4)
#define PHY_C10_VDR_CMN(idx) (0xC20 + (idx))
#define C10_CMN0_REF_RANGE REG_FIELD_PREP(REG_GENMASK(4, 0), 1)
--
2.45.2
next prev parent reply other threads:[~2024-08-13 3:18 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-13 3:19 [PATCH 0/5] Add HDMI PLL Algorithm for SNPS/C10PHY Ankit Nautiyal
2024-08-13 3:19 ` [PATCH 1/5] drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2 Ankit Nautiyal
2024-08-16 12:44 ` kernel test robot
2025-01-10 5:46 ` Kandpal, Suraj
2025-01-19 17:43 ` Nautiyal, Ankit K
2024-08-13 3:19 ` [PATCH 2/5] drm/i915/snps_phy: Use " Ankit Nautiyal
2025-01-10 5:48 ` Kandpal, Suraj
2024-08-13 3:19 ` Ankit Nautiyal [this message]
2025-01-10 5:50 ` [PATCH 3/5] drm/i915/cx0_phy_regs: Add C10 registers bits Kandpal, Suraj
2024-08-13 3:19 ` [PATCH 4/5] drm/i915/intel_snps_hdmi_pll: Compute C10 HDMI PLLs with algorithm Ankit Nautiyal
2025-01-10 5:55 ` Kandpal, Suraj
2024-08-13 3:19 ` [PATCH 5/5] drm/i915/cx0_phy: Use HDMI PLL algorithm for C10 PHY Ankit Nautiyal
2025-01-10 6:24 ` Kandpal, Suraj
2024-08-13 3:24 ` ✓ CI.Patch_applied: success for Add HDMI PLL Algorithm for SNPS/C10PHY (rev3) Patchwork
2024-08-13 3:24 ` ✗ CI.checkpatch: warning " Patchwork
2024-08-13 3:25 ` ✓ CI.KUnit: success " Patchwork
2024-08-13 3:37 ` ✓ CI.Build: " Patchwork
2024-08-13 3:40 ` ✓ CI.Hooks: " Patchwork
2024-08-13 3:41 ` ✗ CI.checksparse: warning " Patchwork
2024-08-13 4:03 ` ✓ CI.BAT: success " Patchwork
2024-08-13 7:02 ` ✗ CI.FULL: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2025-01-20 4:21 [PATCH 0/5] Add HDMI PLL Algorithm for SNPS/C10PHY Ankit Nautiyal
2025-01-20 4:21 ` [PATCH 3/5] drm/i915/cx0_phy_regs: Add C10 registers bits Ankit Nautiyal
2025-01-22 11:10 ` Jani Nikula
2025-01-22 16:28 ` Ankit Nautiyal
2024-08-06 12:58 [PATCH 0/5] Add HDMI PLL Algorithm for SNPS/C10PHY Ankit Nautiyal
2024-08-06 12:58 ` [PATCH 3/5] drm/i915/cx0_phy_regs: Add C10 registers bits Ankit Nautiyal
2024-06-26 5:00 [PATCH 0/5] Add HDMI PLL Algorithm for SNPS/C10PHY Ankit Nautiyal
2024-06-26 5:00 ` [PATCH 3/5] drm/i915/cx0_phy_regs: Add C10 registers bits Ankit Nautiyal
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