Re: [PATCH 3/5] drm/i915/cx0_phy_regs: Add C10 registers bits

[Jani Nikula <jani.nikula@linux.intel.com>]

On Mon, 20 Jan 2025, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> Add C10 register bits to be used for computing HDMI PLLs with
> algorithm.
>
> v2: Add bspec reference. (Suraj)
>
> Bspec: 74166
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_cx0_phy_regs.h | 24 +++++++++++++++++++
>  1 file changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index 91eb1d423c71..da27cff878a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -218,10 +218,34 @@
>  
>  /* C10 Vendor Registers */
>  #define PHY_C10_VDR_PLL(idx)		(0xC00 + (idx))
> +#define   C10_PLL0_SSC_EN		REG_BIT8(0)
> +#define   C10_PLL0_DIVCLK_EN		REG_BIT8(1)
> +#define   C10_PLL0_DIV5CLK_EN		REG_BIT8(2)
> +#define   C10_PLL0_WORDDIV2_EN		REG_BIT8(3)
>  #define   C10_PLL0_FRACEN		REG_BIT8(4)
> +#define   C10_PLL0_PMIX_EN		REG_BIT8(5)
> +#define   C10_PLL0_ANA_FREQ_VCO_MASK	REG_GENMASK8(7, 6)
> +#define   C10_PLL1_DIV_MULTIPLIER_MASK	REG_GENMASK8(7, 0)
> +#define   C10_PLL2_MULTIPLIERL_MASK	REG_GENMASK8(7, 0)
>  #define   C10_PLL3_MULTIPLIERH_MASK	REG_GENMASK8(3, 0)
> +#define   C10_PLL8_SSC_UP_SPREAD	REG_BIT(5)

All of the reg bits and masks should use the same width, i.e. REG_BIT8()
here.

> +#define   C10_PLL9_FRACN_DENL_MASK	REG_GENMASK8(7, 0)
> +#define   C10_PLL10_FRACN_DENH_MASK	REG_GENMASK8(7, 0)
> +#define   C10_PLL11_FRACN_QUOT_L_MASK	REG_GENMASK8(7, 0)
> +#define   C10_PLL12_FRACN_QUOT_H_MASK	REG_GENMASK8(7, 0)
> +#define   C10_PLL13_FRACN_REM_L_MASK	REG_GENMASK8(7, 0)
> +#define   C10_PLL14_FRACN_REM_H_MASK	REG_GENMASK8(7, 0)
>  #define   C10_PLL15_TXCLKDIV_MASK	REG_GENMASK8(2, 0)
>  #define   C10_PLL15_HDMIDIV_MASK	REG_GENMASK8(5, 3)
> +#define   C10_PLL15_PIXELCLKDIV_MASK	REG_GENMASK8(7, 6)
> +#define   C10_PLL16_ANA_CPINT		REG_GENMASK8(6, 0)
> +#define   C10_PLL16_ANA_CPINTGS_L	REG_BIT(7)

Ditto.

> +#define   C10_PLL17_ANA_CPINTGS_H_MASK	REG_GENMASK8(5, 0)
> +#define   C10_PLL17_ANA_CPPROP_L_MASK	REG_GENMASK8(7, 6)
> +#define   C10_PLL18_ANA_CPPROP_H_MASK	REG_GENMASK8(4, 0)
> +#define   C10_PLL18_ANA_CPPROPGS_L_MASK	REG_GENMASK8(7, 5)
> +#define   C10_PLL19_ANA_CPPROPGS_H_MASK	REG_GENMASK8(3, 0)
> +#define   C10_PLL19_ANA_V2I_MASK	REG_GENMASK8(5, 4)
>  
>  #define PHY_C10_VDR_CMN(idx)		(0xC20 + (idx))
>  #define   C10_CMN0_REF_RANGE		REG_FIELD_PREP(REG_GENMASK(4, 0), 1)

-- 
Jani Nikula, Intel