* [PATCH 0/6] drm/i915: Some intel_display conversions
@ 2024-09-06 14:33 Ville Syrjala
2024-09-06 14:33 ` [PATCH 1/6] drm/i915/cdclk: Add missing braces Ville Syrjala
` (13 more replies)
0 siblings, 14 replies; 24+ messages in thread
From: Ville Syrjala @ 2024-09-06 14:33 UTC (permalink / raw)
To: intel-gfx; +Cc: intel-xe
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
I somehow ended up in the power domains code and decided
to see how much of it could be converted to use struct
intel_display. The result was still too messy but at least
I managed to convert some of the dependecies in somewhat
decent way. Here they are.
Ville Syrjälä (6):
drm/i915/cdclk: Add missing braces
drm/i915/cdclk: Convert CDCLK code to intel_display
drm/i915/power: Convert low level DC state code to intel_display
drm/i915/vga: Convert VGA code to intel_display
drm/i915/power: Convert "i830 power well" code to intel_display
drm/i915/dmc: Convert DMC code to intel_display
drivers/gpu/drm/i915/display/intel_cdclk.c | 1171 +++++++++--------
drivers/gpu/drm/i915/display/intel_cdclk.h | 24 +-
drivers/gpu/drm/i915/display/intel_display.c | 86 +-
drivers/gpu/drm/i915/display/intel_display.h | 5 +-
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../drm/i915/display/intel_display_device.c | 2 +-
.../drm/i915/display/intel_display_driver.c | 34 +-
.../drm/i915/display/intel_display_power.c | 93 +-
.../i915/display/intel_display_power_well.c | 238 ++--
.../i915/display/intel_display_power_well.h | 15 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 391 +++---
drivers/gpu/drm/i915/display/intel_dmc.h | 26 +-
drivers/gpu/drm/i915/display/intel_dmc_wl.c | 4 +-
.../drm/i915/display/intel_modeset_setup.c | 3 +-
drivers/gpu/drm/i915/display/intel_vga.c | 45 +-
drivers/gpu/drm/i915/display/intel_vga.h | 14 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 3 +-
drivers/gpu/drm/i915/i915_driver.c | 6 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/i915_suspend.c | 3 +-
drivers/gpu/drm/xe/display/xe_display.c | 4 +-
21 files changed, 1137 insertions(+), 1036 deletions(-)
--
2.44.2
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH 1/6] drm/i915/cdclk: Add missing braces 2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala @ 2024-09-06 14:33 ` Ville Syrjala 2024-09-06 15:10 ` Rodrigo Vivi 2024-09-06 15:19 ` Jani Nikula 2024-09-06 14:33 ` [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display Ville Syrjala ` (12 subsequent siblings) 13 siblings, 2 replies; 24+ messages in thread From: Ville Syrjala @ 2024-09-06 14:33 UTC (permalink / raw) To: intel-gfx; +Cc: intel-xe From: Ville Syrjälä <ville.syrjala@linux.intel.com> CodingStyle says when one branch of an if ladder is braced then all of them should be. Make it so. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 66964c7d2a2c..9d870d15d888 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2053,8 +2053,9 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, dg2_cdclk_squash_program(dev_priv, 0); icl_cdclk_pll_update(dev_priv, vco); - } else + } else { bxt_cdclk_pll_update(dev_priv, vco); + } if (HAS_CDCLK_SQUASH(dev_priv)) { u16 waveform = cdclk_squash_waveform(dev_priv, cdclk); -- 2.44.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 1/6] drm/i915/cdclk: Add missing braces 2024-09-06 14:33 ` [PATCH 1/6] drm/i915/cdclk: Add missing braces Ville Syrjala @ 2024-09-06 15:10 ` Rodrigo Vivi 2024-09-06 15:19 ` Jani Nikula 1 sibling, 0 replies; 24+ messages in thread From: Rodrigo Vivi @ 2024-09-06 15:10 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx, intel-xe On Fri, Sep 06, 2024 at 05:33:01PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > CodingStyle says when one branch of an if ladder is braced > then all of them should be. Make it so. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 66964c7d2a2c..9d870d15d888 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2053,8 +2053,9 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, > dg2_cdclk_squash_program(dev_priv, 0); > > icl_cdclk_pll_update(dev_priv, vco); > - } else > + } else { > bxt_cdclk_pll_update(dev_priv, vco); > + } > > if (HAS_CDCLK_SQUASH(dev_priv)) { > u16 waveform = cdclk_squash_waveform(dev_priv, cdclk); > -- > 2.44.2 > ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 1/6] drm/i915/cdclk: Add missing braces 2024-09-06 14:33 ` [PATCH 1/6] drm/i915/cdclk: Add missing braces Ville Syrjala 2024-09-06 15:10 ` Rodrigo Vivi @ 2024-09-06 15:19 ` Jani Nikula 1 sibling, 0 replies; 24+ messages in thread From: Jani Nikula @ 2024-09-06 15:19 UTC (permalink / raw) To: Ville Syrjala, intel-gfx; +Cc: intel-xe On Fri, 06 Sep 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > CodingStyle says when one branch of an if ladder is braced > then all of them should be. Make it so. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 66964c7d2a2c..9d870d15d888 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -2053,8 +2053,9 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, > dg2_cdclk_squash_program(dev_priv, 0); > > icl_cdclk_pll_update(dev_priv, vco); > - } else > + } else { > bxt_cdclk_pll_update(dev_priv, vco); > + } > > if (HAS_CDCLK_SQUASH(dev_priv)) { > u16 waveform = cdclk_squash_waveform(dev_priv, cdclk); -- Jani Nikula, Intel ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display 2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala 2024-09-06 14:33 ` [PATCH 1/6] drm/i915/cdclk: Add missing braces Ville Syrjala @ 2024-09-06 14:33 ` Ville Syrjala 2024-09-06 15:09 ` Rodrigo Vivi 2024-09-06 15:18 ` Jani Nikula 2024-09-06 14:33 ` [PATCH 3/6] drm/i915/power: Convert low level DC state " Ville Syrjala ` (11 subsequent siblings) 13 siblings, 2 replies; 24+ messages in thread From: Ville Syrjala @ 2024-09-06 14:33 UTC (permalink / raw) To: intel-gfx; +Cc: intel-xe From: Ville Syrjälä <ville.syrjala@linux.intel.com> struct intel_display will replace struct drm_i915_private as the main thing for display code. Convert the CDCLK code to use it (as much as possible at this stage). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 1168 +++++++++-------- drivers/gpu/drm/i915/display/intel_cdclk.h | 24 +- .../drm/i915/display/intel_display_debugfs.c | 2 +- .../drm/i915/display/intel_display_device.c | 2 +- .../drm/i915/display/intel_display_driver.c | 17 +- .../drm/i915/display/intel_display_power.c | 35 +- .../i915/display/intel_display_power_well.c | 9 +- drivers/gpu/drm/i915/display/skl_watermark.c | 3 +- 8 files changed, 657 insertions(+), 603 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 9d870d15d888..b4eda0a2a45d 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -113,81 +113,81 @@ */ struct intel_cdclk_funcs { - void (*get_cdclk)(struct drm_i915_private *i915, + void (*get_cdclk)(struct intel_display *display, struct intel_cdclk_config *cdclk_config); - void (*set_cdclk)(struct drm_i915_private *i915, + void (*set_cdclk)(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, enum pipe pipe); int (*modeset_calc_cdclk)(struct intel_atomic_state *state); u8 (*calc_voltage_level)(int cdclk); }; -void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, +void intel_cdclk_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { - dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); + display->funcs.cdclk->get_cdclk(display, cdclk_config); } -static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv, +static void intel_cdclk_set_cdclk(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { - dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); + display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); } static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); - return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(state); + return display->funcs.cdclk->modeset_calc_cdclk(state); } -static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv, +static u8 intel_cdclk_calc_voltage_level(struct intel_display *display, int cdclk) { - return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); + return display->funcs.cdclk->calc_voltage_level(cdclk); } -static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, +static void fixed_133mhz_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { cdclk_config->cdclk = 133333; } -static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, +static void fixed_200mhz_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { cdclk_config->cdclk = 200000; } -static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, +static void fixed_266mhz_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { cdclk_config->cdclk = 266667; } -static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, +static void fixed_333mhz_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { cdclk_config->cdclk = 333333; } -static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, +static void fixed_400mhz_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { cdclk_config->cdclk = 400000; } -static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, +static void fixed_450mhz_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { cdclk_config->cdclk = 450000; } -static void i85x_get_cdclk(struct drm_i915_private *dev_priv, +static void i85x_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); + struct pci_dev *pdev = to_pci_dev(display->drm->dev); u16 hpllcc = 0; /* @@ -226,10 +226,10 @@ static void i85x_get_cdclk(struct drm_i915_private *dev_priv, } } -static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, +static void i915gm_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); + struct pci_dev *pdev = to_pci_dev(display->drm->dev); u16 gcfgc = 0; pci_read_config_word(pdev, GCFGC, &gcfgc); @@ -250,10 +250,10 @@ static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, } } -static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, +static void i945gm_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); + struct pci_dev *pdev = to_pci_dev(display->drm->dev); u16 gcfgc = 0; pci_read_config_word(pdev, GCFGC, &gcfgc); @@ -274,7 +274,7 @@ static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, } } -static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) +static unsigned int intel_hpll_vco(struct intel_display *display) { static const unsigned int blb_vco[8] = { [0] = 3200000, @@ -313,6 +313,7 @@ static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) [4] = 2666667, [5] = 4266667, }; + struct drm_i915_private *dev_priv = to_i915(display->drm); const unsigned int *vco_table; unsigned int vco; u8 tmp = 0; @@ -331,23 +332,23 @@ static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) else return 0; - tmp = intel_de_read(dev_priv, + tmp = intel_de_read(display, IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); vco = vco_table[tmp & 0x7]; if (vco == 0) - drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", + drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); else - drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); + drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco); return vco; } -static void g33_get_cdclk(struct drm_i915_private *dev_priv, +static void g33_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); + struct pci_dev *pdev = to_pci_dev(display->drm->dev); static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; @@ -356,7 +357,7 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv, unsigned int cdclk_sel; u16 tmp = 0; - cdclk_config->vco = intel_hpll_vco(dev_priv); + cdclk_config->vco = intel_hpll_vco(display); pci_read_config_word(pdev, GCFGC, &tmp); @@ -387,16 +388,16 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv, return; fail: - drm_err(&dev_priv->drm, + drm_err(display->drm, "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", cdclk_config->vco, tmp); cdclk_config->cdclk = 190476; } -static void pnv_get_cdclk(struct drm_i915_private *dev_priv, +static void pnv_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); + struct pci_dev *pdev = to_pci_dev(display->drm->dev); u16 gcfgc = 0; pci_read_config_word(pdev, GCFGC, &gcfgc); @@ -415,7 +416,7 @@ static void pnv_get_cdclk(struct drm_i915_private *dev_priv, cdclk_config->cdclk = 200000; break; default: - drm_err(&dev_priv->drm, + drm_err(display->drm, "Unknown pnv display core clock 0x%04x\n", gcfgc); fallthrough; case GC_DISPLAY_CLOCK_133_MHZ_PNV: @@ -427,10 +428,10 @@ static void pnv_get_cdclk(struct drm_i915_private *dev_priv, } } -static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, +static void i965gm_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); + struct pci_dev *pdev = to_pci_dev(display->drm->dev); static const u8 div_3200[] = { 16, 10, 8 }; static const u8 div_4000[] = { 20, 12, 10 }; static const u8 div_5333[] = { 24, 16, 14 }; @@ -438,7 +439,7 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, unsigned int cdclk_sel; u16 tmp = 0; - cdclk_config->vco = intel_hpll_vco(dev_priv); + cdclk_config->vco = intel_hpll_vco(display); pci_read_config_word(pdev, GCFGC, &tmp); @@ -466,20 +467,20 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, return; fail: - drm_err(&dev_priv->drm, + drm_err(display->drm, "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", cdclk_config->vco, tmp); cdclk_config->cdclk = 200000; } -static void gm45_get_cdclk(struct drm_i915_private *dev_priv, +static void gm45_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); + struct pci_dev *pdev = to_pci_dev(display->drm->dev); unsigned int cdclk_sel; u16 tmp = 0; - cdclk_config->vco = intel_hpll_vco(dev_priv); + cdclk_config->vco = intel_hpll_vco(display); pci_read_config_word(pdev, GCFGC, &tmp); @@ -495,7 +496,7 @@ static void gm45_get_cdclk(struct drm_i915_private *dev_priv, cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; break; default: - drm_err(&dev_priv->drm, + drm_err(display->drm, "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", cdclk_config->vco, tmp); cdclk_config->cdclk = 222222; @@ -503,15 +504,16 @@ static void gm45_get_cdclk(struct drm_i915_private *dev_priv, } } -static void hsw_get_cdclk(struct drm_i915_private *dev_priv, +static void hsw_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { - u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); + struct drm_i915_private *dev_priv = to_i915(display->drm); + u32 lcpll = intel_de_read(display, LCPLL_CTL); u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; if (lcpll & LCPLL_CD_SOURCE_FCLK) cdclk_config->cdclk = 800000; - else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) + else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) cdclk_config->cdclk = 450000; else if (freq == LCPLL_CLK_FREQ_450) cdclk_config->cdclk = 450000; @@ -521,8 +523,9 @@ static void hsw_get_cdclk(struct drm_i915_private *dev_priv, cdclk_config->cdclk = 540000; } -static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) +static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk) { + struct drm_i915_private *dev_priv = to_i915(display->drm); int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; @@ -541,8 +544,10 @@ static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) return 200000; } -static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) +static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) { + struct drm_i915_private *dev_priv = to_i915(display->drm); + if (IS_VALLEYVIEW(dev_priv)) { if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ return 2; @@ -560,9 +565,10 @@ static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) } } -static void vlv_get_cdclk(struct drm_i915_private *dev_priv, +static void vlv_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { + struct drm_i915_private *dev_priv = to_i915(display->drm); u32 val; vlv_iosf_sb_get(dev_priv, @@ -586,8 +592,9 @@ static void vlv_get_cdclk(struct drm_i915_private *dev_priv, DSPFREQGUAR_SHIFT_CHV; } -static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) +static void vlv_program_pfi_credits(struct intel_display *display) { + struct drm_i915_private *dev_priv = to_i915(display->drm); unsigned int credits, default_credits; if (IS_CHERRYVIEW(dev_priv)) @@ -595,7 +602,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) else default_credits = PFI_CREDIT(8); - if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { + if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) { /* CHV suggested value is 31 or 63 */ if (IS_CHERRYVIEW(dev_priv)) credits = PFI_CREDIT_63; @@ -609,24 +616,25 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) * WA - write default credits before re-programming * FIXME: should we also set the resend bit here? */ - intel_de_write(dev_priv, GCI_CONTROL, + intel_de_write(display, GCI_CONTROL, VGA_FAST_MODE_DISABLE | default_credits); - intel_de_write(dev_priv, GCI_CONTROL, + intel_de_write(display, GCI_CONTROL, VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); /* * FIXME is this guaranteed to clear * immediately or should we poll for it? */ - drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); + drm_WARN_ON(display->drm, + intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND); } -static void vlv_set_cdclk(struct drm_i915_private *dev_priv, +static void vlv_set_cdclk(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { + struct drm_i915_private *dev_priv = to_i915(display->drm); int cdclk = cdclk_config->cdclk; u32 val, cmd = cdclk_config->voltage_level; intel_wakeref_t wakeref; @@ -663,7 +671,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 50)) { - drm_err(&dev_priv->drm, + drm_err(display->drm, "timed out waiting for CDclk change\n"); } @@ -682,7 +690,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 50)) - drm_err(&dev_priv->drm, + drm_err(display->drm, "timed out waiting for CDclk change\n"); } @@ -705,17 +713,18 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, BIT(VLV_IOSF_SB_BUNIT) | BIT(VLV_IOSF_SB_PUNIT)); - intel_update_cdclk(dev_priv); + intel_update_cdclk(display); - vlv_program_pfi_credits(dev_priv); + vlv_program_pfi_credits(display); intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); } -static void chv_set_cdclk(struct drm_i915_private *dev_priv, +static void chv_set_cdclk(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { + struct drm_i915_private *dev_priv = to_i915(display->drm); int cdclk = cdclk_config->cdclk; u32 val, cmd = cdclk_config->voltage_level; intel_wakeref_t wakeref; @@ -747,15 +756,15 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv, if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 50)) { - drm_err(&dev_priv->drm, + drm_err(display->drm, "timed out waiting for CDclk change\n"); } vlv_punit_put(dev_priv); - intel_update_cdclk(dev_priv); + intel_update_cdclk(display); - vlv_program_pfi_credits(dev_priv); + vlv_program_pfi_credits(display); intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); } @@ -787,15 +796,15 @@ static u8 bdw_calc_voltage_level(int cdclk) } } -static void bdw_get_cdclk(struct drm_i915_private *dev_priv, +static void bdw_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { - u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); + u32 lcpll = intel_de_read(display, LCPLL_CTL); u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; if (lcpll & LCPLL_CD_SOURCE_FCLK) cdclk_config->cdclk = 800000; - else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) + else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) cdclk_config->cdclk = 450000; else if (freq == LCPLL_CLK_FREQ_450) cdclk_config->cdclk = 450000; @@ -831,15 +840,16 @@ static u32 bdw_cdclk_freq_sel(int cdclk) } } -static void bdw_set_cdclk(struct drm_i915_private *dev_priv, +static void bdw_set_cdclk(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { + struct drm_i915_private *dev_priv = to_i915(display->drm); int cdclk = cdclk_config->cdclk; int ret; - if (drm_WARN(&dev_priv->drm, - (intel_de_read(dev_priv, LCPLL_CTL) & + if (drm_WARN(display->drm, + (intel_de_read(display, LCPLL_CTL) & (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | @@ -849,39 +859,39 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); if (ret) { - drm_err(&dev_priv->drm, + drm_err(display->drm, "failed to inform pcode about cdclk change\n"); return; } - intel_de_rmw(dev_priv, LCPLL_CTL, + intel_de_rmw(display, LCPLL_CTL, 0, LCPLL_CD_SOURCE_FCLK); /* * According to the spec, it should be enough to poll for this 1 us. * However, extensive testing shows that this can take longer. */ - if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & + if (wait_for_us(intel_de_read(display, LCPLL_CTL) & LCPLL_CD_SOURCE_FCLK_DONE, 100)) - drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); + drm_err(display->drm, "Switching to FCLK failed\n"); - intel_de_rmw(dev_priv, LCPLL_CTL, + intel_de_rmw(display, LCPLL_CTL, LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); - intel_de_rmw(dev_priv, LCPLL_CTL, + intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0); - if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & + if (wait_for_us((intel_de_read(display, LCPLL_CTL) & LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) - drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); + drm_err(display->drm, "Switching back to LCPLL failed\n"); snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, cdclk_config->voltage_level); - intel_de_write(dev_priv, CDCLK_FREQ, + intel_de_write(display, CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); - intel_update_cdclk(dev_priv); + intel_update_cdclk(display); } static int skl_calc_cdclk(int min_cdclk, int vco) @@ -919,7 +929,7 @@ static u8 skl_calc_voltage_level(int cdclk) return 0; } -static void skl_dpll0_update(struct drm_i915_private *dev_priv, +static void skl_dpll0_update(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { u32 val; @@ -927,16 +937,16 @@ static void skl_dpll0_update(struct drm_i915_private *dev_priv, cdclk_config->ref = 24000; cdclk_config->vco = 0; - val = intel_de_read(dev_priv, LCPLL1_CTL); + val = intel_de_read(display, LCPLL1_CTL); if ((val & LCPLL_PLL_ENABLE) == 0) return; - if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) + if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0)) return; - val = intel_de_read(dev_priv, DPLL_CTRL1); + val = intel_de_read(display, DPLL_CTRL1); - if (drm_WARN_ON(&dev_priv->drm, + if (drm_WARN_ON(display->drm, (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != @@ -960,19 +970,19 @@ static void skl_dpll0_update(struct drm_i915_private *dev_priv, } } -static void skl_get_cdclk(struct drm_i915_private *dev_priv, +static void skl_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { u32 cdctl; - skl_dpll0_update(dev_priv, cdclk_config); + skl_dpll0_update(display, cdclk_config); cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; if (cdclk_config->vco == 0) goto out; - cdctl = intel_de_read(dev_priv, CDCLK_CTL); + cdctl = intel_de_read(display, CDCLK_CTL); if (cdclk_config->vco == 8640000) { switch (cdctl & CDCLK_FREQ_SEL_MASK) { @@ -1027,19 +1037,19 @@ static int skl_cdclk_decimal(int cdclk) return DIV_ROUND_CLOSEST(cdclk - 1000, 500); } -static void skl_set_preferred_cdclk_vco(struct drm_i915_private *i915, int vco) +static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco) { - bool changed = i915->display.cdclk.skl_preferred_vco_freq != vco; + bool changed = display->cdclk.skl_preferred_vco_freq != vco; - i915->display.cdclk.skl_preferred_vco_freq = vco; + display->cdclk.skl_preferred_vco_freq = vco; if (changed) - intel_update_max_cdclk(i915); + intel_update_max_cdclk(display); } -static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) +static u32 skl_dpll0_link_rate(struct intel_display *display, int vco) { - drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); + drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); /* * We always enable DPLL0 with the lowest link rate possible, but still @@ -1056,47 +1066,47 @@ static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); } -static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) +static void skl_dpll0_enable(struct intel_display *display, int vco) { - intel_de_rmw(dev_priv, DPLL_CTRL1, + intel_de_rmw(display, DPLL_CTRL1, DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | - skl_dpll0_link_rate(dev_priv, vco)); - intel_de_posting_read(dev_priv, DPLL_CTRL1); + skl_dpll0_link_rate(display, vco)); + intel_de_posting_read(display, DPLL_CTRL1); - intel_de_rmw(dev_priv, LCPLL1_CTL, + intel_de_rmw(display, LCPLL1_CTL, 0, LCPLL_PLL_ENABLE); - if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) - drm_err(&dev_priv->drm, "DPLL0 not locked\n"); + if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) + drm_err(display->drm, "DPLL0 not locked\n"); - dev_priv->display.cdclk.hw.vco = vco; + display->cdclk.hw.vco = vco; /* We'll want to keep using the current vco from now on. */ - skl_set_preferred_cdclk_vco(dev_priv, vco); + skl_set_preferred_cdclk_vco(display, vco); } -static void skl_dpll0_disable(struct drm_i915_private *dev_priv) +static void skl_dpll0_disable(struct intel_display *display) { - intel_de_rmw(dev_priv, LCPLL1_CTL, + intel_de_rmw(display, LCPLL1_CTL, LCPLL_PLL_ENABLE, 0); - if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) - drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); + if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) + drm_err(display->drm, "Couldn't disable DPLL0\n"); - dev_priv->display.cdclk.hw.vco = 0; + display->cdclk.hw.vco = 0; } -static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv, +static u32 skl_cdclk_freq_sel(struct intel_display *display, int cdclk, int vco) { switch (cdclk) { default: - drm_WARN_ON(&dev_priv->drm, - cdclk != dev_priv->display.cdclk.hw.bypass); - drm_WARN_ON(&dev_priv->drm, vco != 0); + drm_WARN_ON(display->drm, + cdclk != display->cdclk.hw.bypass); + drm_WARN_ON(display->drm, vco != 0); fallthrough; case 308571: case 337500: @@ -1112,10 +1122,11 @@ static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv, } } -static void skl_set_cdclk(struct drm_i915_private *dev_priv, +static void skl_set_cdclk(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { + struct drm_i915_private *dev_priv = to_i915(display->drm); int cdclk = cdclk_config->cdclk; int vco = cdclk_config->vco; u32 freq_select, cdclk_ctl; @@ -1129,7 +1140,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, * use the corresponding VCO freq as that always leads to using the * minimum 308MHz CDCLK. */ - drm_WARN_ON_ONCE(&dev_priv->drm, + drm_WARN_ON_ONCE(display->drm, IS_SKYLAKE(dev_priv) && vco == 8640000); ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, @@ -1137,54 +1148,54 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, SKL_CDCLK_READY_FOR_CHANGE, SKL_CDCLK_READY_FOR_CHANGE, 3); if (ret) { - drm_err(&dev_priv->drm, + drm_err(display->drm, "Failed to inform PCU about cdclk change (%d)\n", ret); return; } - freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); + freq_select = skl_cdclk_freq_sel(display, cdclk, vco); - if (dev_priv->display.cdclk.hw.vco != 0 && - dev_priv->display.cdclk.hw.vco != vco) - skl_dpll0_disable(dev_priv); + if (display->cdclk.hw.vco != 0 && + display->cdclk.hw.vco != vco) + skl_dpll0_disable(display); - cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); + cdclk_ctl = intel_de_read(display, CDCLK_CTL); - if (dev_priv->display.cdclk.hw.vco != vco) { + if (display->cdclk.hw.vco != vco) { /* Wa Display #1183: skl,kbl,cfl */ cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); - intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); + intel_de_write(display, CDCLK_CTL, cdclk_ctl); } /* Wa Display #1183: skl,kbl,cfl */ cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; - intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); - intel_de_posting_read(dev_priv, CDCLK_CTL); + intel_de_write(display, CDCLK_CTL, cdclk_ctl); + intel_de_posting_read(display, CDCLK_CTL); - if (dev_priv->display.cdclk.hw.vco != vco) - skl_dpll0_enable(dev_priv, vco); + if (display->cdclk.hw.vco != vco) + skl_dpll0_enable(display, vco); /* Wa Display #1183: skl,kbl,cfl */ cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); - intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); + intel_de_write(display, CDCLK_CTL, cdclk_ctl); cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); - intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); + intel_de_write(display, CDCLK_CTL, cdclk_ctl); /* Wa Display #1183: skl,kbl,cfl */ cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; - intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); - intel_de_posting_read(dev_priv, CDCLK_CTL); + intel_de_write(display, CDCLK_CTL, cdclk_ctl); + intel_de_posting_read(display, CDCLK_CTL); /* inform PCU of the change */ snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, cdclk_config->voltage_level); - intel_update_cdclk(dev_priv); + intel_update_cdclk(display); } -static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) +static void skl_sanitize_cdclk(struct intel_display *display) { u32 cdctl, expected; @@ -1193,15 +1204,15 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) * There is SWF18 scratchpad register defined which is set by the * pre-os which can be used by the OS drivers to check the status */ - if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) + if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) goto sanitize; - intel_update_cdclk(dev_priv); - intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); + intel_update_cdclk(display); + intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); /* Is PLL enabled and locked ? */ - if (dev_priv->display.cdclk.hw.vco == 0 || - dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) + if (display->cdclk.hw.vco == 0 || + display->cdclk.hw.cdclk == display->cdclk.hw.bypass) goto sanitize; /* DPLL okay; verify the cdclock @@ -1210,60 +1221,60 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) * decimal part is programmed wrong from BIOS where pre-os does not * enable display. Verify the same as well. */ - cdctl = intel_de_read(dev_priv, CDCLK_CTL); + cdctl = intel_de_read(display, CDCLK_CTL); expected = (cdctl & CDCLK_FREQ_SEL_MASK) | - skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); + skl_cdclk_decimal(display->cdclk.hw.cdclk); if (cdctl == expected) /* All well; nothing to sanitize */ return; sanitize: - drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); + drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); /* force cdclk programming */ - dev_priv->display.cdclk.hw.cdclk = 0; + display->cdclk.hw.cdclk = 0; /* force full PLL disable + enable */ - dev_priv->display.cdclk.hw.vco = ~0; + display->cdclk.hw.vco = ~0; } -static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) +static void skl_cdclk_init_hw(struct intel_display *display) { struct intel_cdclk_config cdclk_config; - skl_sanitize_cdclk(dev_priv); + skl_sanitize_cdclk(display); - if (dev_priv->display.cdclk.hw.cdclk != 0 && - dev_priv->display.cdclk.hw.vco != 0) { + if (display->cdclk.hw.cdclk != 0 && + display->cdclk.hw.vco != 0) { /* * Use the current vco as our initial * guess as to what the preferred vco is. */ - if (dev_priv->display.cdclk.skl_preferred_vco_freq == 0) - skl_set_preferred_cdclk_vco(dev_priv, - dev_priv->display.cdclk.hw.vco); + if (display->cdclk.skl_preferred_vco_freq == 0) + skl_set_preferred_cdclk_vco(display, + display->cdclk.hw.vco); return; } - cdclk_config = dev_priv->display.cdclk.hw; + cdclk_config = display->cdclk.hw; - cdclk_config.vco = dev_priv->display.cdclk.skl_preferred_vco_freq; + cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; if (cdclk_config.vco == 0) cdclk_config.vco = 8100000; cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); - skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); + skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); } -static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) +static void skl_cdclk_uninit_hw(struct intel_display *display) { - struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; + struct intel_cdclk_config cdclk_config = display->cdclk.hw; cdclk_config.cdclk = cdclk_config.bypass; cdclk_config.vco = 0; cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); - skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); + skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); } struct intel_cdclk_vals { @@ -1471,37 +1482,37 @@ static int cdclk_divider(int cdclk, int vco, u16 waveform) cdclk * cdclk_squash_len); } -static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) +static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk) { - const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; + const struct intel_cdclk_vals *table = display->cdclk.table; int i; for (i = 0; table[i].refclk; i++) - if (table[i].refclk == dev_priv->display.cdclk.hw.ref && + if (table[i].refclk == display->cdclk.hw.ref && table[i].cdclk >= min_cdclk) return table[i].cdclk; - drm_WARN(&dev_priv->drm, 1, + drm_WARN(display->drm, 1, "Cannot satisfy minimum cdclk %d with refclk %u\n", - min_cdclk, dev_priv->display.cdclk.hw.ref); + min_cdclk, display->cdclk.hw.ref); return 0; } -static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) +static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk) { - const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; + const struct intel_cdclk_vals *table = display->cdclk.table; int i; - if (cdclk == dev_priv->display.cdclk.hw.bypass) + if (cdclk == display->cdclk.hw.bypass) return 0; for (i = 0; table[i].refclk; i++) - if (table[i].refclk == dev_priv->display.cdclk.hw.ref && + if (table[i].refclk == display->cdclk.hw.ref && table[i].cdclk == cdclk) - return dev_priv->display.cdclk.hw.ref * table[i].ratio; + return display->cdclk.hw.ref * table[i].ratio; - drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", - cdclk, dev_priv->display.cdclk.hw.ref); + drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", + cdclk, display->cdclk.hw.ref); return 0; } @@ -1583,10 +1594,10 @@ static u8 rplu_calc_voltage_level(int cdclk) rplu_voltage_level_max_cdclk); } -static void icl_readout_refclk(struct drm_i915_private *dev_priv, +static void icl_readout_refclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { - u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; + u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; switch (dssm) { default: @@ -1604,19 +1615,20 @@ static void icl_readout_refclk(struct drm_i915_private *dev_priv, } } -static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, +static void bxt_de_pll_readout(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { + struct drm_i915_private *dev_priv = to_i915(display->drm); u32 val, ratio; if (IS_DG2(dev_priv)) cdclk_config->ref = 38400; - else if (DISPLAY_VER(dev_priv) >= 11) - icl_readout_refclk(dev_priv, cdclk_config); + else if (DISPLAY_VER(display) >= 11) + icl_readout_refclk(display, cdclk_config); else cdclk_config->ref = 19200; - val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); + val = intel_de_read(display, BXT_DE_PLL_ENABLE); if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || (val & BXT_DE_PLL_LOCK) == 0) { /* @@ -1631,26 +1643,26 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, * gen9lp had it in a separate PLL control register. */ - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) ratio = val & ICL_CDCLK_PLL_RATIO_MASK; else - ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; + ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; cdclk_config->vco = ratio * cdclk_config->ref; } -static void bxt_get_cdclk(struct drm_i915_private *dev_priv, +static void bxt_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config) { u32 squash_ctl = 0; u32 divider; int div; - bxt_de_pll_readout(dev_priv, cdclk_config); + bxt_de_pll_readout(display, cdclk_config); - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) cdclk_config->bypass = cdclk_config->ref / 2; - else if (DISPLAY_VER(dev_priv) >= 11) + else if (DISPLAY_VER(display) >= 11) cdclk_config->bypass = 50000; else cdclk_config->bypass = cdclk_config->ref; @@ -1660,7 +1672,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, goto out; } - divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; + divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; switch (divider) { case BXT_CDCLK_CD2X_DIV_SEL_1: @@ -1680,8 +1692,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, return; } - if (HAS_CDCLK_SQUASH(dev_priv)) - squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL); + if (HAS_CDCLK_SQUASH(display)) + squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL); if (squash_ctl & CDCLK_SQUASH_ENABLE) { u16 waveform; @@ -1697,107 +1709,107 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, } out: - if (DISPLAY_VER(dev_priv) >= 20) - cdclk_config->joined_mbus = intel_de_read(dev_priv, MBUS_CTL) & MBUS_JOIN; + if (DISPLAY_VER(display) >= 20) + cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; /* * Can't read this out :( Let's assume it's * at least what the CDCLK frequency requires. */ cdclk_config->voltage_level = - intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); + intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); } -static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) +static void bxt_de_pll_disable(struct intel_display *display) { - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); + intel_de_write(display, BXT_DE_PLL_ENABLE, 0); /* Timeout 200us */ - if (intel_de_wait_for_clear(dev_priv, + if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) - drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); + drm_err(display->drm, "timeout waiting for DE PLL unlock\n"); - dev_priv->display.cdclk.hw.vco = 0; + display->cdclk.hw.vco = 0; } -static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) +static void bxt_de_pll_enable(struct intel_display *display, int vco) { - int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); + int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); - intel_de_rmw(dev_priv, BXT_DE_PLL_CTL, + intel_de_rmw(display, BXT_DE_PLL_CTL, BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); + intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); /* Timeout 200us */ - if (intel_de_wait_for_set(dev_priv, + if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) - drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); + drm_err(display->drm, "timeout waiting for DE PLL lock\n"); - dev_priv->display.cdclk.hw.vco = vco; + display->cdclk.hw.vco = vco; } -static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv) +static void icl_cdclk_pll_disable(struct intel_display *display) { - intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE, + intel_de_rmw(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE, 0); /* Timeout 200us */ - if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) - drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); + if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) + drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n"); - dev_priv->display.cdclk.hw.vco = 0; + display->cdclk.hw.vco = 0; } -static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) +static void icl_cdclk_pll_enable(struct intel_display *display, int vco) { - int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); + int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); u32 val; val = ICL_CDCLK_PLL_RATIO(ratio); - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); + intel_de_write(display, BXT_DE_PLL_ENABLE, val); val |= BXT_DE_PLL_PLL_ENABLE; - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); + intel_de_write(display, BXT_DE_PLL_ENABLE, val); /* Timeout 200us */ - if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) - drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); + if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) + drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n"); - dev_priv->display.cdclk.hw.vco = vco; + display->cdclk.hw.vco = vco; } -static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) +static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco) { - int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); + int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); u32 val; /* Write PLL ratio without disabling */ val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); + intel_de_write(display, BXT_DE_PLL_ENABLE, val); /* Submit freq change request */ val |= BXT_DE_PLL_FREQ_REQ; - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); + intel_de_write(display, BXT_DE_PLL_ENABLE, val); /* Timeout 200us */ - if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, + if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) - drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n"); + drm_err(display->drm, "timeout waiting for FREQ change request ack\n"); val &= ~BXT_DE_PLL_FREQ_REQ; - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); + intel_de_write(display, BXT_DE_PLL_ENABLE, val); - dev_priv->display.cdclk.hw.vco = vco; + display->cdclk.hw.vco = vco; } -static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) +static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe) { - if (DISPLAY_VER(dev_priv) >= 12) { + if (DISPLAY_VER(display) >= 12) { if (pipe == INVALID_PIPE) return TGL_CDCLK_CD2X_PIPE_NONE; else return TGL_CDCLK_CD2X_PIPE(pipe); - } else if (DISPLAY_VER(dev_priv) >= 11) { + } else if (DISPLAY_VER(display) >= 11) { if (pipe == INVALID_PIPE) return ICL_CDCLK_CD2X_PIPE_NONE; else @@ -1810,15 +1822,15 @@ static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe } } -static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, +static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, int cdclk, int vco, u16 waveform) { /* cdclk = vco / 2 / div{1,1.5,2,4} */ switch (cdclk_divider(cdclk, vco, waveform)) { default: - drm_WARN_ON(&dev_priv->drm, - cdclk != dev_priv->display.cdclk.hw.bypass); - drm_WARN_ON(&dev_priv->drm, vco != 0); + drm_WARN_ON(display->drm, + cdclk != display->cdclk.hw.bypass); + drm_WARN_ON(display->drm, vco != 0); fallthrough; case 2: return BXT_CDCLK_CD2X_DIV_SEL_1; @@ -1831,47 +1843,47 @@ static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, } } -static u16 cdclk_squash_waveform(struct drm_i915_private *dev_priv, +static u16 cdclk_squash_waveform(struct intel_display *display, int cdclk) { - const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; + const struct intel_cdclk_vals *table = display->cdclk.table; int i; - if (cdclk == dev_priv->display.cdclk.hw.bypass) + if (cdclk == display->cdclk.hw.bypass) return 0; for (i = 0; table[i].refclk; i++) - if (table[i].refclk == dev_priv->display.cdclk.hw.ref && + if (table[i].refclk == display->cdclk.hw.ref && table[i].cdclk == cdclk) return table[i].waveform; - drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", - cdclk, dev_priv->display.cdclk.hw.ref); + drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", + cdclk, display->cdclk.hw.ref); return 0xffff; } -static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco) +static void icl_cdclk_pll_update(struct intel_display *display, int vco) { - if (i915->display.cdclk.hw.vco != 0 && - i915->display.cdclk.hw.vco != vco) - icl_cdclk_pll_disable(i915); + if (display->cdclk.hw.vco != 0 && + display->cdclk.hw.vco != vco) + icl_cdclk_pll_disable(display); - if (i915->display.cdclk.hw.vco != vco) - icl_cdclk_pll_enable(i915, vco); + if (display->cdclk.hw.vco != vco) + icl_cdclk_pll_enable(display, vco); } -static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco) +static void bxt_cdclk_pll_update(struct intel_display *display, int vco) { - if (i915->display.cdclk.hw.vco != 0 && - i915->display.cdclk.hw.vco != vco) - bxt_de_pll_disable(i915); + if (display->cdclk.hw.vco != 0 && + display->cdclk.hw.vco != vco) + bxt_de_pll_disable(display); - if (i915->display.cdclk.hw.vco != vco) - bxt_de_pll_enable(i915, vco); + if (display->cdclk.hw.vco != vco) + bxt_de_pll_enable(display, vco); } -static void dg2_cdclk_squash_program(struct drm_i915_private *i915, +static void dg2_cdclk_squash_program(struct intel_display *display, u16 waveform) { u32 squash_ctl = 0; @@ -1880,7 +1892,7 @@ static void dg2_cdclk_squash_program(struct drm_i915_private *i915, squash_ctl = CDCLK_SQUASH_ENABLE | CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; - intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl); + intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl); } static bool cdclk_pll_is_unknown(unsigned int vco) @@ -1893,38 +1905,40 @@ static bool cdclk_pll_is_unknown(unsigned int vco) return vco == ~0; } -static bool mdclk_source_is_cdclk_pll(struct drm_i915_private *i915) +static bool mdclk_source_is_cdclk_pll(struct intel_display *display) { - return DISPLAY_VER(i915) >= 20; + return DISPLAY_VER(display) >= 20; } -static u32 xe2lpd_mdclk_source_sel(struct drm_i915_private *i915) +static u32 xe2lpd_mdclk_source_sel(struct intel_display *display) { - if (mdclk_source_is_cdclk_pll(i915)) + if (mdclk_source_is_cdclk_pll(display)) return MDCLK_SOURCE_SEL_CDCLK_PLL; return MDCLK_SOURCE_SEL_CD2XCLK; } -int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915, +int intel_mdclk_cdclk_ratio(struct intel_display *display, const struct intel_cdclk_config *cdclk_config) { - if (mdclk_source_is_cdclk_pll(i915)) + if (mdclk_source_is_cdclk_pll(display)) return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); /* Otherwise, source for MDCLK is CD2XCLK. */ return 2; } -static void xe2lpd_mdclk_cdclk_ratio_program(struct drm_i915_private *i915, +static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display, const struct intel_cdclk_config *cdclk_config) { + struct drm_i915_private *i915 = to_i915(display->drm); + intel_dbuf_mdclk_cdclk_ratio_update(i915, - intel_mdclk_cdclk_ratio(i915, cdclk_config), + intel_mdclk_cdclk_ratio(display, cdclk_config), cdclk_config->joined_mbus); } -static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915, +static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display, const struct intel_cdclk_config *old_cdclk_config, const struct intel_cdclk_config *new_cdclk_config, struct intel_cdclk_config *mid_cdclk_config) @@ -1937,11 +1951,11 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91 return false; /* Return if both Squash and Crawl are not present */ - if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915)) + if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) return false; - old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk); - new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk); + old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); + new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); /* Return if Squash only or Crawl only is the desired action */ if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || @@ -1958,7 +1972,7 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91 * Should not happen currently. We might need more midpoint * transitions if we need to also change the cd2x divider. */ - if (drm_WARN_ON(&i915->drm, old_div != new_div)) + if (drm_WARN_ON(display->drm, old_div != new_div)) return false; *mid_cdclk_config = *new_cdclk_config; @@ -1987,37 +2001,40 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91 /* make sure the mid clock came out sane */ - drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk < + drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); - drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk > - i915->display.cdclk.max_cdclk_freq); - drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) != + drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > + display->cdclk.max_cdclk_freq); + drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != mid_waveform); return true; } -static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) +static bool pll_enable_wa_needed(struct intel_display *display) { - return (DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0) || - DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0) || + struct drm_i915_private *dev_priv = to_i915(display->drm); + + return (DISPLAY_VER_FULL(display) == IP_VER(20, 0) || + DISPLAY_VER_FULL(display) == IP_VER(14, 0) || IS_DG2(dev_priv)) && - dev_priv->display.cdclk.hw.vco > 0; + display->cdclk.hw.vco > 0; } -static u32 bxt_cdclk_ctl(struct drm_i915_private *i915, +static u32 bxt_cdclk_ctl(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { + struct drm_i915_private *i915 = to_i915(display->drm); int cdclk = cdclk_config->cdclk; int vco = cdclk_config->vco; u16 waveform; u32 val; - waveform = cdclk_squash_waveform(i915, cdclk); + waveform = cdclk_squash_waveform(display, cdclk); - val = bxt_cdclk_cd2x_div_sel(i915, cdclk, vco, waveform) | - bxt_cdclk_cd2x_pipe(i915, pipe); + val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) | + bxt_cdclk_cd2x_pipe(display, pipe); /* * Disable SSA Precharge when CD clock frequency < 500 MHz, @@ -2027,52 +2044,52 @@ static u32 bxt_cdclk_ctl(struct drm_i915_private *i915, cdclk >= 500000) val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; - if (DISPLAY_VER(i915) >= 20) - val |= xe2lpd_mdclk_source_sel(i915); + if (DISPLAY_VER(display) >= 20) + val |= xe2lpd_mdclk_source_sel(display); else val |= skl_cdclk_decimal(cdclk); return val; } -static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, +static void _bxt_set_cdclk(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { - struct intel_display *display = &dev_priv->display; int cdclk = cdclk_config->cdclk; int vco = cdclk_config->vco; - if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && - !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { - if (dev_priv->display.cdclk.hw.vco != vco) - adlp_cdclk_pll_crawl(dev_priv, vco); - } else if (DISPLAY_VER(dev_priv) >= 11) { + if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && + !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { + if (display->cdclk.hw.vco != vco) + adlp_cdclk_pll_crawl(display, vco); + } else if (DISPLAY_VER(display) >= 11) { /* wa_15010685871: dg2, mtl */ - if (pll_enable_wa_needed(dev_priv)) - dg2_cdclk_squash_program(dev_priv, 0); + if (pll_enable_wa_needed(display)) + dg2_cdclk_squash_program(display, 0); - icl_cdclk_pll_update(dev_priv, vco); + icl_cdclk_pll_update(display, vco); } else { - bxt_cdclk_pll_update(dev_priv, vco); + bxt_cdclk_pll_update(display, vco); } - if (HAS_CDCLK_SQUASH(dev_priv)) { - u16 waveform = cdclk_squash_waveform(dev_priv, cdclk); + if (HAS_CDCLK_SQUASH(display)) { + u16 waveform = cdclk_squash_waveform(display, cdclk); - dg2_cdclk_squash_program(dev_priv, waveform); + dg2_cdclk_squash_program(display, waveform); } - intel_de_write(dev_priv, CDCLK_CTL, bxt_cdclk_ctl(dev_priv, cdclk_config, pipe)); + intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe)); if (pipe != INVALID_PIPE) intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); } -static void bxt_set_cdclk(struct drm_i915_private *dev_priv, +static void bxt_set_cdclk(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_cdclk_config mid_cdclk_config; int cdclk = cdclk_config->cdclk; int ret = 0; @@ -2083,9 +2100,9 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, * mailbox communication, skip * this step. */ - if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv)) + if (DISPLAY_VER(display) >= 14 || IS_DG2(dev_priv)) /* NOOP */; - else if (DISPLAY_VER(dev_priv) >= 11) + else if (DISPLAY_VER(display) >= 11) ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, SKL_CDCLK_PREPARE_FOR_CHANGE, SKL_CDCLK_READY_FOR_CHANGE, @@ -2100,35 +2117,35 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 0x80000000, 150, 2); if (ret) { - drm_err(&dev_priv->drm, + drm_err(display->drm, "Failed to inform PCU about cdclk change (err %d, freq %d)\n", ret, cdclk); return; } - if (DISPLAY_VER(dev_priv) >= 20 && cdclk < dev_priv->display.cdclk.hw.cdclk) - xe2lpd_mdclk_cdclk_ratio_program(dev_priv, cdclk_config); + if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) + xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); - if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, + if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, cdclk_config, &mid_cdclk_config)) { - _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe); - _bxt_set_cdclk(dev_priv, cdclk_config, pipe); + _bxt_set_cdclk(display, &mid_cdclk_config, pipe); + _bxt_set_cdclk(display, cdclk_config, pipe); } else { - _bxt_set_cdclk(dev_priv, cdclk_config, pipe); + _bxt_set_cdclk(display, cdclk_config, pipe); } - if (DISPLAY_VER(dev_priv) >= 20 && cdclk > dev_priv->display.cdclk.hw.cdclk) - xe2lpd_mdclk_cdclk_ratio_program(dev_priv, cdclk_config); + if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) + xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); - if (DISPLAY_VER(dev_priv) >= 14) + if (DISPLAY_VER(display) >= 14) /* * NOOP - No Pcode communication needed for * Display versions 14 and beyond */; - else if (DISPLAY_VER(dev_priv) >= 11 && !IS_DG2(dev_priv)) + else if (DISPLAY_VER(display) >= 11 && !IS_DG2(dev_priv)) ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, cdclk_config->voltage_level); - if (DISPLAY_VER(dev_priv) < 11) { + if (DISPLAY_VER(display) < 11) { /* * The timeout isn't specified, the 2ms used here is based on * experiment. @@ -2141,42 +2158,42 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 150, 2); } if (ret) { - drm_err(&dev_priv->drm, + drm_err(display->drm, "PCode CDCLK freq set failed, (err %d, freq %d)\n", ret, cdclk); return; } - intel_update_cdclk(dev_priv); + intel_update_cdclk(display); - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) /* * Can't read out the voltage level :( * Let's just assume everything is as expected. */ - dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; + display->cdclk.hw.voltage_level = cdclk_config->voltage_level; } -static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) +static void bxt_sanitize_cdclk(struct intel_display *display) { u32 cdctl, expected; int cdclk, vco; - intel_update_cdclk(dev_priv); - intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); + intel_update_cdclk(display); + intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); - if (dev_priv->display.cdclk.hw.vco == 0 || - dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) + if (display->cdclk.hw.vco == 0 || + display->cdclk.hw.cdclk == display->cdclk.hw.bypass) goto sanitize; /* Make sure this is a legal cdclk value for the platform */ - cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); - if (cdclk != dev_priv->display.cdclk.hw.cdclk) + cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); + if (cdclk != display->cdclk.hw.cdclk) goto sanitize; /* Make sure the VCO is correct for the cdclk */ - vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); - if (vco != dev_priv->display.cdclk.hw.vco) + vco = bxt_calc_cdclk_pll_vco(display, cdclk); + if (vco != display->cdclk.hw.vco) goto sanitize; /* @@ -2184,129 +2201,133 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, * so sanitize this register. */ - cdctl = intel_de_read(dev_priv, CDCLK_CTL); - expected = bxt_cdclk_ctl(dev_priv, &dev_priv->display.cdclk.hw, INVALID_PIPE); + cdctl = intel_de_read(display, CDCLK_CTL); + expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); /* * Let's ignore the pipe field, since BIOS could have configured the * dividers both synching to an active pipe, or asynchronously * (PIPE_NONE). */ - cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); - expected &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); + cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); + expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); if (cdctl == expected) /* All well; nothing to sanitize */ return; sanitize: - drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); + drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); /* force cdclk programming */ - dev_priv->display.cdclk.hw.cdclk = 0; + display->cdclk.hw.cdclk = 0; /* force full PLL disable + enable */ - dev_priv->display.cdclk.hw.vco = ~0; + display->cdclk.hw.vco = ~0; } -static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) +static void bxt_cdclk_init_hw(struct intel_display *display) { struct intel_cdclk_config cdclk_config; - bxt_sanitize_cdclk(dev_priv); + bxt_sanitize_cdclk(display); - if (dev_priv->display.cdclk.hw.cdclk != 0 && - dev_priv->display.cdclk.hw.vco != 0) + if (display->cdclk.hw.cdclk != 0 && + display->cdclk.hw.vco != 0) return; - cdclk_config = dev_priv->display.cdclk.hw; + cdclk_config = display->cdclk.hw; /* * FIXME: * - The initial CDCLK needs to be read from VBT. * Need to make this change after VBT has changes for BXT. */ - cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); - cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); + cdclk_config.cdclk = bxt_calc_cdclk(display, 0); + cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); cdclk_config.voltage_level = - intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); + intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); - bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); + bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); } -static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) +static void bxt_cdclk_uninit_hw(struct intel_display *display) { - struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; + struct intel_cdclk_config cdclk_config = display->cdclk.hw; cdclk_config.cdclk = cdclk_config.bypass; cdclk_config.vco = 0; cdclk_config.voltage_level = - intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); + intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); - bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); + bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); } /** * intel_cdclk_init_hw - Initialize CDCLK hardware - * @i915: i915 device + * @display: display instance * - * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and + * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and * sanitizing the state of the hardware if needed. This is generally done only * during the display core initialization sequence, after which the DMC will * take care of turning CDCLK off/on as needed. */ -void intel_cdclk_init_hw(struct drm_i915_private *i915) +void intel_cdclk_init_hw(struct intel_display *display) { - if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) - bxt_cdclk_init_hw(i915); - else if (DISPLAY_VER(i915) == 9) - skl_cdclk_init_hw(i915); + struct drm_i915_private *i915 = to_i915(display->drm); + + if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915)) + bxt_cdclk_init_hw(display); + else if (DISPLAY_VER(display) == 9) + skl_cdclk_init_hw(display); } /** * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware - * @i915: i915 device + * @display: display instance * * Uninitialize CDCLK. This is done only during the display core * uninitialization sequence. */ -void intel_cdclk_uninit_hw(struct drm_i915_private *i915) +void intel_cdclk_uninit_hw(struct intel_display *display) { - if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) - bxt_cdclk_uninit_hw(i915); - else if (DISPLAY_VER(i915) == 9) - skl_cdclk_uninit_hw(i915); + struct drm_i915_private *i915 = to_i915(display->drm); + + if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915)) + bxt_cdclk_uninit_hw(display); + else if (DISPLAY_VER(display) == 9) + skl_cdclk_uninit_hw(display); } -static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915, +static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b) { u16 old_waveform; u16 new_waveform; - drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco)); + drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco)); if (a->vco == 0 || b->vco == 0) return false; - if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915)) + if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) return false; - old_waveform = cdclk_squash_waveform(i915, a->cdclk); - new_waveform = cdclk_squash_waveform(i915, b->cdclk); + old_waveform = cdclk_squash_waveform(display, a->cdclk); + new_waveform = cdclk_squash_waveform(display, b->cdclk); return a->vco != b->vco && old_waveform != new_waveform; } -static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, +static bool intel_cdclk_can_crawl(struct intel_display *display, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b) { int a_div, b_div; - if (!HAS_CDCLK_CRAWL(dev_priv)) + if (!HAS_CDCLK_CRAWL(display)) return false; /* @@ -2322,7 +2343,7 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, a->ref == b->ref; } -static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, +static bool intel_cdclk_can_squash(struct intel_display *display, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b) { @@ -2332,7 +2353,7 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, * the moment all platforms with squasher use a fixed cd2x * divider. */ - if (!HAS_CDCLK_SQUASH(dev_priv)) + if (!HAS_CDCLK_SQUASH(display)) return false; return a->cdclk != b->cdclk && @@ -2361,7 +2382,7 @@ bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, /** * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK * configurations requires only a cd2x divider update - * @dev_priv: i915 device + * @display: display instance * @a: first CDCLK configuration * @b: second CDCLK configuration * @@ -2369,12 +2390,14 @@ bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, * True if changing between the two CDCLK configurations * can be done with just a cd2x divider update, false if not. */ -static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, +static bool intel_cdclk_can_cd2x_update(struct intel_display *display, const struct intel_cdclk_config *a, const struct intel_cdclk_config *b) { + struct drm_i915_private *dev_priv = to_i915(display->drm); + /* Older hw doesn't have the capability */ - if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv)) + if (DISPLAY_VER(display) < 10 && !IS_BROXTON(dev_priv)) return false; /* @@ -2383,7 +2406,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, * the moment all platforms with squasher use a fixed cd2x * divider. */ - if (HAS_CDCLK_SQUASH(dev_priv)) + if (HAS_CDCLK_SQUASH(display)) return false; return a->cdclk != b->cdclk && @@ -2407,23 +2430,24 @@ static bool intel_cdclk_changed(const struct intel_cdclk_config *a, a->voltage_level != b->voltage_level; } -void intel_cdclk_dump_config(struct drm_i915_private *i915, +void intel_cdclk_dump_config(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, const char *context) { - drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", + drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", context, cdclk_config->cdclk, cdclk_config->vco, cdclk_config->ref, cdclk_config->bypass, cdclk_config->voltage_level); } -static void intel_pcode_notify(struct drm_i915_private *i915, +static void intel_pcode_notify(struct intel_display *display, u8 voltage_level, u8 active_pipe_count, u16 cdclk, bool cdclk_update_valid, bool pipe_count_update_valid) { + struct drm_i915_private *i915 = to_i915(display->drm); int ret; u32 update_mask = 0; @@ -2444,26 +2468,27 @@ static void intel_pcode_notify(struct drm_i915_private *i915, SKL_CDCLK_READY_FOR_CHANGE, SKL_CDCLK_READY_FOR_CHANGE, 3); if (ret) - drm_err(&i915->drm, + drm_err(display->drm, "Failed to inform PCU about display config (err %d)\n", ret); } -static void intel_set_cdclk(struct drm_i915_private *dev_priv, +static void intel_set_cdclk(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, enum pipe pipe, const char *context) { + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_encoder *encoder; - if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) + if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) return; - if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) + if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk)) return; - intel_cdclk_dump_config(dev_priv, cdclk_config, context); + intel_cdclk_dump_config(display, cdclk_config, context); - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { + for_each_intel_encoder_with_psr(display->drm, encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); intel_psr_pause(intel_dp); @@ -2476,24 +2501,24 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, * functions use cdclk. Not all platforms/ports do, * but we'll lock them all for simplicity. */ - mutex_lock(&dev_priv->display.gmbus.mutex); - for_each_intel_dp(&dev_priv->drm, encoder) { + mutex_lock(&display->gmbus.mutex); + for_each_intel_dp(display->drm, encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, - &dev_priv->display.gmbus.mutex); + &display->gmbus.mutex); } - intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); + intel_cdclk_set_cdclk(display, cdclk_config, pipe); - for_each_intel_dp(&dev_priv->drm, encoder) { + for_each_intel_dp(display->drm, encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); mutex_unlock(&intel_dp->aux.hw_mutex); } - mutex_unlock(&dev_priv->display.gmbus.mutex); + mutex_unlock(&display->gmbus.mutex); - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { + for_each_intel_encoder_with_psr(display->drm, encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); intel_psr_resume(intel_dp); @@ -2501,17 +2526,17 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, intel_audio_cdclk_change_post(dev_priv); - if (drm_WARN(&dev_priv->drm, - intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), + if (drm_WARN(display->drm, + intel_cdclk_changed(&display->cdclk.hw, cdclk_config), "cdclk state doesn't match!\n")) { - intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); - intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]"); + intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); + intel_cdclk_dump_config(display, cdclk_config, "[sw state]"); } } static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_cdclk_state *old_cdclk_state = intel_atomic_get_old_cdclk_state(state); const struct intel_cdclk_state *new_cdclk_state = @@ -2550,13 +2575,13 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) if (update_pipe_count) num_active_pipes = hweight8(new_cdclk_state->active_pipes); - intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk, + intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, change_cdclk, update_pipe_count); } static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); const struct intel_cdclk_state *new_cdclk_state = intel_atomic_get_new_cdclk_state(state); const struct intel_cdclk_state *old_cdclk_state = @@ -2587,7 +2612,7 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) if (update_pipe_count) num_active_pipes = hweight8(new_cdclk_state->active_pipes); - intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk, + intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, update_cdclk, update_pipe_count); } @@ -2612,7 +2637,8 @@ bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state) void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); + struct drm_i915_private *i915 = to_i915(display->drm); const struct intel_cdclk_state *old_cdclk_state = intel_atomic_get_old_cdclk_state(state); const struct intel_cdclk_state *new_cdclk_state = @@ -2649,9 +2675,9 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) */ cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus; - drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); + drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); - intel_set_cdclk(i915, &cdclk_config, pipe, + intel_set_cdclk(display, &cdclk_config, pipe, "Pre changing CDCLK to"); } @@ -2665,7 +2691,8 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) { - struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); + struct drm_i915_private *i915 = to_i915(display->drm); const struct intel_cdclk_state *old_cdclk_state = intel_atomic_get_old_cdclk_state(state); const struct intel_cdclk_state *new_cdclk_state = @@ -2685,20 +2712,21 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) else pipe = INVALID_PIPE; - drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); + drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); - intel_set_cdclk(i915, &new_cdclk_state->actual, pipe, + intel_set_cdclk(display, &new_cdclk_state->actual, pipe, "Post changing CDCLK to"); } static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = to_intel_display(crtc_state->uapi.crtc->dev); + struct drm_i915_private *dev_priv = to_i915(display->drm); int pixel_rate = crtc_state->pixel_rate; - if (DISPLAY_VER(dev_priv) >= 10) + if (DISPLAY_VER(display) >= 10) return DIV_ROUND_UP(pixel_rate, 2); - else if (DISPLAY_VER(dev_priv) == 9 || + else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) return pixel_rate; else if (IS_CHERRYVIEW(dev_priv)) @@ -2712,11 +2740,11 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); struct intel_plane *plane; int min_cdclk = 0; - for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) + for_each_intel_plane_on_crtc(display->drm, crtc, plane) min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); return min_cdclk; @@ -2725,7 +2753,7 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct intel_display *display = to_intel_display(crtc); int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); int min_cdclk = 0; @@ -2754,7 +2782,7 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) * Since PPC = 2 with bigjoiner * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits */ - int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; + int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24; int min_cdclk_bj = (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) * pixel_clock) / (2 * bigjoiner_interface_bits); @@ -2767,8 +2795,9 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = - to_i915(crtc_state->uapi.crtc->dev); + struct intel_display *display = + to_intel_display(crtc_state->uapi.crtc->dev); + struct drm_i915_private *dev_priv = to_i915(display->drm); int min_cdclk; if (!crtc_state->hw.enable) @@ -2789,10 +2818,10 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) crtc_state->has_audio && crtc_state->port_clock >= 540000 && crtc_state->lane_count == 4) { - if (DISPLAY_VER(dev_priv) == 10) { + if (DISPLAY_VER(display) == 10) { /* Display WA #1145: glk */ min_cdclk = max(316800, min_cdclk); - } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) { + } else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) { /* Display WA #1144: skl,bxt */ min_cdclk = max(432000, min_cdclk); } @@ -2802,7 +2831,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) * According to BSpec, "The CD clock frequency must be at least twice * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. */ - if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) + if (crtc_state->has_audio && DISPLAY_VER(display) >= 9) min_cdclk = max(2 * 96000, min_cdclk); /* @@ -2844,7 +2873,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) static int intel_compute_min_cdclk(struct intel_atomic_state *state) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_cdclk_state *cdclk_state = intel_atomic_get_new_cdclk_state(state); const struct intel_bw_state *bw_state; @@ -2887,7 +2917,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state) min_cdclk = max(cdclk_state->force_min_cdclk, cdclk_state->bw_min_cdclk); - for_each_pipe(dev_priv, pipe) + for_each_pipe(display, pipe) min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); /* @@ -2902,10 +2932,10 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state) !is_power_of_2(cdclk_state->active_pipes)) min_cdclk = max(2 * 96000, min_cdclk); - if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { - drm_dbg_kms(&dev_priv->drm, + if (min_cdclk > display->cdclk.max_cdclk_freq) { + drm_dbg_kms(display->drm, "required cdclk (%d kHz) exceeds max (%d kHz)\n", - min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); + min_cdclk, display->cdclk.max_cdclk_freq); return -EINVAL; } @@ -2927,7 +2957,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state) */ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_cdclk_state *cdclk_state = intel_atomic_get_new_cdclk_state(state); struct intel_crtc *crtc; @@ -2955,7 +2985,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) } min_voltage_level = 0; - for_each_pipe(dev_priv, pipe) + for_each_pipe(display, pipe) min_voltage_level = max(cdclk_state->min_voltage_level[pipe], min_voltage_level); @@ -2964,7 +2994,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_cdclk_state *cdclk_state = intel_atomic_get_new_cdclk_state(state); int min_cdclk, cdclk; @@ -2973,18 +3003,18 @@ static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) if (min_cdclk < 0) return min_cdclk; - cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); + cdclk = vlv_calc_cdclk(display, min_cdclk); cdclk_state->logical.cdclk = cdclk; cdclk_state->logical.voltage_level = - vlv_calc_voltage_level(dev_priv, cdclk); + vlv_calc_voltage_level(display, cdclk); if (!cdclk_state->active_pipes) { - cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); + cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); cdclk_state->actual.cdclk = cdclk; cdclk_state->actual.voltage_level = - vlv_calc_voltage_level(dev_priv, cdclk); + vlv_calc_voltage_level(display, cdclk); } else { cdclk_state->actual = cdclk_state->logical; } @@ -3023,7 +3053,7 @@ static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) static int skl_dpll0_vco(struct intel_atomic_state *state) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_cdclk_state *cdclk_state = intel_atomic_get_new_cdclk_state(state); struct intel_crtc *crtc; @@ -3032,7 +3062,7 @@ static int skl_dpll0_vco(struct intel_atomic_state *state) vco = cdclk_state->logical.vco; if (!vco) - vco = dev_priv->display.cdclk.skl_preferred_vco_freq; + vco = display->cdclk.skl_preferred_vco_freq; for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { if (!crtc_state->hw.enable) @@ -3094,7 +3124,7 @@ static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_cdclk_state *cdclk_state = intel_atomic_get_new_cdclk_state(state); int min_cdclk, min_voltage_level, cdclk, vco; @@ -3107,23 +3137,23 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) if (min_voltage_level < 0) return min_voltage_level; - cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); - vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); + cdclk = bxt_calc_cdclk(display, min_cdclk); + vco = bxt_calc_cdclk_pll_vco(display, cdclk); cdclk_state->logical.vco = vco; cdclk_state->logical.cdclk = cdclk; cdclk_state->logical.voltage_level = max_t(int, min_voltage_level, - intel_cdclk_calc_voltage_level(dev_priv, cdclk)); + intel_cdclk_calc_voltage_level(display, cdclk)); if (!cdclk_state->active_pipes) { - cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); - vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); + cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); + vco = bxt_calc_cdclk_pll_vco(display, cdclk); cdclk_state->actual.vco = vco; cdclk_state->actual.cdclk = cdclk; cdclk_state->actual.voltage_level = - intel_cdclk_calc_voltage_level(dev_priv, cdclk); + intel_cdclk_calc_voltage_level(display, cdclk); } else { cdclk_state->actual = cdclk_state->logical; } @@ -3175,10 +3205,10 @@ static const struct intel_global_state_funcs intel_cdclk_funcs = { struct intel_cdclk_state * intel_atomic_get_cdclk_state(struct intel_atomic_state *state) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_display *display = to_intel_display(state); struct intel_global_state *cdclk_state; - cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); + cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); if (IS_ERR(cdclk_state)) return ERR_CAST(cdclk_state); @@ -3234,24 +3264,26 @@ int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joi return intel_atomic_lock_global_state(&cdclk_state->base); } -int intel_cdclk_init(struct drm_i915_private *dev_priv) +int intel_cdclk_init(struct intel_display *display) { + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_cdclk_state *cdclk_state; cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); if (!cdclk_state) return -ENOMEM; - intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, + intel_atomic_global_obj_init(dev_priv, &display->cdclk.obj, &cdclk_state->base, &intel_cdclk_funcs); return 0; } -static bool intel_cdclk_need_serialize(struct drm_i915_private *i915, +static bool intel_cdclk_need_serialize(struct intel_display *display, const struct intel_cdclk_state *old_cdclk_state, const struct intel_cdclk_state *new_cdclk_state) { + struct drm_i915_private *i915 = to_i915(display->drm); bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) != hweight8(new_cdclk_state->active_pipes); bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual, @@ -3266,7 +3298,6 @@ static bool intel_cdclk_need_serialize(struct drm_i915_private *i915, int intel_modeset_calc_cdclk(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); - struct drm_i915_private *dev_priv = to_i915(state->base.dev); const struct intel_cdclk_state *old_cdclk_state; struct intel_cdclk_state *new_cdclk_state; enum pipe pipe = INVALID_PIPE; @@ -3285,7 +3316,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) if (ret) return ret; - if (intel_cdclk_need_serialize(dev_priv, old_cdclk_state, new_cdclk_state)) { + if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) { /* * Also serialize commits across all crtcs * if the actual hw needs to be poked. @@ -3305,7 +3336,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) } if (is_power_of_2(new_cdclk_state->active_pipes) && - intel_cdclk_can_cd2x_update(dev_priv, + intel_cdclk_can_cd2x_update(display, &old_cdclk_state->actual, &new_cdclk_state->actual)) { struct intel_crtc *crtc; @@ -3322,25 +3353,25 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) pipe = INVALID_PIPE; } - if (intel_cdclk_can_crawl_and_squash(dev_priv, + if (intel_cdclk_can_crawl_and_squash(display, &old_cdclk_state->actual, &new_cdclk_state->actual)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Can change cdclk via crawling and squashing\n"); - } else if (intel_cdclk_can_squash(dev_priv, + } else if (intel_cdclk_can_squash(display, &old_cdclk_state->actual, &new_cdclk_state->actual)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Can change cdclk via squashing\n"); - } else if (intel_cdclk_can_crawl(dev_priv, + } else if (intel_cdclk_can_crawl(display, &old_cdclk_state->actual, &new_cdclk_state->actual)) { - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Can change cdclk via crawling\n"); } else if (pipe != INVALID_PIPE) { new_cdclk_state->pipe = pipe; - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Can change cdclk cd2x divider with pipe %c active\n", pipe_name(pipe)); } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual, @@ -3352,24 +3383,24 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) new_cdclk_state->disable_pipes = true; - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Modeset required for cdclk change\n"); } - if (intel_mdclk_cdclk_ratio(dev_priv, &old_cdclk_state->actual) != - intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual)) { - int ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual); + if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) != + intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) { + int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual); ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio); if (ret) return ret; } - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "New cdclk calculated to be logical %u kHz, actual %u kHz\n", new_cdclk_state->logical.cdclk, new_cdclk_state->actual.cdclk); - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "New voltage level calculated to be logical %u, actual %u\n", new_cdclk_state->logical.voltage_level, new_cdclk_state->actual.voltage_level); @@ -3377,18 +3408,19 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) return 0; } -static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) +static int intel_compute_max_dotclk(struct intel_display *display) { - int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; + struct drm_i915_private *dev_priv = to_i915(display->drm); + int max_cdclk_freq = display->cdclk.max_cdclk_freq; - if (DISPLAY_VER(dev_priv) >= 10) + if (DISPLAY_VER(display) >= 10) return 2 * max_cdclk_freq; - else if (DISPLAY_VER(dev_priv) == 9 || + else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) return max_cdclk_freq; else if (IS_CHERRYVIEW(dev_priv)) return max_cdclk_freq*95/100; - else if (DISPLAY_VER(dev_priv) < 4) + else if (DISPLAY_VER(display) < 4) return 2*max_cdclk_freq*90/100; else return max_cdclk_freq*90/100; @@ -3396,34 +3428,36 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) /** * intel_update_max_cdclk - Determine the maximum support CDCLK frequency - * @dev_priv: i915 device + * @display: display instance * * Determine the maximum CDCLK frequency the platform supports, and also * derive the maximum dot clock frequency the maximum CDCLK frequency * allows. */ -void intel_update_max_cdclk(struct drm_i915_private *dev_priv) +void intel_update_max_cdclk(struct intel_display *display) { + struct drm_i915_private *dev_priv = to_i915(display->drm); + if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { - if (dev_priv->display.cdclk.hw.ref == 24000) - dev_priv->display.cdclk.max_cdclk_freq = 552000; + if (display->cdclk.hw.ref == 24000) + display->cdclk.max_cdclk_freq = 552000; else - dev_priv->display.cdclk.max_cdclk_freq = 556800; - } else if (DISPLAY_VER(dev_priv) >= 11) { - if (dev_priv->display.cdclk.hw.ref == 24000) - dev_priv->display.cdclk.max_cdclk_freq = 648000; + display->cdclk.max_cdclk_freq = 556800; + } else if (DISPLAY_VER(display) >= 11) { + if (display->cdclk.hw.ref == 24000) + display->cdclk.max_cdclk_freq = 648000; else - dev_priv->display.cdclk.max_cdclk_freq = 652800; + display->cdclk.max_cdclk_freq = 652800; } else if (IS_GEMINILAKE(dev_priv)) { - dev_priv->display.cdclk.max_cdclk_freq = 316800; + display->cdclk.max_cdclk_freq = 316800; } else if (IS_BROXTON(dev_priv)) { - dev_priv->display.cdclk.max_cdclk_freq = 624000; - } else if (DISPLAY_VER(dev_priv) == 9) { - u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; + display->cdclk.max_cdclk_freq = 624000; + } else if (DISPLAY_VER(display) == 9) { + u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; int max_cdclk, vco; - vco = dev_priv->display.cdclk.skl_preferred_vco_freq; - drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); + vco = display->cdclk.skl_preferred_vco_freq; + drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); /* * Use the lower (vco 8640) cdclk values as a @@ -3439,7 +3473,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) else max_cdclk = 308571; - dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); + display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); } else if (IS_BROADWELL(dev_priv)) { /* * FIXME with extra cooling we can allow @@ -3447,41 +3481,43 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) * How can we know if extra cooling is * available? PCI ID, VTB, something else? */ - if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) - dev_priv->display.cdclk.max_cdclk_freq = 450000; + if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) + display->cdclk.max_cdclk_freq = 450000; else if (IS_BROADWELL_ULX(dev_priv)) - dev_priv->display.cdclk.max_cdclk_freq = 450000; + display->cdclk.max_cdclk_freq = 450000; else if (IS_BROADWELL_ULT(dev_priv)) - dev_priv->display.cdclk.max_cdclk_freq = 540000; + display->cdclk.max_cdclk_freq = 540000; else - dev_priv->display.cdclk.max_cdclk_freq = 675000; + display->cdclk.max_cdclk_freq = 675000; } else if (IS_CHERRYVIEW(dev_priv)) { - dev_priv->display.cdclk.max_cdclk_freq = 320000; + display->cdclk.max_cdclk_freq = 320000; } else if (IS_VALLEYVIEW(dev_priv)) { - dev_priv->display.cdclk.max_cdclk_freq = 400000; + display->cdclk.max_cdclk_freq = 400000; } else { /* otherwise assume cdclk is fixed */ - dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; + display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; } - dev_priv->display.cdclk.max_dotclk_freq = intel_compute_max_dotclk(dev_priv); + display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); - drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", - dev_priv->display.cdclk.max_cdclk_freq); + drm_dbg(display->drm, "Max CD clock rate: %d kHz\n", + display->cdclk.max_cdclk_freq); - drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", - dev_priv->display.cdclk.max_dotclk_freq); + drm_dbg(display->drm, "Max dotclock rate: %d kHz\n", + display->cdclk.max_dotclk_freq); } /** * intel_update_cdclk - Determine the current CDCLK frequency - * @dev_priv: i915 device + * @display: display instance * * Determine the current CDCLK frequency. */ -void intel_update_cdclk(struct drm_i915_private *dev_priv) +void intel_update_cdclk(struct intel_display *display) { - intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); + struct drm_i915_private *dev_priv = to_i915(display->drm); + + intel_cdclk_get_cdclk(display, &display->cdclk.hw); /* * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): @@ -3490,28 +3526,29 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv) * generate GMBus clock. This will vary with the cdclk freq. */ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - intel_de_write(dev_priv, GMBUSFREQ_VLV, - DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); + intel_de_write(display, GMBUSFREQ_VLV, + DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); } -static int dg1_rawclk(struct drm_i915_private *dev_priv) +static int dg1_rawclk(struct intel_display *display) { /* * DG1 always uses a 38.4 MHz rawclk. The bspec tells us * "Program Numerator=2, Denominator=4, Divider=37 decimal." */ - intel_de_write(dev_priv, PCH_RAWCLK_FREQ, + intel_de_write(display, PCH_RAWCLK_FREQ, CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); return 38400; } -static int cnp_rawclk(struct drm_i915_private *dev_priv) +static int cnp_rawclk(struct intel_display *display) { - u32 rawclk; + struct drm_i915_private *dev_priv = to_i915(display->drm); int divider, fraction; + u32 rawclk; - if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { + if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { /* 24 MHz */ divider = 24000; fraction = 0; @@ -3531,37 +3568,42 @@ static int cnp_rawclk(struct drm_i915_private *dev_priv) rawclk |= ICP_RAWCLK_NUM(numerator); } - intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk); + intel_de_write(display, PCH_RAWCLK_FREQ, rawclk); return divider + fraction; } -static int pch_rawclk(struct drm_i915_private *dev_priv) +static int pch_rawclk(struct intel_display *display) { - return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; + return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; } -static int vlv_hrawclk(struct drm_i915_private *dev_priv) +static int vlv_hrawclk(struct intel_display *display) { + struct drm_i915_private *dev_priv = to_i915(display->drm); + /* RAWCLK_FREQ_VLV register updated from power well code */ return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", CCK_DISPLAY_REF_CLOCK_CONTROL); } -static int i9xx_hrawclk(struct drm_i915_private *i915) +static int i9xx_hrawclk(struct intel_display *display) { + struct drm_i915_private *i915 = to_i915(display->drm); + /* hrawclock is 1/4 the FSB frequency */ return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4); } /** * intel_read_rawclk - Determine the current RAWCLK frequency - * @dev_priv: i915 device + * @display: display instance * * Determine the current RAWCLK frequency. RAWCLK is a fixed * frequency clock so this needs to done only once. */ -u32 intel_read_rawclk(struct drm_i915_private *dev_priv) +u32 intel_read_rawclk(struct intel_display *display) { + struct drm_i915_private *dev_priv = to_i915(display->drm); u32 freq; if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL) @@ -3572,15 +3614,15 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) */ freq = 38400; else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) - freq = dg1_rawclk(dev_priv); + freq = dg1_rawclk(display); else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) - freq = cnp_rawclk(dev_priv); + freq = cnp_rawclk(display); else if (HAS_PCH_SPLIT(dev_priv)) - freq = pch_rawclk(dev_priv); + freq = pch_rawclk(display); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - freq = vlv_hrawclk(dev_priv); - else if (DISPLAY_VER(dev_priv) >= 3) - freq = i9xx_hrawclk(dev_priv); + freq = vlv_hrawclk(display); + else if (DISPLAY_VER(display) >= 3) + freq = i9xx_hrawclk(display); else /* no rawclk on other platforms, or no need to know it */ return 0; @@ -3590,23 +3632,23 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) static int i915_cdclk_info_show(struct seq_file *m, void *unused) { - struct drm_i915_private *i915 = m->private; + struct intel_display *display = m->private; - seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); - seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); - seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->display.cdclk.max_dotclk_freq); + seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); + seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); + seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); return 0; } DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info); -void intel_cdclk_debugfs_register(struct drm_i915_private *i915) +void intel_cdclk_debugfs_register(struct intel_display *display) { - struct drm_minor *minor = i915->drm.primary; + struct drm_minor *minor = display->drm->primary; debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root, - i915, &i915_cdclk_info_fops); + display, &i915_cdclk_info_fops); } static const struct intel_cdclk_funcs rplu_cdclk_funcs = { @@ -3747,97 +3789,99 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = { /** * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks - * @dev_priv: i915 device + * @display: display instance */ -void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) +void intel_init_cdclk_hooks(struct intel_display *display) { - if (DISPLAY_VER(dev_priv) >= 20) { - dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; - dev_priv->display.cdclk.table = xe2lpd_cdclk_table; - } else if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1)) { - dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; - dev_priv->display.cdclk.table = xe2hpd_cdclk_table; - } else if (DISPLAY_VER(dev_priv) >= 14) { - dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; - dev_priv->display.cdclk.table = mtl_cdclk_table; + struct drm_i915_private *dev_priv = to_i915(display->drm); + + if (DISPLAY_VER(display) >= 20) { + display->funcs.cdclk = &rplu_cdclk_funcs; + display->cdclk.table = xe2lpd_cdclk_table; + } else if (DISPLAY_VER_FULL(display) >= IP_VER(14, 1)) { + display->funcs.cdclk = &rplu_cdclk_funcs; + display->cdclk.table = xe2hpd_cdclk_table; + } else if (DISPLAY_VER(display) >= 14) { + display->funcs.cdclk = &rplu_cdclk_funcs; + display->cdclk.table = mtl_cdclk_table; } else if (IS_DG2(dev_priv)) { - dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; - dev_priv->display.cdclk.table = dg2_cdclk_table; + display->funcs.cdclk = &tgl_cdclk_funcs; + display->cdclk.table = dg2_cdclk_table; } else if (IS_ALDERLAKE_P(dev_priv)) { /* Wa_22011320316:adl-p[a0] */ if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { - dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; - dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; + display->cdclk.table = adlp_a_step_cdclk_table; + display->funcs.cdclk = &tgl_cdclk_funcs; } else if (IS_RAPTORLAKE_U(dev_priv)) { - dev_priv->display.cdclk.table = rplu_cdclk_table; - dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; + display->cdclk.table = rplu_cdclk_table; + display->funcs.cdclk = &rplu_cdclk_funcs; } else { - dev_priv->display.cdclk.table = adlp_cdclk_table; - dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; + display->cdclk.table = adlp_cdclk_table; + display->funcs.cdclk = &tgl_cdclk_funcs; } } else if (IS_ROCKETLAKE(dev_priv)) { - dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; - dev_priv->display.cdclk.table = rkl_cdclk_table; - } else if (DISPLAY_VER(dev_priv) >= 12) { - dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; - dev_priv->display.cdclk.table = icl_cdclk_table; + display->funcs.cdclk = &tgl_cdclk_funcs; + display->cdclk.table = rkl_cdclk_table; + } else if (DISPLAY_VER(display) >= 12) { + display->funcs.cdclk = &tgl_cdclk_funcs; + display->cdclk.table = icl_cdclk_table; } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { - dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; - dev_priv->display.cdclk.table = icl_cdclk_table; - } else if (DISPLAY_VER(dev_priv) >= 11) { - dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; - dev_priv->display.cdclk.table = icl_cdclk_table; + display->funcs.cdclk = &ehl_cdclk_funcs; + display->cdclk.table = icl_cdclk_table; + } else if (DISPLAY_VER(display) >= 11) { + display->funcs.cdclk = &icl_cdclk_funcs; + display->cdclk.table = icl_cdclk_table; } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { - dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; + display->funcs.cdclk = &bxt_cdclk_funcs; if (IS_GEMINILAKE(dev_priv)) - dev_priv->display.cdclk.table = glk_cdclk_table; + display->cdclk.table = glk_cdclk_table; else - dev_priv->display.cdclk.table = bxt_cdclk_table; - } else if (DISPLAY_VER(dev_priv) == 9) { - dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; + display->cdclk.table = bxt_cdclk_table; + } else if (DISPLAY_VER(display) == 9) { + display->funcs.cdclk = &skl_cdclk_funcs; } else if (IS_BROADWELL(dev_priv)) { - dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; + display->funcs.cdclk = &bdw_cdclk_funcs; } else if (IS_HASWELL(dev_priv)) { - dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; + display->funcs.cdclk = &hsw_cdclk_funcs; } else if (IS_CHERRYVIEW(dev_priv)) { - dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; + display->funcs.cdclk = &chv_cdclk_funcs; } else if (IS_VALLEYVIEW(dev_priv)) { - dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; + display->funcs.cdclk = &vlv_cdclk_funcs; } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) { - dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; + display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; } else if (IS_IRONLAKE(dev_priv)) { - dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; + display->funcs.cdclk = &ilk_cdclk_funcs; } else if (IS_GM45(dev_priv)) { - dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; + display->funcs.cdclk = &gm45_cdclk_funcs; } else if (IS_G45(dev_priv)) { - dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; + display->funcs.cdclk = &g33_cdclk_funcs; } else if (IS_I965GM(dev_priv)) { - dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; + display->funcs.cdclk = &i965gm_cdclk_funcs; } else if (IS_I965G(dev_priv)) { - dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; + display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; } else if (IS_PINEVIEW(dev_priv)) { - dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; + display->funcs.cdclk = &pnv_cdclk_funcs; } else if (IS_G33(dev_priv)) { - dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; + display->funcs.cdclk = &g33_cdclk_funcs; } else if (IS_I945GM(dev_priv)) { - dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; + display->funcs.cdclk = &i945gm_cdclk_funcs; } else if (IS_I945G(dev_priv)) { - dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; + display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; } else if (IS_I915GM(dev_priv)) { - dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; + display->funcs.cdclk = &i915gm_cdclk_funcs; } else if (IS_I915G(dev_priv)) { - dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; + display->funcs.cdclk = &i915g_cdclk_funcs; } else if (IS_I865G(dev_priv)) { - dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; + display->funcs.cdclk = &i865g_cdclk_funcs; } else if (IS_I85X(dev_priv)) { - dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; + display->funcs.cdclk = &i85x_cdclk_funcs; } else if (IS_I845G(dev_priv)) { - dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; + display->funcs.cdclk = &i845g_cdclk_funcs; } else if (IS_I830(dev_priv)) { - dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; + display->funcs.cdclk = &i830_cdclk_funcs; } - if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, + if (drm_WARN(display->drm, !display->funcs.cdclk, "Unknown platform. Assuming i830\n")) - dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; + display->funcs.cdclk = &i830_cdclk_funcs; } diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index 1fe445a3a30b..6b0e7a41eba3 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -11,9 +11,9 @@ #include "intel_display_limits.h" #include "intel_global_state.h" -struct drm_i915_private; struct intel_atomic_state; struct intel_crtc_state; +struct intel_display; struct intel_cdclk_config { unsigned int cdclk, vco, ref, bypass; @@ -59,24 +59,24 @@ struct intel_cdclk_state { }; int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); -void intel_cdclk_init_hw(struct drm_i915_private *i915); -void intel_cdclk_uninit_hw(struct drm_i915_private *i915); -void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); -void intel_update_max_cdclk(struct drm_i915_private *dev_priv); -void intel_update_cdclk(struct drm_i915_private *dev_priv); -u32 intel_read_rawclk(struct drm_i915_private *dev_priv); +void intel_cdclk_init_hw(struct intel_display *display); +void intel_cdclk_uninit_hw(struct intel_display *display); +void intel_init_cdclk_hooks(struct intel_display *display); +void intel_update_max_cdclk(struct intel_display *display); +void intel_update_cdclk(struct intel_display *display); +u32 intel_read_rawclk(struct intel_display *display); bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, const struct intel_cdclk_config *b); -int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915, +int intel_mdclk_cdclk_ratio(struct intel_display *display, const struct intel_cdclk_config *cdclk_config); bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state); void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state); void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state); -void intel_cdclk_dump_config(struct drm_i915_private *i915, +void intel_cdclk_dump_config(struct intel_display *display, const struct intel_cdclk_config *cdclk_config, const char *context); int intel_modeset_calc_cdclk(struct intel_atomic_state *state); -void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, +void intel_cdclk_get_cdclk(struct intel_display *display, struct intel_cdclk_config *cdclk_config); int intel_cdclk_atomic_check(struct intel_atomic_state *state, bool *need_cdclk_calc); @@ -92,7 +92,7 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state); #define intel_atomic_get_new_cdclk_state(state) \ to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->cdclk.obj)) -int intel_cdclk_init(struct drm_i915_private *dev_priv); -void intel_cdclk_debugfs_register(struct drm_i915_private *i915); +int intel_cdclk_init(struct intel_display *display); +void intel_cdclk_debugfs_register(struct intel_display *display); #endif /* __INTEL_CDCLK_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 830b9eb60976..c1bef34d1ffd 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -1068,7 +1068,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915) minor->debugfs_root, minor); intel_bios_debugfs_register(display); - intel_cdclk_debugfs_register(i915); + intel_cdclk_debugfs_register(display); intel_dmc_debugfs_register(i915); intel_fbc_debugfs_register(display); intel_hpd_debugfs_register(i915); diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 408c76852495..9ff08dbefc76 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -1678,7 +1678,7 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9 } } - display_runtime->rawclk_freq = intel_read_rawclk(i915); + display_runtime->rawclk_freq = intel_read_rawclk(&i915->display); drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq); return; diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index e7670774ecd0..434e52f450ff 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -82,16 +82,17 @@ bool intel_display_driver_probe_defer(struct pci_dev *pdev) void intel_display_driver_init_hw(struct drm_i915_private *i915) { + struct intel_display *display = &i915->display; struct intel_cdclk_state *cdclk_state; if (!HAS_DISPLAY(i915)) return; - cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); + cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state); - intel_update_cdclk(i915); - intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); - cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; + intel_update_cdclk(display); + intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); + cdclk_state->logical = cdclk_state->actual = display->cdclk.hw; intel_display_wa_apply(i915); } @@ -194,7 +195,7 @@ void intel_display_driver_early_probe(struct drm_i915_private *i915) intel_display_irq_init(i915); intel_dkl_phy_init(i915); intel_color_init_hooks(i915); - intel_init_cdclk_hooks(i915); + intel_init_cdclk_hooks(&i915->display); intel_audio_hooks_init(i915); intel_dpll_init_clock_hook(i915); intel_init_display_hooks(i915); @@ -244,7 +245,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915) intel_mode_config_init(i915); - ret = intel_cdclk_init(i915); + ret = intel_cdclk_init(display); if (ret) goto cleanup_vga_client_pw_domain_dmc; @@ -451,8 +452,8 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915) intel_display_driver_init_hw(i915); intel_dpll_update_ref_clks(i915); - if (i915->display.cdclk.max_cdclk_freq == 0) - intel_update_max_cdclk(i915); + if (display->cdclk.max_cdclk_freq == 0) + intel_update_max_cdclk(display); intel_hti_init(display); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index ef2fdbf97346..eb3e2a56af1d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1300,6 +1300,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, */ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) { + struct intel_display *display = &dev_priv->display; u32 val; val = intel_de_read(dev_priv, LCPLL_CTL); @@ -1343,8 +1344,8 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); - intel_update_cdclk(dev_priv); - intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); + intel_update_cdclk(display); + intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); } /* @@ -1416,7 +1417,8 @@ static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv, static void skl_display_core_init(struct drm_i915_private *dev_priv, bool resume) { - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; + struct intel_display *display = &dev_priv->display; + struct i915_power_domains *power_domains = &display->power.domains; struct i915_power_well *well; gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); @@ -1438,7 +1440,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, mutex_unlock(&power_domains->lock); - intel_cdclk_init_hw(dev_priv); + intel_cdclk_init_hw(display); gen9_dbuf_enable(dev_priv); @@ -1448,7 +1450,8 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, static void skl_display_core_uninit(struct drm_i915_private *dev_priv) { - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; + struct intel_display *display = &dev_priv->display; + struct i915_power_domains *power_domains = &display->power.domains; struct i915_power_well *well; if (!HAS_DISPLAY(dev_priv)) @@ -1459,7 +1462,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv) gen9_dbuf_disable(dev_priv); - intel_cdclk_uninit_hw(dev_priv); + intel_cdclk_uninit_hw(display); /* The spec doesn't call for removing the reset handshake flag */ /* disable PG1 and Misc I/O */ @@ -1482,7 +1485,8 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv) static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume) { - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; + struct intel_display *display = &dev_priv->display; + struct i915_power_domains *power_domains = &display->power.domains; struct i915_power_well *well; gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); @@ -1506,7 +1510,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume mutex_unlock(&power_domains->lock); - intel_cdclk_init_hw(dev_priv); + intel_cdclk_init_hw(display); gen9_dbuf_enable(dev_priv); @@ -1516,7 +1520,8 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) { - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; + struct intel_display *display = &dev_priv->display; + struct i915_power_domains *power_domains = &display->power.domains; struct i915_power_well *well; if (!HAS_DISPLAY(dev_priv)) @@ -1527,7 +1532,7 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) gen9_dbuf_disable(dev_priv); - intel_cdclk_uninit_hw(dev_priv); + intel_cdclk_uninit_hw(display); /* The spec doesn't call for removing the reset handshake flag */ @@ -1623,7 +1628,8 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) static void icl_display_core_init(struct drm_i915_private *dev_priv, bool resume) { - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; + struct intel_display *display = &dev_priv->display; + struct i915_power_domains *power_domains = &display->power.domains; struct i915_power_well *well; gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); @@ -1657,7 +1663,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0); /* 4. Enable CDCLK. */ - intel_cdclk_init_hw(dev_priv); + intel_cdclk_init_hw(display); if (DISPLAY_VER(dev_priv) >= 12) gen12_dbuf_slices_config(dev_priv); @@ -1704,7 +1710,8 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, static void icl_display_core_uninit(struct drm_i915_private *dev_priv) { - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; + struct intel_display *display = &dev_priv->display; + struct i915_power_domains *power_domains = &display->power.domains; struct i915_power_well *well; if (!HAS_DISPLAY(dev_priv)) @@ -1719,7 +1726,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) gen9_dbuf_disable(dev_priv); /* 3. Disable CD clock */ - intel_cdclk_uninit_hw(dev_priv); + intel_cdclk_uninit_hw(display); if (DISPLAY_VER(dev_priv) == 14) intel_de_rmw(dev_priv, DC_STATE_EN, 0, diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 46e9eff12c23..7b40a5b88214 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -967,7 +967,8 @@ static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) void gen9_disable_dc_states(struct drm_i915_private *dev_priv) { - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; + struct intel_display *display = &dev_priv->display; + struct i915_power_domains *power_domains = &display->power.domains; struct intel_cdclk_config cdclk_config = {}; if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) { @@ -982,10 +983,10 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv) intel_dmc_wl_disable(&dev_priv->display); - intel_cdclk_get_cdclk(dev_priv, &cdclk_config); + intel_cdclk_get_cdclk(display, &cdclk_config); /* Can't read out voltage_level so can't use intel_cdclk_changed() */ - drm_WARN_ON(&dev_priv->drm, - intel_cdclk_clock_changed(&dev_priv->display.cdclk.hw, + drm_WARN_ON(display->drm, + intel_cdclk_clock_changed(&display->cdclk.hw, &cdclk_config)); gen9_assert_dbuf_enabled(dev_priv); diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 29835b638495..6e1f04d5ef47 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2973,6 +2973,7 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, static void skl_wm_get_hw_state(struct drm_i915_private *i915) { + struct intel_display *display = &i915->display; struct intel_dbuf_state *dbuf_state = to_intel_dbuf_state(i915->display.dbuf.obj.state); struct intel_crtc *crtc; @@ -2980,7 +2981,7 @@ static void skl_wm_get_hw_state(struct drm_i915_private *i915) if (HAS_MBUS_JOINING(i915)) dbuf_state->joined_mbus = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN; - dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(i915, &i915->display.cdclk.hw); + dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(display, &display->cdclk.hw); for_each_intel_crtc(&i915->drm, crtc) { struct intel_crtc_state *crtc_state = -- 2.44.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display 2024-09-06 14:33 ` [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display Ville Syrjala @ 2024-09-06 15:09 ` Rodrigo Vivi 2024-09-06 15:18 ` Jani Nikula 1 sibling, 0 replies; 24+ messages in thread From: Rodrigo Vivi @ 2024-09-06 15:09 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx, intel-xe On Fri, Sep 06, 2024 at 05:33:02PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > struct intel_display will replace struct drm_i915_private as > the main thing for display code. Convert the CDCLK code to > use it (as much as possible at this stage). better to take this one in quickly before it starts to conflict on rebases. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 1168 +++++++++-------- > drivers/gpu/drm/i915/display/intel_cdclk.h | 24 +- > .../drm/i915/display/intel_display_debugfs.c | 2 +- > .../drm/i915/display/intel_display_device.c | 2 +- > .../drm/i915/display/intel_display_driver.c | 17 +- > .../drm/i915/display/intel_display_power.c | 35 +- > .../i915/display/intel_display_power_well.c | 9 +- > drivers/gpu/drm/i915/display/skl_watermark.c | 3 +- > 8 files changed, 657 insertions(+), 603 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 9d870d15d888..b4eda0a2a45d 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -113,81 +113,81 @@ > */ > > struct intel_cdclk_funcs { > - void (*get_cdclk)(struct drm_i915_private *i915, > + void (*get_cdclk)(struct intel_display *display, > struct intel_cdclk_config *cdclk_config); > - void (*set_cdclk)(struct drm_i915_private *i915, > + void (*set_cdclk)(struct intel_display *display, > const struct intel_cdclk_config *cdclk_config, > enum pipe pipe); > int (*modeset_calc_cdclk)(struct intel_atomic_state *state); > u8 (*calc_voltage_level)(int cdclk); > }; > > -void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, > +void intel_cdclk_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > - dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); > + display->funcs.cdclk->get_cdclk(display, cdclk_config); > } > > -static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv, > +static void intel_cdclk_set_cdclk(struct intel_display *display, > const struct intel_cdclk_config *cdclk_config, > enum pipe pipe) > { > - dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); > + display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); > } > > static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state) > { > - struct drm_i915_private *dev_priv = to_i915(state->base.dev); > + struct intel_display *display = to_intel_display(state); > > - return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(state); > + return display->funcs.cdclk->modeset_calc_cdclk(state); > } > > -static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv, > +static u8 intel_cdclk_calc_voltage_level(struct intel_display *display, > int cdclk) > { > - return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); > + return display->funcs.cdclk->calc_voltage_level(cdclk); > } > > -static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, > +static void fixed_133mhz_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > cdclk_config->cdclk = 133333; > } > > -static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, > +static void fixed_200mhz_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > cdclk_config->cdclk = 200000; > } > > -static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, > +static void fixed_266mhz_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > cdclk_config->cdclk = 266667; > } > > -static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, > +static void fixed_333mhz_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > cdclk_config->cdclk = 333333; > } > > -static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, > +static void fixed_400mhz_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > cdclk_config->cdclk = 400000; > } > > -static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, > +static void fixed_450mhz_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > cdclk_config->cdclk = 450000; > } > > -static void i85x_get_cdclk(struct drm_i915_private *dev_priv, > +static void i85x_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); > + struct pci_dev *pdev = to_pci_dev(display->drm->dev); > u16 hpllcc = 0; > > /* > @@ -226,10 +226,10 @@ static void i85x_get_cdclk(struct drm_i915_private *dev_priv, > } > } > > -static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, > +static void i915gm_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); > + struct pci_dev *pdev = to_pci_dev(display->drm->dev); > u16 gcfgc = 0; > > pci_read_config_word(pdev, GCFGC, &gcfgc); > @@ -250,10 +250,10 @@ static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, > } > } > > -static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, > +static void i945gm_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); > + struct pci_dev *pdev = to_pci_dev(display->drm->dev); > u16 gcfgc = 0; > > pci_read_config_word(pdev, GCFGC, &gcfgc); > @@ -274,7 +274,7 @@ static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, > } > } > > -static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) > +static unsigned int intel_hpll_vco(struct intel_display *display) > { > static const unsigned int blb_vco[8] = { > [0] = 3200000, > @@ -313,6 +313,7 @@ static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) > [4] = 2666667, > [5] = 4266667, > }; > + struct drm_i915_private *dev_priv = to_i915(display->drm); > const unsigned int *vco_table; > unsigned int vco; > u8 tmp = 0; > @@ -331,23 +332,23 @@ static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) > else > return 0; > > - tmp = intel_de_read(dev_priv, > + tmp = intel_de_read(display, > IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); > > vco = vco_table[tmp & 0x7]; > if (vco == 0) > - drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", > + drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", > tmp); > else > - drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); > + drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco); > > return vco; > } > > -static void g33_get_cdclk(struct drm_i915_private *dev_priv, > +static void g33_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); > + struct pci_dev *pdev = to_pci_dev(display->drm->dev); > static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; > static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 }; > static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 }; > @@ -356,7 +357,7 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv, > unsigned int cdclk_sel; > u16 tmp = 0; > > - cdclk_config->vco = intel_hpll_vco(dev_priv); > + cdclk_config->vco = intel_hpll_vco(display); > > pci_read_config_word(pdev, GCFGC, &tmp); > > @@ -387,16 +388,16 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv, > return; > > fail: > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", > cdclk_config->vco, tmp); > cdclk_config->cdclk = 190476; > } > > -static void pnv_get_cdclk(struct drm_i915_private *dev_priv, > +static void pnv_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); > + struct pci_dev *pdev = to_pci_dev(display->drm->dev); > u16 gcfgc = 0; > > pci_read_config_word(pdev, GCFGC, &gcfgc); > @@ -415,7 +416,7 @@ static void pnv_get_cdclk(struct drm_i915_private *dev_priv, > cdclk_config->cdclk = 200000; > break; > default: > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "Unknown pnv display core clock 0x%04x\n", gcfgc); > fallthrough; > case GC_DISPLAY_CLOCK_133_MHZ_PNV: > @@ -427,10 +428,10 @@ static void pnv_get_cdclk(struct drm_i915_private *dev_priv, > } > } > > -static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, > +static void i965gm_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); > + struct pci_dev *pdev = to_pci_dev(display->drm->dev); > static const u8 div_3200[] = { 16, 10, 8 }; > static const u8 div_4000[] = { 20, 12, 10 }; > static const u8 div_5333[] = { 24, 16, 14 }; > @@ -438,7 +439,7 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, > unsigned int cdclk_sel; > u16 tmp = 0; > > - cdclk_config->vco = intel_hpll_vco(dev_priv); > + cdclk_config->vco = intel_hpll_vco(display); > > pci_read_config_word(pdev, GCFGC, &tmp); > > @@ -466,20 +467,20 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, > return; > > fail: > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", > cdclk_config->vco, tmp); > cdclk_config->cdclk = 200000; > } > > -static void gm45_get_cdclk(struct drm_i915_private *dev_priv, > +static void gm45_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); > + struct pci_dev *pdev = to_pci_dev(display->drm->dev); > unsigned int cdclk_sel; > u16 tmp = 0; > > - cdclk_config->vco = intel_hpll_vco(dev_priv); > + cdclk_config->vco = intel_hpll_vco(display); > > pci_read_config_word(pdev, GCFGC, &tmp); > > @@ -495,7 +496,7 @@ static void gm45_get_cdclk(struct drm_i915_private *dev_priv, > cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; > break; > default: > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", > cdclk_config->vco, tmp); > cdclk_config->cdclk = 222222; > @@ -503,15 +504,16 @@ static void gm45_get_cdclk(struct drm_i915_private *dev_priv, > } > } > > -static void hsw_get_cdclk(struct drm_i915_private *dev_priv, > +static void hsw_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > - u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); > + struct drm_i915_private *dev_priv = to_i915(display->drm); > + u32 lcpll = intel_de_read(display, LCPLL_CTL); > u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; > > if (lcpll & LCPLL_CD_SOURCE_FCLK) > cdclk_config->cdclk = 800000; > - else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) > + else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) > cdclk_config->cdclk = 450000; > else if (freq == LCPLL_CLK_FREQ_450) > cdclk_config->cdclk = 450000; > @@ -521,8 +523,9 @@ static void hsw_get_cdclk(struct drm_i915_private *dev_priv, > cdclk_config->cdclk = 540000; > } > > -static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) > +static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? > 333333 : 320000; > > @@ -541,8 +544,10 @@ static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) > return 200000; > } > > -static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) > +static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > + > if (IS_VALLEYVIEW(dev_priv)) { > if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ > return 2; > @@ -560,9 +565,10 @@ static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) > } > } > > -static void vlv_get_cdclk(struct drm_i915_private *dev_priv, > +static void vlv_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > u32 val; > > vlv_iosf_sb_get(dev_priv, > @@ -586,8 +592,9 @@ static void vlv_get_cdclk(struct drm_i915_private *dev_priv, > DSPFREQGUAR_SHIFT_CHV; > } > > -static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) > +static void vlv_program_pfi_credits(struct intel_display *display) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > unsigned int credits, default_credits; > > if (IS_CHERRYVIEW(dev_priv)) > @@ -595,7 +602,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) > else > default_credits = PFI_CREDIT(8); > > - if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { > + if (display->cdclk.hw.cdclk >= dev_priv->czclk_freq) { > /* CHV suggested value is 31 or 63 */ > if (IS_CHERRYVIEW(dev_priv)) > credits = PFI_CREDIT_63; > @@ -609,24 +616,25 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) > * WA - write default credits before re-programming > * FIXME: should we also set the resend bit here? > */ > - intel_de_write(dev_priv, GCI_CONTROL, > + intel_de_write(display, GCI_CONTROL, > VGA_FAST_MODE_DISABLE | default_credits); > > - intel_de_write(dev_priv, GCI_CONTROL, > + intel_de_write(display, GCI_CONTROL, > VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); > > /* > * FIXME is this guaranteed to clear > * immediately or should we poll for it? > */ > - drm_WARN_ON(&dev_priv->drm, > - intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); > + drm_WARN_ON(display->drm, > + intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND); > } > > -static void vlv_set_cdclk(struct drm_i915_private *dev_priv, > +static void vlv_set_cdclk(struct intel_display *display, > const struct intel_cdclk_config *cdclk_config, > enum pipe pipe) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > int cdclk = cdclk_config->cdclk; > u32 val, cmd = cdclk_config->voltage_level; > intel_wakeref_t wakeref; > @@ -663,7 +671,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, > if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & > DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), > 50)) { > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "timed out waiting for CDclk change\n"); > } > > @@ -682,7 +690,7 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, > if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & > CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), > 50)) > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "timed out waiting for CDclk change\n"); > } > > @@ -705,17 +713,18 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, > BIT(VLV_IOSF_SB_BUNIT) | > BIT(VLV_IOSF_SB_PUNIT)); > > - intel_update_cdclk(dev_priv); > + intel_update_cdclk(display); > > - vlv_program_pfi_credits(dev_priv); > + vlv_program_pfi_credits(display); > > intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); > } > > -static void chv_set_cdclk(struct drm_i915_private *dev_priv, > +static void chv_set_cdclk(struct intel_display *display, > const struct intel_cdclk_config *cdclk_config, > enum pipe pipe) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > int cdclk = cdclk_config->cdclk; > u32 val, cmd = cdclk_config->voltage_level; > intel_wakeref_t wakeref; > @@ -747,15 +756,15 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv, > if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & > DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), > 50)) { > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "timed out waiting for CDclk change\n"); > } > > vlv_punit_put(dev_priv); > > - intel_update_cdclk(dev_priv); > + intel_update_cdclk(display); > > - vlv_program_pfi_credits(dev_priv); > + vlv_program_pfi_credits(display); > > intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); > } > @@ -787,15 +796,15 @@ static u8 bdw_calc_voltage_level(int cdclk) > } > } > > -static void bdw_get_cdclk(struct drm_i915_private *dev_priv, > +static void bdw_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > - u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); > + u32 lcpll = intel_de_read(display, LCPLL_CTL); > u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; > > if (lcpll & LCPLL_CD_SOURCE_FCLK) > cdclk_config->cdclk = 800000; > - else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) > + else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) > cdclk_config->cdclk = 450000; > else if (freq == LCPLL_CLK_FREQ_450) > cdclk_config->cdclk = 450000; > @@ -831,15 +840,16 @@ static u32 bdw_cdclk_freq_sel(int cdclk) > } > } > > -static void bdw_set_cdclk(struct drm_i915_private *dev_priv, > +static void bdw_set_cdclk(struct intel_display *display, > const struct intel_cdclk_config *cdclk_config, > enum pipe pipe) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > int cdclk = cdclk_config->cdclk; > int ret; > > - if (drm_WARN(&dev_priv->drm, > - (intel_de_read(dev_priv, LCPLL_CTL) & > + if (drm_WARN(display->drm, > + (intel_de_read(display, LCPLL_CTL) & > (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | > LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | > LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | > @@ -849,39 +859,39 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, > > ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); > if (ret) { > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "failed to inform pcode about cdclk change\n"); > return; > } > > - intel_de_rmw(dev_priv, LCPLL_CTL, > + intel_de_rmw(display, LCPLL_CTL, > 0, LCPLL_CD_SOURCE_FCLK); > > /* > * According to the spec, it should be enough to poll for this 1 us. > * However, extensive testing shows that this can take longer. > */ > - if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & > + if (wait_for_us(intel_de_read(display, LCPLL_CTL) & > LCPLL_CD_SOURCE_FCLK_DONE, 100)) > - drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); > + drm_err(display->drm, "Switching to FCLK failed\n"); > > - intel_de_rmw(dev_priv, LCPLL_CTL, > + intel_de_rmw(display, LCPLL_CTL, > LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk)); > > - intel_de_rmw(dev_priv, LCPLL_CTL, > + intel_de_rmw(display, LCPLL_CTL, > LCPLL_CD_SOURCE_FCLK, 0); > > - if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & > + if (wait_for_us((intel_de_read(display, LCPLL_CTL) & > LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) > - drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); > + drm_err(display->drm, "Switching back to LCPLL failed\n"); > > snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, > cdclk_config->voltage_level); > > - intel_de_write(dev_priv, CDCLK_FREQ, > + intel_de_write(display, CDCLK_FREQ, > DIV_ROUND_CLOSEST(cdclk, 1000) - 1); > > - intel_update_cdclk(dev_priv); > + intel_update_cdclk(display); > } > > static int skl_calc_cdclk(int min_cdclk, int vco) > @@ -919,7 +929,7 @@ static u8 skl_calc_voltage_level(int cdclk) > return 0; > } > > -static void skl_dpll0_update(struct drm_i915_private *dev_priv, > +static void skl_dpll0_update(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > u32 val; > @@ -927,16 +937,16 @@ static void skl_dpll0_update(struct drm_i915_private *dev_priv, > cdclk_config->ref = 24000; > cdclk_config->vco = 0; > > - val = intel_de_read(dev_priv, LCPLL1_CTL); > + val = intel_de_read(display, LCPLL1_CTL); > if ((val & LCPLL_PLL_ENABLE) == 0) > return; > > - if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) > + if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0)) > return; > > - val = intel_de_read(dev_priv, DPLL_CTRL1); > + val = intel_de_read(display, DPLL_CTRL1); > > - if (drm_WARN_ON(&dev_priv->drm, > + if (drm_WARN_ON(display->drm, > (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | > DPLL_CTRL1_SSC(SKL_DPLL0) | > DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != > @@ -960,19 +970,19 @@ static void skl_dpll0_update(struct drm_i915_private *dev_priv, > } > } > > -static void skl_get_cdclk(struct drm_i915_private *dev_priv, > +static void skl_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > u32 cdctl; > > - skl_dpll0_update(dev_priv, cdclk_config); > + skl_dpll0_update(display, cdclk_config); > > cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; > > if (cdclk_config->vco == 0) > goto out; > > - cdctl = intel_de_read(dev_priv, CDCLK_CTL); > + cdctl = intel_de_read(display, CDCLK_CTL); > > if (cdclk_config->vco == 8640000) { > switch (cdctl & CDCLK_FREQ_SEL_MASK) { > @@ -1027,19 +1037,19 @@ static int skl_cdclk_decimal(int cdclk) > return DIV_ROUND_CLOSEST(cdclk - 1000, 500); > } > > -static void skl_set_preferred_cdclk_vco(struct drm_i915_private *i915, int vco) > +static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco) > { > - bool changed = i915->display.cdclk.skl_preferred_vco_freq != vco; > + bool changed = display->cdclk.skl_preferred_vco_freq != vco; > > - i915->display.cdclk.skl_preferred_vco_freq = vco; > + display->cdclk.skl_preferred_vco_freq = vco; > > if (changed) > - intel_update_max_cdclk(i915); > + intel_update_max_cdclk(display); > } > > -static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) > +static u32 skl_dpll0_link_rate(struct intel_display *display, int vco) > { > - drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); > + drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); > > /* > * We always enable DPLL0 with the lowest link rate possible, but still > @@ -1056,47 +1066,47 @@ static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) > return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); > } > > -static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) > +static void skl_dpll0_enable(struct intel_display *display, int vco) > { > - intel_de_rmw(dev_priv, DPLL_CTRL1, > + intel_de_rmw(display, DPLL_CTRL1, > DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | > DPLL_CTRL1_SSC(SKL_DPLL0) | > DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), > DPLL_CTRL1_OVERRIDE(SKL_DPLL0) | > - skl_dpll0_link_rate(dev_priv, vco)); > - intel_de_posting_read(dev_priv, DPLL_CTRL1); > + skl_dpll0_link_rate(display, vco)); > + intel_de_posting_read(display, DPLL_CTRL1); > > - intel_de_rmw(dev_priv, LCPLL1_CTL, > + intel_de_rmw(display, LCPLL1_CTL, > 0, LCPLL_PLL_ENABLE); > > - if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) > - drm_err(&dev_priv->drm, "DPLL0 not locked\n"); > + if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) > + drm_err(display->drm, "DPLL0 not locked\n"); > > - dev_priv->display.cdclk.hw.vco = vco; > + display->cdclk.hw.vco = vco; > > /* We'll want to keep using the current vco from now on. */ > - skl_set_preferred_cdclk_vco(dev_priv, vco); > + skl_set_preferred_cdclk_vco(display, vco); > } > > -static void skl_dpll0_disable(struct drm_i915_private *dev_priv) > +static void skl_dpll0_disable(struct intel_display *display) > { > - intel_de_rmw(dev_priv, LCPLL1_CTL, > + intel_de_rmw(display, LCPLL1_CTL, > LCPLL_PLL_ENABLE, 0); > > - if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) > - drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); > + if (intel_de_wait_for_clear(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) > + drm_err(display->drm, "Couldn't disable DPLL0\n"); > > - dev_priv->display.cdclk.hw.vco = 0; > + display->cdclk.hw.vco = 0; > } > > -static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv, > +static u32 skl_cdclk_freq_sel(struct intel_display *display, > int cdclk, int vco) > { > switch (cdclk) { > default: > - drm_WARN_ON(&dev_priv->drm, > - cdclk != dev_priv->display.cdclk.hw.bypass); > - drm_WARN_ON(&dev_priv->drm, vco != 0); > + drm_WARN_ON(display->drm, > + cdclk != display->cdclk.hw.bypass); > + drm_WARN_ON(display->drm, vco != 0); > fallthrough; > case 308571: > case 337500: > @@ -1112,10 +1122,11 @@ static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv, > } > } > > -static void skl_set_cdclk(struct drm_i915_private *dev_priv, > +static void skl_set_cdclk(struct intel_display *display, > const struct intel_cdclk_config *cdclk_config, > enum pipe pipe) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > int cdclk = cdclk_config->cdclk; > int vco = cdclk_config->vco; > u32 freq_select, cdclk_ctl; > @@ -1129,7 +1140,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, > * use the corresponding VCO freq as that always leads to using the > * minimum 308MHz CDCLK. > */ > - drm_WARN_ON_ONCE(&dev_priv->drm, > + drm_WARN_ON_ONCE(display->drm, > IS_SKYLAKE(dev_priv) && vco == 8640000); > > ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, > @@ -1137,54 +1148,54 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, > SKL_CDCLK_READY_FOR_CHANGE, > SKL_CDCLK_READY_FOR_CHANGE, 3); > if (ret) { > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "Failed to inform PCU about cdclk change (%d)\n", ret); > return; > } > > - freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); > + freq_select = skl_cdclk_freq_sel(display, cdclk, vco); > > - if (dev_priv->display.cdclk.hw.vco != 0 && > - dev_priv->display.cdclk.hw.vco != vco) > - skl_dpll0_disable(dev_priv); > + if (display->cdclk.hw.vco != 0 && > + display->cdclk.hw.vco != vco) > + skl_dpll0_disable(display); > > - cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); > + cdclk_ctl = intel_de_read(display, CDCLK_CTL); > > - if (dev_priv->display.cdclk.hw.vco != vco) { > + if (display->cdclk.hw.vco != vco) { > /* Wa Display #1183: skl,kbl,cfl */ > cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); > cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); > - intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); > + intel_de_write(display, CDCLK_CTL, cdclk_ctl); > } > > /* Wa Display #1183: skl,kbl,cfl */ > cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; > - intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); > - intel_de_posting_read(dev_priv, CDCLK_CTL); > + intel_de_write(display, CDCLK_CTL, cdclk_ctl); > + intel_de_posting_read(display, CDCLK_CTL); > > - if (dev_priv->display.cdclk.hw.vco != vco) > - skl_dpll0_enable(dev_priv, vco); > + if (display->cdclk.hw.vco != vco) > + skl_dpll0_enable(display, vco); > > /* Wa Display #1183: skl,kbl,cfl */ > cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); > - intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); > + intel_de_write(display, CDCLK_CTL, cdclk_ctl); > > cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); > - intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); > + intel_de_write(display, CDCLK_CTL, cdclk_ctl); > > /* Wa Display #1183: skl,kbl,cfl */ > cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; > - intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); > - intel_de_posting_read(dev_priv, CDCLK_CTL); > + intel_de_write(display, CDCLK_CTL, cdclk_ctl); > + intel_de_posting_read(display, CDCLK_CTL); > > /* inform PCU of the change */ > snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, > cdclk_config->voltage_level); > > - intel_update_cdclk(dev_priv); > + intel_update_cdclk(display); > } > > -static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) > +static void skl_sanitize_cdclk(struct intel_display *display) > { > u32 cdctl, expected; > > @@ -1193,15 +1204,15 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) > * There is SWF18 scratchpad register defined which is set by the > * pre-os which can be used by the OS drivers to check the status > */ > - if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) > + if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) > goto sanitize; > > - intel_update_cdclk(dev_priv); > - intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); > + intel_update_cdclk(display); > + intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); > > /* Is PLL enabled and locked ? */ > - if (dev_priv->display.cdclk.hw.vco == 0 || > - dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) > + if (display->cdclk.hw.vco == 0 || > + display->cdclk.hw.cdclk == display->cdclk.hw.bypass) > goto sanitize; > > /* DPLL okay; verify the cdclock > @@ -1210,60 +1221,60 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) > * decimal part is programmed wrong from BIOS where pre-os does not > * enable display. Verify the same as well. > */ > - cdctl = intel_de_read(dev_priv, CDCLK_CTL); > + cdctl = intel_de_read(display, CDCLK_CTL); > expected = (cdctl & CDCLK_FREQ_SEL_MASK) | > - skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); > + skl_cdclk_decimal(display->cdclk.hw.cdclk); > if (cdctl == expected) > /* All well; nothing to sanitize */ > return; > > sanitize: > - drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); > + drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); > > /* force cdclk programming */ > - dev_priv->display.cdclk.hw.cdclk = 0; > + display->cdclk.hw.cdclk = 0; > /* force full PLL disable + enable */ > - dev_priv->display.cdclk.hw.vco = ~0; > + display->cdclk.hw.vco = ~0; > } > > -static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) > +static void skl_cdclk_init_hw(struct intel_display *display) > { > struct intel_cdclk_config cdclk_config; > > - skl_sanitize_cdclk(dev_priv); > + skl_sanitize_cdclk(display); > > - if (dev_priv->display.cdclk.hw.cdclk != 0 && > - dev_priv->display.cdclk.hw.vco != 0) { > + if (display->cdclk.hw.cdclk != 0 && > + display->cdclk.hw.vco != 0) { > /* > * Use the current vco as our initial > * guess as to what the preferred vco is. > */ > - if (dev_priv->display.cdclk.skl_preferred_vco_freq == 0) > - skl_set_preferred_cdclk_vco(dev_priv, > - dev_priv->display.cdclk.hw.vco); > + if (display->cdclk.skl_preferred_vco_freq == 0) > + skl_set_preferred_cdclk_vco(display, > + display->cdclk.hw.vco); > return; > } > > - cdclk_config = dev_priv->display.cdclk.hw; > + cdclk_config = display->cdclk.hw; > > - cdclk_config.vco = dev_priv->display.cdclk.skl_preferred_vco_freq; > + cdclk_config.vco = display->cdclk.skl_preferred_vco_freq; > if (cdclk_config.vco == 0) > cdclk_config.vco = 8100000; > cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); > cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); > > - skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); > + skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); > } > > -static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) > +static void skl_cdclk_uninit_hw(struct intel_display *display) > { > - struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; > + struct intel_cdclk_config cdclk_config = display->cdclk.hw; > > cdclk_config.cdclk = cdclk_config.bypass; > cdclk_config.vco = 0; > cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); > > - skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); > + skl_set_cdclk(display, &cdclk_config, INVALID_PIPE); > } > > struct intel_cdclk_vals { > @@ -1471,37 +1482,37 @@ static int cdclk_divider(int cdclk, int vco, u16 waveform) > cdclk * cdclk_squash_len); > } > > -static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) > +static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk) > { > - const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; > + const struct intel_cdclk_vals *table = display->cdclk.table; > int i; > > for (i = 0; table[i].refclk; i++) > - if (table[i].refclk == dev_priv->display.cdclk.hw.ref && > + if (table[i].refclk == display->cdclk.hw.ref && > table[i].cdclk >= min_cdclk) > return table[i].cdclk; > > - drm_WARN(&dev_priv->drm, 1, > + drm_WARN(display->drm, 1, > "Cannot satisfy minimum cdclk %d with refclk %u\n", > - min_cdclk, dev_priv->display.cdclk.hw.ref); > + min_cdclk, display->cdclk.hw.ref); > return 0; > } > > -static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) > +static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk) > { > - const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; > + const struct intel_cdclk_vals *table = display->cdclk.table; > int i; > > - if (cdclk == dev_priv->display.cdclk.hw.bypass) > + if (cdclk == display->cdclk.hw.bypass) > return 0; > > for (i = 0; table[i].refclk; i++) > - if (table[i].refclk == dev_priv->display.cdclk.hw.ref && > + if (table[i].refclk == display->cdclk.hw.ref && > table[i].cdclk == cdclk) > - return dev_priv->display.cdclk.hw.ref * table[i].ratio; > + return display->cdclk.hw.ref * table[i].ratio; > > - drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", > - cdclk, dev_priv->display.cdclk.hw.ref); > + drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", > + cdclk, display->cdclk.hw.ref); > return 0; > } > > @@ -1583,10 +1594,10 @@ static u8 rplu_calc_voltage_level(int cdclk) > rplu_voltage_level_max_cdclk); > } > > -static void icl_readout_refclk(struct drm_i915_private *dev_priv, > +static void icl_readout_refclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > - u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; > + u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; > > switch (dssm) { > default: > @@ -1604,19 +1615,20 @@ static void icl_readout_refclk(struct drm_i915_private *dev_priv, > } > } > > -static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, > +static void bxt_de_pll_readout(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > u32 val, ratio; > > if (IS_DG2(dev_priv)) > cdclk_config->ref = 38400; > - else if (DISPLAY_VER(dev_priv) >= 11) > - icl_readout_refclk(dev_priv, cdclk_config); > + else if (DISPLAY_VER(display) >= 11) > + icl_readout_refclk(display, cdclk_config); > else > cdclk_config->ref = 19200; > > - val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); > + val = intel_de_read(display, BXT_DE_PLL_ENABLE); > if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || > (val & BXT_DE_PLL_LOCK) == 0) { > /* > @@ -1631,26 +1643,26 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, > * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register, > * gen9lp had it in a separate PLL control register. > */ > - if (DISPLAY_VER(dev_priv) >= 11) > + if (DISPLAY_VER(display) >= 11) > ratio = val & ICL_CDCLK_PLL_RATIO_MASK; > else > - ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; > + ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; > > cdclk_config->vco = ratio * cdclk_config->ref; > } > > -static void bxt_get_cdclk(struct drm_i915_private *dev_priv, > +static void bxt_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config) > { > u32 squash_ctl = 0; > u32 divider; > int div; > > - bxt_de_pll_readout(dev_priv, cdclk_config); > + bxt_de_pll_readout(display, cdclk_config); > > - if (DISPLAY_VER(dev_priv) >= 12) > + if (DISPLAY_VER(display) >= 12) > cdclk_config->bypass = cdclk_config->ref / 2; > - else if (DISPLAY_VER(dev_priv) >= 11) > + else if (DISPLAY_VER(display) >= 11) > cdclk_config->bypass = 50000; > else > cdclk_config->bypass = cdclk_config->ref; > @@ -1660,7 +1672,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, > goto out; > } > > - divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; > + divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; > > switch (divider) { > case BXT_CDCLK_CD2X_DIV_SEL_1: > @@ -1680,8 +1692,8 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, > return; > } > > - if (HAS_CDCLK_SQUASH(dev_priv)) > - squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL); > + if (HAS_CDCLK_SQUASH(display)) > + squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL); > > if (squash_ctl & CDCLK_SQUASH_ENABLE) { > u16 waveform; > @@ -1697,107 +1709,107 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, > } > > out: > - if (DISPLAY_VER(dev_priv) >= 20) > - cdclk_config->joined_mbus = intel_de_read(dev_priv, MBUS_CTL) & MBUS_JOIN; > + if (DISPLAY_VER(display) >= 20) > + cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN; > /* > * Can't read this out :( Let's assume it's > * at least what the CDCLK frequency requires. > */ > cdclk_config->voltage_level = > - intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); > + intel_cdclk_calc_voltage_level(display, cdclk_config->cdclk); > } > > -static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) > +static void bxt_de_pll_disable(struct intel_display *display) > { > - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); > + intel_de_write(display, BXT_DE_PLL_ENABLE, 0); > > /* Timeout 200us */ > - if (intel_de_wait_for_clear(dev_priv, > + if (intel_de_wait_for_clear(display, > BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) > - drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); > + drm_err(display->drm, "timeout waiting for DE PLL unlock\n"); > > - dev_priv->display.cdclk.hw.vco = 0; > + display->cdclk.hw.vco = 0; > } > > -static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) > +static void bxt_de_pll_enable(struct intel_display *display, int vco) > { > - int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); > + int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); > > - intel_de_rmw(dev_priv, BXT_DE_PLL_CTL, > + intel_de_rmw(display, BXT_DE_PLL_CTL, > BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio)); > > - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); > + intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); > > /* Timeout 200us */ > - if (intel_de_wait_for_set(dev_priv, > + if (intel_de_wait_for_set(display, > BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) > - drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); > + drm_err(display->drm, "timeout waiting for DE PLL lock\n"); > > - dev_priv->display.cdclk.hw.vco = vco; > + display->cdclk.hw.vco = vco; > } > > -static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv) > +static void icl_cdclk_pll_disable(struct intel_display *display) > { > - intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE, > + intel_de_rmw(display, BXT_DE_PLL_ENABLE, > BXT_DE_PLL_PLL_ENABLE, 0); > > /* Timeout 200us */ > - if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) > - drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); > + if (intel_de_wait_for_clear(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) > + drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n"); > > - dev_priv->display.cdclk.hw.vco = 0; > + display->cdclk.hw.vco = 0; > } > > -static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) > +static void icl_cdclk_pll_enable(struct intel_display *display, int vco) > { > - int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); > + int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); > u32 val; > > val = ICL_CDCLK_PLL_RATIO(ratio); > - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); > + intel_de_write(display, BXT_DE_PLL_ENABLE, val); > > val |= BXT_DE_PLL_PLL_ENABLE; > - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); > + intel_de_write(display, BXT_DE_PLL_ENABLE, val); > > /* Timeout 200us */ > - if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) > - drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); > + if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) > + drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n"); > > - dev_priv->display.cdclk.hw.vco = vco; > + display->cdclk.hw.vco = vco; > } > > -static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) > +static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco) > { > - int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); > + int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref); > u32 val; > > /* Write PLL ratio without disabling */ > val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE; > - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); > + intel_de_write(display, BXT_DE_PLL_ENABLE, val); > > /* Submit freq change request */ > val |= BXT_DE_PLL_FREQ_REQ; > - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); > + intel_de_write(display, BXT_DE_PLL_ENABLE, val); > > /* Timeout 200us */ > - if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, > + if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, > BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1)) > - drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n"); > + drm_err(display->drm, "timeout waiting for FREQ change request ack\n"); > > val &= ~BXT_DE_PLL_FREQ_REQ; > - intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); > + intel_de_write(display, BXT_DE_PLL_ENABLE, val); > > - dev_priv->display.cdclk.hw.vco = vco; > + display->cdclk.hw.vco = vco; > } > > -static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) > +static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe) > { > - if (DISPLAY_VER(dev_priv) >= 12) { > + if (DISPLAY_VER(display) >= 12) { > if (pipe == INVALID_PIPE) > return TGL_CDCLK_CD2X_PIPE_NONE; > else > return TGL_CDCLK_CD2X_PIPE(pipe); > - } else if (DISPLAY_VER(dev_priv) >= 11) { > + } else if (DISPLAY_VER(display) >= 11) { > if (pipe == INVALID_PIPE) > return ICL_CDCLK_CD2X_PIPE_NONE; > else > @@ -1810,15 +1822,15 @@ static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe > } > } > > -static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, > +static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display, > int cdclk, int vco, u16 waveform) > { > /* cdclk = vco / 2 / div{1,1.5,2,4} */ > switch (cdclk_divider(cdclk, vco, waveform)) { > default: > - drm_WARN_ON(&dev_priv->drm, > - cdclk != dev_priv->display.cdclk.hw.bypass); > - drm_WARN_ON(&dev_priv->drm, vco != 0); > + drm_WARN_ON(display->drm, > + cdclk != display->cdclk.hw.bypass); > + drm_WARN_ON(display->drm, vco != 0); > fallthrough; > case 2: > return BXT_CDCLK_CD2X_DIV_SEL_1; > @@ -1831,47 +1843,47 @@ static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, > } > } > > -static u16 cdclk_squash_waveform(struct drm_i915_private *dev_priv, > +static u16 cdclk_squash_waveform(struct intel_display *display, > int cdclk) > { > - const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; > + const struct intel_cdclk_vals *table = display->cdclk.table; > int i; > > - if (cdclk == dev_priv->display.cdclk.hw.bypass) > + if (cdclk == display->cdclk.hw.bypass) > return 0; > > for (i = 0; table[i].refclk; i++) > - if (table[i].refclk == dev_priv->display.cdclk.hw.ref && > + if (table[i].refclk == display->cdclk.hw.ref && > table[i].cdclk == cdclk) > return table[i].waveform; > > - drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", > - cdclk, dev_priv->display.cdclk.hw.ref); > + drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n", > + cdclk, display->cdclk.hw.ref); > > return 0xffff; > } > > -static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco) > +static void icl_cdclk_pll_update(struct intel_display *display, int vco) > { > - if (i915->display.cdclk.hw.vco != 0 && > - i915->display.cdclk.hw.vco != vco) > - icl_cdclk_pll_disable(i915); > + if (display->cdclk.hw.vco != 0 && > + display->cdclk.hw.vco != vco) > + icl_cdclk_pll_disable(display); > > - if (i915->display.cdclk.hw.vco != vco) > - icl_cdclk_pll_enable(i915, vco); > + if (display->cdclk.hw.vco != vco) > + icl_cdclk_pll_enable(display, vco); > } > > -static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco) > +static void bxt_cdclk_pll_update(struct intel_display *display, int vco) > { > - if (i915->display.cdclk.hw.vco != 0 && > - i915->display.cdclk.hw.vco != vco) > - bxt_de_pll_disable(i915); > + if (display->cdclk.hw.vco != 0 && > + display->cdclk.hw.vco != vco) > + bxt_de_pll_disable(display); > > - if (i915->display.cdclk.hw.vco != vco) > - bxt_de_pll_enable(i915, vco); > + if (display->cdclk.hw.vco != vco) > + bxt_de_pll_enable(display, vco); > } > > -static void dg2_cdclk_squash_program(struct drm_i915_private *i915, > +static void dg2_cdclk_squash_program(struct intel_display *display, > u16 waveform) > { > u32 squash_ctl = 0; > @@ -1880,7 +1892,7 @@ static void dg2_cdclk_squash_program(struct drm_i915_private *i915, > squash_ctl = CDCLK_SQUASH_ENABLE | > CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; > > - intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl); > + intel_de_write(display, CDCLK_SQUASH_CTL, squash_ctl); > } > > static bool cdclk_pll_is_unknown(unsigned int vco) > @@ -1893,38 +1905,40 @@ static bool cdclk_pll_is_unknown(unsigned int vco) > return vco == ~0; > } > > -static bool mdclk_source_is_cdclk_pll(struct drm_i915_private *i915) > +static bool mdclk_source_is_cdclk_pll(struct intel_display *display) > { > - return DISPLAY_VER(i915) >= 20; > + return DISPLAY_VER(display) >= 20; > } > > -static u32 xe2lpd_mdclk_source_sel(struct drm_i915_private *i915) > +static u32 xe2lpd_mdclk_source_sel(struct intel_display *display) > { > - if (mdclk_source_is_cdclk_pll(i915)) > + if (mdclk_source_is_cdclk_pll(display)) > return MDCLK_SOURCE_SEL_CDCLK_PLL; > > return MDCLK_SOURCE_SEL_CD2XCLK; > } > > -int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915, > +int intel_mdclk_cdclk_ratio(struct intel_display *display, > const struct intel_cdclk_config *cdclk_config) > { > - if (mdclk_source_is_cdclk_pll(i915)) > + if (mdclk_source_is_cdclk_pll(display)) > return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk); > > /* Otherwise, source for MDCLK is CD2XCLK. */ > return 2; > } > > -static void xe2lpd_mdclk_cdclk_ratio_program(struct drm_i915_private *i915, > +static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display, > const struct intel_cdclk_config *cdclk_config) > { > + struct drm_i915_private *i915 = to_i915(display->drm); > + > intel_dbuf_mdclk_cdclk_ratio_update(i915, > - intel_mdclk_cdclk_ratio(i915, cdclk_config), > + intel_mdclk_cdclk_ratio(display, cdclk_config), > cdclk_config->joined_mbus); > } > > -static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915, > +static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display, > const struct intel_cdclk_config *old_cdclk_config, > const struct intel_cdclk_config *new_cdclk_config, > struct intel_cdclk_config *mid_cdclk_config) > @@ -1937,11 +1951,11 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91 > return false; > > /* Return if both Squash and Crawl are not present */ > - if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915)) > + if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) > return false; > > - old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk); > - new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk); > + old_waveform = cdclk_squash_waveform(display, old_cdclk_config->cdclk); > + new_waveform = cdclk_squash_waveform(display, new_cdclk_config->cdclk); > > /* Return if Squash only or Crawl only is the desired action */ > if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || > @@ -1958,7 +1972,7 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91 > * Should not happen currently. We might need more midpoint > * transitions if we need to also change the cd2x divider. > */ > - if (drm_WARN_ON(&i915->drm, old_div != new_div)) > + if (drm_WARN_ON(display->drm, old_div != new_div)) > return false; > > *mid_cdclk_config = *new_cdclk_config; > @@ -1987,37 +2001,40 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91 > > /* make sure the mid clock came out sane */ > > - drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk < > + drm_WARN_ON(display->drm, mid_cdclk_config->cdclk < > min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); > - drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk > > - i915->display.cdclk.max_cdclk_freq); > - drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) != > + drm_WARN_ON(display->drm, mid_cdclk_config->cdclk > > + display->cdclk.max_cdclk_freq); > + drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) != > mid_waveform); > > return true; > } > > -static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) > +static bool pll_enable_wa_needed(struct intel_display *display) > { > - return (DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0) || > - DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0) || > + struct drm_i915_private *dev_priv = to_i915(display->drm); > + > + return (DISPLAY_VER_FULL(display) == IP_VER(20, 0) || > + DISPLAY_VER_FULL(display) == IP_VER(14, 0) || > IS_DG2(dev_priv)) && > - dev_priv->display.cdclk.hw.vco > 0; > + display->cdclk.hw.vco > 0; > } > > -static u32 bxt_cdclk_ctl(struct drm_i915_private *i915, > +static u32 bxt_cdclk_ctl(struct intel_display *display, > const struct intel_cdclk_config *cdclk_config, > enum pipe pipe) > { > + struct drm_i915_private *i915 = to_i915(display->drm); > int cdclk = cdclk_config->cdclk; > int vco = cdclk_config->vco; > u16 waveform; > u32 val; > > - waveform = cdclk_squash_waveform(i915, cdclk); > + waveform = cdclk_squash_waveform(display, cdclk); > > - val = bxt_cdclk_cd2x_div_sel(i915, cdclk, vco, waveform) | > - bxt_cdclk_cd2x_pipe(i915, pipe); > + val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) | > + bxt_cdclk_cd2x_pipe(display, pipe); > > /* > * Disable SSA Precharge when CD clock frequency < 500 MHz, > @@ -2027,52 +2044,52 @@ static u32 bxt_cdclk_ctl(struct drm_i915_private *i915, > cdclk >= 500000) > val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; > > - if (DISPLAY_VER(i915) >= 20) > - val |= xe2lpd_mdclk_source_sel(i915); > + if (DISPLAY_VER(display) >= 20) > + val |= xe2lpd_mdclk_source_sel(display); > else > val |= skl_cdclk_decimal(cdclk); > > return val; > } > > -static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, > +static void _bxt_set_cdclk(struct intel_display *display, > const struct intel_cdclk_config *cdclk_config, > enum pipe pipe) > { > - struct intel_display *display = &dev_priv->display; > int cdclk = cdclk_config->cdclk; > int vco = cdclk_config->vco; > > - if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && > - !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { > - if (dev_priv->display.cdclk.hw.vco != vco) > - adlp_cdclk_pll_crawl(dev_priv, vco); > - } else if (DISPLAY_VER(dev_priv) >= 11) { > + if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 && > + !cdclk_pll_is_unknown(display->cdclk.hw.vco)) { > + if (display->cdclk.hw.vco != vco) > + adlp_cdclk_pll_crawl(display, vco); > + } else if (DISPLAY_VER(display) >= 11) { > /* wa_15010685871: dg2, mtl */ > - if (pll_enable_wa_needed(dev_priv)) > - dg2_cdclk_squash_program(dev_priv, 0); > + if (pll_enable_wa_needed(display)) > + dg2_cdclk_squash_program(display, 0); > > - icl_cdclk_pll_update(dev_priv, vco); > + icl_cdclk_pll_update(display, vco); > } else { > - bxt_cdclk_pll_update(dev_priv, vco); > + bxt_cdclk_pll_update(display, vco); > } > > - if (HAS_CDCLK_SQUASH(dev_priv)) { > - u16 waveform = cdclk_squash_waveform(dev_priv, cdclk); > + if (HAS_CDCLK_SQUASH(display)) { > + u16 waveform = cdclk_squash_waveform(display, cdclk); > > - dg2_cdclk_squash_program(dev_priv, waveform); > + dg2_cdclk_squash_program(display, waveform); > } > > - intel_de_write(dev_priv, CDCLK_CTL, bxt_cdclk_ctl(dev_priv, cdclk_config, pipe)); > + intel_de_write(display, CDCLK_CTL, bxt_cdclk_ctl(display, cdclk_config, pipe)); > > if (pipe != INVALID_PIPE) > intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); > } > > -static void bxt_set_cdclk(struct drm_i915_private *dev_priv, > +static void bxt_set_cdclk(struct intel_display *display, > const struct intel_cdclk_config *cdclk_config, > enum pipe pipe) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > struct intel_cdclk_config mid_cdclk_config; > int cdclk = cdclk_config->cdclk; > int ret = 0; > @@ -2083,9 +2100,9 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, > * mailbox communication, skip > * this step. > */ > - if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv)) > + if (DISPLAY_VER(display) >= 14 || IS_DG2(dev_priv)) > /* NOOP */; > - else if (DISPLAY_VER(dev_priv) >= 11) > + else if (DISPLAY_VER(display) >= 11) > ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, > SKL_CDCLK_PREPARE_FOR_CHANGE, > SKL_CDCLK_READY_FOR_CHANGE, > @@ -2100,35 +2117,35 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, > 0x80000000, 150, 2); > > if (ret) { > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "Failed to inform PCU about cdclk change (err %d, freq %d)\n", > ret, cdclk); > return; > } > > - if (DISPLAY_VER(dev_priv) >= 20 && cdclk < dev_priv->display.cdclk.hw.cdclk) > - xe2lpd_mdclk_cdclk_ratio_program(dev_priv, cdclk_config); > + if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk) > + xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); > > - if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, > + if (cdclk_compute_crawl_and_squash_midpoint(display, &display->cdclk.hw, > cdclk_config, &mid_cdclk_config)) { > - _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe); > - _bxt_set_cdclk(dev_priv, cdclk_config, pipe); > + _bxt_set_cdclk(display, &mid_cdclk_config, pipe); > + _bxt_set_cdclk(display, cdclk_config, pipe); > } else { > - _bxt_set_cdclk(dev_priv, cdclk_config, pipe); > + _bxt_set_cdclk(display, cdclk_config, pipe); > } > > - if (DISPLAY_VER(dev_priv) >= 20 && cdclk > dev_priv->display.cdclk.hw.cdclk) > - xe2lpd_mdclk_cdclk_ratio_program(dev_priv, cdclk_config); > + if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk) > + xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config); > > - if (DISPLAY_VER(dev_priv) >= 14) > + if (DISPLAY_VER(display) >= 14) > /* > * NOOP - No Pcode communication needed for > * Display versions 14 and beyond > */; > - else if (DISPLAY_VER(dev_priv) >= 11 && !IS_DG2(dev_priv)) > + else if (DISPLAY_VER(display) >= 11 && !IS_DG2(dev_priv)) > ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, > cdclk_config->voltage_level); > - if (DISPLAY_VER(dev_priv) < 11) { > + if (DISPLAY_VER(display) < 11) { > /* > * The timeout isn't specified, the 2ms used here is based on > * experiment. > @@ -2141,42 +2158,42 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, > 150, 2); > } > if (ret) { > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "PCode CDCLK freq set failed, (err %d, freq %d)\n", > ret, cdclk); > return; > } > > - intel_update_cdclk(dev_priv); > + intel_update_cdclk(display); > > - if (DISPLAY_VER(dev_priv) >= 11) > + if (DISPLAY_VER(display) >= 11) > /* > * Can't read out the voltage level :( > * Let's just assume everything is as expected. > */ > - dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; > + display->cdclk.hw.voltage_level = cdclk_config->voltage_level; > } > > -static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) > +static void bxt_sanitize_cdclk(struct intel_display *display) > { > u32 cdctl, expected; > int cdclk, vco; > > - intel_update_cdclk(dev_priv); > - intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); > + intel_update_cdclk(display); > + intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); > > - if (dev_priv->display.cdclk.hw.vco == 0 || > - dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) > + if (display->cdclk.hw.vco == 0 || > + display->cdclk.hw.cdclk == display->cdclk.hw.bypass) > goto sanitize; > > /* Make sure this is a legal cdclk value for the platform */ > - cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); > - if (cdclk != dev_priv->display.cdclk.hw.cdclk) > + cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); > + if (cdclk != display->cdclk.hw.cdclk) > goto sanitize; > > /* Make sure the VCO is correct for the cdclk */ > - vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); > - if (vco != dev_priv->display.cdclk.hw.vco) > + vco = bxt_calc_cdclk_pll_vco(display, cdclk); > + if (vco != display->cdclk.hw.vco) > goto sanitize; > > /* > @@ -2184,129 +2201,133 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) > * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, > * so sanitize this register. > */ > - cdctl = intel_de_read(dev_priv, CDCLK_CTL); > - expected = bxt_cdclk_ctl(dev_priv, &dev_priv->display.cdclk.hw, INVALID_PIPE); > + cdctl = intel_de_read(display, CDCLK_CTL); > + expected = bxt_cdclk_ctl(display, &display->cdclk.hw, INVALID_PIPE); > > /* > * Let's ignore the pipe field, since BIOS could have configured the > * dividers both synching to an active pipe, or asynchronously > * (PIPE_NONE). > */ > - cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); > - expected &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); > + cdctl &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); > + expected &= ~bxt_cdclk_cd2x_pipe(display, INVALID_PIPE); > > if (cdctl == expected) > /* All well; nothing to sanitize */ > return; > > sanitize: > - drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); > + drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n"); > > /* force cdclk programming */ > - dev_priv->display.cdclk.hw.cdclk = 0; > + display->cdclk.hw.cdclk = 0; > > /* force full PLL disable + enable */ > - dev_priv->display.cdclk.hw.vco = ~0; > + display->cdclk.hw.vco = ~0; > } > > -static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) > +static void bxt_cdclk_init_hw(struct intel_display *display) > { > struct intel_cdclk_config cdclk_config; > > - bxt_sanitize_cdclk(dev_priv); > + bxt_sanitize_cdclk(display); > > - if (dev_priv->display.cdclk.hw.cdclk != 0 && > - dev_priv->display.cdclk.hw.vco != 0) > + if (display->cdclk.hw.cdclk != 0 && > + display->cdclk.hw.vco != 0) > return; > > - cdclk_config = dev_priv->display.cdclk.hw; > + cdclk_config = display->cdclk.hw; > > /* > * FIXME: > * - The initial CDCLK needs to be read from VBT. > * Need to make this change after VBT has changes for BXT. > */ > - cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); > - cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); > + cdclk_config.cdclk = bxt_calc_cdclk(display, 0); > + cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk_config.cdclk); > cdclk_config.voltage_level = > - intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); > + intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); > > - bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); > + bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); > } > > -static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) > +static void bxt_cdclk_uninit_hw(struct intel_display *display) > { > - struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; > + struct intel_cdclk_config cdclk_config = display->cdclk.hw; > > cdclk_config.cdclk = cdclk_config.bypass; > cdclk_config.vco = 0; > cdclk_config.voltage_level = > - intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); > + intel_cdclk_calc_voltage_level(display, cdclk_config.cdclk); > > - bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); > + bxt_set_cdclk(display, &cdclk_config, INVALID_PIPE); > } > > /** > * intel_cdclk_init_hw - Initialize CDCLK hardware > - * @i915: i915 device > + * @display: display instance > * > - * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and > + * Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and > * sanitizing the state of the hardware if needed. This is generally done only > * during the display core initialization sequence, after which the DMC will > * take care of turning CDCLK off/on as needed. > */ > -void intel_cdclk_init_hw(struct drm_i915_private *i915) > +void intel_cdclk_init_hw(struct intel_display *display) > { > - if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) > - bxt_cdclk_init_hw(i915); > - else if (DISPLAY_VER(i915) == 9) > - skl_cdclk_init_hw(i915); > + struct drm_i915_private *i915 = to_i915(display->drm); > + > + if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915)) > + bxt_cdclk_init_hw(display); > + else if (DISPLAY_VER(display) == 9) > + skl_cdclk_init_hw(display); > } > > /** > * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware > - * @i915: i915 device > + * @display: display instance > * > * Uninitialize CDCLK. This is done only during the display core > * uninitialization sequence. > */ > -void intel_cdclk_uninit_hw(struct drm_i915_private *i915) > +void intel_cdclk_uninit_hw(struct intel_display *display) > { > - if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915)) > - bxt_cdclk_uninit_hw(i915); > - else if (DISPLAY_VER(i915) == 9) > - skl_cdclk_uninit_hw(i915); > + struct drm_i915_private *i915 = to_i915(display->drm); > + > + if (DISPLAY_VER(display) >= 10 || IS_BROXTON(i915)) > + bxt_cdclk_uninit_hw(display); > + else if (DISPLAY_VER(display) == 9) > + skl_cdclk_uninit_hw(display); > } > > -static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915, > +static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display, > const struct intel_cdclk_config *a, > const struct intel_cdclk_config *b) > { > u16 old_waveform; > u16 new_waveform; > > - drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco)); > + drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco)); > > if (a->vco == 0 || b->vco == 0) > return false; > > - if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915)) > + if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display)) > return false; > > - old_waveform = cdclk_squash_waveform(i915, a->cdclk); > - new_waveform = cdclk_squash_waveform(i915, b->cdclk); > + old_waveform = cdclk_squash_waveform(display, a->cdclk); > + new_waveform = cdclk_squash_waveform(display, b->cdclk); > > return a->vco != b->vco && > old_waveform != new_waveform; > } > > -static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, > +static bool intel_cdclk_can_crawl(struct intel_display *display, > const struct intel_cdclk_config *a, > const struct intel_cdclk_config *b) > { > int a_div, b_div; > > - if (!HAS_CDCLK_CRAWL(dev_priv)) > + if (!HAS_CDCLK_CRAWL(display)) > return false; > > /* > @@ -2322,7 +2343,7 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, > a->ref == b->ref; > } > > -static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, > +static bool intel_cdclk_can_squash(struct intel_display *display, > const struct intel_cdclk_config *a, > const struct intel_cdclk_config *b) > { > @@ -2332,7 +2353,7 @@ static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, > * the moment all platforms with squasher use a fixed cd2x > * divider. > */ > - if (!HAS_CDCLK_SQUASH(dev_priv)) > + if (!HAS_CDCLK_SQUASH(display)) > return false; > > return a->cdclk != b->cdclk && > @@ -2361,7 +2382,7 @@ bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, > /** > * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK > * configurations requires only a cd2x divider update > - * @dev_priv: i915 device > + * @display: display instance > * @a: first CDCLK configuration > * @b: second CDCLK configuration > * > @@ -2369,12 +2390,14 @@ bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, > * True if changing between the two CDCLK configurations > * can be done with just a cd2x divider update, false if not. > */ > -static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, > +static bool intel_cdclk_can_cd2x_update(struct intel_display *display, > const struct intel_cdclk_config *a, > const struct intel_cdclk_config *b) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > + > /* Older hw doesn't have the capability */ > - if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv)) > + if (DISPLAY_VER(display) < 10 && !IS_BROXTON(dev_priv)) > return false; > > /* > @@ -2383,7 +2406,7 @@ static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, > * the moment all platforms with squasher use a fixed cd2x > * divider. > */ > - if (HAS_CDCLK_SQUASH(dev_priv)) > + if (HAS_CDCLK_SQUASH(display)) > return false; > > return a->cdclk != b->cdclk && > @@ -2407,23 +2430,24 @@ static bool intel_cdclk_changed(const struct intel_cdclk_config *a, > a->voltage_level != b->voltage_level; > } > > -void intel_cdclk_dump_config(struct drm_i915_private *i915, > +void intel_cdclk_dump_config(struct intel_display *display, > const struct intel_cdclk_config *cdclk_config, > const char *context) > { > - drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", > + drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", > context, cdclk_config->cdclk, cdclk_config->vco, > cdclk_config->ref, cdclk_config->bypass, > cdclk_config->voltage_level); > } > > -static void intel_pcode_notify(struct drm_i915_private *i915, > +static void intel_pcode_notify(struct intel_display *display, > u8 voltage_level, > u8 active_pipe_count, > u16 cdclk, > bool cdclk_update_valid, > bool pipe_count_update_valid) > { > + struct drm_i915_private *i915 = to_i915(display->drm); > int ret; > u32 update_mask = 0; > > @@ -2444,26 +2468,27 @@ static void intel_pcode_notify(struct drm_i915_private *i915, > SKL_CDCLK_READY_FOR_CHANGE, > SKL_CDCLK_READY_FOR_CHANGE, 3); > if (ret) > - drm_err(&i915->drm, > + drm_err(display->drm, > "Failed to inform PCU about display config (err %d)\n", > ret); > } > > -static void intel_set_cdclk(struct drm_i915_private *dev_priv, > +static void intel_set_cdclk(struct intel_display *display, > const struct intel_cdclk_config *cdclk_config, > enum pipe pipe, const char *context) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > struct intel_encoder *encoder; > > - if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) > + if (!intel_cdclk_changed(&display->cdclk.hw, cdclk_config)) > return; > > - if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) > + if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk)) > return; > > - intel_cdclk_dump_config(dev_priv, cdclk_config, context); > + intel_cdclk_dump_config(display, cdclk_config, context); > > - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { > + for_each_intel_encoder_with_psr(display->drm, encoder) { > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > intel_psr_pause(intel_dp); > @@ -2476,24 +2501,24 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, > * functions use cdclk. Not all platforms/ports do, > * but we'll lock them all for simplicity. > */ > - mutex_lock(&dev_priv->display.gmbus.mutex); > - for_each_intel_dp(&dev_priv->drm, encoder) { > + mutex_lock(&display->gmbus.mutex); > + for_each_intel_dp(display->drm, encoder) { > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, > - &dev_priv->display.gmbus.mutex); > + &display->gmbus.mutex); > } > > - intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); > + intel_cdclk_set_cdclk(display, cdclk_config, pipe); > > - for_each_intel_dp(&dev_priv->drm, encoder) { > + for_each_intel_dp(display->drm, encoder) { > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > mutex_unlock(&intel_dp->aux.hw_mutex); > } > - mutex_unlock(&dev_priv->display.gmbus.mutex); > + mutex_unlock(&display->gmbus.mutex); > > - for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { > + for_each_intel_encoder_with_psr(display->drm, encoder) { > struct intel_dp *intel_dp = enc_to_intel_dp(encoder); > > intel_psr_resume(intel_dp); > @@ -2501,17 +2526,17 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, > > intel_audio_cdclk_change_post(dev_priv); > > - if (drm_WARN(&dev_priv->drm, > - intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), > + if (drm_WARN(display->drm, > + intel_cdclk_changed(&display->cdclk.hw, cdclk_config), > "cdclk state doesn't match!\n")) { > - intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); > - intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]"); > + intel_cdclk_dump_config(display, &display->cdclk.hw, "[hw state]"); > + intel_cdclk_dump_config(display, cdclk_config, "[sw state]"); > } > } > > static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) > { > - struct drm_i915_private *i915 = to_i915(state->base.dev); > + struct intel_display *display = to_intel_display(state); > const struct intel_cdclk_state *old_cdclk_state = > intel_atomic_get_old_cdclk_state(state); > const struct intel_cdclk_state *new_cdclk_state = > @@ -2550,13 +2575,13 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) > if (update_pipe_count) > num_active_pipes = hweight8(new_cdclk_state->active_pipes); > > - intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk, > + intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, > change_cdclk, update_pipe_count); > } > > static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) > { > - struct drm_i915_private *i915 = to_i915(state->base.dev); > + struct intel_display *display = to_intel_display(state); > const struct intel_cdclk_state *new_cdclk_state = > intel_atomic_get_new_cdclk_state(state); > const struct intel_cdclk_state *old_cdclk_state = > @@ -2587,7 +2612,7 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) > if (update_pipe_count) > num_active_pipes = hweight8(new_cdclk_state->active_pipes); > > - intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk, > + intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, > update_cdclk, update_pipe_count); > } > > @@ -2612,7 +2637,8 @@ bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state) > void > intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) > { > - struct drm_i915_private *i915 = to_i915(state->base.dev); > + struct intel_display *display = to_intel_display(state); > + struct drm_i915_private *i915 = to_i915(display->drm); > const struct intel_cdclk_state *old_cdclk_state = > intel_atomic_get_old_cdclk_state(state); > const struct intel_cdclk_state *new_cdclk_state = > @@ -2649,9 +2675,9 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) > */ > cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus; > > - drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); > + drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); > > - intel_set_cdclk(i915, &cdclk_config, pipe, > + intel_set_cdclk(display, &cdclk_config, pipe, > "Pre changing CDCLK to"); > } > > @@ -2665,7 +2691,8 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) > void > intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) > { > - struct drm_i915_private *i915 = to_i915(state->base.dev); > + struct intel_display *display = to_intel_display(state); > + struct drm_i915_private *i915 = to_i915(display->drm); > const struct intel_cdclk_state *old_cdclk_state = > intel_atomic_get_old_cdclk_state(state); > const struct intel_cdclk_state *new_cdclk_state = > @@ -2685,20 +2712,21 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) > else > pipe = INVALID_PIPE; > > - drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); > + drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); > > - intel_set_cdclk(i915, &new_cdclk_state->actual, pipe, > + intel_set_cdclk(display, &new_cdclk_state->actual, pipe, > "Post changing CDCLK to"); > } > > static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) > { > - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); > + struct intel_display *display = to_intel_display(crtc_state->uapi.crtc->dev); > + struct drm_i915_private *dev_priv = to_i915(display->drm); > int pixel_rate = crtc_state->pixel_rate; > > - if (DISPLAY_VER(dev_priv) >= 10) > + if (DISPLAY_VER(display) >= 10) > return DIV_ROUND_UP(pixel_rate, 2); > - else if (DISPLAY_VER(dev_priv) == 9 || > + else if (DISPLAY_VER(display) == 9 || > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) > return pixel_rate; > else if (IS_CHERRYVIEW(dev_priv)) > @@ -2712,11 +2740,11 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) > static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) > { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > + struct intel_display *display = to_intel_display(crtc); > struct intel_plane *plane; > int min_cdclk = 0; > > - for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) > + for_each_intel_plane_on_crtc(display->drm, crtc, plane) > min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); > > return min_cdclk; > @@ -2725,7 +2753,7 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state) > static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) > { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > - struct drm_i915_private *i915 = to_i915(crtc->base.dev); > + struct intel_display *display = to_intel_display(crtc); > int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); > int min_cdclk = 0; > > @@ -2754,7 +2782,7 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) > * Since PPC = 2 with bigjoiner > * => CDCLK >= compressed_bpp * Pixel clock / 2 * Bigjoiner Interface bits > */ > - int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24; > + int bigjoiner_interface_bits = DISPLAY_VER(display) >= 14 ? 36 : 24; > int min_cdclk_bj = > (fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) * > pixel_clock) / (2 * bigjoiner_interface_bits); > @@ -2767,8 +2795,9 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) > > int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > { > - struct drm_i915_private *dev_priv = > - to_i915(crtc_state->uapi.crtc->dev); > + struct intel_display *display = > + to_intel_display(crtc_state->uapi.crtc->dev); > + struct drm_i915_private *dev_priv = to_i915(display->drm); > int min_cdclk; > > if (!crtc_state->hw.enable) > @@ -2789,10 +2818,10 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > crtc_state->has_audio && > crtc_state->port_clock >= 540000 && > crtc_state->lane_count == 4) { > - if (DISPLAY_VER(dev_priv) == 10) { > + if (DISPLAY_VER(display) == 10) { > /* Display WA #1145: glk */ > min_cdclk = max(316800, min_cdclk); > - } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) { > + } else if (DISPLAY_VER(display) == 9 || IS_BROADWELL(dev_priv)) { > /* Display WA #1144: skl,bxt */ > min_cdclk = max(432000, min_cdclk); > } > @@ -2802,7 +2831,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > * According to BSpec, "The CD clock frequency must be at least twice > * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. > */ > - if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) > + if (crtc_state->has_audio && DISPLAY_VER(display) >= 9) > min_cdclk = max(2 * 96000, min_cdclk); > > /* > @@ -2844,7 +2873,8 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > > static int intel_compute_min_cdclk(struct intel_atomic_state *state) > { > - struct drm_i915_private *dev_priv = to_i915(state->base.dev); > + struct intel_display *display = to_intel_display(state); > + struct drm_i915_private *dev_priv = to_i915(display->drm); > struct intel_cdclk_state *cdclk_state = > intel_atomic_get_new_cdclk_state(state); > const struct intel_bw_state *bw_state; > @@ -2887,7 +2917,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state) > > min_cdclk = max(cdclk_state->force_min_cdclk, > cdclk_state->bw_min_cdclk); > - for_each_pipe(dev_priv, pipe) > + for_each_pipe(display, pipe) > min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); > > /* > @@ -2902,10 +2932,10 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state) > !is_power_of_2(cdclk_state->active_pipes)) > min_cdclk = max(2 * 96000, min_cdclk); > > - if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { > - drm_dbg_kms(&dev_priv->drm, > + if (min_cdclk > display->cdclk.max_cdclk_freq) { > + drm_dbg_kms(display->drm, > "required cdclk (%d kHz) exceeds max (%d kHz)\n", > - min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); > + min_cdclk, display->cdclk.max_cdclk_freq); > return -EINVAL; > } > > @@ -2927,7 +2957,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state) > */ > static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) > { > - struct drm_i915_private *dev_priv = to_i915(state->base.dev); > + struct intel_display *display = to_intel_display(state); > struct intel_cdclk_state *cdclk_state = > intel_atomic_get_new_cdclk_state(state); > struct intel_crtc *crtc; > @@ -2955,7 +2985,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) > } > > min_voltage_level = 0; > - for_each_pipe(dev_priv, pipe) > + for_each_pipe(display, pipe) > min_voltage_level = max(cdclk_state->min_voltage_level[pipe], > min_voltage_level); > > @@ -2964,7 +2994,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) > > static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) > { > - struct drm_i915_private *dev_priv = to_i915(state->base.dev); > + struct intel_display *display = to_intel_display(state); > struct intel_cdclk_state *cdclk_state = > intel_atomic_get_new_cdclk_state(state); > int min_cdclk, cdclk; > @@ -2973,18 +3003,18 @@ static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) > if (min_cdclk < 0) > return min_cdclk; > > - cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); > + cdclk = vlv_calc_cdclk(display, min_cdclk); > > cdclk_state->logical.cdclk = cdclk; > cdclk_state->logical.voltage_level = > - vlv_calc_voltage_level(dev_priv, cdclk); > + vlv_calc_voltage_level(display, cdclk); > > if (!cdclk_state->active_pipes) { > - cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); > + cdclk = vlv_calc_cdclk(display, cdclk_state->force_min_cdclk); > > cdclk_state->actual.cdclk = cdclk; > cdclk_state->actual.voltage_level = > - vlv_calc_voltage_level(dev_priv, cdclk); > + vlv_calc_voltage_level(display, cdclk); > } else { > cdclk_state->actual = cdclk_state->logical; > } > @@ -3023,7 +3053,7 @@ static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) > > static int skl_dpll0_vco(struct intel_atomic_state *state) > { > - struct drm_i915_private *dev_priv = to_i915(state->base.dev); > + struct intel_display *display = to_intel_display(state); > struct intel_cdclk_state *cdclk_state = > intel_atomic_get_new_cdclk_state(state); > struct intel_crtc *crtc; > @@ -3032,7 +3062,7 @@ static int skl_dpll0_vco(struct intel_atomic_state *state) > > vco = cdclk_state->logical.vco; > if (!vco) > - vco = dev_priv->display.cdclk.skl_preferred_vco_freq; > + vco = display->cdclk.skl_preferred_vco_freq; > > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { > if (!crtc_state->hw.enable) > @@ -3094,7 +3124,7 @@ static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) > > static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) > { > - struct drm_i915_private *dev_priv = to_i915(state->base.dev); > + struct intel_display *display = to_intel_display(state); > struct intel_cdclk_state *cdclk_state = > intel_atomic_get_new_cdclk_state(state); > int min_cdclk, min_voltage_level, cdclk, vco; > @@ -3107,23 +3137,23 @@ static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) > if (min_voltage_level < 0) > return min_voltage_level; > > - cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); > - vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); > + cdclk = bxt_calc_cdclk(display, min_cdclk); > + vco = bxt_calc_cdclk_pll_vco(display, cdclk); > > cdclk_state->logical.vco = vco; > cdclk_state->logical.cdclk = cdclk; > cdclk_state->logical.voltage_level = > max_t(int, min_voltage_level, > - intel_cdclk_calc_voltage_level(dev_priv, cdclk)); > + intel_cdclk_calc_voltage_level(display, cdclk)); > > if (!cdclk_state->active_pipes) { > - cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); > - vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); > + cdclk = bxt_calc_cdclk(display, cdclk_state->force_min_cdclk); > + vco = bxt_calc_cdclk_pll_vco(display, cdclk); > > cdclk_state->actual.vco = vco; > cdclk_state->actual.cdclk = cdclk; > cdclk_state->actual.voltage_level = > - intel_cdclk_calc_voltage_level(dev_priv, cdclk); > + intel_cdclk_calc_voltage_level(display, cdclk); > } else { > cdclk_state->actual = cdclk_state->logical; > } > @@ -3175,10 +3205,10 @@ static const struct intel_global_state_funcs intel_cdclk_funcs = { > struct intel_cdclk_state * > intel_atomic_get_cdclk_state(struct intel_atomic_state *state) > { > - struct drm_i915_private *dev_priv = to_i915(state->base.dev); > + struct intel_display *display = to_intel_display(state); > struct intel_global_state *cdclk_state; > > - cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); > + cdclk_state = intel_atomic_get_global_obj_state(state, &display->cdclk.obj); > if (IS_ERR(cdclk_state)) > return ERR_CAST(cdclk_state); > > @@ -3234,24 +3264,26 @@ int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joi > return intel_atomic_lock_global_state(&cdclk_state->base); > } > > -int intel_cdclk_init(struct drm_i915_private *dev_priv) > +int intel_cdclk_init(struct intel_display *display) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > struct intel_cdclk_state *cdclk_state; > > cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); > if (!cdclk_state) > return -ENOMEM; > > - intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, > + intel_atomic_global_obj_init(dev_priv, &display->cdclk.obj, > &cdclk_state->base, &intel_cdclk_funcs); > > return 0; > } > > -static bool intel_cdclk_need_serialize(struct drm_i915_private *i915, > +static bool intel_cdclk_need_serialize(struct intel_display *display, > const struct intel_cdclk_state *old_cdclk_state, > const struct intel_cdclk_state *new_cdclk_state) > { > + struct drm_i915_private *i915 = to_i915(display->drm); > bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) != > hweight8(new_cdclk_state->active_pipes); > bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual, > @@ -3266,7 +3298,6 @@ static bool intel_cdclk_need_serialize(struct drm_i915_private *i915, > int intel_modeset_calc_cdclk(struct intel_atomic_state *state) > { > struct intel_display *display = to_intel_display(state); > - struct drm_i915_private *dev_priv = to_i915(state->base.dev); > const struct intel_cdclk_state *old_cdclk_state; > struct intel_cdclk_state *new_cdclk_state; > enum pipe pipe = INVALID_PIPE; > @@ -3285,7 +3316,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) > if (ret) > return ret; > > - if (intel_cdclk_need_serialize(dev_priv, old_cdclk_state, new_cdclk_state)) { > + if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) { > /* > * Also serialize commits across all crtcs > * if the actual hw needs to be poked. > @@ -3305,7 +3336,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) > } > > if (is_power_of_2(new_cdclk_state->active_pipes) && > - intel_cdclk_can_cd2x_update(dev_priv, > + intel_cdclk_can_cd2x_update(display, > &old_cdclk_state->actual, > &new_cdclk_state->actual)) { > struct intel_crtc *crtc; > @@ -3322,25 +3353,25 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) > pipe = INVALID_PIPE; > } > > - if (intel_cdclk_can_crawl_and_squash(dev_priv, > + if (intel_cdclk_can_crawl_and_squash(display, > &old_cdclk_state->actual, > &new_cdclk_state->actual)) { > - drm_dbg_kms(&dev_priv->drm, > + drm_dbg_kms(display->drm, > "Can change cdclk via crawling and squashing\n"); > - } else if (intel_cdclk_can_squash(dev_priv, > + } else if (intel_cdclk_can_squash(display, > &old_cdclk_state->actual, > &new_cdclk_state->actual)) { > - drm_dbg_kms(&dev_priv->drm, > + drm_dbg_kms(display->drm, > "Can change cdclk via squashing\n"); > - } else if (intel_cdclk_can_crawl(dev_priv, > + } else if (intel_cdclk_can_crawl(display, > &old_cdclk_state->actual, > &new_cdclk_state->actual)) { > - drm_dbg_kms(&dev_priv->drm, > + drm_dbg_kms(display->drm, > "Can change cdclk via crawling\n"); > } else if (pipe != INVALID_PIPE) { > new_cdclk_state->pipe = pipe; > > - drm_dbg_kms(&dev_priv->drm, > + drm_dbg_kms(display->drm, > "Can change cdclk cd2x divider with pipe %c active\n", > pipe_name(pipe)); > } else if (intel_cdclk_clock_changed(&old_cdclk_state->actual, > @@ -3352,24 +3383,24 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) > > new_cdclk_state->disable_pipes = true; > > - drm_dbg_kms(&dev_priv->drm, > + drm_dbg_kms(display->drm, > "Modeset required for cdclk change\n"); > } > > - if (intel_mdclk_cdclk_ratio(dev_priv, &old_cdclk_state->actual) != > - intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual)) { > - int ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual); > + if (intel_mdclk_cdclk_ratio(display, &old_cdclk_state->actual) != > + intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual)) { > + int ratio = intel_mdclk_cdclk_ratio(display, &new_cdclk_state->actual); > > ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio); > if (ret) > return ret; > } > > - drm_dbg_kms(&dev_priv->drm, > + drm_dbg_kms(display->drm, > "New cdclk calculated to be logical %u kHz, actual %u kHz\n", > new_cdclk_state->logical.cdclk, > new_cdclk_state->actual.cdclk); > - drm_dbg_kms(&dev_priv->drm, > + drm_dbg_kms(display->drm, > "New voltage level calculated to be logical %u, actual %u\n", > new_cdclk_state->logical.voltage_level, > new_cdclk_state->actual.voltage_level); > @@ -3377,18 +3408,19 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) > return 0; > } > > -static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) > +static int intel_compute_max_dotclk(struct intel_display *display) > { > - int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; > + struct drm_i915_private *dev_priv = to_i915(display->drm); > + int max_cdclk_freq = display->cdclk.max_cdclk_freq; > > - if (DISPLAY_VER(dev_priv) >= 10) > + if (DISPLAY_VER(display) >= 10) > return 2 * max_cdclk_freq; > - else if (DISPLAY_VER(dev_priv) == 9 || > + else if (DISPLAY_VER(display) == 9 || > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) > return max_cdclk_freq; > else if (IS_CHERRYVIEW(dev_priv)) > return max_cdclk_freq*95/100; > - else if (DISPLAY_VER(dev_priv) < 4) > + else if (DISPLAY_VER(display) < 4) > return 2*max_cdclk_freq*90/100; > else > return max_cdclk_freq*90/100; > @@ -3396,34 +3428,36 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) > > /** > * intel_update_max_cdclk - Determine the maximum support CDCLK frequency > - * @dev_priv: i915 device > + * @display: display instance > * > * Determine the maximum CDCLK frequency the platform supports, and also > * derive the maximum dot clock frequency the maximum CDCLK frequency > * allows. > */ > -void intel_update_max_cdclk(struct drm_i915_private *dev_priv) > +void intel_update_max_cdclk(struct intel_display *display) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > + > if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { > - if (dev_priv->display.cdclk.hw.ref == 24000) > - dev_priv->display.cdclk.max_cdclk_freq = 552000; > + if (display->cdclk.hw.ref == 24000) > + display->cdclk.max_cdclk_freq = 552000; > else > - dev_priv->display.cdclk.max_cdclk_freq = 556800; > - } else if (DISPLAY_VER(dev_priv) >= 11) { > - if (dev_priv->display.cdclk.hw.ref == 24000) > - dev_priv->display.cdclk.max_cdclk_freq = 648000; > + display->cdclk.max_cdclk_freq = 556800; > + } else if (DISPLAY_VER(display) >= 11) { > + if (display->cdclk.hw.ref == 24000) > + display->cdclk.max_cdclk_freq = 648000; > else > - dev_priv->display.cdclk.max_cdclk_freq = 652800; > + display->cdclk.max_cdclk_freq = 652800; > } else if (IS_GEMINILAKE(dev_priv)) { > - dev_priv->display.cdclk.max_cdclk_freq = 316800; > + display->cdclk.max_cdclk_freq = 316800; > } else if (IS_BROXTON(dev_priv)) { > - dev_priv->display.cdclk.max_cdclk_freq = 624000; > - } else if (DISPLAY_VER(dev_priv) == 9) { > - u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; > + display->cdclk.max_cdclk_freq = 624000; > + } else if (DISPLAY_VER(display) == 9) { > + u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; > int max_cdclk, vco; > > - vco = dev_priv->display.cdclk.skl_preferred_vco_freq; > - drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); > + vco = display->cdclk.skl_preferred_vco_freq; > + drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000); > > /* > * Use the lower (vco 8640) cdclk values as a > @@ -3439,7 +3473,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) > else > max_cdclk = 308571; > > - dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); > + display->cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); > } else if (IS_BROADWELL(dev_priv)) { > /* > * FIXME with extra cooling we can allow > @@ -3447,41 +3481,43 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) > * How can we know if extra cooling is > * available? PCI ID, VTB, something else? > */ > - if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) > - dev_priv->display.cdclk.max_cdclk_freq = 450000; > + if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT) > + display->cdclk.max_cdclk_freq = 450000; > else if (IS_BROADWELL_ULX(dev_priv)) > - dev_priv->display.cdclk.max_cdclk_freq = 450000; > + display->cdclk.max_cdclk_freq = 450000; > else if (IS_BROADWELL_ULT(dev_priv)) > - dev_priv->display.cdclk.max_cdclk_freq = 540000; > + display->cdclk.max_cdclk_freq = 540000; > else > - dev_priv->display.cdclk.max_cdclk_freq = 675000; > + display->cdclk.max_cdclk_freq = 675000; > } else if (IS_CHERRYVIEW(dev_priv)) { > - dev_priv->display.cdclk.max_cdclk_freq = 320000; > + display->cdclk.max_cdclk_freq = 320000; > } else if (IS_VALLEYVIEW(dev_priv)) { > - dev_priv->display.cdclk.max_cdclk_freq = 400000; > + display->cdclk.max_cdclk_freq = 400000; > } else { > /* otherwise assume cdclk is fixed */ > - dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; > + display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; > } > > - dev_priv->display.cdclk.max_dotclk_freq = intel_compute_max_dotclk(dev_priv); > + display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display); > > - drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", > - dev_priv->display.cdclk.max_cdclk_freq); > + drm_dbg(display->drm, "Max CD clock rate: %d kHz\n", > + display->cdclk.max_cdclk_freq); > > - drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", > - dev_priv->display.cdclk.max_dotclk_freq); > + drm_dbg(display->drm, "Max dotclock rate: %d kHz\n", > + display->cdclk.max_dotclk_freq); > } > > /** > * intel_update_cdclk - Determine the current CDCLK frequency > - * @dev_priv: i915 device > + * @display: display instance > * > * Determine the current CDCLK frequency. > */ > -void intel_update_cdclk(struct drm_i915_private *dev_priv) > +void intel_update_cdclk(struct intel_display *display) > { > - intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); > + struct drm_i915_private *dev_priv = to_i915(display->drm); > + > + intel_cdclk_get_cdclk(display, &display->cdclk.hw); > > /* > * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): > @@ -3490,28 +3526,29 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv) > * generate GMBus clock. This will vary with the cdclk freq. > */ > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > - intel_de_write(dev_priv, GMBUSFREQ_VLV, > - DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); > + intel_de_write(display, GMBUSFREQ_VLV, > + DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000)); > } > > -static int dg1_rawclk(struct drm_i915_private *dev_priv) > +static int dg1_rawclk(struct intel_display *display) > { > /* > * DG1 always uses a 38.4 MHz rawclk. The bspec tells us > * "Program Numerator=2, Denominator=4, Divider=37 decimal." > */ > - intel_de_write(dev_priv, PCH_RAWCLK_FREQ, > + intel_de_write(display, PCH_RAWCLK_FREQ, > CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2)); > > return 38400; > } > > -static int cnp_rawclk(struct drm_i915_private *dev_priv) > +static int cnp_rawclk(struct intel_display *display) > { > - u32 rawclk; > + struct drm_i915_private *dev_priv = to_i915(display->drm); > int divider, fraction; > + u32 rawclk; > > - if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { > + if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { > /* 24 MHz */ > divider = 24000; > fraction = 0; > @@ -3531,37 +3568,42 @@ static int cnp_rawclk(struct drm_i915_private *dev_priv) > rawclk |= ICP_RAWCLK_NUM(numerator); > } > > - intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk); > + intel_de_write(display, PCH_RAWCLK_FREQ, rawclk); > return divider + fraction; > } > > -static int pch_rawclk(struct drm_i915_private *dev_priv) > +static int pch_rawclk(struct intel_display *display) > { > - return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; > + return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; > } > > -static int vlv_hrawclk(struct drm_i915_private *dev_priv) > +static int vlv_hrawclk(struct intel_display *display) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > + > /* RAWCLK_FREQ_VLV register updated from power well code */ > return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", > CCK_DISPLAY_REF_CLOCK_CONTROL); > } > > -static int i9xx_hrawclk(struct drm_i915_private *i915) > +static int i9xx_hrawclk(struct intel_display *display) > { > + struct drm_i915_private *i915 = to_i915(display->drm); > + > /* hrawclock is 1/4 the FSB frequency */ > return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4); > } > > /** > * intel_read_rawclk - Determine the current RAWCLK frequency > - * @dev_priv: i915 device > + * @display: display instance > * > * Determine the current RAWCLK frequency. RAWCLK is a fixed > * frequency clock so this needs to done only once. > */ > -u32 intel_read_rawclk(struct drm_i915_private *dev_priv) > +u32 intel_read_rawclk(struct intel_display *display) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > u32 freq; > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL) > @@ -3572,15 +3614,15 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) > */ > freq = 38400; > else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) > - freq = dg1_rawclk(dev_priv); > + freq = dg1_rawclk(display); > else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) > - freq = cnp_rawclk(dev_priv); > + freq = cnp_rawclk(display); > else if (HAS_PCH_SPLIT(dev_priv)) > - freq = pch_rawclk(dev_priv); > + freq = pch_rawclk(display); > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > - freq = vlv_hrawclk(dev_priv); > - else if (DISPLAY_VER(dev_priv) >= 3) > - freq = i9xx_hrawclk(dev_priv); > + freq = vlv_hrawclk(display); > + else if (DISPLAY_VER(display) >= 3) > + freq = i9xx_hrawclk(display); > else > /* no rawclk on other platforms, or no need to know it */ > return 0; > @@ -3590,23 +3632,23 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) > > static int i915_cdclk_info_show(struct seq_file *m, void *unused) > { > - struct drm_i915_private *i915 = m->private; > + struct intel_display *display = m->private; > > - seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); > - seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); > - seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->display.cdclk.max_dotclk_freq); > + seq_printf(m, "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk); > + seq_printf(m, "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq); > + seq_printf(m, "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq); > > return 0; > } > > DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info); > > -void intel_cdclk_debugfs_register(struct drm_i915_private *i915) > +void intel_cdclk_debugfs_register(struct intel_display *display) > { > - struct drm_minor *minor = i915->drm.primary; > + struct drm_minor *minor = display->drm->primary; > > debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root, > - i915, &i915_cdclk_info_fops); > + display, &i915_cdclk_info_fops); > } > > static const struct intel_cdclk_funcs rplu_cdclk_funcs = { > @@ -3747,97 +3789,99 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = { > > /** > * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks > - * @dev_priv: i915 device > + * @display: display instance > */ > -void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) > +void intel_init_cdclk_hooks(struct intel_display *display) > { > - if (DISPLAY_VER(dev_priv) >= 20) { > - dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; > - dev_priv->display.cdclk.table = xe2lpd_cdclk_table; > - } else if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1)) { > - dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; > - dev_priv->display.cdclk.table = xe2hpd_cdclk_table; > - } else if (DISPLAY_VER(dev_priv) >= 14) { > - dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; > - dev_priv->display.cdclk.table = mtl_cdclk_table; > + struct drm_i915_private *dev_priv = to_i915(display->drm); > + > + if (DISPLAY_VER(display) >= 20) { > + display->funcs.cdclk = &rplu_cdclk_funcs; > + display->cdclk.table = xe2lpd_cdclk_table; > + } else if (DISPLAY_VER_FULL(display) >= IP_VER(14, 1)) { > + display->funcs.cdclk = &rplu_cdclk_funcs; > + display->cdclk.table = xe2hpd_cdclk_table; > + } else if (DISPLAY_VER(display) >= 14) { > + display->funcs.cdclk = &rplu_cdclk_funcs; > + display->cdclk.table = mtl_cdclk_table; > } else if (IS_DG2(dev_priv)) { > - dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; > - dev_priv->display.cdclk.table = dg2_cdclk_table; > + display->funcs.cdclk = &tgl_cdclk_funcs; > + display->cdclk.table = dg2_cdclk_table; > } else if (IS_ALDERLAKE_P(dev_priv)) { > /* Wa_22011320316:adl-p[a0] */ > if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { > - dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; > - dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; > + display->cdclk.table = adlp_a_step_cdclk_table; > + display->funcs.cdclk = &tgl_cdclk_funcs; > } else if (IS_RAPTORLAKE_U(dev_priv)) { > - dev_priv->display.cdclk.table = rplu_cdclk_table; > - dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; > + display->cdclk.table = rplu_cdclk_table; > + display->funcs.cdclk = &rplu_cdclk_funcs; > } else { > - dev_priv->display.cdclk.table = adlp_cdclk_table; > - dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; > + display->cdclk.table = adlp_cdclk_table; > + display->funcs.cdclk = &tgl_cdclk_funcs; > } > } else if (IS_ROCKETLAKE(dev_priv)) { > - dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; > - dev_priv->display.cdclk.table = rkl_cdclk_table; > - } else if (DISPLAY_VER(dev_priv) >= 12) { > - dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; > - dev_priv->display.cdclk.table = icl_cdclk_table; > + display->funcs.cdclk = &tgl_cdclk_funcs; > + display->cdclk.table = rkl_cdclk_table; > + } else if (DISPLAY_VER(display) >= 12) { > + display->funcs.cdclk = &tgl_cdclk_funcs; > + display->cdclk.table = icl_cdclk_table; > } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { > - dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; > - dev_priv->display.cdclk.table = icl_cdclk_table; > - } else if (DISPLAY_VER(dev_priv) >= 11) { > - dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; > - dev_priv->display.cdclk.table = icl_cdclk_table; > + display->funcs.cdclk = &ehl_cdclk_funcs; > + display->cdclk.table = icl_cdclk_table; > + } else if (DISPLAY_VER(display) >= 11) { > + display->funcs.cdclk = &icl_cdclk_funcs; > + display->cdclk.table = icl_cdclk_table; > } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { > - dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; > + display->funcs.cdclk = &bxt_cdclk_funcs; > if (IS_GEMINILAKE(dev_priv)) > - dev_priv->display.cdclk.table = glk_cdclk_table; > + display->cdclk.table = glk_cdclk_table; > else > - dev_priv->display.cdclk.table = bxt_cdclk_table; > - } else if (DISPLAY_VER(dev_priv) == 9) { > - dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; > + display->cdclk.table = bxt_cdclk_table; > + } else if (DISPLAY_VER(display) == 9) { > + display->funcs.cdclk = &skl_cdclk_funcs; > } else if (IS_BROADWELL(dev_priv)) { > - dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; > + display->funcs.cdclk = &bdw_cdclk_funcs; > } else if (IS_HASWELL(dev_priv)) { > - dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; > + display->funcs.cdclk = &hsw_cdclk_funcs; > } else if (IS_CHERRYVIEW(dev_priv)) { > - dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; > + display->funcs.cdclk = &chv_cdclk_funcs; > } else if (IS_VALLEYVIEW(dev_priv)) { > - dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; > + display->funcs.cdclk = &vlv_cdclk_funcs; > } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) { > - dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; > + display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; > } else if (IS_IRONLAKE(dev_priv)) { > - dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; > + display->funcs.cdclk = &ilk_cdclk_funcs; > } else if (IS_GM45(dev_priv)) { > - dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; > + display->funcs.cdclk = &gm45_cdclk_funcs; > } else if (IS_G45(dev_priv)) { > - dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; > + display->funcs.cdclk = &g33_cdclk_funcs; > } else if (IS_I965GM(dev_priv)) { > - dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; > + display->funcs.cdclk = &i965gm_cdclk_funcs; > } else if (IS_I965G(dev_priv)) { > - dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; > + display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; > } else if (IS_PINEVIEW(dev_priv)) { > - dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; > + display->funcs.cdclk = &pnv_cdclk_funcs; > } else if (IS_G33(dev_priv)) { > - dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; > + display->funcs.cdclk = &g33_cdclk_funcs; > } else if (IS_I945GM(dev_priv)) { > - dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; > + display->funcs.cdclk = &i945gm_cdclk_funcs; > } else if (IS_I945G(dev_priv)) { > - dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; > + display->funcs.cdclk = &fixed_400mhz_cdclk_funcs; > } else if (IS_I915GM(dev_priv)) { > - dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; > + display->funcs.cdclk = &i915gm_cdclk_funcs; > } else if (IS_I915G(dev_priv)) { > - dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; > + display->funcs.cdclk = &i915g_cdclk_funcs; > } else if (IS_I865G(dev_priv)) { > - dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; > + display->funcs.cdclk = &i865g_cdclk_funcs; > } else if (IS_I85X(dev_priv)) { > - dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; > + display->funcs.cdclk = &i85x_cdclk_funcs; > } else if (IS_I845G(dev_priv)) { > - dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; > + display->funcs.cdclk = &i845g_cdclk_funcs; > } else if (IS_I830(dev_priv)) { > - dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; > + display->funcs.cdclk = &i830_cdclk_funcs; > } > > - if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, > + if (drm_WARN(display->drm, !display->funcs.cdclk, > "Unknown platform. Assuming i830\n")) > - dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; > + display->funcs.cdclk = &i830_cdclk_funcs; > } > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h > index 1fe445a3a30b..6b0e7a41eba3 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.h > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h > @@ -11,9 +11,9 @@ > #include "intel_display_limits.h" > #include "intel_global_state.h" > > -struct drm_i915_private; > struct intel_atomic_state; > struct intel_crtc_state; > +struct intel_display; > > struct intel_cdclk_config { > unsigned int cdclk, vco, ref, bypass; > @@ -59,24 +59,24 @@ struct intel_cdclk_state { > }; > > int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); > -void intel_cdclk_init_hw(struct drm_i915_private *i915); > -void intel_cdclk_uninit_hw(struct drm_i915_private *i915); > -void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); > -void intel_update_max_cdclk(struct drm_i915_private *dev_priv); > -void intel_update_cdclk(struct drm_i915_private *dev_priv); > -u32 intel_read_rawclk(struct drm_i915_private *dev_priv); > +void intel_cdclk_init_hw(struct intel_display *display); > +void intel_cdclk_uninit_hw(struct intel_display *display); > +void intel_init_cdclk_hooks(struct intel_display *display); > +void intel_update_max_cdclk(struct intel_display *display); > +void intel_update_cdclk(struct intel_display *display); > +u32 intel_read_rawclk(struct intel_display *display); > bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a, > const struct intel_cdclk_config *b); > -int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915, > +int intel_mdclk_cdclk_ratio(struct intel_display *display, > const struct intel_cdclk_config *cdclk_config); > bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state); > void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state); > void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state); > -void intel_cdclk_dump_config(struct drm_i915_private *i915, > +void intel_cdclk_dump_config(struct intel_display *display, > const struct intel_cdclk_config *cdclk_config, > const char *context); > int intel_modeset_calc_cdclk(struct intel_atomic_state *state); > -void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, > +void intel_cdclk_get_cdclk(struct intel_display *display, > struct intel_cdclk_config *cdclk_config); > int intel_cdclk_atomic_check(struct intel_atomic_state *state, > bool *need_cdclk_calc); > @@ -92,7 +92,7 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state); > #define intel_atomic_get_new_cdclk_state(state) \ > to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->cdclk.obj)) > > -int intel_cdclk_init(struct drm_i915_private *dev_priv); > -void intel_cdclk_debugfs_register(struct drm_i915_private *i915); > +int intel_cdclk_init(struct intel_display *display); > +void intel_cdclk_debugfs_register(struct intel_display *display); > > #endif /* __INTEL_CDCLK_H__ */ > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > index 830b9eb60976..c1bef34d1ffd 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > @@ -1068,7 +1068,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915) > minor->debugfs_root, minor); > > intel_bios_debugfs_register(display); > - intel_cdclk_debugfs_register(i915); > + intel_cdclk_debugfs_register(display); > intel_dmc_debugfs_register(i915); > intel_fbc_debugfs_register(display); > intel_hpd_debugfs_register(i915); > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c > index 408c76852495..9ff08dbefc76 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.c > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c > @@ -1678,7 +1678,7 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9 > } > } > > - display_runtime->rawclk_freq = intel_read_rawclk(i915); > + display_runtime->rawclk_freq = intel_read_rawclk(&i915->display); > drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq); > > return; > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c > index e7670774ecd0..434e52f450ff 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c > @@ -82,16 +82,17 @@ bool intel_display_driver_probe_defer(struct pci_dev *pdev) > > void intel_display_driver_init_hw(struct drm_i915_private *i915) > { > + struct intel_display *display = &i915->display; > struct intel_cdclk_state *cdclk_state; > > if (!HAS_DISPLAY(i915)) > return; > > - cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state); > + cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state); > > - intel_update_cdclk(i915); > - intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK"); > - cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw; > + intel_update_cdclk(display); > + intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); > + cdclk_state->logical = cdclk_state->actual = display->cdclk.hw; > > intel_display_wa_apply(i915); > } > @@ -194,7 +195,7 @@ void intel_display_driver_early_probe(struct drm_i915_private *i915) > intel_display_irq_init(i915); > intel_dkl_phy_init(i915); > intel_color_init_hooks(i915); > - intel_init_cdclk_hooks(i915); > + intel_init_cdclk_hooks(&i915->display); > intel_audio_hooks_init(i915); > intel_dpll_init_clock_hook(i915); > intel_init_display_hooks(i915); > @@ -244,7 +245,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915) > > intel_mode_config_init(i915); > > - ret = intel_cdclk_init(i915); > + ret = intel_cdclk_init(display); > if (ret) > goto cleanup_vga_client_pw_domain_dmc; > > @@ -451,8 +452,8 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915) > intel_display_driver_init_hw(i915); > intel_dpll_update_ref_clks(i915); > > - if (i915->display.cdclk.max_cdclk_freq == 0) > - intel_update_max_cdclk(i915); > + if (display->cdclk.max_cdclk_freq == 0) > + intel_update_max_cdclk(display); > > intel_hti_init(display); > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index ef2fdbf97346..eb3e2a56af1d 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -1300,6 +1300,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, > */ > static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) > { > + struct intel_display *display = &dev_priv->display; > u32 val; > > val = intel_de_read(dev_priv, LCPLL_CTL); > @@ -1343,8 +1344,8 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) > > intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); > > - intel_update_cdclk(dev_priv); > - intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); > + intel_update_cdclk(display); > + intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); > } > > /* > @@ -1416,7 +1417,8 @@ static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv, > static void skl_display_core_init(struct drm_i915_private *dev_priv, > bool resume) > { > - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; > + struct intel_display *display = &dev_priv->display; > + struct i915_power_domains *power_domains = &display->power.domains; > struct i915_power_well *well; > > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); > @@ -1438,7 +1440,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, > > mutex_unlock(&power_domains->lock); > > - intel_cdclk_init_hw(dev_priv); > + intel_cdclk_init_hw(display); > > gen9_dbuf_enable(dev_priv); > > @@ -1448,7 +1450,8 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, > > static void skl_display_core_uninit(struct drm_i915_private *dev_priv) > { > - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; > + struct intel_display *display = &dev_priv->display; > + struct i915_power_domains *power_domains = &display->power.domains; > struct i915_power_well *well; > > if (!HAS_DISPLAY(dev_priv)) > @@ -1459,7 +1462,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv) > > gen9_dbuf_disable(dev_priv); > > - intel_cdclk_uninit_hw(dev_priv); > + intel_cdclk_uninit_hw(display); > > /* The spec doesn't call for removing the reset handshake flag */ > /* disable PG1 and Misc I/O */ > @@ -1482,7 +1485,8 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv) > > static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume) > { > - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; > + struct intel_display *display = &dev_priv->display; > + struct i915_power_domains *power_domains = &display->power.domains; > struct i915_power_well *well; > > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); > @@ -1506,7 +1510,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume > > mutex_unlock(&power_domains->lock); > > - intel_cdclk_init_hw(dev_priv); > + intel_cdclk_init_hw(display); > > gen9_dbuf_enable(dev_priv); > > @@ -1516,7 +1520,8 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume > > static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) > { > - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; > + struct intel_display *display = &dev_priv->display; > + struct i915_power_domains *power_domains = &display->power.domains; > struct i915_power_well *well; > > if (!HAS_DISPLAY(dev_priv)) > @@ -1527,7 +1532,7 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) > > gen9_dbuf_disable(dev_priv); > > - intel_cdclk_uninit_hw(dev_priv); > + intel_cdclk_uninit_hw(display); > > /* The spec doesn't call for removing the reset handshake flag */ > > @@ -1623,7 +1628,8 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) > static void icl_display_core_init(struct drm_i915_private *dev_priv, > bool resume) > { > - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; > + struct intel_display *display = &dev_priv->display; > + struct i915_power_domains *power_domains = &display->power.domains; > struct i915_power_well *well; > > gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); > @@ -1657,7 +1663,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, > HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0); > > /* 4. Enable CDCLK. */ > - intel_cdclk_init_hw(dev_priv); > + intel_cdclk_init_hw(display); > > if (DISPLAY_VER(dev_priv) >= 12) > gen12_dbuf_slices_config(dev_priv); > @@ -1704,7 +1710,8 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, > > static void icl_display_core_uninit(struct drm_i915_private *dev_priv) > { > - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; > + struct intel_display *display = &dev_priv->display; > + struct i915_power_domains *power_domains = &display->power.domains; > struct i915_power_well *well; > > if (!HAS_DISPLAY(dev_priv)) > @@ -1719,7 +1726,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) > gen9_dbuf_disable(dev_priv); > > /* 3. Disable CD clock */ > - intel_cdclk_uninit_hw(dev_priv); > + intel_cdclk_uninit_hw(display); > > if (DISPLAY_VER(dev_priv) == 14) > intel_de_rmw(dev_priv, DC_STATE_EN, 0, > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c > index 46e9eff12c23..7b40a5b88214 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c > @@ -967,7 +967,8 @@ static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) > > void gen9_disable_dc_states(struct drm_i915_private *dev_priv) > { > - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; > + struct intel_display *display = &dev_priv->display; > + struct i915_power_domains *power_domains = &display->power.domains; > struct intel_cdclk_config cdclk_config = {}; > > if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) { > @@ -982,10 +983,10 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv) > > intel_dmc_wl_disable(&dev_priv->display); > > - intel_cdclk_get_cdclk(dev_priv, &cdclk_config); > + intel_cdclk_get_cdclk(display, &cdclk_config); > /* Can't read out voltage_level so can't use intel_cdclk_changed() */ > - drm_WARN_ON(&dev_priv->drm, > - intel_cdclk_clock_changed(&dev_priv->display.cdclk.hw, > + drm_WARN_ON(display->drm, > + intel_cdclk_clock_changed(&display->cdclk.hw, > &cdclk_config)); > > gen9_assert_dbuf_enabled(dev_priv); > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c > index 29835b638495..6e1f04d5ef47 100644 > --- a/drivers/gpu/drm/i915/display/skl_watermark.c > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c > @@ -2973,6 +2973,7 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, > > static void skl_wm_get_hw_state(struct drm_i915_private *i915) > { > + struct intel_display *display = &i915->display; > struct intel_dbuf_state *dbuf_state = > to_intel_dbuf_state(i915->display.dbuf.obj.state); > struct intel_crtc *crtc; > @@ -2980,7 +2981,7 @@ static void skl_wm_get_hw_state(struct drm_i915_private *i915) > if (HAS_MBUS_JOINING(i915)) > dbuf_state->joined_mbus = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN; > > - dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(i915, &i915->display.cdclk.hw); > + dbuf_state->mdclk_cdclk_ratio = intel_mdclk_cdclk_ratio(display, &display->cdclk.hw); > > for_each_intel_crtc(&i915->drm, crtc) { > struct intel_crtc_state *crtc_state = > -- > 2.44.2 > ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display 2024-09-06 14:33 ` [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display Ville Syrjala 2024-09-06 15:09 ` Rodrigo Vivi @ 2024-09-06 15:18 ` Jani Nikula 2024-09-06 16:17 ` Ville Syrjälä 1 sibling, 1 reply; 24+ messages in thread From: Jani Nikula @ 2024-09-06 15:18 UTC (permalink / raw) To: Ville Syrjala, intel-gfx; +Cc: intel-xe On Fri, 06 Sep 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > struct intel_display will replace struct drm_i915_private as > the main thing for display code. Convert the CDCLK code to > use it (as much as possible at this stage). > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Some nitpicks inline, but overall Reviewed-by: Jani Nikula <jani.nikula@intel.com> [snip] > @@ -2685,20 +2712,21 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) > else > pipe = INVALID_PIPE; > > - drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); > + drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); > > - intel_set_cdclk(i915, &new_cdclk_state->actual, pipe, > + intel_set_cdclk(display, &new_cdclk_state->actual, pipe, > "Post changing CDCLK to"); > } > > static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) > { > - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); > + struct intel_display *display = to_intel_display(crtc_state->uapi.crtc->dev); This works, but to_intel_display(crtc_state) is enough. > + struct drm_i915_private *dev_priv = to_i915(display->drm); I usually don't bother with changing the dev_priv initialization if it keeps working. I just put the display stuff first. But this works. > int pixel_rate = crtc_state->pixel_rate; > > - if (DISPLAY_VER(dev_priv) >= 10) > + if (DISPLAY_VER(display) >= 10) > return DIV_ROUND_UP(pixel_rate, 2); > - else if (DISPLAY_VER(dev_priv) == 9 || > + else if (DISPLAY_VER(display) == 9 || > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) > return pixel_rate; > else if (IS_CHERRYVIEW(dev_priv)) > @@ -2712,11 +2740,11 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) [snip] > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c > index 408c76852495..9ff08dbefc76 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.c > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c > @@ -1678,7 +1678,7 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9 > } > } > > - display_runtime->rawclk_freq = intel_read_rawclk(i915); > + display_runtime->rawclk_freq = intel_read_rawclk(&i915->display); I generally prefer adding that struct intel_display local variable when I need it the first time, so the subsequent changes are less churn. -- Jani Nikula, Intel ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display 2024-09-06 15:18 ` Jani Nikula @ 2024-09-06 16:17 ` Ville Syrjälä 0 siblings, 0 replies; 24+ messages in thread From: Ville Syrjälä @ 2024-09-06 16:17 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, intel-xe On Fri, Sep 06, 2024 at 06:18:58PM +0300, Jani Nikula wrote: > On Fri, 06 Sep 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > struct intel_display will replace struct drm_i915_private as > > the main thing for display code. Convert the CDCLK code to > > use it (as much as possible at this stage). > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Some nitpicks inline, but overall > > Reviewed-by: Jani Nikula <jani.nikula@intel.com> > > [snip] > > > @@ -2685,20 +2712,21 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) > > else > > pipe = INVALID_PIPE; > > > > - drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); > > + drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); > > > > - intel_set_cdclk(i915, &new_cdclk_state->actual, pipe, > > + intel_set_cdclk(display, &new_cdclk_state->actual, pipe, > > "Post changing CDCLK to"); > > } > > > > static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) > > { > > - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); > > + struct intel_display *display = to_intel_display(crtc_state->uapi.crtc->dev); > > This works, but to_intel_display(crtc_state) is enough. Not entirely sure I like the magic going quite that deep. Though I suppose we do have a lot of that, so maybe it's best to make it simple as possible. > > + struct drm_i915_private *dev_priv = to_i915(display->drm); > > I usually don't bother with changing the dev_priv initialization if it > keeps working. I just put the display stuff first. But this works. > > > int pixel_rate = crtc_state->pixel_rate; > > > > - if (DISPLAY_VER(dev_priv) >= 10) > > + if (DISPLAY_VER(display) >= 10) > > return DIV_ROUND_UP(pixel_rate, 2); > > - else if (DISPLAY_VER(dev_priv) == 9 || > > + else if (DISPLAY_VER(display) == 9 || > > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) > > return pixel_rate; > > else if (IS_CHERRYVIEW(dev_priv)) > > @@ -2712,11 +2740,11 @@ static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) > > [snip] > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c > > index 408c76852495..9ff08dbefc76 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_device.c > > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c > > @@ -1678,7 +1678,7 @@ static void __intel_display_device_info_runtime_init(struct drm_i915_private *i9 > > } > > } > > > > - display_runtime->rawclk_freq = intel_read_rawclk(i915); > > + display_runtime->rawclk_freq = intel_read_rawclk(&i915->display); > > I generally prefer adding that struct intel_display local variable when > I need it the first time, so the subsequent changes are less churn. Yeah, I tried to follow that, unless the surrounding code already has tons of &i915->display stuff in it. But here that isn't the case, so apparently I just failed to follow the procedure fully. -- Ville Syrjälä Intel ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 3/6] drm/i915/power: Convert low level DC state code to intel_display 2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala 2024-09-06 14:33 ` [PATCH 1/6] drm/i915/cdclk: Add missing braces Ville Syrjala 2024-09-06 14:33 ` [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display Ville Syrjala @ 2024-09-06 14:33 ` Ville Syrjala 2024-09-06 15:10 ` Rodrigo Vivi 2024-09-06 14:33 ` [PATCH 4/6] drm/i915/vga: Convert VGA " Ville Syrjala ` (10 subsequent siblings) 13 siblings, 1 reply; 24+ messages in thread From: Ville Syrjala @ 2024-09-06 14:33 UTC (permalink / raw) To: intel-gfx; +Cc: intel-xe From: Ville Syrjälä <ville.syrjala@linux.intel.com> struct intel_display will replace struct drm_i915_private as the main thing for display code. Convert the lower level DC state code to use it (as much as possible at this stage). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_display_power.c | 41 ++-- .../i915/display/intel_display_power_well.c | 199 ++++++++++-------- .../i915/display/intel_display_power_well.h | 15 +- 3 files changed, 139 insertions(+), 116 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index eb3e2a56af1d..86ac494ed33b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1421,7 +1421,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, struct i915_power_domains *power_domains = &display->power.domains; struct i915_power_well *well; - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + gen9_set_dc_state(display, DC_STATE_DISABLE); /* enable PCH reset handshake */ intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); @@ -1457,7 +1457,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv) if (!HAS_DISPLAY(dev_priv)) return; - gen9_disable_dc_states(dev_priv); + gen9_disable_dc_states(display); /* TODO: disable DMC program */ gen9_dbuf_disable(dev_priv); @@ -1489,7 +1489,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume struct i915_power_domains *power_domains = &display->power.domains; struct i915_power_well *well; - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + gen9_set_dc_state(display, DC_STATE_DISABLE); /* * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT @@ -1527,7 +1527,7 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) if (!HAS_DISPLAY(dev_priv)) return; - gen9_disable_dc_states(dev_priv); + gen9_disable_dc_states(display); /* TODO: disable DMC program */ gen9_dbuf_disable(dev_priv); @@ -1632,7 +1632,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, struct i915_power_domains *power_domains = &display->power.domains; struct i915_power_well *well; - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + gen9_set_dc_state(display, DC_STATE_DISABLE); /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */ if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && @@ -1717,7 +1717,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) if (!HAS_DISPLAY(dev_priv)) return; - gen9_disable_dc_states(dev_priv); + gen9_disable_dc_states(display); intel_dmc_disable_program(dev_priv); /* 1. Disable all display engine functions -> aready done */ @@ -2232,9 +2232,11 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915) void intel_display_power_suspend_late(struct drm_i915_private *i915) { + struct intel_display *display = &i915->display; + if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { - bxt_enable_dc9(i915); + bxt_enable_dc9(display); } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { hsw_enable_pc8(i915); } @@ -2246,10 +2248,12 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915) void intel_display_power_resume_early(struct drm_i915_private *i915) { + struct intel_display *display = &i915->display; + if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { - gen9_sanitize_dc_state(i915); - bxt_disable_dc9(i915); + gen9_sanitize_dc_state(display); + bxt_disable_dc9(display); } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { hsw_disable_pc8(i915); } @@ -2261,12 +2265,14 @@ void intel_display_power_resume_early(struct drm_i915_private *i915) void intel_display_power_suspend(struct drm_i915_private *i915) { + struct intel_display *display = &i915->display; + if (DISPLAY_VER(i915) >= 11) { icl_display_core_uninit(i915); - bxt_enable_dc9(i915); + bxt_enable_dc9(display); } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { bxt_display_core_uninit(i915); - bxt_enable_dc9(i915); + bxt_enable_dc9(display); } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { hsw_enable_pc8(i915); } @@ -2274,23 +2280,24 @@ void intel_display_power_suspend(struct drm_i915_private *i915) void intel_display_power_resume(struct drm_i915_private *i915) { - struct i915_power_domains *power_domains = &i915->display.power.domains; + struct intel_display *display = &i915->display; + struct i915_power_domains *power_domains = &display->power.domains; if (DISPLAY_VER(i915) >= 11) { - bxt_disable_dc9(i915); + bxt_disable_dc9(display); icl_display_core_init(i915, true); if (intel_dmc_has_payload(i915)) { if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6) - skl_enable_dc6(i915); + skl_enable_dc6(display); else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5) - gen9_enable_dc5(i915); + gen9_enable_dc5(display); } } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { - bxt_disable_dc9(i915); + bxt_disable_dc9(display); bxt_display_core_init(i915, true); if (intel_dmc_has_payload(i915) && (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) - gen9_enable_dc5(i915); + gen9_enable_dc5(display); } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { hsw_disable_pc8(i915); } diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 7b40a5b88214..1f0084ca6248 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -601,20 +601,22 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, return (val & mask) == mask; } -static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) +static void assert_can_enable_dc9(struct intel_display *display) { - drm_WARN_ONCE(&dev_priv->drm, - (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9), + struct drm_i915_private *dev_priv = to_i915(display->drm); + + drm_WARN_ONCE(display->drm, + (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9), "DC9 already programmed to be enabled.\n"); - drm_WARN_ONCE(&dev_priv->drm, - intel_de_read(dev_priv, DC_STATE_EN) & + drm_WARN_ONCE(display->drm, + intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, "DC5 still not disabled to enable DC9.\n"); - drm_WARN_ONCE(&dev_priv->drm, - intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) & + drm_WARN_ONCE(display->drm, + intel_de_read(display, HSW_PWR_WELL_CTL2) & HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), "Power well 2 on.\n"); - drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), + drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); /* @@ -626,12 +628,14 @@ static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) */ } -static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) +static void assert_can_disable_dc9(struct intel_display *display) { - drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), + struct drm_i915_private *dev_priv = to_i915(display->drm); + + drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); - drm_WARN_ONCE(&dev_priv->drm, - intel_de_read(dev_priv, DC_STATE_EN) & + drm_WARN_ONCE(display->drm, + intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, "DC5 still not disabled.\n"); @@ -644,14 +648,14 @@ static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) */ } -static void gen9_write_dc_state(struct drm_i915_private *dev_priv, +static void gen9_write_dc_state(struct intel_display *display, u32 state) { int rewrites = 0; int rereads = 0; u32 v; - intel_de_write(dev_priv, DC_STATE_EN, state); + intel_de_write(display, DC_STATE_EN, state); /* It has been observed that disabling the dc6 state sometimes * doesn't stick and dmc keeps returning old value. Make sure @@ -659,10 +663,10 @@ static void gen9_write_dc_state(struct drm_i915_private *dev_priv, * we are confident that state is exactly what we want. */ do { - v = intel_de_read(dev_priv, DC_STATE_EN); + v = intel_de_read(display, DC_STATE_EN); if (v != state) { - intel_de_write(dev_priv, DC_STATE_EN, state); + intel_de_write(display, DC_STATE_EN, state); rewrites++; rereads = 0; } else if (rereads++ > 5) { @@ -672,27 +676,28 @@ static void gen9_write_dc_state(struct drm_i915_private *dev_priv, } while (rewrites < 100); if (v != state) - drm_err(&dev_priv->drm, + drm_err(display->drm, "Writing dc state to 0x%x failed, now 0x%x\n", state, v); /* Most of the times we need one retry, avoid spam */ if (rewrites > 1) - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "Rewrote dc state to 0x%x %d times\n", state, rewrites); } -static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) +static u32 gen9_dc_mask(struct intel_display *display) { + struct drm_i915_private *dev_priv = to_i915(display->drm); u32 mask; mask = DC_STATE_EN_UPTO_DC5; - if (DISPLAY_VER(dev_priv) >= 12) + if (DISPLAY_VER(display) >= 12) mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; - else if (DISPLAY_VER(dev_priv) == 11) + else if (DISPLAY_VER(display) == 11) mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) mask |= DC_STATE_EN_DC9; @@ -702,17 +707,17 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) return mask; } -void gen9_sanitize_dc_state(struct drm_i915_private *i915) +void gen9_sanitize_dc_state(struct intel_display *display) { - struct i915_power_domains *power_domains = &i915->display.power.domains; + struct i915_power_domains *power_domains = &display->power.domains; u32 val; - if (!HAS_DISPLAY(i915)) + if (!HAS_DISPLAY(display)) return; - val = intel_de_read(i915, DC_STATE_EN) & gen9_dc_mask(i915); + val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display); - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "Resetting DC state tracking from %02x to %02x\n", power_domains->dc_state, val); power_domains->dc_state = val; @@ -720,7 +725,7 @@ void gen9_sanitize_dc_state(struct drm_i915_private *i915) /** * gen9_set_dc_state - set target display C power state - * @dev_priv: i915 device instance + * @display: display instance * @state: target DC power state * - DC_STATE_DISABLE * - DC_STATE_EN_UPTO_DC5 @@ -741,70 +746,71 @@ void gen9_sanitize_dc_state(struct drm_i915_private *i915) * back on and register state is restored. This is guaranteed by the MMIO write * to DC_STATE_EN blocking until the state is restored. */ -void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) +void gen9_set_dc_state(struct intel_display *display, u32 state) { - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; + struct i915_power_domains *power_domains = &display->power.domains; u32 val; u32 mask; - if (!HAS_DISPLAY(dev_priv)) + if (!HAS_DISPLAY(display)) return; - if (drm_WARN_ON_ONCE(&dev_priv->drm, + if (drm_WARN_ON_ONCE(display->drm, state & ~power_domains->allowed_dc_mask)) state &= power_domains->allowed_dc_mask; - val = intel_de_read(dev_priv, DC_STATE_EN); - mask = gen9_dc_mask(dev_priv); - drm_dbg_kms(&dev_priv->drm, "Setting DC state from %02x to %02x\n", + val = intel_de_read(display, DC_STATE_EN); + mask = gen9_dc_mask(display); + drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n", val & mask, state); /* Check if DMC is ignoring our DC state requests */ if ((val & mask) != power_domains->dc_state) - drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n", + drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n", power_domains->dc_state, val & mask); val &= ~mask; val |= state; - gen9_write_dc_state(dev_priv, val); + gen9_write_dc_state(display, val); power_domains->dc_state = val & mask; } -static void tgl_enable_dc3co(struct drm_i915_private *dev_priv) +static void tgl_enable_dc3co(struct intel_display *display) { - drm_dbg_kms(&dev_priv->drm, "Enabling DC3CO\n"); - gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO); + drm_dbg_kms(display->drm, "Enabling DC3CO\n"); + gen9_set_dc_state(display, DC_STATE_EN_DC3CO); } -static void tgl_disable_dc3co(struct drm_i915_private *dev_priv) +static void tgl_disable_dc3co(struct intel_display *display) { - drm_dbg_kms(&dev_priv->drm, "Disabling DC3CO\n"); - intel_de_rmw(dev_priv, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0); - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + drm_dbg_kms(display->drm, "Disabling DC3CO\n"); + intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0); + gen9_set_dc_state(display, DC_STATE_DISABLE); /* * Delay of 200us DC3CO Exit time B.Spec 49196 */ usleep_range(200, 210); } -static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) +static void assert_can_enable_dc5(struct intel_display *display) { + struct drm_i915_private *dev_priv = to_i915(display->drm); enum i915_power_well_id high_pg; /* Power wells at this level and above must be disabled for DC5 entry */ - if (DISPLAY_VER(dev_priv) == 12) + if (DISPLAY_VER(display) == 12) high_pg = ICL_DISP_PW_3; else high_pg = SKL_DISP_PW_2; - drm_WARN_ONCE(&dev_priv->drm, + drm_WARN_ONCE(display->drm, intel_display_power_well_is_enabled(dev_priv, high_pg), "Power wells above platform's DC5 limit still enabled.\n"); - drm_WARN_ONCE(&dev_priv->drm, - (intel_de_read(dev_priv, DC_STATE_EN) & + drm_WARN_ONCE(display->drm, + (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), "DC5 already programmed to be enabled.\n"); assert_rpm_wakelock_held(&dev_priv->runtime_pm); @@ -812,60 +818,66 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) assert_dmc_loaded(dev_priv); } -void gen9_enable_dc5(struct drm_i915_private *dev_priv) +void gen9_enable_dc5(struct intel_display *display) { - assert_can_enable_dc5(dev_priv); + struct drm_i915_private *dev_priv = to_i915(display->drm); - drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n"); + assert_can_enable_dc5(display); + + drm_dbg_kms(display->drm, "Enabling DC5\n"); /* Wa Display #1183: skl,kbl,cfl */ - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) - intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, + if (DISPLAY_VER(display) == 9 && !IS_BROXTON(dev_priv)) + intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, SKL_SELECT_ALTERNATE_DC_EXIT); - intel_dmc_wl_enable(&dev_priv->display); + intel_dmc_wl_enable(display); - gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); + gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC5); } -static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) +static void assert_can_enable_dc6(struct intel_display *display) { - drm_WARN_ONCE(&dev_priv->drm, - (intel_de_read(dev_priv, UTIL_PIN_CTL) & + struct drm_i915_private *dev_priv = to_i915(display->drm); + + drm_WARN_ONCE(display->drm, + (intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), "Utility pin enabled in PWM mode\n"); - drm_WARN_ONCE(&dev_priv->drm, - (intel_de_read(dev_priv, DC_STATE_EN) & + drm_WARN_ONCE(display->drm, + (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), "DC6 already programmed to be enabled.\n"); assert_dmc_loaded(dev_priv); } -void skl_enable_dc6(struct drm_i915_private *dev_priv) +void skl_enable_dc6(struct intel_display *display) { - assert_can_enable_dc6(dev_priv); + struct drm_i915_private *dev_priv = to_i915(display->drm); - drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n"); + assert_can_enable_dc6(display); + + drm_dbg_kms(display->drm, "Enabling DC6\n"); /* Wa Display #1183: skl,kbl,cfl */ - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) - intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, + if (DISPLAY_VER(display) == 9 && !IS_BROXTON(dev_priv)) + intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, SKL_SELECT_ALTERNATE_DC_EXIT); - intel_dmc_wl_enable(&dev_priv->display); + intel_dmc_wl_enable(display); - gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); + gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6); } -void bxt_enable_dc9(struct drm_i915_private *dev_priv) +void bxt_enable_dc9(struct intel_display *display) { - struct intel_display *display = &dev_priv->display; + struct drm_i915_private *dev_priv = to_i915(display->drm); - assert_can_enable_dc9(dev_priv); + assert_can_enable_dc9(display); - drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n"); + drm_dbg_kms(display->drm, "Enabling DC9\n"); /* * Power sequencer reset is not needed on * platforms with South Display Engine on PCH, @@ -873,18 +885,16 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv) */ if (!HAS_PCH_SPLIT(dev_priv)) intel_pps_reset_all(display); - gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); + gen9_set_dc_state(display, DC_STATE_EN_DC9); } -void bxt_disable_dc9(struct drm_i915_private *dev_priv) +void bxt_disable_dc9(struct intel_display *display) { - struct intel_display *display = &dev_priv->display; + assert_can_disable_dc9(display); - assert_can_disable_dc9(dev_priv); + drm_dbg_kms(display->drm, "Disabling DC9\n"); - drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n"); - - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + gen9_set_dc_state(display, DC_STATE_DISABLE); intel_pps_unlock_regs_wa(display); } @@ -949,8 +959,10 @@ static void bxt_verify_dpio_phy_power_wells(struct drm_i915_private *dev_priv) static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - return ((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && - (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); + struct intel_display *display = &dev_priv->display; + + return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && + (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); } static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) @@ -965,23 +977,23 @@ static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) enabled_dbuf_slices); } -void gen9_disable_dc_states(struct drm_i915_private *dev_priv) +void gen9_disable_dc_states(struct intel_display *display) { - struct intel_display *display = &dev_priv->display; + struct drm_i915_private *dev_priv = to_i915(display->drm); struct i915_power_domains *power_domains = &display->power.domains; struct intel_cdclk_config cdclk_config = {}; if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) { - tgl_disable_dc3co(dev_priv); + tgl_disable_dc3co(display); return; } - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); + gen9_set_dc_state(display, DC_STATE_DISABLE); - if (!HAS_DISPLAY(dev_priv)) + if (!HAS_DISPLAY(display)) return; - intel_dmc_wl_disable(&dev_priv->display); + intel_dmc_wl_disable(display); intel_cdclk_get_cdclk(display, &cdclk_config); /* Can't read out voltage_level so can't use intel_cdclk_changed() */ @@ -994,7 +1006,7 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv) if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) bxt_verify_dpio_phy_power_wells(dev_priv); - if (DISPLAY_VER(dev_priv) >= 11) + if (DISPLAY_VER(display) >= 11) /* * DMC retains HW context only for port A, the other combo * PHY's HW context for port B is lost after DC transitions, @@ -1006,26 +1018,29 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv) static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - gen9_disable_dc_states(dev_priv); + struct intel_display *display = &dev_priv->display; + + gen9_disable_dc_states(display); } static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; + struct intel_display *display = &dev_priv->display; + struct i915_power_domains *power_domains = &display->power.domains; if (!intel_dmc_has_payload(dev_priv)) return; switch (power_domains->target_dc_state) { case DC_STATE_EN_DC3CO: - tgl_enable_dc3co(dev_priv); + tgl_enable_dc3co(display); break; case DC_STATE_EN_UPTO_DC6: - skl_enable_dc6(dev_priv); + skl_enable_dc6(display); break; case DC_STATE_EN_UPTO_DC5: - gen9_enable_dc5(dev_priv); + gen9_enable_dc5(display); break; } } diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h index 9357a9a73c06..93559f7c6100 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h @@ -12,6 +12,7 @@ struct drm_i915_private; struct i915_power_well_ops; +struct intel_display; struct intel_encoder; #define for_each_power_well(__dev_priv, __power_well) \ @@ -154,13 +155,13 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder, bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, enum dpio_channel ch, bool override); -void gen9_enable_dc5(struct drm_i915_private *dev_priv); -void skl_enable_dc6(struct drm_i915_private *dev_priv); -void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv); -void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state); -void gen9_disable_dc_states(struct drm_i915_private *dev_priv); -void bxt_enable_dc9(struct drm_i915_private *dev_priv); -void bxt_disable_dc9(struct drm_i915_private *dev_priv); +void gen9_enable_dc5(struct intel_display *display); +void skl_enable_dc6(struct intel_display *display); +void gen9_sanitize_dc_state(struct intel_display *display); +void gen9_set_dc_state(struct intel_display *display, u32 state); +void gen9_disable_dc_states(struct intel_display *display); +void bxt_enable_dc9(struct intel_display *display); +void bxt_disable_dc9(struct intel_display *display); extern const struct i915_power_well_ops i9xx_always_on_power_well_ops; extern const struct i915_power_well_ops chv_pipe_power_well_ops; -- 2.44.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 3/6] drm/i915/power: Convert low level DC state code to intel_display 2024-09-06 14:33 ` [PATCH 3/6] drm/i915/power: Convert low level DC state " Ville Syrjala @ 2024-09-06 15:10 ` Rodrigo Vivi 0 siblings, 0 replies; 24+ messages in thread From: Rodrigo Vivi @ 2024-09-06 15:10 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx, intel-xe On Fri, Sep 06, 2024 at 05:33:03PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > struct intel_display will replace struct drm_i915_private as > the main thing for display code. Convert the lower level > DC state code to use it (as much as possible at this stage). > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > .../drm/i915/display/intel_display_power.c | 41 ++-- > .../i915/display/intel_display_power_well.c | 199 ++++++++++-------- > .../i915/display/intel_display_power_well.h | 15 +- > 3 files changed, 139 insertions(+), 116 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index eb3e2a56af1d..86ac494ed33b 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -1421,7 +1421,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, > struct i915_power_domains *power_domains = &display->power.domains; > struct i915_power_well *well; > > - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); > + gen9_set_dc_state(display, DC_STATE_DISABLE); > > /* enable PCH reset handshake */ > intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); > @@ -1457,7 +1457,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv) > if (!HAS_DISPLAY(dev_priv)) > return; > > - gen9_disable_dc_states(dev_priv); > + gen9_disable_dc_states(display); > /* TODO: disable DMC program */ > > gen9_dbuf_disable(dev_priv); > @@ -1489,7 +1489,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume > struct i915_power_domains *power_domains = &display->power.domains; > struct i915_power_well *well; > > - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); > + gen9_set_dc_state(display, DC_STATE_DISABLE); > > /* > * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT > @@ -1527,7 +1527,7 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) > if (!HAS_DISPLAY(dev_priv)) > return; > > - gen9_disable_dc_states(dev_priv); > + gen9_disable_dc_states(display); > /* TODO: disable DMC program */ > > gen9_dbuf_disable(dev_priv); > @@ -1632,7 +1632,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, > struct i915_power_domains *power_domains = &display->power.domains; > struct i915_power_well *well; > > - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); > + gen9_set_dc_state(display, DC_STATE_DISABLE); > > /* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */ > if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && > @@ -1717,7 +1717,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) > if (!HAS_DISPLAY(dev_priv)) > return; > > - gen9_disable_dc_states(dev_priv); > + gen9_disable_dc_states(display); > intel_dmc_disable_program(dev_priv); > > /* 1. Disable all display engine functions -> aready done */ > @@ -2232,9 +2232,11 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915) > > void intel_display_power_suspend_late(struct drm_i915_private *i915) > { > + struct intel_display *display = &i915->display; > + > if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) || > IS_BROXTON(i915)) { > - bxt_enable_dc9(i915); > + bxt_enable_dc9(display); > } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { > hsw_enable_pc8(i915); > } > @@ -2246,10 +2248,12 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915) > > void intel_display_power_resume_early(struct drm_i915_private *i915) > { > + struct intel_display *display = &i915->display; > + > if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) || > IS_BROXTON(i915)) { > - gen9_sanitize_dc_state(i915); > - bxt_disable_dc9(i915); > + gen9_sanitize_dc_state(display); > + bxt_disable_dc9(display); > } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { > hsw_disable_pc8(i915); > } > @@ -2261,12 +2265,14 @@ void intel_display_power_resume_early(struct drm_i915_private *i915) > > void intel_display_power_suspend(struct drm_i915_private *i915) > { > + struct intel_display *display = &i915->display; > + > if (DISPLAY_VER(i915) >= 11) { > icl_display_core_uninit(i915); > - bxt_enable_dc9(i915); > + bxt_enable_dc9(display); > } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { > bxt_display_core_uninit(i915); > - bxt_enable_dc9(i915); > + bxt_enable_dc9(display); > } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { > hsw_enable_pc8(i915); > } > @@ -2274,23 +2280,24 @@ void intel_display_power_suspend(struct drm_i915_private *i915) > > void intel_display_power_resume(struct drm_i915_private *i915) > { > - struct i915_power_domains *power_domains = &i915->display.power.domains; > + struct intel_display *display = &i915->display; > + struct i915_power_domains *power_domains = &display->power.domains; > > if (DISPLAY_VER(i915) >= 11) { > - bxt_disable_dc9(i915); > + bxt_disable_dc9(display); > icl_display_core_init(i915, true); > if (intel_dmc_has_payload(i915)) { > if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6) > - skl_enable_dc6(i915); > + skl_enable_dc6(display); > else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5) > - gen9_enable_dc5(i915); > + gen9_enable_dc5(display); > } > } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { > - bxt_disable_dc9(i915); > + bxt_disable_dc9(display); > bxt_display_core_init(i915, true); > if (intel_dmc_has_payload(i915) && > (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) > - gen9_enable_dc5(i915); > + gen9_enable_dc5(display); > } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { > hsw_disable_pc8(i915); > } > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c > index 7b40a5b88214..1f0084ca6248 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c > @@ -601,20 +601,22 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, > return (val & mask) == mask; > } > > -static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) > +static void assert_can_enable_dc9(struct intel_display *display) > { > - drm_WARN_ONCE(&dev_priv->drm, > - (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9), > + struct drm_i915_private *dev_priv = to_i915(display->drm); > + > + drm_WARN_ONCE(display->drm, > + (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC9), > "DC9 already programmed to be enabled.\n"); > - drm_WARN_ONCE(&dev_priv->drm, > - intel_de_read(dev_priv, DC_STATE_EN) & > + drm_WARN_ONCE(display->drm, > + intel_de_read(display, DC_STATE_EN) & > DC_STATE_EN_UPTO_DC5, > "DC5 still not disabled to enable DC9.\n"); > - drm_WARN_ONCE(&dev_priv->drm, > - intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) & > + drm_WARN_ONCE(display->drm, > + intel_de_read(display, HSW_PWR_WELL_CTL2) & > HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), > "Power well 2 on.\n"); > - drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), > + drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), > "Interrupts not disabled yet.\n"); > > /* > @@ -626,12 +628,14 @@ static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) > */ > } > > -static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) > +static void assert_can_disable_dc9(struct intel_display *display) > { > - drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), > + struct drm_i915_private *dev_priv = to_i915(display->drm); > + > + drm_WARN_ONCE(display->drm, intel_irqs_enabled(dev_priv), > "Interrupts not disabled yet.\n"); > - drm_WARN_ONCE(&dev_priv->drm, > - intel_de_read(dev_priv, DC_STATE_EN) & > + drm_WARN_ONCE(display->drm, > + intel_de_read(display, DC_STATE_EN) & > DC_STATE_EN_UPTO_DC5, > "DC5 still not disabled.\n"); > > @@ -644,14 +648,14 @@ static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) > */ > } > > -static void gen9_write_dc_state(struct drm_i915_private *dev_priv, > +static void gen9_write_dc_state(struct intel_display *display, > u32 state) > { > int rewrites = 0; > int rereads = 0; > u32 v; > > - intel_de_write(dev_priv, DC_STATE_EN, state); > + intel_de_write(display, DC_STATE_EN, state); > > /* It has been observed that disabling the dc6 state sometimes > * doesn't stick and dmc keeps returning old value. Make sure > @@ -659,10 +663,10 @@ static void gen9_write_dc_state(struct drm_i915_private *dev_priv, > * we are confident that state is exactly what we want. > */ > do { > - v = intel_de_read(dev_priv, DC_STATE_EN); > + v = intel_de_read(display, DC_STATE_EN); > > if (v != state) { > - intel_de_write(dev_priv, DC_STATE_EN, state); > + intel_de_write(display, DC_STATE_EN, state); > rewrites++; > rereads = 0; > } else if (rereads++ > 5) { > @@ -672,27 +676,28 @@ static void gen9_write_dc_state(struct drm_i915_private *dev_priv, > } while (rewrites < 100); > > if (v != state) > - drm_err(&dev_priv->drm, > + drm_err(display->drm, > "Writing dc state to 0x%x failed, now 0x%x\n", > state, v); > > /* Most of the times we need one retry, avoid spam */ > if (rewrites > 1) > - drm_dbg_kms(&dev_priv->drm, > + drm_dbg_kms(display->drm, > "Rewrote dc state to 0x%x %d times\n", > state, rewrites); > } > > -static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) > +static u32 gen9_dc_mask(struct intel_display *display) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > u32 mask; > > mask = DC_STATE_EN_UPTO_DC5; > > - if (DISPLAY_VER(dev_priv) >= 12) > + if (DISPLAY_VER(display) >= 12) > mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6 > | DC_STATE_EN_DC9; > - else if (DISPLAY_VER(dev_priv) == 11) > + else if (DISPLAY_VER(display) == 11) > mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; > else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) > mask |= DC_STATE_EN_DC9; > @@ -702,17 +707,17 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) > return mask; > } > > -void gen9_sanitize_dc_state(struct drm_i915_private *i915) > +void gen9_sanitize_dc_state(struct intel_display *display) > { > - struct i915_power_domains *power_domains = &i915->display.power.domains; > + struct i915_power_domains *power_domains = &display->power.domains; > u32 val; > > - if (!HAS_DISPLAY(i915)) > + if (!HAS_DISPLAY(display)) > return; > > - val = intel_de_read(i915, DC_STATE_EN) & gen9_dc_mask(i915); > + val = intel_de_read(display, DC_STATE_EN) & gen9_dc_mask(display); > > - drm_dbg_kms(&i915->drm, > + drm_dbg_kms(display->drm, > "Resetting DC state tracking from %02x to %02x\n", > power_domains->dc_state, val); > power_domains->dc_state = val; > @@ -720,7 +725,7 @@ void gen9_sanitize_dc_state(struct drm_i915_private *i915) > > /** > * gen9_set_dc_state - set target display C power state > - * @dev_priv: i915 device instance > + * @display: display instance > * @state: target DC power state > * - DC_STATE_DISABLE > * - DC_STATE_EN_UPTO_DC5 > @@ -741,70 +746,71 @@ void gen9_sanitize_dc_state(struct drm_i915_private *i915) > * back on and register state is restored. This is guaranteed by the MMIO write > * to DC_STATE_EN blocking until the state is restored. > */ > -void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) > +void gen9_set_dc_state(struct intel_display *display, u32 state) > { > - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; > + struct i915_power_domains *power_domains = &display->power.domains; > u32 val; > u32 mask; > > - if (!HAS_DISPLAY(dev_priv)) > + if (!HAS_DISPLAY(display)) > return; > > - if (drm_WARN_ON_ONCE(&dev_priv->drm, > + if (drm_WARN_ON_ONCE(display->drm, > state & ~power_domains->allowed_dc_mask)) > state &= power_domains->allowed_dc_mask; > > - val = intel_de_read(dev_priv, DC_STATE_EN); > - mask = gen9_dc_mask(dev_priv); > - drm_dbg_kms(&dev_priv->drm, "Setting DC state from %02x to %02x\n", > + val = intel_de_read(display, DC_STATE_EN); > + mask = gen9_dc_mask(display); > + drm_dbg_kms(display->drm, "Setting DC state from %02x to %02x\n", > val & mask, state); > > /* Check if DMC is ignoring our DC state requests */ > if ((val & mask) != power_domains->dc_state) > - drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n", > + drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n", > power_domains->dc_state, val & mask); > > val &= ~mask; > val |= state; > > - gen9_write_dc_state(dev_priv, val); > + gen9_write_dc_state(display, val); > > power_domains->dc_state = val & mask; > } > > -static void tgl_enable_dc3co(struct drm_i915_private *dev_priv) > +static void tgl_enable_dc3co(struct intel_display *display) > { > - drm_dbg_kms(&dev_priv->drm, "Enabling DC3CO\n"); > - gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO); > + drm_dbg_kms(display->drm, "Enabling DC3CO\n"); > + gen9_set_dc_state(display, DC_STATE_EN_DC3CO); > } > > -static void tgl_disable_dc3co(struct drm_i915_private *dev_priv) > +static void tgl_disable_dc3co(struct intel_display *display) > { > - drm_dbg_kms(&dev_priv->drm, "Disabling DC3CO\n"); > - intel_de_rmw(dev_priv, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0); > - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); > + drm_dbg_kms(display->drm, "Disabling DC3CO\n"); > + intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0); > + gen9_set_dc_state(display, DC_STATE_DISABLE); > /* > * Delay of 200us DC3CO Exit time B.Spec 49196 > */ > usleep_range(200, 210); > } > > -static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) > +static void assert_can_enable_dc5(struct intel_display *display) > { > + struct drm_i915_private *dev_priv = to_i915(display->drm); > enum i915_power_well_id high_pg; > > /* Power wells at this level and above must be disabled for DC5 entry */ > - if (DISPLAY_VER(dev_priv) == 12) > + if (DISPLAY_VER(display) == 12) > high_pg = ICL_DISP_PW_3; > else > high_pg = SKL_DISP_PW_2; > > - drm_WARN_ONCE(&dev_priv->drm, > + drm_WARN_ONCE(display->drm, > intel_display_power_well_is_enabled(dev_priv, high_pg), > "Power wells above platform's DC5 limit still enabled.\n"); > > - drm_WARN_ONCE(&dev_priv->drm, > - (intel_de_read(dev_priv, DC_STATE_EN) & > + drm_WARN_ONCE(display->drm, > + (intel_de_read(display, DC_STATE_EN) & > DC_STATE_EN_UPTO_DC5), > "DC5 already programmed to be enabled.\n"); > assert_rpm_wakelock_held(&dev_priv->runtime_pm); > @@ -812,60 +818,66 @@ static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) > assert_dmc_loaded(dev_priv); > } > > -void gen9_enable_dc5(struct drm_i915_private *dev_priv) > +void gen9_enable_dc5(struct intel_display *display) > { > - assert_can_enable_dc5(dev_priv); > + struct drm_i915_private *dev_priv = to_i915(display->drm); > > - drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n"); > + assert_can_enable_dc5(display); > + > + drm_dbg_kms(display->drm, "Enabling DC5\n"); > > /* Wa Display #1183: skl,kbl,cfl */ > - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) > - intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, > + if (DISPLAY_VER(display) == 9 && !IS_BROXTON(dev_priv)) > + intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, > 0, SKL_SELECT_ALTERNATE_DC_EXIT); > > - intel_dmc_wl_enable(&dev_priv->display); > + intel_dmc_wl_enable(display); > > - gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); > + gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC5); > } > > -static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) > +static void assert_can_enable_dc6(struct intel_display *display) > { > - drm_WARN_ONCE(&dev_priv->drm, > - (intel_de_read(dev_priv, UTIL_PIN_CTL) & > + struct drm_i915_private *dev_priv = to_i915(display->drm); > + > + drm_WARN_ONCE(display->drm, > + (intel_de_read(display, UTIL_PIN_CTL) & > (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == > (UTIL_PIN_ENABLE | UTIL_PIN_MODE_PWM), > "Utility pin enabled in PWM mode\n"); > - drm_WARN_ONCE(&dev_priv->drm, > - (intel_de_read(dev_priv, DC_STATE_EN) & > + drm_WARN_ONCE(display->drm, > + (intel_de_read(display, DC_STATE_EN) & > DC_STATE_EN_UPTO_DC6), > "DC6 already programmed to be enabled.\n"); > > assert_dmc_loaded(dev_priv); > } > > -void skl_enable_dc6(struct drm_i915_private *dev_priv) > +void skl_enable_dc6(struct intel_display *display) > { > - assert_can_enable_dc6(dev_priv); > + struct drm_i915_private *dev_priv = to_i915(display->drm); > > - drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n"); > + assert_can_enable_dc6(display); > + > + drm_dbg_kms(display->drm, "Enabling DC6\n"); > > /* Wa Display #1183: skl,kbl,cfl */ > - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) > - intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, > + if (DISPLAY_VER(display) == 9 && !IS_BROXTON(dev_priv)) > + intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, > 0, SKL_SELECT_ALTERNATE_DC_EXIT); > > - intel_dmc_wl_enable(&dev_priv->display); > + intel_dmc_wl_enable(display); > > - gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); > + gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6); > } > > -void bxt_enable_dc9(struct drm_i915_private *dev_priv) > +void bxt_enable_dc9(struct intel_display *display) > { > - struct intel_display *display = &dev_priv->display; > + struct drm_i915_private *dev_priv = to_i915(display->drm); > > - assert_can_enable_dc9(dev_priv); > + assert_can_enable_dc9(display); > > - drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n"); > + drm_dbg_kms(display->drm, "Enabling DC9\n"); > /* > * Power sequencer reset is not needed on > * platforms with South Display Engine on PCH, > @@ -873,18 +885,16 @@ void bxt_enable_dc9(struct drm_i915_private *dev_priv) > */ > if (!HAS_PCH_SPLIT(dev_priv)) > intel_pps_reset_all(display); > - gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); > + gen9_set_dc_state(display, DC_STATE_EN_DC9); > } > > -void bxt_disable_dc9(struct drm_i915_private *dev_priv) > +void bxt_disable_dc9(struct intel_display *display) > { > - struct intel_display *display = &dev_priv->display; > + assert_can_disable_dc9(display); > > - assert_can_disable_dc9(dev_priv); > + drm_dbg_kms(display->drm, "Disabling DC9\n"); > > - drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n"); > - > - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); > + gen9_set_dc_state(display, DC_STATE_DISABLE); > > intel_pps_unlock_regs_wa(display); > } > @@ -949,8 +959,10 @@ static void bxt_verify_dpio_phy_power_wells(struct drm_i915_private *dev_priv) > static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, > struct i915_power_well *power_well) > { > - return ((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && > - (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); > + struct intel_display *display = &dev_priv->display; > + > + return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && > + (intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); > } > > static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) > @@ -965,23 +977,23 @@ static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) > enabled_dbuf_slices); > } > > -void gen9_disable_dc_states(struct drm_i915_private *dev_priv) > +void gen9_disable_dc_states(struct intel_display *display) > { > - struct intel_display *display = &dev_priv->display; > + struct drm_i915_private *dev_priv = to_i915(display->drm); > struct i915_power_domains *power_domains = &display->power.domains; > struct intel_cdclk_config cdclk_config = {}; > > if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) { > - tgl_disable_dc3co(dev_priv); > + tgl_disable_dc3co(display); > return; > } > > - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); > + gen9_set_dc_state(display, DC_STATE_DISABLE); > > - if (!HAS_DISPLAY(dev_priv)) > + if (!HAS_DISPLAY(display)) > return; > > - intel_dmc_wl_disable(&dev_priv->display); > + intel_dmc_wl_disable(display); > > intel_cdclk_get_cdclk(display, &cdclk_config); > /* Can't read out voltage_level so can't use intel_cdclk_changed() */ > @@ -994,7 +1006,7 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv) > if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) > bxt_verify_dpio_phy_power_wells(dev_priv); > > - if (DISPLAY_VER(dev_priv) >= 11) > + if (DISPLAY_VER(display) >= 11) > /* > * DMC retains HW context only for port A, the other combo > * PHY's HW context for port B is lost after DC transitions, > @@ -1006,26 +1018,29 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv) > static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, > struct i915_power_well *power_well) > { > - gen9_disable_dc_states(dev_priv); > + struct intel_display *display = &dev_priv->display; > + > + gen9_disable_dc_states(display); > } > > static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, > struct i915_power_well *power_well) > { > - struct i915_power_domains *power_domains = &dev_priv->display.power.domains; > + struct intel_display *display = &dev_priv->display; > + struct i915_power_domains *power_domains = &display->power.domains; > > if (!intel_dmc_has_payload(dev_priv)) > return; > > switch (power_domains->target_dc_state) { > case DC_STATE_EN_DC3CO: > - tgl_enable_dc3co(dev_priv); > + tgl_enable_dc3co(display); > break; > case DC_STATE_EN_UPTO_DC6: > - skl_enable_dc6(dev_priv); > + skl_enable_dc6(display); > break; > case DC_STATE_EN_UPTO_DC5: > - gen9_enable_dc5(dev_priv); > + gen9_enable_dc5(display); > break; > } > } > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h > index 9357a9a73c06..93559f7c6100 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h > @@ -12,6 +12,7 @@ > > struct drm_i915_private; > struct i915_power_well_ops; > +struct intel_display; > struct intel_encoder; > > #define for_each_power_well(__dev_priv, __power_well) \ > @@ -154,13 +155,13 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder, > bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, > enum dpio_channel ch, bool override); > > -void gen9_enable_dc5(struct drm_i915_private *dev_priv); > -void skl_enable_dc6(struct drm_i915_private *dev_priv); > -void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv); > -void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state); > -void gen9_disable_dc_states(struct drm_i915_private *dev_priv); > -void bxt_enable_dc9(struct drm_i915_private *dev_priv); > -void bxt_disable_dc9(struct drm_i915_private *dev_priv); > +void gen9_enable_dc5(struct intel_display *display); > +void skl_enable_dc6(struct intel_display *display); > +void gen9_sanitize_dc_state(struct intel_display *display); > +void gen9_set_dc_state(struct intel_display *display, u32 state); > +void gen9_disable_dc_states(struct intel_display *display); > +void bxt_enable_dc9(struct intel_display *display); > +void bxt_disable_dc9(struct intel_display *display); > > extern const struct i915_power_well_ops i9xx_always_on_power_well_ops; > extern const struct i915_power_well_ops chv_pipe_power_well_ops; > -- > 2.44.2 > ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 4/6] drm/i915/vga: Convert VGA code to intel_display 2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala ` (2 preceding siblings ...) 2024-09-06 14:33 ` [PATCH 3/6] drm/i915/power: Convert low level DC state " Ville Syrjala @ 2024-09-06 14:33 ` Ville Syrjala 2024-09-06 15:12 ` Rodrigo Vivi 2024-09-06 14:33 ` [PATCH 5/6] drm/i915/power: Convert "i830 power well" " Ville Syrjala ` (9 subsequent siblings) 13 siblings, 1 reply; 24+ messages in thread From: Ville Syrjala @ 2024-09-06 14:33 UTC (permalink / raw) To: intel-gfx; +Cc: intel-xe From: Ville Syrjälä <ville.syrjala@linux.intel.com> struct intel_display will replace struct drm_i915_private as the main thing for display code. Convert the VGA code to use it (as much as possible at this stage). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- .../drm/i915/display/intel_display_driver.c | 11 ++--- .../i915/display/intel_display_power_well.c | 6 ++- drivers/gpu/drm/i915/display/intel_vga.c | 45 ++++++++++--------- drivers/gpu/drm/i915/display/intel_vga.h | 14 +++--- drivers/gpu/drm/i915/i915_suspend.c | 3 +- 5 files changed, 43 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index 434e52f450ff..f8da72af2107 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -221,7 +221,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915) intel_bios_init(display); - ret = intel_vga_register(i915); + ret = intel_vga_register(display); if (ret) goto cleanup_bios; @@ -275,7 +275,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915) intel_dmc_fini(i915); intel_power_domains_driver_remove(i915); cleanup_vga: - intel_vga_unregister(i915); + intel_vga_unregister(display); cleanup_bios: intel_bios_driver_remove(display); @@ -458,7 +458,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915) intel_hti_init(display); /* Just disable it once at startup */ - intel_vga_disable(i915); + intel_vga_disable(display); intel_setup_outputs(i915); ret = intel_dp_tunnel_mgr_init(display); @@ -625,7 +625,7 @@ void intel_display_driver_remove_nogem(struct drm_i915_private *i915) intel_power_domains_driver_remove(i915); - intel_vga_unregister(i915); + intel_vga_unregister(display); intel_bios_driver_remove(display); } @@ -683,12 +683,13 @@ __intel_display_driver_resume(struct drm_i915_private *i915, struct drm_atomic_state *state, struct drm_modeset_acquire_ctx *ctx) { + struct intel_display *display = &i915->display; struct drm_crtc_state *crtc_state; struct drm_crtc *crtc; int ret, i; intel_modeset_setup_hw_state(i915, ctx); - intel_vga_redisable(i915); + intel_vga_redisable(display); if (!state) return 0; diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 1f0084ca6248..a5d9b17e03a2 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -187,8 +187,10 @@ int intel_power_well_refcount(struct i915_power_well *power_well) static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, u8 irq_pipe_mask, bool has_vga) { + struct intel_display *display = &dev_priv->display; + if (has_vga) - intel_vga_reset_io_mem(dev_priv); + intel_vga_reset_io_mem(display); if (irq_pipe_mask) gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); @@ -1248,7 +1250,7 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) intel_crt_reset(&encoder->base); } - intel_vga_redisable_power_on(dev_priv); + intel_vga_redisable_power_on(display); intel_pps_unlock_regs_wa(display); } diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index 0b5916c15307..2c76a0176a35 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -14,24 +14,26 @@ #include "intel_de.h" #include "intel_vga.h" -static i915_reg_t intel_vga_cntrl_reg(struct drm_i915_private *i915) +static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display) { + struct drm_i915_private *i915 = to_i915(display->drm); + if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) return VLV_VGACNTRL; - else if (DISPLAY_VER(i915) >= 5) + else if (DISPLAY_VER(display) >= 5) return CPU_VGACNTRL; else return VGACNTRL; } /* Disable the VGA plane that we never use */ -void intel_vga_disable(struct drm_i915_private *dev_priv) +void intel_vga_disable(struct intel_display *display) { - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); - i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv); + struct pci_dev *pdev = to_pci_dev(display->drm->dev); + i915_reg_t vga_reg = intel_vga_cntrl_reg(display); u8 sr1; - if (intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE) + if (intel_de_read(display, vga_reg) & VGA_DISP_DISABLE) return; /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ @@ -42,23 +44,24 @@ void intel_vga_disable(struct drm_i915_private *dev_priv) vga_put(pdev, VGA_RSRC_LEGACY_IO); udelay(300); - intel_de_write(dev_priv, vga_reg, VGA_DISP_DISABLE); - intel_de_posting_read(dev_priv, vga_reg); + intel_de_write(display, vga_reg, VGA_DISP_DISABLE); + intel_de_posting_read(display, vga_reg); } -void intel_vga_redisable_power_on(struct drm_i915_private *dev_priv) +void intel_vga_redisable_power_on(struct intel_display *display) { - i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv); + i915_reg_t vga_reg = intel_vga_cntrl_reg(display); - if (!(intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE)) { - drm_dbg_kms(&dev_priv->drm, + if (!(intel_de_read(display, vga_reg) & VGA_DISP_DISABLE)) { + drm_dbg_kms(display->drm, "Something enabled VGA plane, disabling it\n"); - intel_vga_disable(dev_priv); + intel_vga_disable(display); } } -void intel_vga_redisable(struct drm_i915_private *i915) +void intel_vga_redisable(struct intel_display *display) { + struct drm_i915_private *i915 = to_i915(display->drm); intel_wakeref_t wakeref; /* @@ -74,14 +77,14 @@ void intel_vga_redisable(struct drm_i915_private *i915) if (!wakeref) return; - intel_vga_redisable_power_on(i915); + intel_vga_redisable_power_on(display); intel_display_power_put(i915, POWER_DOMAIN_VGA, wakeref); } -void intel_vga_reset_io_mem(struct drm_i915_private *i915) +void intel_vga_reset_io_mem(struct intel_display *display) { - struct pci_dev *pdev = to_pci_dev(i915->drm.dev); + struct pci_dev *pdev = to_pci_dev(display->drm->dev); /* * After we re-enable the power well, if we touch VGA register 0x3d5 @@ -98,10 +101,10 @@ void intel_vga_reset_io_mem(struct drm_i915_private *i915) vga_put(pdev, VGA_RSRC_LEGACY_IO); } -int intel_vga_register(struct drm_i915_private *i915) +int intel_vga_register(struct intel_display *display) { - struct pci_dev *pdev = to_pci_dev(i915->drm.dev); + struct pci_dev *pdev = to_pci_dev(display->drm->dev); int ret; /* @@ -119,9 +122,9 @@ int intel_vga_register(struct drm_i915_private *i915) return 0; } -void intel_vga_unregister(struct drm_i915_private *i915) +void intel_vga_unregister(struct intel_display *display) { - struct pci_dev *pdev = to_pci_dev(i915->drm.dev); + struct pci_dev *pdev = to_pci_dev(display->drm->dev); vga_client_unregister(pdev); } diff --git a/drivers/gpu/drm/i915/display/intel_vga.h b/drivers/gpu/drm/i915/display/intel_vga.h index ba5b55b917f0..824dfc32a199 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.h +++ b/drivers/gpu/drm/i915/display/intel_vga.h @@ -6,13 +6,13 @@ #ifndef __INTEL_VGA_H__ #define __INTEL_VGA_H__ -struct drm_i915_private; +struct intel_display; -void intel_vga_reset_io_mem(struct drm_i915_private *i915); -void intel_vga_disable(struct drm_i915_private *i915); -void intel_vga_redisable(struct drm_i915_private *i915); -void intel_vga_redisable_power_on(struct drm_i915_private *i915); -int intel_vga_register(struct drm_i915_private *i915); -void intel_vga_unregister(struct drm_i915_private *i915); +void intel_vga_reset_io_mem(struct intel_display *display); +void intel_vga_disable(struct intel_display *display); +void intel_vga_redisable(struct intel_display *display); +void intel_vga_redisable_power_on(struct intel_display *display); +int intel_vga_register(struct intel_display *display); +void intel_vga_unregister(struct intel_display *display); #endif /* __INTEL_VGA_H__ */ diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index f8373a461f17..9d3d9b983032 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -118,6 +118,7 @@ void i915_save_display(struct drm_i915_private *dev_priv) void i915_restore_display(struct drm_i915_private *dev_priv) { + struct intel_display *display = &dev_priv->display; struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); if (!HAS_DISPLAY(dev_priv)) @@ -134,7 +135,7 @@ void i915_restore_display(struct drm_i915_private *dev_priv) intel_de_write(dev_priv, DSPARB(dev_priv), dev_priv->regfile.saveDSPARB); - intel_vga_redisable(dev_priv); + intel_vga_redisable(display); intel_gmbus_reset(dev_priv); } -- 2.44.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 4/6] drm/i915/vga: Convert VGA code to intel_display 2024-09-06 14:33 ` [PATCH 4/6] drm/i915/vga: Convert VGA " Ville Syrjala @ 2024-09-06 15:12 ` Rodrigo Vivi 0 siblings, 0 replies; 24+ messages in thread From: Rodrigo Vivi @ 2024-09-06 15:12 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx, intel-xe On Fri, Sep 06, 2024 at 05:33:04PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > struct intel_display will replace struct drm_i915_private as > the main thing for display code. Convert the VGA code to > use it (as much as possible at this stage). > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > .../drm/i915/display/intel_display_driver.c | 11 ++--- > .../i915/display/intel_display_power_well.c | 6 ++- > drivers/gpu/drm/i915/display/intel_vga.c | 45 ++++++++++--------- > drivers/gpu/drm/i915/display/intel_vga.h | 14 +++--- > drivers/gpu/drm/i915/i915_suspend.c | 3 +- > 5 files changed, 43 insertions(+), 36 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c > index 434e52f450ff..f8da72af2107 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c > @@ -221,7 +221,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915) > > intel_bios_init(display); > > - ret = intel_vga_register(i915); > + ret = intel_vga_register(display); > if (ret) > goto cleanup_bios; > > @@ -275,7 +275,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915) > intel_dmc_fini(i915); > intel_power_domains_driver_remove(i915); > cleanup_vga: > - intel_vga_unregister(i915); > + intel_vga_unregister(display); > cleanup_bios: > intel_bios_driver_remove(display); > > @@ -458,7 +458,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915) > intel_hti_init(display); > > /* Just disable it once at startup */ > - intel_vga_disable(i915); > + intel_vga_disable(display); > intel_setup_outputs(i915); > > ret = intel_dp_tunnel_mgr_init(display); > @@ -625,7 +625,7 @@ void intel_display_driver_remove_nogem(struct drm_i915_private *i915) > > intel_power_domains_driver_remove(i915); > > - intel_vga_unregister(i915); > + intel_vga_unregister(display); > > intel_bios_driver_remove(display); > } > @@ -683,12 +683,13 @@ __intel_display_driver_resume(struct drm_i915_private *i915, > struct drm_atomic_state *state, > struct drm_modeset_acquire_ctx *ctx) > { > + struct intel_display *display = &i915->display; > struct drm_crtc_state *crtc_state; > struct drm_crtc *crtc; > int ret, i; > > intel_modeset_setup_hw_state(i915, ctx); > - intel_vga_redisable(i915); > + intel_vga_redisable(display); > > if (!state) > return 0; > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c > index 1f0084ca6248..a5d9b17e03a2 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c > @@ -187,8 +187,10 @@ int intel_power_well_refcount(struct i915_power_well *power_well) > static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, > u8 irq_pipe_mask, bool has_vga) > { > + struct intel_display *display = &dev_priv->display; I was going to say that it would be probably good to replace the function argument.. > + > if (has_vga) > - intel_vga_reset_io_mem(dev_priv); > + intel_vga_reset_io_mem(display); > > if (irq_pipe_mask) > gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); but then I noticed it is still used internally... but anyway, I believe it is already a step towards the right direction and we replace the inner cases as we go... Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > @@ -1248,7 +1250,7 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) > intel_crt_reset(&encoder->base); > } > > - intel_vga_redisable_power_on(dev_priv); > + intel_vga_redisable_power_on(display); > > intel_pps_unlock_regs_wa(display); > } > diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c > index 0b5916c15307..2c76a0176a35 100644 > --- a/drivers/gpu/drm/i915/display/intel_vga.c > +++ b/drivers/gpu/drm/i915/display/intel_vga.c > @@ -14,24 +14,26 @@ > #include "intel_de.h" > #include "intel_vga.h" > > -static i915_reg_t intel_vga_cntrl_reg(struct drm_i915_private *i915) > +static i915_reg_t intel_vga_cntrl_reg(struct intel_display *display) > { > + struct drm_i915_private *i915 = to_i915(display->drm); > + > if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) > return VLV_VGACNTRL; > - else if (DISPLAY_VER(i915) >= 5) > + else if (DISPLAY_VER(display) >= 5) > return CPU_VGACNTRL; > else > return VGACNTRL; > } > > /* Disable the VGA plane that we never use */ > -void intel_vga_disable(struct drm_i915_private *dev_priv) > +void intel_vga_disable(struct intel_display *display) > { > - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); > - i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv); > + struct pci_dev *pdev = to_pci_dev(display->drm->dev); > + i915_reg_t vga_reg = intel_vga_cntrl_reg(display); > u8 sr1; > > - if (intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE) > + if (intel_de_read(display, vga_reg) & VGA_DISP_DISABLE) > return; > > /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ > @@ -42,23 +44,24 @@ void intel_vga_disable(struct drm_i915_private *dev_priv) > vga_put(pdev, VGA_RSRC_LEGACY_IO); > udelay(300); > > - intel_de_write(dev_priv, vga_reg, VGA_DISP_DISABLE); > - intel_de_posting_read(dev_priv, vga_reg); > + intel_de_write(display, vga_reg, VGA_DISP_DISABLE); > + intel_de_posting_read(display, vga_reg); > } > > -void intel_vga_redisable_power_on(struct drm_i915_private *dev_priv) > +void intel_vga_redisable_power_on(struct intel_display *display) > { > - i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv); > + i915_reg_t vga_reg = intel_vga_cntrl_reg(display); > > - if (!(intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE)) { > - drm_dbg_kms(&dev_priv->drm, > + if (!(intel_de_read(display, vga_reg) & VGA_DISP_DISABLE)) { > + drm_dbg_kms(display->drm, > "Something enabled VGA plane, disabling it\n"); > - intel_vga_disable(dev_priv); > + intel_vga_disable(display); > } > } > > -void intel_vga_redisable(struct drm_i915_private *i915) > +void intel_vga_redisable(struct intel_display *display) > { > + struct drm_i915_private *i915 = to_i915(display->drm); > intel_wakeref_t wakeref; > > /* > @@ -74,14 +77,14 @@ void intel_vga_redisable(struct drm_i915_private *i915) > if (!wakeref) > return; > > - intel_vga_redisable_power_on(i915); > + intel_vga_redisable_power_on(display); > > intel_display_power_put(i915, POWER_DOMAIN_VGA, wakeref); > } > > -void intel_vga_reset_io_mem(struct drm_i915_private *i915) > +void intel_vga_reset_io_mem(struct intel_display *display) > { > - struct pci_dev *pdev = to_pci_dev(i915->drm.dev); > + struct pci_dev *pdev = to_pci_dev(display->drm->dev); > > /* > * After we re-enable the power well, if we touch VGA register 0x3d5 > @@ -98,10 +101,10 @@ void intel_vga_reset_io_mem(struct drm_i915_private *i915) > vga_put(pdev, VGA_RSRC_LEGACY_IO); > } > > -int intel_vga_register(struct drm_i915_private *i915) > +int intel_vga_register(struct intel_display *display) > { > > - struct pci_dev *pdev = to_pci_dev(i915->drm.dev); > + struct pci_dev *pdev = to_pci_dev(display->drm->dev); > int ret; > > /* > @@ -119,9 +122,9 @@ int intel_vga_register(struct drm_i915_private *i915) > return 0; > } > > -void intel_vga_unregister(struct drm_i915_private *i915) > +void intel_vga_unregister(struct intel_display *display) > { > - struct pci_dev *pdev = to_pci_dev(i915->drm.dev); > + struct pci_dev *pdev = to_pci_dev(display->drm->dev); > > vga_client_unregister(pdev); > } > diff --git a/drivers/gpu/drm/i915/display/intel_vga.h b/drivers/gpu/drm/i915/display/intel_vga.h > index ba5b55b917f0..824dfc32a199 100644 > --- a/drivers/gpu/drm/i915/display/intel_vga.h > +++ b/drivers/gpu/drm/i915/display/intel_vga.h > @@ -6,13 +6,13 @@ > #ifndef __INTEL_VGA_H__ > #define __INTEL_VGA_H__ > > -struct drm_i915_private; > +struct intel_display; > > -void intel_vga_reset_io_mem(struct drm_i915_private *i915); > -void intel_vga_disable(struct drm_i915_private *i915); > -void intel_vga_redisable(struct drm_i915_private *i915); > -void intel_vga_redisable_power_on(struct drm_i915_private *i915); > -int intel_vga_register(struct drm_i915_private *i915); > -void intel_vga_unregister(struct drm_i915_private *i915); > +void intel_vga_reset_io_mem(struct intel_display *display); > +void intel_vga_disable(struct intel_display *display); > +void intel_vga_redisable(struct intel_display *display); > +void intel_vga_redisable_power_on(struct intel_display *display); > +int intel_vga_register(struct intel_display *display); > +void intel_vga_unregister(struct intel_display *display); > > #endif /* __INTEL_VGA_H__ */ > diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c > index f8373a461f17..9d3d9b983032 100644 > --- a/drivers/gpu/drm/i915/i915_suspend.c > +++ b/drivers/gpu/drm/i915/i915_suspend.c > @@ -118,6 +118,7 @@ void i915_save_display(struct drm_i915_private *dev_priv) > > void i915_restore_display(struct drm_i915_private *dev_priv) > { > + struct intel_display *display = &dev_priv->display; > struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); > > if (!HAS_DISPLAY(dev_priv)) > @@ -134,7 +135,7 @@ void i915_restore_display(struct drm_i915_private *dev_priv) > intel_de_write(dev_priv, DSPARB(dev_priv), > dev_priv->regfile.saveDSPARB); > > - intel_vga_redisable(dev_priv); > + intel_vga_redisable(display); > > intel_gmbus_reset(dev_priv); > } > -- > 2.44.2 > ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 5/6] drm/i915/power: Convert "i830 power well" code to intel_display 2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala ` (3 preceding siblings ...) 2024-09-06 14:33 ` [PATCH 4/6] drm/i915/vga: Convert VGA " Ville Syrjala @ 2024-09-06 14:33 ` Ville Syrjala 2024-09-06 15:13 ` Rodrigo Vivi 2024-09-06 14:33 ` [PATCH 6/6] drm/i915/dmc: Convert DMC " Ville Syrjala ` (8 subsequent siblings) 13 siblings, 1 reply; 24+ messages in thread From: Ville Syrjala @ 2024-09-06 14:33 UTC (permalink / raw) To: intel-gfx; +Cc: intel-xe From: Ville Syrjälä <ville.syrjala@linux.intel.com> struct intel_display will replace struct drm_i915_private as the main thing for display code. Convert the "i830 power well" code to use it (as much as possible at this stage). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 79 +++++++++---------- drivers/gpu/drm/i915/display/intel_display.h | 5 +- .../i915/display/intel_display_power_well.c | 22 ++++-- 3 files changed, 56 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b4ec9bf12aa7..0ec78b06ca80 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2226,9 +2226,10 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) static void i9xx_crtc_disable(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(state); + struct drm_i915_private *dev_priv = to_i915(display->drm); struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; /* @@ -2267,7 +2268,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state, /* clock the pipe down to 640x480@60 to potentially save power */ if (IS_I830(dev_priv)) - i830_enable_pipe(dev_priv, pipe); + i830_enable_pipe(display, pipe); } void intel_encoder_destroy(struct drm_encoder *encoder) @@ -8257,9 +8258,8 @@ int intel_initial_commit(struct drm_device *dev) return ret; } -void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) +void i830_enable_pipe(struct intel_display *display, enum pipe pipe) { - struct intel_display *display = &dev_priv->display; struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); enum transcoder cpu_transcoder = (enum transcoder)pipe; /* 640x480@60Hz, ~25175 kHz */ @@ -8273,10 +8273,10 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) u32 dpll, fp; int i; - drm_WARN_ON(&dev_priv->drm, + drm_WARN_ON(display->drm, i9xx_calc_dpll_params(48000, &clock) != 25154); - drm_dbg_kms(&dev_priv->drm, + drm_dbg_kms(display->drm, "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", pipe_name(pipe), clock.vco, clock.dot); @@ -8288,35 +8288,35 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) PLL_REF_INPUT_DREFCLK | DPLL_VCO_ENABLE; - intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder), HACTIVE(640 - 1) | HTOTAL(800 - 1)); - intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder), HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); - intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder), HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); - intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), VACTIVE(480 - 1) | VTOTAL(525 - 1)); - intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); - intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder), + intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); - intel_de_write(dev_priv, PIPESRC(dev_priv, pipe), + intel_de_write(display, PIPESRC(display, pipe), PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); - intel_de_write(dev_priv, FP0(pipe), fp); - intel_de_write(dev_priv, FP1(pipe), fp); + intel_de_write(display, FP0(pipe), fp); + intel_de_write(display, FP1(pipe), fp); /* * Apparently we need to have VGA mode enabled prior to changing * the P1/P2 dividers. Otherwise the DPLL will keep using the old * dividers, even though the register value does change. */ - intel_de_write(dev_priv, DPLL(dev_priv, pipe), + intel_de_write(display, DPLL(display, pipe), dpll & ~DPLL_VGA_MODE_DIS); - intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll); + intel_de_write(display, DPLL(display, pipe), dpll); /* Wait for the clocks to stabilize. */ - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); + intel_de_posting_read(display, DPLL(display, pipe)); udelay(150); /* The pixel multiplier can only be updated once the @@ -8324,47 +8324,46 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) * * So write it again. */ - intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll); + intel_de_write(display, DPLL(display, pipe), dpll); /* We do this three times for luck */ for (i = 0; i < 3 ; i++) { - intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll); - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); + intel_de_write(display, DPLL(display, pipe), dpll); + intel_de_posting_read(display, DPLL(display, pipe)); udelay(150); /* wait for warmup */ } - intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), TRANSCONF_ENABLE); - intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe)); + intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE); + intel_de_posting_read(display, TRANSCONF(display, pipe)); intel_wait_for_pipe_scanline_moving(crtc); } -void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) +void i830_disable_pipe(struct intel_display *display, enum pipe pipe) { - struct intel_display *display = &dev_priv->display; struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); - drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", + drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n", pipe_name(pipe)); - drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_A)) & DISP_ENABLE); - drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_B)) & DISP_ENABLE); - drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_C)) & DISP_ENABLE); - drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & MCURSOR_MODE_MASK); - drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_B)) & MCURSOR_MODE_MASK); + drm_WARN_ON(display->drm, + intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE); + drm_WARN_ON(display->drm, + intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE); + drm_WARN_ON(display->drm, + intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE); + drm_WARN_ON(display->drm, + intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK); + drm_WARN_ON(display->drm, + intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK); - intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), 0); - intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe)); + intel_de_write(display, TRANSCONF(display, pipe), 0); + intel_de_posting_read(display, TRANSCONF(display, pipe)); intel_wait_for_pipe_scanline_stopped(crtc); - intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS); - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); + intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS); + intel_de_posting_read(display, DPLL(display, pipe)); } void intel_hpd_poll_fini(struct drm_i915_private *i915) diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index b21d9578d5db..7ca26e5cb20e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -52,6 +52,7 @@ struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; struct intel_digital_port; +struct intel_display; struct intel_dp; struct intel_encoder; struct intel_initial_plane_config; @@ -437,8 +438,8 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state); void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state); -void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); -void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); +void i830_enable_pipe(struct intel_display *display, enum pipe pipe); +void i830_disable_pipe(struct intel_display *display, enum pipe pipe); int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); int vlv_get_cck_clock(struct drm_i915_private *dev_priv, const char *name, u32 reg, int ref_freq); diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index a5d9b17e03a2..9f275a6674a1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -1066,24 +1066,30 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE) == 0) - i830_enable_pipe(dev_priv, PIPE_A); - if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE) == 0) - i830_enable_pipe(dev_priv, PIPE_B); + struct intel_display *display = &dev_priv->display; + + if ((intel_de_read(display, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE) == 0) + i830_enable_pipe(display, PIPE_A); + if ((intel_de_read(display, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE) == 0) + i830_enable_pipe(display, PIPE_B); } static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - i830_disable_pipe(dev_priv, PIPE_B); - i830_disable_pipe(dev_priv, PIPE_A); + struct intel_display *display = &dev_priv->display; + + i830_disable_pipe(display, PIPE_B); + i830_disable_pipe(display, PIPE_A); } static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - return intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE && - intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE; + struct intel_display *display = &dev_priv->display; + + return intel_de_read(display, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE && + intel_de_read(display, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE; } static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, -- 2.44.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 5/6] drm/i915/power: Convert "i830 power well" code to intel_display 2024-09-06 14:33 ` [PATCH 5/6] drm/i915/power: Convert "i830 power well" " Ville Syrjala @ 2024-09-06 15:13 ` Rodrigo Vivi 0 siblings, 0 replies; 24+ messages in thread From: Rodrigo Vivi @ 2024-09-06 15:13 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx, intel-xe On Fri, Sep 06, 2024 at 05:33:05PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > struct intel_display will replace struct drm_i915_private as > the main thing for display code. Convert the "i830 power well" > code to use it (as much as possible at this stage). > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 79 +++++++++---------- > drivers/gpu/drm/i915/display/intel_display.h | 5 +- > .../i915/display/intel_display_power_well.c | 22 ++++-- > 3 files changed, 56 insertions(+), 50 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index b4ec9bf12aa7..0ec78b06ca80 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -2226,9 +2226,10 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) > static void i9xx_crtc_disable(struct intel_atomic_state *state, > struct intel_crtc *crtc) > { > + struct intel_display *display = to_intel_display(state); > + struct drm_i915_private *dev_priv = to_i915(display->drm); > struct intel_crtc_state *old_crtc_state = > intel_atomic_get_old_crtc_state(state, crtc); > - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum pipe pipe = crtc->pipe; > > /* > @@ -2267,7 +2268,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state, > > /* clock the pipe down to 640x480@60 to potentially save power */ > if (IS_I830(dev_priv)) > - i830_enable_pipe(dev_priv, pipe); > + i830_enable_pipe(display, pipe); > } > > void intel_encoder_destroy(struct drm_encoder *encoder) > @@ -8257,9 +8258,8 @@ int intel_initial_commit(struct drm_device *dev) > return ret; > } > > -void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) > +void i830_enable_pipe(struct intel_display *display, enum pipe pipe) > { > - struct intel_display *display = &dev_priv->display; > struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); > enum transcoder cpu_transcoder = (enum transcoder)pipe; > /* 640x480@60Hz, ~25175 kHz */ > @@ -8273,10 +8273,10 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) > u32 dpll, fp; > int i; > > - drm_WARN_ON(&dev_priv->drm, > + drm_WARN_ON(display->drm, > i9xx_calc_dpll_params(48000, &clock) != 25154); > > - drm_dbg_kms(&dev_priv->drm, > + drm_dbg_kms(display->drm, > "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", > pipe_name(pipe), clock.vco, clock.dot); > > @@ -8288,35 +8288,35 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) > PLL_REF_INPUT_DREFCLK | > DPLL_VCO_ENABLE; > > - intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder), > + intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder), > HACTIVE(640 - 1) | HTOTAL(800 - 1)); > - intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder), > + intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder), > HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); > - intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder), > + intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder), > HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); > - intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder), > + intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder), > VACTIVE(480 - 1) | VTOTAL(525 - 1)); > - intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder), > + intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder), > VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); > - intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder), > + intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder), > VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); > - intel_de_write(dev_priv, PIPESRC(dev_priv, pipe), > + intel_de_write(display, PIPESRC(display, pipe), > PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); > > - intel_de_write(dev_priv, FP0(pipe), fp); > - intel_de_write(dev_priv, FP1(pipe), fp); > + intel_de_write(display, FP0(pipe), fp); > + intel_de_write(display, FP1(pipe), fp); > > /* > * Apparently we need to have VGA mode enabled prior to changing > * the P1/P2 dividers. Otherwise the DPLL will keep using the old > * dividers, even though the register value does change. > */ > - intel_de_write(dev_priv, DPLL(dev_priv, pipe), > + intel_de_write(display, DPLL(display, pipe), > dpll & ~DPLL_VGA_MODE_DIS); > - intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll); > + intel_de_write(display, DPLL(display, pipe), dpll); > > /* Wait for the clocks to stabilize. */ > - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); > + intel_de_posting_read(display, DPLL(display, pipe)); > udelay(150); > > /* The pixel multiplier can only be updated once the > @@ -8324,47 +8324,46 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) > * > * So write it again. > */ > - intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll); > + intel_de_write(display, DPLL(display, pipe), dpll); > > /* We do this three times for luck */ > for (i = 0; i < 3 ; i++) { > - intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll); > - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); > + intel_de_write(display, DPLL(display, pipe), dpll); > + intel_de_posting_read(display, DPLL(display, pipe)); > udelay(150); /* wait for warmup */ > } > > - intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), TRANSCONF_ENABLE); > - intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe)); > + intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE); > + intel_de_posting_read(display, TRANSCONF(display, pipe)); > > intel_wait_for_pipe_scanline_moving(crtc); > } > > -void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) > +void i830_disable_pipe(struct intel_display *display, enum pipe pipe) > { > - struct intel_display *display = &dev_priv->display; > struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); > > - drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", > + drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n", > pipe_name(pipe)); > > - drm_WARN_ON(&dev_priv->drm, > - intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_A)) & DISP_ENABLE); > - drm_WARN_ON(&dev_priv->drm, > - intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_B)) & DISP_ENABLE); > - drm_WARN_ON(&dev_priv->drm, > - intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_C)) & DISP_ENABLE); > - drm_WARN_ON(&dev_priv->drm, > - intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & MCURSOR_MODE_MASK); > - drm_WARN_ON(&dev_priv->drm, > - intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_B)) & MCURSOR_MODE_MASK); > + drm_WARN_ON(display->drm, > + intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE); > + drm_WARN_ON(display->drm, > + intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE); > + drm_WARN_ON(display->drm, > + intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE); > + drm_WARN_ON(display->drm, > + intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK); > + drm_WARN_ON(display->drm, > + intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK); > > - intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), 0); > - intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe)); > + intel_de_write(display, TRANSCONF(display, pipe), 0); > + intel_de_posting_read(display, TRANSCONF(display, pipe)); > > intel_wait_for_pipe_scanline_stopped(crtc); > > - intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS); > - intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); > + intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS); > + intel_de_posting_read(display, DPLL(display, pipe)); > } > > void intel_hpd_poll_fini(struct drm_i915_private *i915) > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h > index b21d9578d5db..7ca26e5cb20e 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.h > +++ b/drivers/gpu/drm/i915/display/intel_display.h > @@ -52,6 +52,7 @@ struct intel_atomic_state; > struct intel_crtc; > struct intel_crtc_state; > struct intel_digital_port; > +struct intel_display; > struct intel_dp; > struct intel_encoder; > struct intel_initial_plane_config; > @@ -437,8 +438,8 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); > void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); > void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state); > void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state); > -void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); > -void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); > +void i830_enable_pipe(struct intel_display *display, enum pipe pipe); > +void i830_disable_pipe(struct intel_display *display, enum pipe pipe); > int vlv_get_hpll_vco(struct drm_i915_private *dev_priv); > int vlv_get_cck_clock(struct drm_i915_private *dev_priv, > const char *name, u32 reg, int ref_freq); > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c > index a5d9b17e03a2..9f275a6674a1 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c > @@ -1066,24 +1066,30 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, > static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv, > struct i915_power_well *power_well) > { > - if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE) == 0) > - i830_enable_pipe(dev_priv, PIPE_A); > - if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE) == 0) > - i830_enable_pipe(dev_priv, PIPE_B); > + struct intel_display *display = &dev_priv->display; > + > + if ((intel_de_read(display, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE) == 0) > + i830_enable_pipe(display, PIPE_A); > + if ((intel_de_read(display, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE) == 0) > + i830_enable_pipe(display, PIPE_B); > } > > static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv, > struct i915_power_well *power_well) > { > - i830_disable_pipe(dev_priv, PIPE_B); > - i830_disable_pipe(dev_priv, PIPE_A); > + struct intel_display *display = &dev_priv->display; > + > + i830_disable_pipe(display, PIPE_B); > + i830_disable_pipe(display, PIPE_A); > } > > static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv, > struct i915_power_well *power_well) > { > - return intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE && > - intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE; > + struct intel_display *display = &dev_priv->display; > + > + return intel_de_read(display, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE && > + intel_de_read(display, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE; > } > > static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, > -- > 2.44.2 > ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH 6/6] drm/i915/dmc: Convert DMC code to intel_display 2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala ` (4 preceding siblings ...) 2024-09-06 14:33 ` [PATCH 5/6] drm/i915/power: Convert "i830 power well" " Ville Syrjala @ 2024-09-06 14:33 ` Ville Syrjala 2024-09-06 15:16 ` Rodrigo Vivi 2024-09-06 14:38 ` ✓ CI.Patch_applied: success for drm/i915: Some intel_display conversions Patchwork ` (7 subsequent siblings) 13 siblings, 1 reply; 24+ messages in thread From: Ville Syrjala @ 2024-09-06 14:33 UTC (permalink / raw) To: intel-gfx; +Cc: intel-xe From: Ville Syrjälä <ville.syrjala@linux.intel.com> struct intel_display will replace struct drm_i915_private as the main thing for display code. Convert the DMC code to use it (as much as possible at this stage). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/display/intel_display.c | 7 +- .../drm/i915/display/intel_display_debugfs.c | 2 +- .../drm/i915/display/intel_display_driver.c | 6 +- .../drm/i915/display/intel_display_power.c | 17 +- .../i915/display/intel_display_power_well.c | 8 +- drivers/gpu/drm/i915/display/intel_dmc.c | 391 +++++++++--------- drivers/gpu/drm/i915/display/intel_dmc.h | 26 +- drivers/gpu/drm/i915/display/intel_dmc_wl.c | 4 +- .../drm/i915/display/intel_modeset_setup.c | 3 +- drivers/gpu/drm/i915/i915_driver.c | 6 +- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/xe/display/xe_display.c | 4 +- 12 files changed, 243 insertions(+), 233 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0ec78b06ca80..fdf244a32b24 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1690,7 +1690,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, intel_crtc_joined_pipe_mask(new_crtc_state)) - intel_dmc_enable_pipe(dev_priv, pipe_crtc->pipe); + intel_dmc_enable_pipe(display, pipe_crtc->pipe); intel_encoders_pre_pll_enable(state, crtc); @@ -1843,9 +1843,10 @@ static void ilk_crtc_disable(struct intel_atomic_state *state, static void hsw_crtc_disable(struct intel_atomic_state *state, struct intel_crtc *crtc) { + struct intel_display *display = to_intel_display(state); + struct drm_i915_private *i915 = to_i915(display->drm); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_crtc *pipe_crtc; /* @@ -1867,7 +1868,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state, for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, intel_crtc_joined_pipe_mask(old_crtc_state)) - intel_dmc_disable_pipe(i915, pipe_crtc->pipe); + intel_dmc_disable_pipe(display, pipe_crtc->pipe); } static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index c1bef34d1ffd..b75361e95e97 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -1069,7 +1069,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915) intel_bios_debugfs_register(display); intel_cdclk_debugfs_register(display); - intel_dmc_debugfs_register(i915); + intel_dmc_debugfs_register(display); intel_fbc_debugfs_register(display); intel_hpd_debugfs_register(i915); intel_opregion_debugfs_register(display); diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index f8da72af2107..c106fb2dd20b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -237,7 +237,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915) if (!HAS_DISPLAY(i915)) return 0; - intel_dmc_init(i915); + intel_dmc_init(display); i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0); i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI | @@ -272,7 +272,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915) return 0; cleanup_vga_client_pw_domain_dmc: - intel_dmc_fini(i915); + intel_dmc_fini(display); intel_power_domains_driver_remove(i915); cleanup_vga: intel_vga_unregister(display); @@ -621,7 +621,7 @@ void intel_display_driver_remove_nogem(struct drm_i915_private *i915) { struct intel_display *display = &i915->display; - intel_dmc_fini(i915); + intel_dmc_fini(display); intel_power_domains_driver_remove(i915); diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 86ac494ed33b..ecabb674644b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1445,7 +1445,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, gen9_dbuf_enable(dev_priv); if (resume) - intel_dmc_load_program(dev_priv); + intel_dmc_load_program(display); } static void skl_display_core_uninit(struct drm_i915_private *dev_priv) @@ -1515,7 +1515,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume gen9_dbuf_enable(dev_priv); if (resume) - intel_dmc_load_program(dev_priv); + intel_dmc_load_program(display); } static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) @@ -1687,7 +1687,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); if (resume) - intel_dmc_load_program(dev_priv); + intel_dmc_load_program(display); /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */ if (IS_DISPLAY_VER_FULL(dev_priv, IP_VER(12, 0), IP_VER(13, 0))) @@ -1718,7 +1718,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) return; gen9_disable_dc_states(display); - intel_dmc_disable_program(dev_priv); + intel_dmc_disable_program(display); /* 1. Disable all display engine functions -> aready done */ @@ -2073,7 +2073,8 @@ void intel_power_domains_disable(struct drm_i915_private *i915) */ void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle) { - struct i915_power_domains *power_domains = &i915->display.power.domains; + struct intel_display *display = &i915->display; + struct i915_power_domains *power_domains = &display->power.domains; intel_wakeref_t wakeref __maybe_unused = fetch_and_zero(&power_domains->init_wakeref); @@ -2087,7 +2088,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle) * that would be blocked if the firmware was inactive. */ if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle && - intel_dmc_has_payload(i915)) { + intel_dmc_has_payload(display)) { intel_display_power_flush_work(i915); intel_power_domains_verify_state(i915); return; @@ -2286,7 +2287,7 @@ void intel_display_power_resume(struct drm_i915_private *i915) if (DISPLAY_VER(i915) >= 11) { bxt_disable_dc9(display); icl_display_core_init(i915, true); - if (intel_dmc_has_payload(i915)) { + if (intel_dmc_has_payload(display)) { if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6) skl_enable_dc6(display); else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5) @@ -2295,7 +2296,7 @@ void intel_display_power_resume(struct drm_i915_private *i915) } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { bxt_disable_dc9(display); bxt_display_core_init(i915, true); - if (intel_dmc_has_payload(i915) && + if (intel_dmc_has_payload(display) && (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) gen9_enable_dc5(display); } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 9f275a6674a1..1898aff50ac4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -817,7 +817,7 @@ static void assert_can_enable_dc5(struct intel_display *display) "DC5 already programmed to be enabled.\n"); assert_rpm_wakelock_held(&dev_priv->runtime_pm); - assert_dmc_loaded(dev_priv); + assert_dmc_loaded(display); } void gen9_enable_dc5(struct intel_display *display) @@ -840,8 +840,6 @@ void gen9_enable_dc5(struct intel_display *display) static void assert_can_enable_dc6(struct intel_display *display) { - struct drm_i915_private *dev_priv = to_i915(display->drm); - drm_WARN_ONCE(display->drm, (intel_de_read(display, UTIL_PIN_CTL) & (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == @@ -852,7 +850,7 @@ static void assert_can_enable_dc6(struct intel_display *display) DC_STATE_EN_UPTO_DC6), "DC6 already programmed to be enabled.\n"); - assert_dmc_loaded(dev_priv); + assert_dmc_loaded(display); } void skl_enable_dc6(struct intel_display *display) @@ -1031,7 +1029,7 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, struct intel_display *display = &dev_priv->display; struct i915_power_domains *power_domains = &display->power.domains; - if (!intel_dmc_has_payload(dev_priv)) + if (!intel_dmc_has_payload(display)) return; switch (power_domains->target_dc_state) { diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 7c756d5ba2a2..bbac6bfd1752 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -52,7 +52,7 @@ enum intel_dmc_id { }; struct intel_dmc { - struct drm_i915_private *i915; + struct intel_display *display; struct work_struct work; const char *fw_path; u32 max_fw_size; /* bytes */ @@ -70,21 +70,21 @@ struct intel_dmc { }; /* Note: This may be NULL. */ -static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915) +static struct intel_dmc *display_to_dmc(struct intel_display *display) { - return i915->display.dmc.dmc; + return display->dmc.dmc; } -static const char *dmc_firmware_param(struct drm_i915_private *i915) +static const char *dmc_firmware_param(struct intel_display *display) { - const char *p = i915->display.params.dmc_firmware_path; + const char *p = display->params.dmc_firmware_path; return p && *p ? p : NULL; } -static bool dmc_firmware_param_disabled(struct drm_i915_private *i915) +static bool dmc_firmware_param_disabled(struct intel_display *display) { - const char *p = dmc_firmware_param(i915); + const char *p = dmc_firmware_param(display); /* Magic path to indicate disabled */ return p && !strcmp(p, "/dev/null"); @@ -162,18 +162,19 @@ MODULE_FIRMWARE(SKL_DMC_PATH); #define BXT_DMC_MAX_FW_SIZE 0x3000 MODULE_FIRMWARE(BXT_DMC_PATH); -static const char *dmc_firmware_default(struct drm_i915_private *i915, u32 *size) +static const char *dmc_firmware_default(struct intel_display *display, u32 *size) { + struct drm_i915_private *i915 = to_i915(display->drm); const char *fw_path = NULL; u32 max_fw_size = 0; - if (DISPLAY_VER_FULL(i915) == IP_VER(20, 0)) { + if (DISPLAY_VER_FULL(display) == IP_VER(20, 0)) { fw_path = XE2LPD_DMC_PATH; max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; - } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) { + } else if (DISPLAY_VER_FULL(display) == IP_VER(14, 1)) { fw_path = BMG_DMC_PATH; max_fw_size = XELPDP_DMC_MAX_FW_SIZE; - } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) { + } else if (DISPLAY_VER_FULL(display) == IP_VER(14, 0)) { fw_path = MTL_DMC_PATH; max_fw_size = XELPDP_DMC_MAX_FW_SIZE; } else if (IS_DG2(i915)) { @@ -194,7 +195,7 @@ static const char *dmc_firmware_default(struct drm_i915_private *i915, u32 *size } else if (IS_TIGERLAKE(i915)) { fw_path = TGL_DMC_PATH; max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; - } else if (DISPLAY_VER(i915) == 11) { + } else if (DISPLAY_VER(display) == 11) { fw_path = ICL_DMC_PATH; max_fw_size = ICL_DMC_MAX_FW_SIZE; } else if (IS_GEMINILAKE(i915)) { @@ -375,70 +376,70 @@ static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; } -static bool has_dmc_id_fw(struct drm_i915_private *i915, enum intel_dmc_id dmc_id) +static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id) { - struct intel_dmc *dmc = i915_to_dmc(i915); + struct intel_dmc *dmc = display_to_dmc(display); return dmc && dmc->dmc_info[dmc_id].payload; } -bool intel_dmc_has_payload(struct drm_i915_private *i915) +bool intel_dmc_has_payload(struct intel_display *display) { - return has_dmc_id_fw(i915, DMC_FW_MAIN); + return has_dmc_id_fw(display, DMC_FW_MAIN); } static const struct stepping_info * -intel_get_stepping_info(struct drm_i915_private *i915, +intel_get_stepping_info(struct intel_display *display, struct stepping_info *si) { - const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(i915)); + const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display)); si->stepping = step_name[0]; si->substepping = step_name[1]; return si; } -static void gen9_set_dc_state_debugmask(struct drm_i915_private *i915) +static void gen9_set_dc_state_debugmask(struct intel_display *display) { /* The below bit doesn't need to be cleared ever afterwards */ - intel_de_rmw(i915, DC_STATE_DEBUG, 0, + intel_de_rmw(display, DC_STATE_DEBUG, 0, DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); - intel_de_posting_read(i915, DC_STATE_DEBUG); + intel_de_posting_read(display, DC_STATE_DEBUG); } -static void disable_event_handler(struct drm_i915_private *i915, +static void disable_event_handler(struct intel_display *display, i915_reg_t ctl_reg, i915_reg_t htp_reg) { - intel_de_write(i915, ctl_reg, + intel_de_write(display, ctl_reg, REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, DMC_EVT_CTL_TYPE_EDGE_0_1) | REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, DMC_EVT_CTL_EVENT_ID_FALSE)); - intel_de_write(i915, htp_reg, 0); + intel_de_write(display, htp_reg, 0); } -static void disable_all_event_handlers(struct drm_i915_private *i915) +static void disable_all_event_handlers(struct intel_display *display) { enum intel_dmc_id dmc_id; /* TODO: disable the event handlers on pre-GEN12 platforms as well */ - if (DISPLAY_VER(i915) < 12) + if (DISPLAY_VER(display) < 12) return; for_each_dmc_id(dmc_id) { int handler; - if (!has_dmc_id_fw(i915, dmc_id)) + if (!has_dmc_id_fw(display, dmc_id)) continue; for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) - disable_event_handler(i915, - DMC_EVT_CTL(i915, dmc_id, handler), - DMC_EVT_HTP(i915, dmc_id, handler)); + disable_event_handler(display, + DMC_EVT_CTL(display, dmc_id, handler), + DMC_EVT_HTP(display, dmc_id, handler)); } } -static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) +static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable) { enum pipe pipe; @@ -451,84 +452,86 @@ static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool ena */ if (enable) for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) - intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), + intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), 0, PIPEDMC_GATING_DIS); else for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) - intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), + intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), PIPEDMC_GATING_DIS, 0); } -static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915) +static void mtl_pipedmc_clock_gating_wa(struct intel_display *display) { /* * Wa_16015201720 * The WA requires clock gating to be disabled all the time * for pipe A and B. */ - intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, + intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B); } -static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) +static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable) { - if (DISPLAY_VER(i915) >= 14 && enable) - mtl_pipedmc_clock_gating_wa(i915); - else if (DISPLAY_VER(i915) == 13) - adlp_pipedmc_clock_gating_wa(i915, enable); + if (DISPLAY_VER(display) >= 14 && enable) + mtl_pipedmc_clock_gating_wa(display); + else if (DISPLAY_VER(display) == 13) + adlp_pipedmc_clock_gating_wa(display, enable); } -void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe) +void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe) { enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); - if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id)) + if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) return; - if (DISPLAY_VER(i915) >= 14) - intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); + if (DISPLAY_VER(display) >= 14) + intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); else - intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); + intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); } -void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe) +void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe) { enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); - if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id)) + if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) return; - if (DISPLAY_VER(i915) >= 14) - intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); + if (DISPLAY_VER(display) >= 14) + intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); else - intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); + intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); } -static bool is_dmc_evt_ctl_reg(struct drm_i915_private *i915, +static bool is_dmc_evt_ctl_reg(struct intel_display *display, enum intel_dmc_id dmc_id, i915_reg_t reg) { u32 offset = i915_mmio_reg_offset(reg); - u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, 0)); - u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); + u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); + u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); return offset >= start && offset < end; } -static bool is_dmc_evt_htp_reg(struct drm_i915_private *i915, +static bool is_dmc_evt_htp_reg(struct intel_display *display, enum intel_dmc_id dmc_id, i915_reg_t reg) { u32 offset = i915_mmio_reg_offset(reg); - u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, 0)); - u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); + u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); + u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); return offset >= start && offset < end; } -static bool disable_dmc_evt(struct drm_i915_private *i915, +static bool disable_dmc_evt(struct intel_display *display, enum intel_dmc_id dmc_id, i915_reg_t reg, u32 data) { - if (!is_dmc_evt_ctl_reg(i915, dmc_id, reg)) + struct drm_i915_private *i915 = to_i915(display->drm); + + if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) return false; /* keep all pipe DMC events disabled by default */ @@ -548,11 +551,11 @@ static bool disable_dmc_evt(struct drm_i915_private *i915, return false; } -static u32 dmc_mmiodata(struct drm_i915_private *i915, +static u32 dmc_mmiodata(struct intel_display *display, struct intel_dmc *dmc, enum intel_dmc_id dmc_id, int i) { - if (disable_dmc_evt(i915, dmc_id, + if (disable_dmc_evt(display, dmc_id, dmc->dmc_info[dmc_id].mmioaddr[i], dmc->dmc_info[dmc_id].mmiodata[i])) return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, @@ -565,25 +568,26 @@ static u32 dmc_mmiodata(struct drm_i915_private *i915, /** * intel_dmc_load_program() - write the firmware from memory to register. - * @i915: i915 drm device. + * @display: display instance * * DMC firmware is read from a .bin file and kept in internal memory one time. * Everytime display comes back from low power state this function is called to * copy the firmware from internal memory to registers. */ -void intel_dmc_load_program(struct drm_i915_private *i915) +void intel_dmc_load_program(struct intel_display *display) { - struct i915_power_domains *power_domains = &i915->display.power.domains; - struct intel_dmc *dmc = i915_to_dmc(i915); + struct drm_i915_private *i915 __maybe_unused = to_i915(display->drm); + struct i915_power_domains *power_domains = &display->power.domains; + struct intel_dmc *dmc = display_to_dmc(display); enum intel_dmc_id dmc_id; u32 i; - if (!intel_dmc_has_payload(i915)) + if (!intel_dmc_has_payload(display)) return; - pipedmc_clock_gating_wa(i915, true); + pipedmc_clock_gating_wa(display, true); - disable_all_event_handlers(i915); + disable_all_event_handlers(display); assert_rpm_wakelock_held(&i915->runtime_pm); @@ -591,7 +595,7 @@ void intel_dmc_load_program(struct drm_i915_private *i915) for_each_dmc_id(dmc_id) { for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { - intel_de_write_fw(i915, + intel_de_write_fw(display, DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), dmc->dmc_info[dmc_id].payload[i]); } @@ -601,48 +605,48 @@ void intel_dmc_load_program(struct drm_i915_private *i915) for_each_dmc_id(dmc_id) { for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { - intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i], - dmc_mmiodata(i915, dmc, dmc_id, i)); + intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i], + dmc_mmiodata(display, dmc, dmc_id, i)); } } power_domains->dc_state = 0; - gen9_set_dc_state_debugmask(i915); + gen9_set_dc_state_debugmask(display); - pipedmc_clock_gating_wa(i915, false); + pipedmc_clock_gating_wa(display, false); } /** * intel_dmc_disable_program() - disable the firmware - * @i915: i915 drm device + * @display: display instance * * Disable all event handlers in the firmware, making sure the firmware is * inactive after the display is uninitialized. */ -void intel_dmc_disable_program(struct drm_i915_private *i915) +void intel_dmc_disable_program(struct intel_display *display) { - if (!intel_dmc_has_payload(i915)) + if (!intel_dmc_has_payload(display)) return; - pipedmc_clock_gating_wa(i915, true); - disable_all_event_handlers(i915); - pipedmc_clock_gating_wa(i915, false); + pipedmc_clock_gating_wa(display, true); + disable_all_event_handlers(display); + pipedmc_clock_gating_wa(display, false); - intel_dmc_wl_disable(&i915->display); + intel_dmc_wl_disable(display); } -void assert_dmc_loaded(struct drm_i915_private *i915) +void assert_dmc_loaded(struct intel_display *display) { - struct intel_dmc *dmc = i915_to_dmc(i915); + struct intel_dmc *dmc = display_to_dmc(display); - drm_WARN_ONCE(&i915->drm, !dmc, "DMC not initialized\n"); - drm_WARN_ONCE(&i915->drm, dmc && - !intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), + drm_WARN_ONCE(display->drm, !dmc, "DMC not initialized\n"); + drm_WARN_ONCE(display->drm, dmc && + !intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), "DMC program storage start is NULL\n"); - drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE), + drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_SSP_BASE), "DMC SSP Base Not fine\n"); - drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL), + drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_HTP_SKL), "DMC HTP Not fine\n"); } @@ -673,7 +677,7 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc, const struct stepping_info *si, u8 package_ver) { - struct drm_i915_private *i915 = dmc->i915; + struct intel_display *display = dmc->display; enum intel_dmc_id dmc_id; unsigned int i; @@ -681,7 +685,7 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc, dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; if (!is_valid_dmc_id(dmc_id)) { - drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", dmc_id); + drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id); continue; } @@ -703,7 +707,7 @@ static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, const u32 *mmioaddr, u32 mmio_count, int header_ver, enum intel_dmc_id dmc_id) { - struct drm_i915_private *i915 = dmc->i915; + struct intel_display *display = dmc->display; u32 start_range, end_range; int i; @@ -713,14 +717,14 @@ static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, } else if (dmc_id == DMC_FW_MAIN) { start_range = TGL_MAIN_MMIO_START; end_range = TGL_MAIN_MMIO_END; - } else if (DISPLAY_VER(i915) >= 13) { + } else if (DISPLAY_VER(display) >= 13) { start_range = ADLP_PIPE_MMIO_START; end_range = ADLP_PIPE_MMIO_END; - } else if (DISPLAY_VER(i915) >= 12) { + } else if (DISPLAY_VER(display) >= 12) { start_range = TGL_PIPE_MMIO_START(dmc_id); end_range = TGL_PIPE_MMIO_END(dmc_id); } else { - drm_warn(&i915->drm, "Unknown mmio range for sanity check"); + drm_warn(display->drm, "Unknown mmio range for sanity check"); return false; } @@ -736,7 +740,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc, const struct intel_dmc_header_base *dmc_header, size_t rem_size, enum intel_dmc_id dmc_id) { - struct drm_i915_private *i915 = dmc->i915; + struct intel_display *display = dmc->display; struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; unsigned int header_len_bytes, dmc_header_size, payload_size, i; const u32 *mmioaddr, *mmiodata; @@ -784,39 +788,39 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc, start_mmioaddr = DMC_V1_MMIO_START_RANGE; dmc_header_size = sizeof(*v1); } else { - drm_err(&i915->drm, "Unknown DMC fw header version: %u\n", + drm_err(display->drm, "Unknown DMC fw header version: %u\n", dmc_header->header_ver); return 0; } if (header_len_bytes != dmc_header_size) { - drm_err(&i915->drm, "DMC firmware has wrong dmc header length " + drm_err(display->drm, "DMC firmware has wrong dmc header length " "(%u bytes)\n", header_len_bytes); return 0; } /* Cache the dmc header info. */ if (mmio_count > mmio_count_max) { - drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); + drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); return 0; } if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, dmc_header->header_ver, dmc_id)) { - drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n"); + drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n"); return 0; } - drm_dbg_kms(&i915->drm, "DMC %d:\n", dmc_id); + drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id); for (i = 0; i < mmio_count; i++) { dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); dmc_info->mmiodata[i] = mmiodata[i]; - drm_dbg_kms(&i915->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", + drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", i, mmioaddr[i], mmiodata[i], - is_dmc_evt_ctl_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : - is_dmc_evt_htp_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", - disable_dmc_evt(i915, dmc_id, dmc_info->mmioaddr[i], + is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : + is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", + disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i], dmc_info->mmiodata[i]) ? " (disabling)" : ""); } dmc_info->mmio_count = mmio_count; @@ -830,7 +834,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc, goto error_truncated; if (payload_size > dmc->max_fw_size) { - drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size); + drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size); return 0; } dmc_info->dmc_fw_size = dmc_header->fw_size; @@ -845,7 +849,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc, return header_len_bytes + payload_size; error_truncated: - drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); + drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); return 0; } @@ -855,7 +859,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc, const struct stepping_info *si, size_t rem_size) { - struct drm_i915_private *i915 = dmc->i915; + struct intel_display *display = dmc->display; u32 package_size = sizeof(struct intel_package_header); u32 num_entries, max_entries; const struct intel_fw_info *fw_info; @@ -868,7 +872,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc, } else if (package_header->header_ver == 2) { max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; } else { - drm_err(&i915->drm, "DMC firmware has unknown header version %u\n", + drm_err(display->drm, "DMC firmware has unknown header version %u\n", package_header->header_ver); return 0; } @@ -882,7 +886,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc, goto error_truncated; if (package_header->header_len * 4 != package_size) { - drm_err(&i915->drm, "DMC firmware has wrong package header length " + drm_err(display->drm, "DMC firmware has wrong package header length " "(%u bytes)\n", package_size); return 0; } @@ -900,7 +904,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc, return package_size; error_truncated: - drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); + drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); return 0; } @@ -909,16 +913,16 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc, struct intel_css_header *css_header, size_t rem_size) { - struct drm_i915_private *i915 = dmc->i915; + struct intel_display *display = dmc->display; if (rem_size < sizeof(struct intel_css_header)) { - drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); + drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); return 0; } if (sizeof(struct intel_css_header) != (css_header->header_len * 4)) { - drm_err(&i915->drm, "DMC firmware has wrong CSS header length " + drm_err(display->drm, "DMC firmware has wrong CSS header length " "(%u bytes)\n", (css_header->header_len * 4)); return 0; @@ -931,12 +935,12 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc, static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) { - struct drm_i915_private *i915 = dmc->i915; + struct intel_display *display = dmc->display; struct intel_css_header *css_header; struct intel_package_header *package_header; struct intel_dmc_header_base *dmc_header; struct stepping_info display_info = { '*', '*'}; - const struct stepping_info *si = intel_get_stepping_info(i915, &display_info); + const struct stepping_info *si = intel_get_stepping_info(display, &display_info); enum intel_dmc_id dmc_id; u32 readcount = 0; u32 r, offset; @@ -966,7 +970,7 @@ static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; if (offset > fw->size) { - drm_err(&i915->drm, "Reading beyond the fw_size\n"); + drm_err(display->drm, "Reading beyond the fw_size\n"); continue; } @@ -974,30 +978,35 @@ static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); } - if (!intel_dmc_has_payload(i915)) { - drm_err(&i915->drm, "DMC firmware main program not found\n"); + if (!intel_dmc_has_payload(display)) { + drm_err(display->drm, "DMC firmware main program not found\n"); return -ENOENT; } return 0; } -static void intel_dmc_runtime_pm_get(struct drm_i915_private *i915) +static void intel_dmc_runtime_pm_get(struct intel_display *display) { - drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref); - i915->display.dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); + struct drm_i915_private *i915 = to_i915(display->drm); + + drm_WARN_ON(display->drm, display->dmc.wakeref); + display->dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); } -static void intel_dmc_runtime_pm_put(struct drm_i915_private *i915) +static void intel_dmc_runtime_pm_put(struct intel_display *display) { + struct drm_i915_private *i915 = to_i915(display->drm); intel_wakeref_t wakeref __maybe_unused = - fetch_and_zero(&i915->display.dmc.wakeref); + fetch_and_zero(&display->dmc.wakeref); intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); } -static const char *dmc_fallback_path(struct drm_i915_private *i915) +static const char *dmc_fallback_path(struct intel_display *display) { + struct drm_i915_private *i915 = to_i915(display->drm); + if (IS_ALDERLAKE_P(i915)) return ADLP_DMC_FALLBACK_PATH; @@ -1007,45 +1016,45 @@ static const char *dmc_fallback_path(struct drm_i915_private *i915) static void dmc_load_work_fn(struct work_struct *work) { struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); - struct drm_i915_private *i915 = dmc->i915; + struct intel_display *display = dmc->display; const struct firmware *fw = NULL; const char *fallback_path; int err; - err = request_firmware(&fw, dmc->fw_path, i915->drm.dev); + err = request_firmware(&fw, dmc->fw_path, display->drm->dev); - if (err == -ENOENT && !dmc_firmware_param(i915)) { - fallback_path = dmc_fallback_path(i915); + if (err == -ENOENT && !dmc_firmware_param(display)) { + fallback_path = dmc_fallback_path(display); if (fallback_path) { - drm_dbg_kms(&i915->drm, "%s not found, falling back to %s\n", + drm_dbg_kms(display->drm, "%s not found, falling back to %s\n", dmc->fw_path, fallback_path); - err = request_firmware(&fw, fallback_path, i915->drm.dev); + err = request_firmware(&fw, fallback_path, display->drm->dev); if (err == 0) dmc->fw_path = fallback_path; } } if (err) { - drm_notice(&i915->drm, + drm_notice(display->drm, "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n", dmc->fw_path, ERR_PTR(err)); - drm_notice(&i915->drm, "DMC firmware homepage: %s", + drm_notice(display->drm, "DMC firmware homepage: %s", INTEL_DMC_FIRMWARE_URL); return; } err = parse_dmc_fw(dmc, fw); if (err) { - drm_notice(&i915->drm, + drm_notice(display->drm, "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n", dmc->fw_path, ERR_PTR(err)); goto out; } - intel_dmc_load_program(i915); - intel_dmc_runtime_pm_put(i915); + intel_dmc_load_program(display); + intel_dmc_runtime_pm_put(display); - drm_info(&i915->drm, "Finished loading DMC firmware %s (v%u.%u)\n", + drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n", dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), DMC_VERSION_MINOR(dmc->version)); @@ -1055,16 +1064,17 @@ static void dmc_load_work_fn(struct work_struct *work) /** * intel_dmc_init() - initialize the firmware loading. - * @i915: i915 drm device. + * @display: display instance * * This function is called at the time of loading the display driver to read * firmware from a .bin file and copied into a internal memory. */ -void intel_dmc_init(struct drm_i915_private *i915) +void intel_dmc_init(struct intel_display *display) { + struct drm_i915_private *i915 = to_i915(display->drm); struct intel_dmc *dmc; - if (!HAS_DMC(i915)) + if (!HAS_DMC(display)) return; /* @@ -1075,35 +1085,35 @@ void intel_dmc_init(struct drm_i915_private *i915) * suspend as runtime suspend *requires* a working DMC for whatever * reason. */ - intel_dmc_runtime_pm_get(i915); + intel_dmc_runtime_pm_get(display); dmc = kzalloc(sizeof(*dmc), GFP_KERNEL); if (!dmc) return; - dmc->i915 = i915; + dmc->display = display; INIT_WORK(&dmc->work, dmc_load_work_fn); - dmc->fw_path = dmc_firmware_default(i915, &dmc->max_fw_size); + dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size); - if (dmc_firmware_param_disabled(i915)) { - drm_info(&i915->drm, "Disabling DMC firmware and runtime PM\n"); + if (dmc_firmware_param_disabled(display)) { + drm_info(display->drm, "Disabling DMC firmware and runtime PM\n"); goto out; } - if (dmc_firmware_param(i915)) - dmc->fw_path = dmc_firmware_param(i915); + if (dmc_firmware_param(display)) + dmc->fw_path = dmc_firmware_param(display); if (!dmc->fw_path) { - drm_dbg_kms(&i915->drm, + drm_dbg_kms(display->drm, "No known DMC firmware for platform, disabling runtime PM\n"); goto out; } - i915->display.dmc.dmc = dmc; + display->dmc.dmc = dmc; - drm_dbg_kms(&i915->drm, "Loading %s\n", dmc->fw_path); + drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path); queue_work(i915->unordered_wq, &dmc->work); return; @@ -1114,87 +1124,87 @@ void intel_dmc_init(struct drm_i915_private *i915) /** * intel_dmc_suspend() - prepare DMC firmware before system suspend - * @i915: i915 drm device + * @display: display instance * * Prepare the DMC firmware before entering system suspend. This includes * flushing pending work items and releasing any resources acquired during * init. */ -void intel_dmc_suspend(struct drm_i915_private *i915) +void intel_dmc_suspend(struct intel_display *display) { - struct intel_dmc *dmc = i915_to_dmc(i915); + struct intel_dmc *dmc = display_to_dmc(display); - if (!HAS_DMC(i915)) + if (!HAS_DMC(display)) return; if (dmc) flush_work(&dmc->work); - intel_dmc_wl_disable(&i915->display); + intel_dmc_wl_disable(display); /* Drop the reference held in case DMC isn't loaded. */ - if (!intel_dmc_has_payload(i915)) - intel_dmc_runtime_pm_put(i915); + if (!intel_dmc_has_payload(display)) + intel_dmc_runtime_pm_put(display); } /** * intel_dmc_resume() - init DMC firmware during system resume - * @i915: i915 drm device + * @display: display instance * * Reinitialize the DMC firmware during system resume, reacquiring any * resources released in intel_dmc_suspend(). */ -void intel_dmc_resume(struct drm_i915_private *i915) +void intel_dmc_resume(struct intel_display *display) { - if (!HAS_DMC(i915)) + if (!HAS_DMC(display)) return; /* * Reacquire the reference to keep RPM disabled in case DMC isn't * loaded. */ - if (!intel_dmc_has_payload(i915)) - intel_dmc_runtime_pm_get(i915); + if (!intel_dmc_has_payload(display)) + intel_dmc_runtime_pm_get(display); } /** * intel_dmc_fini() - unload the DMC firmware. - * @i915: i915 drm device. + * @display: display instance * * Firmmware unloading includes freeing the internal memory and reset the * firmware loading status. */ -void intel_dmc_fini(struct drm_i915_private *i915) +void intel_dmc_fini(struct intel_display *display) { - struct intel_dmc *dmc = i915_to_dmc(i915); + struct intel_dmc *dmc = display_to_dmc(display); enum intel_dmc_id dmc_id; - if (!HAS_DMC(i915)) + if (!HAS_DMC(display)) return; - intel_dmc_suspend(i915); - drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref); + intel_dmc_suspend(display); + drm_WARN_ON(display->drm, display->dmc.wakeref); if (dmc) { for_each_dmc_id(dmc_id) kfree(dmc->dmc_info[dmc_id].payload); kfree(dmc); - i915->display.dmc.dmc = NULL; + display->dmc.dmc = NULL; } } void intel_dmc_print_error_state(struct drm_printer *p, - struct drm_i915_private *i915) + struct intel_display *display) { - struct intel_dmc *dmc = i915_to_dmc(i915); + struct intel_dmc *dmc = display_to_dmc(display); - if (!HAS_DMC(i915)) + if (!HAS_DMC(display)) return; drm_printf(p, "DMC initialized: %s\n", str_yes_no(dmc)); drm_printf(p, "DMC loaded: %s\n", - str_yes_no(intel_dmc_has_payload(i915))); + str_yes_no(intel_dmc_has_payload(display))); if (dmc) drm_printf(p, "DMC fw version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), @@ -1203,40 +1213,41 @@ void intel_dmc_print_error_state(struct drm_printer *p, static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) { - struct drm_i915_private *i915 = m->private; - struct intel_dmc *dmc = i915_to_dmc(i915); + struct intel_display *display = m->private; + struct drm_i915_private *i915 = to_i915(display->drm); + struct intel_dmc *dmc = display_to_dmc(display); intel_wakeref_t wakeref; i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; - if (!HAS_DMC(i915)) + if (!HAS_DMC(display)) return -ENODEV; wakeref = intel_runtime_pm_get(&i915->runtime_pm); seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); seq_printf(m, "fw loaded: %s\n", - str_yes_no(intel_dmc_has_payload(i915))); + str_yes_no(intel_dmc_has_payload(display))); seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); seq_printf(m, "Pipe A fw needed: %s\n", - str_yes_no(DISPLAY_VER(i915) >= 12)); + str_yes_no(DISPLAY_VER(display) >= 12)); seq_printf(m, "Pipe A fw loaded: %s\n", - str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEA))); + str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA))); seq_printf(m, "Pipe B fw needed: %s\n", str_yes_no(IS_ALDERLAKE_P(i915) || - DISPLAY_VER(i915) >= 14)); + DISPLAY_VER(display) >= 14)); seq_printf(m, "Pipe B fw loaded: %s\n", - str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEB))); + str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB))); - if (!intel_dmc_has_payload(i915)) + if (!intel_dmc_has_payload(display)) goto out; seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), DMC_VERSION_MINOR(dmc->version)); - if (DISPLAY_VER(i915) >= 12) { + if (DISPLAY_VER(display) >= 12) { i915_reg_t dc3co_reg; - if (IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) { + if (IS_DGFX(i915) || DISPLAY_VER(display) >= 14) { dc3co_reg = DG1_DMC_DEBUG3; dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; } else { @@ -1246,7 +1257,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) } seq_printf(m, "DC3CO count: %d\n", - intel_de_read(i915, dc3co_reg)); + intel_de_read(display, dc3co_reg)); } else { dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT : SKL_DMC_DC3_DC5_COUNT; @@ -1254,18 +1265,18 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) dc6_reg = SKL_DMC_DC5_DC6_COUNT; } - seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg)); + seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg)); if (i915_mmio_reg_valid(dc6_reg)) seq_printf(m, "DC5 -> DC6 count: %d\n", - intel_de_read(i915, dc6_reg)); + intel_de_read(display, dc6_reg)); seq_printf(m, "program base: 0x%08x\n", - intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); + intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); out: seq_printf(m, "ssp base: 0x%08x\n", - intel_de_read(i915, DMC_SSP_BASE)); - seq_printf(m, "htp: 0x%08x\n", intel_de_read(i915, DMC_HTP_SKL)); + intel_de_read(display, DMC_SSP_BASE)); + seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL)); intel_runtime_pm_put(&i915->runtime_pm, wakeref); @@ -1274,10 +1285,10 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); -void intel_dmc_debugfs_register(struct drm_i915_private *i915) +void intel_dmc_debugfs_register(struct intel_display *display) { - struct drm_minor *minor = i915->drm.primary; + struct drm_minor *minor = display->drm->primary; debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root, - i915, &intel_dmc_debugfs_status_fops); + display, &intel_dmc_debugfs_status_fops); } diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h index 54cff6002e31..2ead2ec1f820 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.h +++ b/drivers/gpu/drm/i915/display/intel_dmc.h @@ -9,22 +9,22 @@ #include <linux/types.h> enum pipe; -struct drm_i915_private; struct drm_printer; +struct intel_display; -void intel_dmc_init(struct drm_i915_private *i915); -void intel_dmc_load_program(struct drm_i915_private *i915); -void intel_dmc_disable_program(struct drm_i915_private *i915); -void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe); -void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe); -void intel_dmc_fini(struct drm_i915_private *i915); -void intel_dmc_suspend(struct drm_i915_private *i915); -void intel_dmc_resume(struct drm_i915_private *i915); -bool intel_dmc_has_payload(struct drm_i915_private *i915); -void intel_dmc_debugfs_register(struct drm_i915_private *i915); +void intel_dmc_init(struct intel_display *display); +void intel_dmc_load_program(struct intel_display *display); +void intel_dmc_disable_program(struct intel_display *display); +void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe); +void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe); +void intel_dmc_fini(struct intel_display *display); +void intel_dmc_suspend(struct intel_display *display); +void intel_dmc_resume(struct intel_display *display); +bool intel_dmc_has_payload(struct intel_display *display); +void intel_dmc_debugfs_register(struct intel_display *display); void intel_dmc_print_error_state(struct drm_printer *p, - struct drm_i915_private *i915); + struct intel_display *display); -void assert_dmc_loaded(struct drm_i915_private *i915); +void assert_dmc_loaded(struct intel_display *display); #endif /* __INTEL_DMC_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c index d9864b9cc429..5634ff07269d 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c @@ -109,10 +109,8 @@ static bool intel_dmc_wl_check_range(u32 address) static bool __intel_dmc_wl_supported(struct intel_display *display) { - struct drm_i915_private *i915 = to_i915(display->drm); - if (DISPLAY_VER(display) < 20 || - !intel_dmc_has_payload(i915) || + !intel_dmc_has_payload(display) || !display->params.enable_dmc_wl) return false; diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index 1f57549fce00..bcc5cf137a88 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -960,6 +960,7 @@ static void intel_early_display_was(struct drm_i915_private *i915) void intel_modeset_setup_hw_state(struct drm_i915_private *i915, struct drm_modeset_acquire_ctx *ctx) { + struct intel_display *display = &i915->display; struct intel_encoder *encoder; struct intel_crtc *crtc; intel_wakeref_t wakeref; @@ -987,7 +988,7 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915, drm_crtc_vblank_reset(&crtc->base); if (crtc_state->hw.active) { - intel_dmc_enable_pipe(i915, crtc->pipe); + intel_dmc_enable_pipe(display, crtc->pipe); intel_crtc_vblank_on(crtc_state); } } diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index fe905d65ddf7..943e938040c0 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -959,7 +959,7 @@ void i915_driver_shutdown(struct drm_i915_private *i915) intel_encoder_suspend_all(&i915->display); intel_encoder_shutdown_all(&i915->display); - intel_dmc_suspend(i915); + intel_dmc_suspend(&i915->display); i915_gem_suspend(i915); @@ -1054,7 +1054,7 @@ static int i915_drm_suspend(struct drm_device *dev) dev_priv->suspend_count++; - intel_dmc_suspend(dev_priv); + intel_dmc_suspend(display); enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); @@ -1164,7 +1164,7 @@ static int i915_drm_resume(struct drm_device *dev) /* Must be called after GGTT is resumed. */ intel_dpt_resume(dev_priv); - intel_dmc_resume(dev_priv); + intel_dmc_resume(display); i915_restore_display(dev_priv); intel_pps_unlock_regs_wa(display); diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 6469b9bcf2ec..b455fa441609 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -875,7 +875,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, err_printf(m, "IOMMU enabled?: %d\n", error->iommu); - intel_dmc_print_error_state(&p, m->i915); + intel_dmc_print_error_state(&p, &m->i915->display); err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock)); err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended)); diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c index c0e9aa7a274f..10d707e05d6e 100644 --- a/drivers/gpu/drm/xe/display/xe_display.c +++ b/drivers/gpu/drm/xe/display/xe_display.c @@ -353,7 +353,7 @@ void xe_display_pm_suspend(struct xe_device *xe, bool runtime) intel_opregion_suspend(display, s2idle ? PCI_D1 : PCI_D3cold); - intel_dmc_suspend(xe); + intel_dmc_suspend(display); } void xe_display_pm_suspend_late(struct xe_device *xe) @@ -395,7 +395,7 @@ void xe_display_pm_resume(struct xe_device *xe, bool runtime) if (!xe->info.probe_display) return; - intel_dmc_resume(xe); + intel_dmc_resume(display); if (has_display(xe)) drm_mode_config_reset(&xe->drm); -- 2.44.2 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH 6/6] drm/i915/dmc: Convert DMC code to intel_display 2024-09-06 14:33 ` [PATCH 6/6] drm/i915/dmc: Convert DMC " Ville Syrjala @ 2024-09-06 15:16 ` Rodrigo Vivi 0 siblings, 0 replies; 24+ messages in thread From: Rodrigo Vivi @ 2024-09-06 15:16 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx, intel-xe On Fri, Sep 06, 2024 at 05:33:06PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > struct intel_display will replace struct drm_i915_private as > the main thing for display code. Convert the DMC code to > use it (as much as possible at this stage). > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 7 +- > .../drm/i915/display/intel_display_debugfs.c | 2 +- > .../drm/i915/display/intel_display_driver.c | 6 +- > .../drm/i915/display/intel_display_power.c | 17 +- > .../i915/display/intel_display_power_well.c | 8 +- > drivers/gpu/drm/i915/display/intel_dmc.c | 391 +++++++++--------- > drivers/gpu/drm/i915/display/intel_dmc.h | 26 +- > drivers/gpu/drm/i915/display/intel_dmc_wl.c | 4 +- > .../drm/i915/display/intel_modeset_setup.c | 3 +- > drivers/gpu/drm/i915/i915_driver.c | 6 +- > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- > drivers/gpu/drm/xe/display/xe_display.c | 4 +- > 12 files changed, 243 insertions(+), 233 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 0ec78b06ca80..fdf244a32b24 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -1690,7 +1690,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, > > for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc, > intel_crtc_joined_pipe_mask(new_crtc_state)) > - intel_dmc_enable_pipe(dev_priv, pipe_crtc->pipe); > + intel_dmc_enable_pipe(display, pipe_crtc->pipe); > > intel_encoders_pre_pll_enable(state, crtc); > > @@ -1843,9 +1843,10 @@ static void ilk_crtc_disable(struct intel_atomic_state *state, > static void hsw_crtc_disable(struct intel_atomic_state *state, > struct intel_crtc *crtc) > { > + struct intel_display *display = to_intel_display(state); > + struct drm_i915_private *i915 = to_i915(display->drm); > const struct intel_crtc_state *old_crtc_state = > intel_atomic_get_old_crtc_state(state, crtc); > - struct drm_i915_private *i915 = to_i915(crtc->base.dev); > struct intel_crtc *pipe_crtc; > > /* > @@ -1867,7 +1868,7 @@ static void hsw_crtc_disable(struct intel_atomic_state *state, > > for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, > intel_crtc_joined_pipe_mask(old_crtc_state)) > - intel_dmc_disable_pipe(i915, pipe_crtc->pipe); > + intel_dmc_disable_pipe(display, pipe_crtc->pipe); > } > > static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > index c1bef34d1ffd..b75361e95e97 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c > @@ -1069,7 +1069,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915) > > intel_bios_debugfs_register(display); > intel_cdclk_debugfs_register(display); > - intel_dmc_debugfs_register(i915); > + intel_dmc_debugfs_register(display); > intel_fbc_debugfs_register(display); > intel_hpd_debugfs_register(i915); > intel_opregion_debugfs_register(display); > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c > index f8da72af2107..c106fb2dd20b 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c > @@ -237,7 +237,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915) > if (!HAS_DISPLAY(i915)) > return 0; > > - intel_dmc_init(i915); > + intel_dmc_init(display); > > i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0); > i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI | > @@ -272,7 +272,7 @@ int intel_display_driver_probe_noirq(struct drm_i915_private *i915) > return 0; > > cleanup_vga_client_pw_domain_dmc: > - intel_dmc_fini(i915); > + intel_dmc_fini(display); > intel_power_domains_driver_remove(i915); > cleanup_vga: > intel_vga_unregister(display); > @@ -621,7 +621,7 @@ void intel_display_driver_remove_nogem(struct drm_i915_private *i915) > { > struct intel_display *display = &i915->display; > > - intel_dmc_fini(i915); > + intel_dmc_fini(display); > > intel_power_domains_driver_remove(i915); > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 86ac494ed33b..ecabb674644b 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -1445,7 +1445,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, > gen9_dbuf_enable(dev_priv); > > if (resume) > - intel_dmc_load_program(dev_priv); > + intel_dmc_load_program(display); > } > > static void skl_display_core_uninit(struct drm_i915_private *dev_priv) > @@ -1515,7 +1515,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume > gen9_dbuf_enable(dev_priv); > > if (resume) > - intel_dmc_load_program(dev_priv); > + intel_dmc_load_program(display); > } > > static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) > @@ -1687,7 +1687,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, > intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); > > if (resume) > - intel_dmc_load_program(dev_priv); > + intel_dmc_load_program(display); > > /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */ > if (IS_DISPLAY_VER_FULL(dev_priv, IP_VER(12, 0), IP_VER(13, 0))) > @@ -1718,7 +1718,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) > return; > > gen9_disable_dc_states(display); > - intel_dmc_disable_program(dev_priv); > + intel_dmc_disable_program(display); > > /* 1. Disable all display engine functions -> aready done */ > > @@ -2073,7 +2073,8 @@ void intel_power_domains_disable(struct drm_i915_private *i915) > */ > void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle) > { > - struct i915_power_domains *power_domains = &i915->display.power.domains; > + struct intel_display *display = &i915->display; > + struct i915_power_domains *power_domains = &display->power.domains; > intel_wakeref_t wakeref __maybe_unused = > fetch_and_zero(&power_domains->init_wakeref); > > @@ -2087,7 +2088,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915, bool s2idle) > * that would be blocked if the firmware was inactive. > */ > if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC9) && s2idle && > - intel_dmc_has_payload(i915)) { > + intel_dmc_has_payload(display)) { > intel_display_power_flush_work(i915); > intel_power_domains_verify_state(i915); > return; > @@ -2286,7 +2287,7 @@ void intel_display_power_resume(struct drm_i915_private *i915) > if (DISPLAY_VER(i915) >= 11) { > bxt_disable_dc9(display); > icl_display_core_init(i915, true); > - if (intel_dmc_has_payload(i915)) { > + if (intel_dmc_has_payload(display)) { > if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC6) > skl_enable_dc6(display); > else if (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5) > @@ -2295,7 +2296,7 @@ void intel_display_power_resume(struct drm_i915_private *i915) > } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { > bxt_disable_dc9(display); > bxt_display_core_init(i915, true); > - if (intel_dmc_has_payload(i915) && > + if (intel_dmc_has_payload(display) && > (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) > gen9_enable_dc5(display); > } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c > index 9f275a6674a1..1898aff50ac4 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c > @@ -817,7 +817,7 @@ static void assert_can_enable_dc5(struct intel_display *display) > "DC5 already programmed to be enabled.\n"); > assert_rpm_wakelock_held(&dev_priv->runtime_pm); > > - assert_dmc_loaded(dev_priv); > + assert_dmc_loaded(display); > } > > void gen9_enable_dc5(struct intel_display *display) > @@ -840,8 +840,6 @@ void gen9_enable_dc5(struct intel_display *display) > > static void assert_can_enable_dc6(struct intel_display *display) > { > - struct drm_i915_private *dev_priv = to_i915(display->drm); > - > drm_WARN_ONCE(display->drm, > (intel_de_read(display, UTIL_PIN_CTL) & > (UTIL_PIN_ENABLE | UTIL_PIN_MODE_MASK)) == > @@ -852,7 +850,7 @@ static void assert_can_enable_dc6(struct intel_display *display) > DC_STATE_EN_UPTO_DC6), > "DC6 already programmed to be enabled.\n"); > > - assert_dmc_loaded(dev_priv); > + assert_dmc_loaded(display); > } > > void skl_enable_dc6(struct intel_display *display) > @@ -1031,7 +1029,7 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, > struct intel_display *display = &dev_priv->display; > struct i915_power_domains *power_domains = &display->power.domains; > > - if (!intel_dmc_has_payload(dev_priv)) > + if (!intel_dmc_has_payload(display)) > return; > > switch (power_domains->target_dc_state) { > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c > index 7c756d5ba2a2..bbac6bfd1752 100644 > --- a/drivers/gpu/drm/i915/display/intel_dmc.c > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c > @@ -52,7 +52,7 @@ enum intel_dmc_id { > }; > > struct intel_dmc { > - struct drm_i915_private *i915; > + struct intel_display *display; > struct work_struct work; > const char *fw_path; > u32 max_fw_size; /* bytes */ > @@ -70,21 +70,21 @@ struct intel_dmc { > }; > > /* Note: This may be NULL. */ > -static struct intel_dmc *i915_to_dmc(struct drm_i915_private *i915) > +static struct intel_dmc *display_to_dmc(struct intel_display *display) > { > - return i915->display.dmc.dmc; > + return display->dmc.dmc; > } > > -static const char *dmc_firmware_param(struct drm_i915_private *i915) > +static const char *dmc_firmware_param(struct intel_display *display) > { > - const char *p = i915->display.params.dmc_firmware_path; > + const char *p = display->params.dmc_firmware_path; > > return p && *p ? p : NULL; > } > > -static bool dmc_firmware_param_disabled(struct drm_i915_private *i915) > +static bool dmc_firmware_param_disabled(struct intel_display *display) > { > - const char *p = dmc_firmware_param(i915); > + const char *p = dmc_firmware_param(display); > > /* Magic path to indicate disabled */ > return p && !strcmp(p, "/dev/null"); > @@ -162,18 +162,19 @@ MODULE_FIRMWARE(SKL_DMC_PATH); > #define BXT_DMC_MAX_FW_SIZE 0x3000 > MODULE_FIRMWARE(BXT_DMC_PATH); > > -static const char *dmc_firmware_default(struct drm_i915_private *i915, u32 *size) > +static const char *dmc_firmware_default(struct intel_display *display, u32 *size) > { > + struct drm_i915_private *i915 = to_i915(display->drm); > const char *fw_path = NULL; > u32 max_fw_size = 0; > > - if (DISPLAY_VER_FULL(i915) == IP_VER(20, 0)) { > + if (DISPLAY_VER_FULL(display) == IP_VER(20, 0)) { > fw_path = XE2LPD_DMC_PATH; > max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; > - } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) { > + } else if (DISPLAY_VER_FULL(display) == IP_VER(14, 1)) { > fw_path = BMG_DMC_PATH; > max_fw_size = XELPDP_DMC_MAX_FW_SIZE; > - } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) { > + } else if (DISPLAY_VER_FULL(display) == IP_VER(14, 0)) { > fw_path = MTL_DMC_PATH; > max_fw_size = XELPDP_DMC_MAX_FW_SIZE; > } else if (IS_DG2(i915)) { > @@ -194,7 +195,7 @@ static const char *dmc_firmware_default(struct drm_i915_private *i915, u32 *size > } else if (IS_TIGERLAKE(i915)) { > fw_path = TGL_DMC_PATH; > max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; > - } else if (DISPLAY_VER(i915) == 11) { > + } else if (DISPLAY_VER(display) == 11) { > fw_path = ICL_DMC_PATH; > max_fw_size = ICL_DMC_MAX_FW_SIZE; > } else if (IS_GEMINILAKE(i915)) { > @@ -375,70 +376,70 @@ static bool is_valid_dmc_id(enum intel_dmc_id dmc_id) > return dmc_id >= DMC_FW_MAIN && dmc_id < DMC_FW_MAX; > } > > -static bool has_dmc_id_fw(struct drm_i915_private *i915, enum intel_dmc_id dmc_id) > +static bool has_dmc_id_fw(struct intel_display *display, enum intel_dmc_id dmc_id) > { > - struct intel_dmc *dmc = i915_to_dmc(i915); > + struct intel_dmc *dmc = display_to_dmc(display); > > return dmc && dmc->dmc_info[dmc_id].payload; > } > > -bool intel_dmc_has_payload(struct drm_i915_private *i915) > +bool intel_dmc_has_payload(struct intel_display *display) > { > - return has_dmc_id_fw(i915, DMC_FW_MAIN); > + return has_dmc_id_fw(display, DMC_FW_MAIN); > } > > static const struct stepping_info * > -intel_get_stepping_info(struct drm_i915_private *i915, > +intel_get_stepping_info(struct intel_display *display, > struct stepping_info *si) > { > - const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(i915)); > + const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(display)); > > si->stepping = step_name[0]; > si->substepping = step_name[1]; > return si; > } > > -static void gen9_set_dc_state_debugmask(struct drm_i915_private *i915) > +static void gen9_set_dc_state_debugmask(struct intel_display *display) > { > /* The below bit doesn't need to be cleared ever afterwards */ > - intel_de_rmw(i915, DC_STATE_DEBUG, 0, > + intel_de_rmw(display, DC_STATE_DEBUG, 0, > DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); > - intel_de_posting_read(i915, DC_STATE_DEBUG); > + intel_de_posting_read(display, DC_STATE_DEBUG); > } > > -static void disable_event_handler(struct drm_i915_private *i915, > +static void disable_event_handler(struct intel_display *display, > i915_reg_t ctl_reg, i915_reg_t htp_reg) > { > - intel_de_write(i915, ctl_reg, > + intel_de_write(display, ctl_reg, > REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, > DMC_EVT_CTL_TYPE_EDGE_0_1) | > REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, > DMC_EVT_CTL_EVENT_ID_FALSE)); > - intel_de_write(i915, htp_reg, 0); > + intel_de_write(display, htp_reg, 0); > } > > -static void disable_all_event_handlers(struct drm_i915_private *i915) > +static void disable_all_event_handlers(struct intel_display *display) > { > enum intel_dmc_id dmc_id; > > /* TODO: disable the event handlers on pre-GEN12 platforms as well */ > - if (DISPLAY_VER(i915) < 12) > + if (DISPLAY_VER(display) < 12) > return; > > for_each_dmc_id(dmc_id) { > int handler; > > - if (!has_dmc_id_fw(i915, dmc_id)) > + if (!has_dmc_id_fw(display, dmc_id)) > continue; > > for (handler = 0; handler < DMC_EVENT_HANDLER_COUNT_GEN12; handler++) > - disable_event_handler(i915, > - DMC_EVT_CTL(i915, dmc_id, handler), > - DMC_EVT_HTP(i915, dmc_id, handler)); > + disable_event_handler(display, > + DMC_EVT_CTL(display, dmc_id, handler), > + DMC_EVT_HTP(display, dmc_id, handler)); > } > } > > -static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) > +static void adlp_pipedmc_clock_gating_wa(struct intel_display *display, bool enable) > { > enum pipe pipe; > > @@ -451,84 +452,86 @@ static void adlp_pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool ena > */ > if (enable) > for (pipe = PIPE_A; pipe <= PIPE_D; pipe++) > - intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), > + intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), > 0, PIPEDMC_GATING_DIS); > else > for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) > - intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), > + intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), > PIPEDMC_GATING_DIS, 0); > } > > -static void mtl_pipedmc_clock_gating_wa(struct drm_i915_private *i915) > +static void mtl_pipedmc_clock_gating_wa(struct intel_display *display) > { > /* > * Wa_16015201720 > * The WA requires clock gating to be disabled all the time > * for pipe A and B. > */ > - intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, > + intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, > MTL_PIPEDMC_GATING_DIS_A | MTL_PIPEDMC_GATING_DIS_B); > } > > -static void pipedmc_clock_gating_wa(struct drm_i915_private *i915, bool enable) > +static void pipedmc_clock_gating_wa(struct intel_display *display, bool enable) > { > - if (DISPLAY_VER(i915) >= 14 && enable) > - mtl_pipedmc_clock_gating_wa(i915); > - else if (DISPLAY_VER(i915) == 13) > - adlp_pipedmc_clock_gating_wa(i915, enable); > + if (DISPLAY_VER(display) >= 14 && enable) > + mtl_pipedmc_clock_gating_wa(display); > + else if (DISPLAY_VER(display) == 13) > + adlp_pipedmc_clock_gating_wa(display, enable); > } > > -void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe) > +void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe) > { > enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); > > - if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id)) > + if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) > return; > > - if (DISPLAY_VER(i915) >= 14) > - intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); > + if (DISPLAY_VER(display) >= 14) > + intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); > else > - intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); > + intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); > } > > -void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe) > +void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe) > { > enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); > > - if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(i915, dmc_id)) > + if (!is_valid_dmc_id(dmc_id) || !has_dmc_id_fw(display, dmc_id)) > return; > > - if (DISPLAY_VER(i915) >= 14) > - intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); > + if (DISPLAY_VER(display) >= 14) > + intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); > else > - intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); > + intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); > } > > -static bool is_dmc_evt_ctl_reg(struct drm_i915_private *i915, > +static bool is_dmc_evt_ctl_reg(struct intel_display *display, > enum intel_dmc_id dmc_id, i915_reg_t reg) > { > u32 offset = i915_mmio_reg_offset(reg); > - u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, 0)); > - u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); > + u32 start = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, 0)); > + u32 end = i915_mmio_reg_offset(DMC_EVT_CTL(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); > > return offset >= start && offset < end; > } > > -static bool is_dmc_evt_htp_reg(struct drm_i915_private *i915, > +static bool is_dmc_evt_htp_reg(struct intel_display *display, > enum intel_dmc_id dmc_id, i915_reg_t reg) > { > u32 offset = i915_mmio_reg_offset(reg); > - u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, 0)); > - u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(i915, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); > + u32 start = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, 0)); > + u32 end = i915_mmio_reg_offset(DMC_EVT_HTP(display, dmc_id, DMC_EVENT_HANDLER_COUNT_GEN12)); > > return offset >= start && offset < end; > } > > -static bool disable_dmc_evt(struct drm_i915_private *i915, > +static bool disable_dmc_evt(struct intel_display *display, > enum intel_dmc_id dmc_id, > i915_reg_t reg, u32 data) > { > - if (!is_dmc_evt_ctl_reg(i915, dmc_id, reg)) > + struct drm_i915_private *i915 = to_i915(display->drm); > + > + if (!is_dmc_evt_ctl_reg(display, dmc_id, reg)) > return false; > > /* keep all pipe DMC events disabled by default */ > @@ -548,11 +551,11 @@ static bool disable_dmc_evt(struct drm_i915_private *i915, > return false; > } > > -static u32 dmc_mmiodata(struct drm_i915_private *i915, > +static u32 dmc_mmiodata(struct intel_display *display, > struct intel_dmc *dmc, > enum intel_dmc_id dmc_id, int i) > { > - if (disable_dmc_evt(i915, dmc_id, > + if (disable_dmc_evt(display, dmc_id, > dmc->dmc_info[dmc_id].mmioaddr[i], > dmc->dmc_info[dmc_id].mmiodata[i])) > return REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, > @@ -565,25 +568,26 @@ static u32 dmc_mmiodata(struct drm_i915_private *i915, > > /** > * intel_dmc_load_program() - write the firmware from memory to register. > - * @i915: i915 drm device. > + * @display: display instance > * > * DMC firmware is read from a .bin file and kept in internal memory one time. > * Everytime display comes back from low power state this function is called to > * copy the firmware from internal memory to registers. > */ > -void intel_dmc_load_program(struct drm_i915_private *i915) > +void intel_dmc_load_program(struct intel_display *display) > { > - struct i915_power_domains *power_domains = &i915->display.power.domains; > - struct intel_dmc *dmc = i915_to_dmc(i915); > + struct drm_i915_private *i915 __maybe_unused = to_i915(display->drm); > + struct i915_power_domains *power_domains = &display->power.domains; > + struct intel_dmc *dmc = display_to_dmc(display); > enum intel_dmc_id dmc_id; > u32 i; > > - if (!intel_dmc_has_payload(i915)) > + if (!intel_dmc_has_payload(display)) > return; > > - pipedmc_clock_gating_wa(i915, true); > + pipedmc_clock_gating_wa(display, true); > > - disable_all_event_handlers(i915); > + disable_all_event_handlers(display); > > assert_rpm_wakelock_held(&i915->runtime_pm); > > @@ -591,7 +595,7 @@ void intel_dmc_load_program(struct drm_i915_private *i915) > > for_each_dmc_id(dmc_id) { > for (i = 0; i < dmc->dmc_info[dmc_id].dmc_fw_size; i++) { > - intel_de_write_fw(i915, > + intel_de_write_fw(display, > DMC_PROGRAM(dmc->dmc_info[dmc_id].start_mmioaddr, i), > dmc->dmc_info[dmc_id].payload[i]); > } > @@ -601,48 +605,48 @@ void intel_dmc_load_program(struct drm_i915_private *i915) > > for_each_dmc_id(dmc_id) { > for (i = 0; i < dmc->dmc_info[dmc_id].mmio_count; i++) { > - intel_de_write(i915, dmc->dmc_info[dmc_id].mmioaddr[i], > - dmc_mmiodata(i915, dmc, dmc_id, i)); > + intel_de_write(display, dmc->dmc_info[dmc_id].mmioaddr[i], > + dmc_mmiodata(display, dmc, dmc_id, i)); > } > } > > power_domains->dc_state = 0; > > - gen9_set_dc_state_debugmask(i915); > + gen9_set_dc_state_debugmask(display); > > - pipedmc_clock_gating_wa(i915, false); > + pipedmc_clock_gating_wa(display, false); > } > > /** > * intel_dmc_disable_program() - disable the firmware > - * @i915: i915 drm device > + * @display: display instance > * > * Disable all event handlers in the firmware, making sure the firmware is > * inactive after the display is uninitialized. > */ > -void intel_dmc_disable_program(struct drm_i915_private *i915) > +void intel_dmc_disable_program(struct intel_display *display) > { > - if (!intel_dmc_has_payload(i915)) > + if (!intel_dmc_has_payload(display)) > return; > > - pipedmc_clock_gating_wa(i915, true); > - disable_all_event_handlers(i915); > - pipedmc_clock_gating_wa(i915, false); > + pipedmc_clock_gating_wa(display, true); > + disable_all_event_handlers(display); > + pipedmc_clock_gating_wa(display, false); > > - intel_dmc_wl_disable(&i915->display); > + intel_dmc_wl_disable(display); > } > > -void assert_dmc_loaded(struct drm_i915_private *i915) > +void assert_dmc_loaded(struct intel_display *display) > { > - struct intel_dmc *dmc = i915_to_dmc(i915); > + struct intel_dmc *dmc = display_to_dmc(display); > > - drm_WARN_ONCE(&i915->drm, !dmc, "DMC not initialized\n"); > - drm_WARN_ONCE(&i915->drm, dmc && > - !intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), > + drm_WARN_ONCE(display->drm, !dmc, "DMC not initialized\n"); > + drm_WARN_ONCE(display->drm, dmc && > + !intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), > "DMC program storage start is NULL\n"); > - drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE), > + drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_SSP_BASE), > "DMC SSP Base Not fine\n"); > - drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL), > + drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_HTP_SKL), > "DMC HTP Not fine\n"); > } > > @@ -673,7 +677,7 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc, > const struct stepping_info *si, > u8 package_ver) > { > - struct drm_i915_private *i915 = dmc->i915; > + struct intel_display *display = dmc->display; > enum intel_dmc_id dmc_id; > unsigned int i; > > @@ -681,7 +685,7 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc, > dmc_id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; > > if (!is_valid_dmc_id(dmc_id)) { > - drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", dmc_id); > + drm_dbg(display->drm, "Unsupported firmware id: %u\n", dmc_id); > continue; > } > > @@ -703,7 +707,7 @@ static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, > const u32 *mmioaddr, u32 mmio_count, > int header_ver, enum intel_dmc_id dmc_id) > { > - struct drm_i915_private *i915 = dmc->i915; > + struct intel_display *display = dmc->display; > u32 start_range, end_range; > int i; > > @@ -713,14 +717,14 @@ static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc, > } else if (dmc_id == DMC_FW_MAIN) { > start_range = TGL_MAIN_MMIO_START; > end_range = TGL_MAIN_MMIO_END; > - } else if (DISPLAY_VER(i915) >= 13) { > + } else if (DISPLAY_VER(display) >= 13) { > start_range = ADLP_PIPE_MMIO_START; > end_range = ADLP_PIPE_MMIO_END; > - } else if (DISPLAY_VER(i915) >= 12) { > + } else if (DISPLAY_VER(display) >= 12) { > start_range = TGL_PIPE_MMIO_START(dmc_id); > end_range = TGL_PIPE_MMIO_END(dmc_id); > } else { > - drm_warn(&i915->drm, "Unknown mmio range for sanity check"); > + drm_warn(display->drm, "Unknown mmio range for sanity check"); > return false; > } > > @@ -736,7 +740,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc, > const struct intel_dmc_header_base *dmc_header, > size_t rem_size, enum intel_dmc_id dmc_id) > { > - struct drm_i915_private *i915 = dmc->i915; > + struct intel_display *display = dmc->display; > struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; > unsigned int header_len_bytes, dmc_header_size, payload_size, i; > const u32 *mmioaddr, *mmiodata; > @@ -784,39 +788,39 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc, > start_mmioaddr = DMC_V1_MMIO_START_RANGE; > dmc_header_size = sizeof(*v1); > } else { > - drm_err(&i915->drm, "Unknown DMC fw header version: %u\n", > + drm_err(display->drm, "Unknown DMC fw header version: %u\n", > dmc_header->header_ver); > return 0; > } > > if (header_len_bytes != dmc_header_size) { > - drm_err(&i915->drm, "DMC firmware has wrong dmc header length " > + drm_err(display->drm, "DMC firmware has wrong dmc header length " > "(%u bytes)\n", header_len_bytes); > return 0; > } > > /* Cache the dmc header info. */ > if (mmio_count > mmio_count_max) { > - drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); > + drm_err(display->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); > return 0; > } > > if (!dmc_mmio_addr_sanity_check(dmc, mmioaddr, mmio_count, > dmc_header->header_ver, dmc_id)) { > - drm_err(&i915->drm, "DMC firmware has Wrong MMIO Addresses\n"); > + drm_err(display->drm, "DMC firmware has Wrong MMIO Addresses\n"); > return 0; > } > > - drm_dbg_kms(&i915->drm, "DMC %d:\n", dmc_id); > + drm_dbg_kms(display->drm, "DMC %d:\n", dmc_id); > for (i = 0; i < mmio_count; i++) { > dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); > dmc_info->mmiodata[i] = mmiodata[i]; > > - drm_dbg_kms(&i915->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", > + drm_dbg_kms(display->drm, " mmio[%d]: 0x%x = 0x%x%s%s\n", > i, mmioaddr[i], mmiodata[i], > - is_dmc_evt_ctl_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : > - is_dmc_evt_htp_reg(i915, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", > - disable_dmc_evt(i915, dmc_id, dmc_info->mmioaddr[i], > + is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : > + is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", > + disable_dmc_evt(display, dmc_id, dmc_info->mmioaddr[i], > dmc_info->mmiodata[i]) ? " (disabling)" : ""); > } > dmc_info->mmio_count = mmio_count; > @@ -830,7 +834,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc, > goto error_truncated; > > if (payload_size > dmc->max_fw_size) { > - drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size); > + drm_err(display->drm, "DMC FW too big (%u bytes)\n", payload_size); > return 0; > } > dmc_info->dmc_fw_size = dmc_header->fw_size; > @@ -845,7 +849,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc, > return header_len_bytes + payload_size; > > error_truncated: > - drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); > + drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); > return 0; > } > > @@ -855,7 +859,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc, > const struct stepping_info *si, > size_t rem_size) > { > - struct drm_i915_private *i915 = dmc->i915; > + struct intel_display *display = dmc->display; > u32 package_size = sizeof(struct intel_package_header); > u32 num_entries, max_entries; > const struct intel_fw_info *fw_info; > @@ -868,7 +872,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc, > } else if (package_header->header_ver == 2) { > max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; > } else { > - drm_err(&i915->drm, "DMC firmware has unknown header version %u\n", > + drm_err(display->drm, "DMC firmware has unknown header version %u\n", > package_header->header_ver); > return 0; > } > @@ -882,7 +886,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc, > goto error_truncated; > > if (package_header->header_len * 4 != package_size) { > - drm_err(&i915->drm, "DMC firmware has wrong package header length " > + drm_err(display->drm, "DMC firmware has wrong package header length " > "(%u bytes)\n", package_size); > return 0; > } > @@ -900,7 +904,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc, > return package_size; > > error_truncated: > - drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); > + drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); > return 0; > } > > @@ -909,16 +913,16 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc, > struct intel_css_header *css_header, > size_t rem_size) > { > - struct drm_i915_private *i915 = dmc->i915; > + struct intel_display *display = dmc->display; > > if (rem_size < sizeof(struct intel_css_header)) { > - drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); > + drm_err(display->drm, "Truncated DMC firmware, refusing.\n"); > return 0; > } > > if (sizeof(struct intel_css_header) != > (css_header->header_len * 4)) { > - drm_err(&i915->drm, "DMC firmware has wrong CSS header length " > + drm_err(display->drm, "DMC firmware has wrong CSS header length " > "(%u bytes)\n", > (css_header->header_len * 4)); > return 0; > @@ -931,12 +935,12 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc, > > static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) > { > - struct drm_i915_private *i915 = dmc->i915; > + struct intel_display *display = dmc->display; > struct intel_css_header *css_header; > struct intel_package_header *package_header; > struct intel_dmc_header_base *dmc_header; > struct stepping_info display_info = { '*', '*'}; > - const struct stepping_info *si = intel_get_stepping_info(i915, &display_info); > + const struct stepping_info *si = intel_get_stepping_info(display, &display_info); > enum intel_dmc_id dmc_id; > u32 readcount = 0; > u32 r, offset; > @@ -966,7 +970,7 @@ static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) > > offset = readcount + dmc->dmc_info[dmc_id].dmc_offset * 4; > if (offset > fw->size) { > - drm_err(&i915->drm, "Reading beyond the fw_size\n"); > + drm_err(display->drm, "Reading beyond the fw_size\n"); > continue; > } > > @@ -974,30 +978,35 @@ static int parse_dmc_fw(struct intel_dmc *dmc, const struct firmware *fw) > parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, dmc_id); > } > > - if (!intel_dmc_has_payload(i915)) { > - drm_err(&i915->drm, "DMC firmware main program not found\n"); > + if (!intel_dmc_has_payload(display)) { > + drm_err(display->drm, "DMC firmware main program not found\n"); > return -ENOENT; > } > > return 0; > } > > -static void intel_dmc_runtime_pm_get(struct drm_i915_private *i915) > +static void intel_dmc_runtime_pm_get(struct intel_display *display) > { > - drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref); > - i915->display.dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); > + struct drm_i915_private *i915 = to_i915(display->drm); > + > + drm_WARN_ON(display->drm, display->dmc.wakeref); > + display->dmc.wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); > } > > -static void intel_dmc_runtime_pm_put(struct drm_i915_private *i915) > +static void intel_dmc_runtime_pm_put(struct intel_display *display) > { > + struct drm_i915_private *i915 = to_i915(display->drm); > intel_wakeref_t wakeref __maybe_unused = > - fetch_and_zero(&i915->display.dmc.wakeref); > + fetch_and_zero(&display->dmc.wakeref); > > intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref); > } > > -static const char *dmc_fallback_path(struct drm_i915_private *i915) > +static const char *dmc_fallback_path(struct intel_display *display) > { > + struct drm_i915_private *i915 = to_i915(display->drm); > + > if (IS_ALDERLAKE_P(i915)) > return ADLP_DMC_FALLBACK_PATH; > > @@ -1007,45 +1016,45 @@ static const char *dmc_fallback_path(struct drm_i915_private *i915) > static void dmc_load_work_fn(struct work_struct *work) > { > struct intel_dmc *dmc = container_of(work, typeof(*dmc), work); > - struct drm_i915_private *i915 = dmc->i915; > + struct intel_display *display = dmc->display; > const struct firmware *fw = NULL; > const char *fallback_path; > int err; > > - err = request_firmware(&fw, dmc->fw_path, i915->drm.dev); > + err = request_firmware(&fw, dmc->fw_path, display->drm->dev); > > - if (err == -ENOENT && !dmc_firmware_param(i915)) { > - fallback_path = dmc_fallback_path(i915); > + if (err == -ENOENT && !dmc_firmware_param(display)) { > + fallback_path = dmc_fallback_path(display); > if (fallback_path) { > - drm_dbg_kms(&i915->drm, "%s not found, falling back to %s\n", > + drm_dbg_kms(display->drm, "%s not found, falling back to %s\n", > dmc->fw_path, fallback_path); > - err = request_firmware(&fw, fallback_path, i915->drm.dev); > + err = request_firmware(&fw, fallback_path, display->drm->dev); > if (err == 0) > dmc->fw_path = fallback_path; > } > } > > if (err) { > - drm_notice(&i915->drm, > + drm_notice(display->drm, > "Failed to load DMC firmware %s (%pe). Disabling runtime power management.\n", > dmc->fw_path, ERR_PTR(err)); > - drm_notice(&i915->drm, "DMC firmware homepage: %s", > + drm_notice(display->drm, "DMC firmware homepage: %s", > INTEL_DMC_FIRMWARE_URL); > return; > } > > err = parse_dmc_fw(dmc, fw); > if (err) { > - drm_notice(&i915->drm, > + drm_notice(display->drm, > "Failed to parse DMC firmware %s (%pe). Disabling runtime power management.\n", > dmc->fw_path, ERR_PTR(err)); > goto out; > } > > - intel_dmc_load_program(i915); > - intel_dmc_runtime_pm_put(i915); > + intel_dmc_load_program(display); > + intel_dmc_runtime_pm_put(display); > > - drm_info(&i915->drm, "Finished loading DMC firmware %s (v%u.%u)\n", > + drm_info(display->drm, "Finished loading DMC firmware %s (v%u.%u)\n", > dmc->fw_path, DMC_VERSION_MAJOR(dmc->version), > DMC_VERSION_MINOR(dmc->version)); > > @@ -1055,16 +1064,17 @@ static void dmc_load_work_fn(struct work_struct *work) > > /** > * intel_dmc_init() - initialize the firmware loading. > - * @i915: i915 drm device. > + * @display: display instance > * > * This function is called at the time of loading the display driver to read > * firmware from a .bin file and copied into a internal memory. > */ > -void intel_dmc_init(struct drm_i915_private *i915) > +void intel_dmc_init(struct intel_display *display) > { > + struct drm_i915_private *i915 = to_i915(display->drm); > struct intel_dmc *dmc; > > - if (!HAS_DMC(i915)) > + if (!HAS_DMC(display)) > return; > > /* > @@ -1075,35 +1085,35 @@ void intel_dmc_init(struct drm_i915_private *i915) > * suspend as runtime suspend *requires* a working DMC for whatever > * reason. > */ > - intel_dmc_runtime_pm_get(i915); > + intel_dmc_runtime_pm_get(display); > > dmc = kzalloc(sizeof(*dmc), GFP_KERNEL); > if (!dmc) > return; > > - dmc->i915 = i915; > + dmc->display = display; > > INIT_WORK(&dmc->work, dmc_load_work_fn); > > - dmc->fw_path = dmc_firmware_default(i915, &dmc->max_fw_size); > + dmc->fw_path = dmc_firmware_default(display, &dmc->max_fw_size); > > - if (dmc_firmware_param_disabled(i915)) { > - drm_info(&i915->drm, "Disabling DMC firmware and runtime PM\n"); > + if (dmc_firmware_param_disabled(display)) { > + drm_info(display->drm, "Disabling DMC firmware and runtime PM\n"); > goto out; > } > > - if (dmc_firmware_param(i915)) > - dmc->fw_path = dmc_firmware_param(i915); > + if (dmc_firmware_param(display)) > + dmc->fw_path = dmc_firmware_param(display); > > if (!dmc->fw_path) { > - drm_dbg_kms(&i915->drm, > + drm_dbg_kms(display->drm, > "No known DMC firmware for platform, disabling runtime PM\n"); > goto out; > } > > - i915->display.dmc.dmc = dmc; > + display->dmc.dmc = dmc; > > - drm_dbg_kms(&i915->drm, "Loading %s\n", dmc->fw_path); > + drm_dbg_kms(display->drm, "Loading %s\n", dmc->fw_path); > queue_work(i915->unordered_wq, &dmc->work); > > return; > @@ -1114,87 +1124,87 @@ void intel_dmc_init(struct drm_i915_private *i915) > > /** > * intel_dmc_suspend() - prepare DMC firmware before system suspend > - * @i915: i915 drm device > + * @display: display instance > * > * Prepare the DMC firmware before entering system suspend. This includes > * flushing pending work items and releasing any resources acquired during > * init. > */ > -void intel_dmc_suspend(struct drm_i915_private *i915) > +void intel_dmc_suspend(struct intel_display *display) > { > - struct intel_dmc *dmc = i915_to_dmc(i915); > + struct intel_dmc *dmc = display_to_dmc(display); > > - if (!HAS_DMC(i915)) > + if (!HAS_DMC(display)) > return; > > if (dmc) > flush_work(&dmc->work); > > - intel_dmc_wl_disable(&i915->display); > + intel_dmc_wl_disable(display); > > /* Drop the reference held in case DMC isn't loaded. */ > - if (!intel_dmc_has_payload(i915)) > - intel_dmc_runtime_pm_put(i915); > + if (!intel_dmc_has_payload(display)) > + intel_dmc_runtime_pm_put(display); > } > > /** > * intel_dmc_resume() - init DMC firmware during system resume > - * @i915: i915 drm device > + * @display: display instance > * > * Reinitialize the DMC firmware during system resume, reacquiring any > * resources released in intel_dmc_suspend(). > */ > -void intel_dmc_resume(struct drm_i915_private *i915) > +void intel_dmc_resume(struct intel_display *display) > { > - if (!HAS_DMC(i915)) > + if (!HAS_DMC(display)) > return; > > /* > * Reacquire the reference to keep RPM disabled in case DMC isn't > * loaded. > */ > - if (!intel_dmc_has_payload(i915)) > - intel_dmc_runtime_pm_get(i915); > + if (!intel_dmc_has_payload(display)) > + intel_dmc_runtime_pm_get(display); > } > > /** > * intel_dmc_fini() - unload the DMC firmware. > - * @i915: i915 drm device. > + * @display: display instance > * > * Firmmware unloading includes freeing the internal memory and reset the > * firmware loading status. > */ > -void intel_dmc_fini(struct drm_i915_private *i915) > +void intel_dmc_fini(struct intel_display *display) > { > - struct intel_dmc *dmc = i915_to_dmc(i915); > + struct intel_dmc *dmc = display_to_dmc(display); > enum intel_dmc_id dmc_id; > > - if (!HAS_DMC(i915)) > + if (!HAS_DMC(display)) > return; > > - intel_dmc_suspend(i915); > - drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref); > + intel_dmc_suspend(display); > + drm_WARN_ON(display->drm, display->dmc.wakeref); > > if (dmc) { > for_each_dmc_id(dmc_id) > kfree(dmc->dmc_info[dmc_id].payload); > > kfree(dmc); > - i915->display.dmc.dmc = NULL; > + display->dmc.dmc = NULL; > } > } > > void intel_dmc_print_error_state(struct drm_printer *p, > - struct drm_i915_private *i915) > + struct intel_display *display) > { > - struct intel_dmc *dmc = i915_to_dmc(i915); > + struct intel_dmc *dmc = display_to_dmc(display); > > - if (!HAS_DMC(i915)) > + if (!HAS_DMC(display)) > return; > > drm_printf(p, "DMC initialized: %s\n", str_yes_no(dmc)); > drm_printf(p, "DMC loaded: %s\n", > - str_yes_no(intel_dmc_has_payload(i915))); > + str_yes_no(intel_dmc_has_payload(display))); > if (dmc) > drm_printf(p, "DMC fw version: %d.%d\n", > DMC_VERSION_MAJOR(dmc->version), > @@ -1203,40 +1213,41 @@ void intel_dmc_print_error_state(struct drm_printer *p, > > static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) > { > - struct drm_i915_private *i915 = m->private; > - struct intel_dmc *dmc = i915_to_dmc(i915); > + struct intel_display *display = m->private; > + struct drm_i915_private *i915 = to_i915(display->drm); > + struct intel_dmc *dmc = display_to_dmc(display); > intel_wakeref_t wakeref; > i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; > > - if (!HAS_DMC(i915)) > + if (!HAS_DMC(display)) > return -ENODEV; > > wakeref = intel_runtime_pm_get(&i915->runtime_pm); > > seq_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); > seq_printf(m, "fw loaded: %s\n", > - str_yes_no(intel_dmc_has_payload(i915))); > + str_yes_no(intel_dmc_has_payload(display))); > seq_printf(m, "path: %s\n", dmc ? dmc->fw_path : "N/A"); > seq_printf(m, "Pipe A fw needed: %s\n", > - str_yes_no(DISPLAY_VER(i915) >= 12)); > + str_yes_no(DISPLAY_VER(display) >= 12)); > seq_printf(m, "Pipe A fw loaded: %s\n", > - str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEA))); > + str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEA))); > seq_printf(m, "Pipe B fw needed: %s\n", > str_yes_no(IS_ALDERLAKE_P(i915) || > - DISPLAY_VER(i915) >= 14)); > + DISPLAY_VER(display) >= 14)); > seq_printf(m, "Pipe B fw loaded: %s\n", > - str_yes_no(has_dmc_id_fw(i915, DMC_FW_PIPEB))); > + str_yes_no(has_dmc_id_fw(display, DMC_FW_PIPEB))); > > - if (!intel_dmc_has_payload(i915)) > + if (!intel_dmc_has_payload(display)) > goto out; > > seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), > DMC_VERSION_MINOR(dmc->version)); > > - if (DISPLAY_VER(i915) >= 12) { > + if (DISPLAY_VER(display) >= 12) { > i915_reg_t dc3co_reg; > > - if (IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) { > + if (IS_DGFX(i915) || DISPLAY_VER(display) >= 14) { > dc3co_reg = DG1_DMC_DEBUG3; > dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; > } else { > @@ -1246,7 +1257,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) > } > > seq_printf(m, "DC3CO count: %d\n", > - intel_de_read(i915, dc3co_reg)); > + intel_de_read(display, dc3co_reg)); > } else { > dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT : > SKL_DMC_DC3_DC5_COUNT; > @@ -1254,18 +1265,18 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) > dc6_reg = SKL_DMC_DC5_DC6_COUNT; > } > > - seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg)); > + seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg)); > if (i915_mmio_reg_valid(dc6_reg)) > seq_printf(m, "DC5 -> DC6 count: %d\n", > - intel_de_read(i915, dc6_reg)); > + intel_de_read(display, dc6_reg)); > > seq_printf(m, "program base: 0x%08x\n", > - intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); > + intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); > > out: > seq_printf(m, "ssp base: 0x%08x\n", > - intel_de_read(i915, DMC_SSP_BASE)); > - seq_printf(m, "htp: 0x%08x\n", intel_de_read(i915, DMC_HTP_SKL)); > + intel_de_read(display, DMC_SSP_BASE)); > + seq_printf(m, "htp: 0x%08x\n", intel_de_read(display, DMC_HTP_SKL)); > > intel_runtime_pm_put(&i915->runtime_pm, wakeref); > > @@ -1274,10 +1285,10 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) > > DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); > > -void intel_dmc_debugfs_register(struct drm_i915_private *i915) > +void intel_dmc_debugfs_register(struct intel_display *display) > { > - struct drm_minor *minor = i915->drm.primary; > + struct drm_minor *minor = display->drm->primary; > > debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root, > - i915, &intel_dmc_debugfs_status_fops); > + display, &intel_dmc_debugfs_status_fops); > } > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h > index 54cff6002e31..2ead2ec1f820 100644 > --- a/drivers/gpu/drm/i915/display/intel_dmc.h > +++ b/drivers/gpu/drm/i915/display/intel_dmc.h > @@ -9,22 +9,22 @@ > #include <linux/types.h> > > enum pipe; > -struct drm_i915_private; > struct drm_printer; > +struct intel_display; > > -void intel_dmc_init(struct drm_i915_private *i915); > -void intel_dmc_load_program(struct drm_i915_private *i915); > -void intel_dmc_disable_program(struct drm_i915_private *i915); > -void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe); > -void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe); > -void intel_dmc_fini(struct drm_i915_private *i915); > -void intel_dmc_suspend(struct drm_i915_private *i915); > -void intel_dmc_resume(struct drm_i915_private *i915); > -bool intel_dmc_has_payload(struct drm_i915_private *i915); > -void intel_dmc_debugfs_register(struct drm_i915_private *i915); > +void intel_dmc_init(struct intel_display *display); > +void intel_dmc_load_program(struct intel_display *display); > +void intel_dmc_disable_program(struct intel_display *display); > +void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe); > +void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe); > +void intel_dmc_fini(struct intel_display *display); > +void intel_dmc_suspend(struct intel_display *display); > +void intel_dmc_resume(struct intel_display *display); > +bool intel_dmc_has_payload(struct intel_display *display); > +void intel_dmc_debugfs_register(struct intel_display *display); > void intel_dmc_print_error_state(struct drm_printer *p, > - struct drm_i915_private *i915); > + struct intel_display *display); > > -void assert_dmc_loaded(struct drm_i915_private *i915); > +void assert_dmc_loaded(struct intel_display *display); > > #endif /* __INTEL_DMC_H__ */ > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c > index d9864b9cc429..5634ff07269d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c > +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c > @@ -109,10 +109,8 @@ static bool intel_dmc_wl_check_range(u32 address) > > static bool __intel_dmc_wl_supported(struct intel_display *display) > { > - struct drm_i915_private *i915 = to_i915(display->drm); > - > if (DISPLAY_VER(display) < 20 || > - !intel_dmc_has_payload(i915) || > + !intel_dmc_has_payload(display) || > !display->params.enable_dmc_wl) > return false; > > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c > index 1f57549fce00..bcc5cf137a88 100644 > --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c > +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c > @@ -960,6 +960,7 @@ static void intel_early_display_was(struct drm_i915_private *i915) > void intel_modeset_setup_hw_state(struct drm_i915_private *i915, > struct drm_modeset_acquire_ctx *ctx) > { > + struct intel_display *display = &i915->display; > struct intel_encoder *encoder; > struct intel_crtc *crtc; > intel_wakeref_t wakeref; > @@ -987,7 +988,7 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915, > drm_crtc_vblank_reset(&crtc->base); > > if (crtc_state->hw.active) { > - intel_dmc_enable_pipe(i915, crtc->pipe); > + intel_dmc_enable_pipe(display, crtc->pipe); > intel_crtc_vblank_on(crtc_state); > } > } > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c > index fe905d65ddf7..943e938040c0 100644 > --- a/drivers/gpu/drm/i915/i915_driver.c > +++ b/drivers/gpu/drm/i915/i915_driver.c > @@ -959,7 +959,7 @@ void i915_driver_shutdown(struct drm_i915_private *i915) > intel_encoder_suspend_all(&i915->display); > intel_encoder_shutdown_all(&i915->display); > > - intel_dmc_suspend(i915); > + intel_dmc_suspend(&i915->display); > > i915_gem_suspend(i915); > > @@ -1054,7 +1054,7 @@ static int i915_drm_suspend(struct drm_device *dev) > > dev_priv->suspend_count++; > > - intel_dmc_suspend(dev_priv); > + intel_dmc_suspend(display); > > enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); > > @@ -1164,7 +1164,7 @@ static int i915_drm_resume(struct drm_device *dev) > /* Must be called after GGTT is resumed. */ > intel_dpt_resume(dev_priv); > > - intel_dmc_resume(dev_priv); > + intel_dmc_resume(display); > > i915_restore_display(dev_priv); > intel_pps_unlock_regs_wa(display); > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index 6469b9bcf2ec..b455fa441609 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -875,7 +875,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, > > err_printf(m, "IOMMU enabled?: %d\n", error->iommu); > > - intel_dmc_print_error_state(&p, m->i915); > + intel_dmc_print_error_state(&p, &m->i915->display); > > err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock)); > err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended)); > diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c > index c0e9aa7a274f..10d707e05d6e 100644 > --- a/drivers/gpu/drm/xe/display/xe_display.c > +++ b/drivers/gpu/drm/xe/display/xe_display.c > @@ -353,7 +353,7 @@ void xe_display_pm_suspend(struct xe_device *xe, bool runtime) > > intel_opregion_suspend(display, s2idle ? PCI_D1 : PCI_D3cold); > > - intel_dmc_suspend(xe); > + intel_dmc_suspend(display); > } > > void xe_display_pm_suspend_late(struct xe_device *xe) > @@ -395,7 +395,7 @@ void xe_display_pm_resume(struct xe_device *xe, bool runtime) > if (!xe->info.probe_display) > return; > > - intel_dmc_resume(xe); > + intel_dmc_resume(display); > > if (has_display(xe)) > drm_mode_config_reset(&xe->drm); > -- > 2.44.2 > ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ CI.Patch_applied: success for drm/i915: Some intel_display conversions 2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala ` (5 preceding siblings ...) 2024-09-06 14:33 ` [PATCH 6/6] drm/i915/dmc: Convert DMC " Ville Syrjala @ 2024-09-06 14:38 ` Patchwork 2024-09-06 14:39 ` ✗ CI.checkpatch: warning " Patchwork ` (6 subsequent siblings) 13 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2024-09-06 14:38 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-xe == Series Details == Series: drm/i915: Some intel_display conversions URL : https://patchwork.freedesktop.org/series/138332/ State : success == Summary == === Applying kernel patches on branch 'drm-tip' with base: === Base commit: 6094a8d70f85 drm-tip: 2024y-09m-06d-13h-50m-21s UTC integration manifest === git am output follows === Applying: drm/i915/cdclk: Add missing braces Applying: drm/i915/cdclk: Convert CDCLK code to intel_display Applying: drm/i915/power: Convert low level DC state code to intel_display Applying: drm/i915/vga: Convert VGA code to intel_display Applying: drm/i915/power: Convert "i830 power well" code to intel_display Applying: drm/i915/dmc: Convert DMC code to intel_display ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✗ CI.checkpatch: warning for drm/i915: Some intel_display conversions 2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala ` (6 preceding siblings ...) 2024-09-06 14:38 ` ✓ CI.Patch_applied: success for drm/i915: Some intel_display conversions Patchwork @ 2024-09-06 14:39 ` Patchwork 2024-09-06 14:40 ` ✓ CI.KUnit: success " Patchwork ` (5 subsequent siblings) 13 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2024-09-06 14:39 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-xe == Series Details == Series: drm/i915: Some intel_display conversions URL : https://patchwork.freedesktop.org/series/138332/ State : warning == Summary == + KERNEL=/kernel + git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt Cloning into 'mt'... warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/ + git -C mt rev-list -n1 origin/master c62d7e164862503a3662a095da1c6c9014248cb2 + cd /kernel + git config --global --add safe.directory /kernel + git log -n1 commit a799ab76dab9756d15c845ede2fc534a88e3b15a Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Fri Sep 6 17:33:06 2024 +0300 drm/i915/dmc: Convert DMC code to intel_display struct intel_display will replace struct drm_i915_private as the main thing for display code. Convert the DMC code to use it (as much as possible at this stage). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> + /mt/dim checkpatch 6094a8d70f8599700297da58bcf80d5b1915adff drm-intel 21ad6884653f drm/i915/cdclk: Add missing braces 6c326db98005 drm/i915/cdclk: Convert CDCLK code to intel_display -:1465: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 26) #1465: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:2103: + if (DISPLAY_VER(display) >= 14 || IS_DG2(dev_priv)) /* NOOP */; -:1506: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 19) #1506: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:2140: + if (DISPLAY_VER(display) >= 14) [...] */; -:2893: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided #2893: FILE: drivers/gpu/drm/i915/display/intel_display_driver.c:95: + cdclk_state->logical = cdclk_state->actual = display->cdclk.hw; total: 0 errors, 2 warnings, 1 checks, 2934 lines checked 85d00811b21f drm/i915/power: Convert low level DC state code to intel_display 260fd3797a3d drm/i915/vga: Convert VGA code to intel_display 0d7e59b0508c drm/i915/power: Convert "i830 power well" code to intel_display a799ab76dab9 drm/i915/dmc: Convert DMC code to intel_display -:602: WARNING:LONG_LINE: line length of 105 exceeds 100 columns #602: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:645: + !intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), -:709: WARNING:LONG_LINE: line length of 103 exceeds 100 columns #709: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:821: + is_dmc_evt_ctl_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_CTL)" : -:710: WARNING:LONG_LINE: line length of 107 exceeds 100 columns #710: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:822: + is_dmc_evt_htp_reg(display, dmc_id, dmc_info->mmioaddr[i]) ? " (EVT_HTP)" : "", -:1168: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #1168: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:1274: + intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); total: 0 errors, 4 warnings, 0 checks, 1210 lines checked ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ CI.KUnit: success for drm/i915: Some intel_display conversions 2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala ` (7 preceding siblings ...) 2024-09-06 14:39 ` ✗ CI.checkpatch: warning " Patchwork @ 2024-09-06 14:40 ` Patchwork 2024-09-06 14:57 ` ✓ CI.Build: " Patchwork ` (4 subsequent siblings) 13 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2024-09-06 14:40 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-xe == Series Details == Series: drm/i915: Some intel_display conversions URL : https://patchwork.freedesktop.org/series/138332/ State : success == Summary == + trap cleanup EXIT + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig [14:39:34] Configuring KUnit Kernel ... Generating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [14:39:38] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make ARCH=um O=.kunit --jobs=48 ../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes] 156 | u64 ioread64_lo_hi(const void __iomem *addr) | ^~~~~~~~~~~~~~ ../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes] 163 | u64 ioread64_hi_lo(const void __iomem *addr) | ^~~~~~~~~~~~~~ ../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes] 170 | u64 ioread64be_lo_hi(const void __iomem *addr) | ^~~~~~~~~~~~~~~~ ../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes] 178 | u64 ioread64be_hi_lo(const void __iomem *addr) | ^~~~~~~~~~~~~~~~ ../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes] 264 | void iowrite64_lo_hi(u64 val, void __iomem *addr) | ^~~~~~~~~~~~~~~ ../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes] 272 | void iowrite64_hi_lo(u64 val, void __iomem *addr) | ^~~~~~~~~~~~~~~ ../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes] 280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr) | ^~~~~~~~~~~~~~~~~ ../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes] 288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr) | ^~~~~~~~~~~~~~~~~ [14:40:04] Starting KUnit Kernel (1/1)... [14:40:04] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [14:40:04] =================== guc_dbm (7 subtests) =================== [14:40:04] [PASSED] test_empty [14:40:04] [PASSED] test_default [14:40:04] ======================== test_size ======================== [14:40:04] [PASSED] 4 [14:40:04] [PASSED] 8 [14:40:04] [PASSED] 32 [14:40:04] [PASSED] 256 [14:40:04] ==================== [PASSED] test_size ==================== [14:40:04] ======================= test_reuse ======================== [14:40:04] [PASSED] 4 [14:40:04] [PASSED] 8 [14:40:04] [PASSED] 32 [14:40:04] [PASSED] 256 [14:40:04] =================== [PASSED] test_reuse ==================== [14:40:04] =================== test_range_overlap ==================== [14:40:04] [PASSED] 4 [14:40:04] [PASSED] 8 [14:40:04] [PASSED] 32 [14:40:04] [PASSED] 256 [14:40:04] =============== [PASSED] test_range_overlap ================ [14:40:04] =================== test_range_compact ==================== [14:40:04] [PASSED] 4 [14:40:04] [PASSED] 8 [14:40:04] [PASSED] 32 [14:40:04] [PASSED] 256 [14:40:04] =============== [PASSED] test_range_compact ================ [14:40:04] ==================== test_range_spare ===================== [14:40:04] [PASSED] 4 [14:40:04] [PASSED] 8 [14:40:04] [PASSED] 32 [14:40:04] [PASSED] 256 [14:40:04] ================ [PASSED] test_range_spare ================= [14:40:04] ===================== [PASSED] guc_dbm ===================== [14:40:04] =================== guc_idm (6 subtests) =================== [14:40:04] [PASSED] bad_init [14:40:04] [PASSED] no_init [14:40:04] [PASSED] init_fini [14:40:04] [PASSED] check_used [14:40:04] [PASSED] check_quota [14:40:04] [PASSED] check_all [14:40:04] ===================== [PASSED] guc_idm ===================== [14:40:04] ================== no_relay (3 subtests) =================== [14:40:04] [PASSED] xe_drops_guc2pf_if_not_ready [14:40:04] [PASSED] xe_drops_guc2vf_if_not_ready [14:40:04] [PASSED] xe_rejects_send_if_not_ready [14:40:04] ==================== [PASSED] no_relay ===================== [14:40:04] ================== pf_relay (14 subtests) ================== [14:40:04] [PASSED] pf_rejects_guc2pf_too_short [14:40:04] [PASSED] pf_rejects_guc2pf_too_long [14:40:04] [PASSED] pf_rejects_guc2pf_no_payload [14:40:04] [PASSED] pf_fails_no_payload [14:40:04] [PASSED] pf_fails_bad_origin [14:40:04] [PASSED] pf_fails_bad_type [14:40:04] [PASSED] pf_txn_reports_error [14:40:04] [PASSED] pf_txn_sends_pf2guc [14:40:04] [PASSED] pf_sends_pf2guc [14:40:04] [SKIPPED] pf_loopback_nop [14:40:04] [SKIPPED] pf_loopback_echo [14:40:04] [SKIPPED] pf_loopback_fail [14:40:04] [SKIPPED] pf_loopback_busy [14:40:04] [SKIPPED] pf_loopback_retry [14:40:04] ==================== [PASSED] pf_relay ===================== [14:40:04] ================== vf_relay (3 subtests) =================== [14:40:04] [PASSED] vf_rejects_guc2vf_too_short [14:40:04] [PASSED] vf_rejects_guc2vf_too_long [14:40:04] [PASSED] vf_rejects_guc2vf_no_payload [14:40:04] ==================== [PASSED] vf_relay ===================== [14:40:04] ================= pf_service (11 subtests) ================= [14:40:04] [PASSED] pf_negotiate_any [14:40:04] [PASSED] pf_negotiate_base_match [14:40:04] [PASSED] pf_negotiate_base_newer [14:40:04] [PASSED] pf_negotiate_base_next [14:40:04] [SKIPPED] pf_negotiate_base_older [14:40:04] [PASSED] pf_negotiate_base_prev [14:40:04] [PASSED] pf_negotiate_latest_match [14:40:04] [PASSED] pf_negotiate_latest_newer [14:40:04] [PASSED] pf_negotiate_latest_next [14:40:04] [SKIPPED] pf_negotiate_latest_older [14:40:04] [SKIPPED] pf_negotiate_latest_prev [14:40:04] =================== [PASSED] pf_service ==================== [14:40:04] ===================== lmtt (1 subtest) ===================== [14:40:04] ======================== test_ops ========================= [14:40:04] [PASSED] 2-level [14:40:04] [PASSED] multi-level [14:40:04] ==================== [PASSED] test_ops ===================== [14:40:04] ====================== [PASSED] lmtt ======================= [14:40:04] =================== xe_mocs (2 subtests) =================== [14:40:04] ================ xe_live_mocs_kernel_kunit ================ [14:40:04] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============ [14:40:04] ================ xe_live_mocs_reset_kunit ================= [14:40:04] ============ [SKIPPED] xe_live_mocs_reset_kunit ============ [14:40:04] ==================== [SKIPPED] xe_mocs ===================== [14:40:04] ================= xe_migrate (2 subtests) ================== [14:40:04] ================= xe_migrate_sanity_kunit ================= [14:40:04] ============ [SKIPPED] xe_migrate_sanity_kunit ============= [14:40:04] ================== xe_validate_ccs_kunit ================== [14:40:04] ============= [SKIPPED] xe_validate_ccs_kunit ============== [14:40:04] =================== [SKIPPED] xe_migrate =================== [14:40:04] ================== xe_dma_buf (1 subtest) ================== [14:40:04] ==================== xe_dma_buf_kunit ===================== [14:40:04] ================ [SKIPPED] xe_dma_buf_kunit ================ [14:40:04] =================== [SKIPPED] xe_dma_buf =================== [14:40:04] ==================== xe_bo (2 subtests) ==================== [14:40:04] ================== xe_ccs_migrate_kunit =================== [14:40:04] ============== [SKIPPED] xe_ccs_migrate_kunit ============== [14:40:04] ==================== xe_bo_evict_kunit ==================== [14:40:04] =============== [SKIPPED] xe_bo_evict_kunit ================ [14:40:04] ===================== [SKIPPED] xe_bo ====================== [14:40:04] ==================== args (11 subtests) ==================== [14:40:04] [PASSED] count_args_test [14:40:04] [PASSED] call_args_example [14:40:04] [PASSED] call_args_test [14:40:04] [PASSED] drop_first_arg_example [14:40:04] [PASSED] drop_first_arg_test [14:40:04] [PASSED] first_arg_example [14:40:04] [PASSED] first_arg_test [14:40:04] [PASSED] last_arg_example [14:40:04] [PASSED] last_arg_test [14:40:04] [PASSED] pick_arg_example [14:40:04] [PASSED] sep_comma_example [14:40:04] ====================== [PASSED] args ======================= [14:40:04] =================== xe_pci (2 subtests) ==================== stty: 'standard input': Inappropriate ioctl for device [14:40:04] [PASSED] xe_gmdid_graphics_ip [14:40:04] [PASSED] xe_gmdid_media_ip [14:40:04] ===================== [PASSED] xe_pci ====================== [14:40:04] =================== xe_rtp (2 subtests) ==================== [14:40:04] =============== xe_rtp_process_to_sr_tests ================ [14:40:04] [PASSED] coalesce-same-reg [14:40:04] [PASSED] no-match-no-add [14:40:04] [PASSED] match-or [14:40:04] [PASSED] match-or-xfail [14:40:04] [PASSED] no-match-no-add-multiple-rules [14:40:04] [PASSED] two-regs-two-entries [14:40:04] [PASSED] clr-one-set-other [14:40:04] [PASSED] set-field [14:40:04] [PASSED] conflict-duplicate [14:40:04] [PASSED] conflict-not-disjoint [14:40:04] [PASSED] conflict-reg-type [14:40:04] =========== [PASSED] xe_rtp_process_to_sr_tests ============ [14:40:04] ================== xe_rtp_process_tests =================== [14:40:04] [PASSED] active1 [14:40:04] [PASSED] active2 [14:40:04] [PASSED] active-inactive [14:40:04] [PASSED] inactive-active [14:40:04] [PASSED] inactive-1st_or_active-inactive [14:40:04] [PASSED] inactive-2nd_or_active-inactive [14:40:04] [PASSED] inactive-last_or_active-inactive [14:40:04] [PASSED] inactive-no_or_active-inactive [14:40:04] ============== [PASSED] xe_rtp_process_tests =============== [14:40:04] ===================== [PASSED] xe_rtp ====================== [14:40:04] ==================== xe_wa (1 subtest) ===================== [14:40:04] ======================== xe_wa_gt ========================= [14:40:04] [PASSED] TIGERLAKE (B0) [14:40:04] [PASSED] DG1 (A0) [14:40:04] [PASSED] DG1 (B0) [14:40:04] [PASSED] ALDERLAKE_S (A0) [14:40:04] [PASSED] ALDERLAKE_S (B0) [14:40:04] [PASSED] ALDERLAKE_S (C0) [14:40:04] [PASSED] ALDERLAKE_S (D0) [14:40:04] [PASSED] ALDERLAKE_P (A0) [14:40:04] [PASSED] ALDERLAKE_P (B0) [14:40:04] [PASSED] ALDERLAKE_P (C0) [14:40:04] [PASSED] ALDERLAKE_S_RPLS (D0) [14:40:04] [PASSED] ALDERLAKE_P_RPLU (E0) [14:40:04] [PASSED] DG2_G10 (C0) [14:40:04] [PASSED] DG2_G11 (B1) [14:40:04] [PASSED] DG2_G12 (A1) [14:40:05] [PASSED] METEORLAKE (g:A0, m:A0) [14:40:05] [PASSED] METEORLAKE (g:A0, m:A0) [14:40:05] [PASSED] METEORLAKE (g:A0, m:A0) [14:40:05] [PASSED] LUNARLAKE (g:A0, m:A0) [14:40:05] [PASSED] LUNARLAKE (g:B0, m:A0) [14:40:05] [PASSED] BATTLEMAGE (g:A0, m:A1) [14:40:05] ==================== [PASSED] xe_wa_gt ===================== [14:40:05] ====================== [PASSED] xe_wa ====================== [14:40:05] ============================================================ [14:40:05] Testing complete. Ran 121 tests: passed: 106, skipped: 15 [14:40:05] Elapsed time: 30.527s total, 4.168s configuring, 26.133s building, 0.188s running + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig [14:40:05] Configuring KUnit Kernel ... Regenerating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [14:40:07] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make ARCH=um O=.kunit --jobs=48 ../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes] 156 | u64 ioread64_lo_hi(const void __iomem *addr) | ^~~~~~~~~~~~~~ ../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes] 163 | u64 ioread64_hi_lo(const void __iomem *addr) | ^~~~~~~~~~~~~~ ../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes] 170 | u64 ioread64be_lo_hi(const void __iomem *addr) | ^~~~~~~~~~~~~~~~ ../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes] 178 | u64 ioread64be_hi_lo(const void __iomem *addr) | ^~~~~~~~~~~~~~~~ ../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes] 264 | void iowrite64_lo_hi(u64 val, void __iomem *addr) | ^~~~~~~~~~~~~~~ ../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes] 272 | void iowrite64_hi_lo(u64 val, void __iomem *addr) | ^~~~~~~~~~~~~~~ ../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes] 280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr) | ^~~~~~~~~~~~~~~~~ ../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes] 288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr) | ^~~~~~~~~~~~~~~~~ [14:40:29] Starting KUnit Kernel (1/1)... [14:40:29] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [14:40:29] ============ drm_test_pick_cmdline (2 subtests) ============ [14:40:29] [PASSED] drm_test_pick_cmdline_res_1920_1080_60 [14:40:29] =============== drm_test_pick_cmdline_named =============== [14:40:29] [PASSED] NTSC [14:40:29] [PASSED] NTSC-J [14:40:29] [PASSED] PAL [14:40:29] [PASSED] PAL-M [14:40:29] =========== [PASSED] drm_test_pick_cmdline_named =========== [14:40:29] ============== [PASSED] drm_test_pick_cmdline ============== [14:40:29] ================== drm_buddy (7 subtests) ================== [14:40:29] [PASSED] drm_test_buddy_alloc_limit [14:40:29] [PASSED] drm_test_buddy_alloc_optimistic [14:40:29] [PASSED] drm_test_buddy_alloc_pessimistic [14:40:29] [PASSED] drm_test_buddy_alloc_pathological [14:40:29] [PASSED] drm_test_buddy_alloc_contiguous [14:40:29] [PASSED] drm_test_buddy_alloc_clear [14:40:29] [PASSED] drm_test_buddy_alloc_range_bias [14:40:29] ==================== [PASSED] drm_buddy ==================== [14:40:29] ============= drm_cmdline_parser (40 subtests) ============= [14:40:29] [PASSED] drm_test_cmdline_force_d_only [14:40:29] [PASSED] drm_test_cmdline_force_D_only_dvi [14:40:29] [PASSED] drm_test_cmdline_force_D_only_hdmi [14:40:29] [PASSED] drm_test_cmdline_force_D_only_not_digital [14:40:29] [PASSED] drm_test_cmdline_force_e_only [14:40:29] [PASSED] drm_test_cmdline_res [14:40:29] [PASSED] drm_test_cmdline_res_vesa [14:40:29] [PASSED] drm_test_cmdline_res_vesa_rblank [14:40:29] [PASSED] drm_test_cmdline_res_rblank [14:40:29] [PASSED] drm_test_cmdline_res_bpp [14:40:29] [PASSED] drm_test_cmdline_res_refresh [14:40:29] [PASSED] drm_test_cmdline_res_bpp_refresh [14:40:29] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced [14:40:29] [PASSED] drm_test_cmdline_res_bpp_refresh_margins [14:40:29] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off [14:40:29] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on [14:40:29] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog [14:40:29] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital [14:40:29] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on [14:40:29] [PASSED] drm_test_cmdline_res_margins_force_on [14:40:29] [PASSED] drm_test_cmdline_res_vesa_margins [14:40:29] [PASSED] drm_test_cmdline_name [14:40:29] [PASSED] drm_test_cmdline_name_bpp [14:40:29] [PASSED] drm_test_cmdline_name_option [14:40:29] [PASSED] drm_test_cmdline_name_bpp_option [14:40:29] [PASSED] drm_test_cmdline_rotate_0 [14:40:29] [PASSED] drm_test_cmdline_rotate_90 [14:40:29] [PASSED] drm_test_cmdline_rotate_180 [14:40:29] [PASSED] drm_test_cmdline_rotate_270 [14:40:29] [PASSED] drm_test_cmdline_hmirror [14:40:29] [PASSED] drm_test_cmdline_vmirror [14:40:29] [PASSED] drm_test_cmdline_margin_options [14:40:29] [PASSED] drm_test_cmdline_multiple_options [14:40:29] [PASSED] drm_test_cmdline_bpp_extra_and_option [14:40:29] [PASSED] drm_test_cmdline_extra_and_option [14:40:29] [PASSED] drm_test_cmdline_freestanding_options [14:40:29] [PASSED] drm_test_cmdline_freestanding_force_e_and_options [14:40:29] [PASSED] drm_test_cmdline_panel_orientation [14:40:29] ================ drm_test_cmdline_invalid ================= [14:40:29] [PASSED] margin_only [14:40:29] [PASSED] interlace_only [14:40:29] [PASSED] res_missing_x [14:40:29] [PASSED] res_missing_y [14:40:29] [PASSED] res_bad_y [14:40:29] [PASSED] res_missing_y_bpp [14:40:29] [PASSED] res_bad_bpp [14:40:29] [PASSED] res_bad_refresh [14:40:29] [PASSED] res_bpp_refresh_force_on_off [14:40:29] [PASSED] res_invalid_mode [14:40:29] [PASSED] res_bpp_wrong_place_mode [14:40:29] [PASSED] name_bpp_refresh [14:40:29] [PASSED] name_refresh [14:40:29] [PASSED] name_refresh_wrong_mode [14:40:29] [PASSED] name_refresh_invalid_mode [14:40:29] [PASSED] rotate_multiple [14:40:29] [PASSED] rotate_invalid_val [14:40:29] [PASSED] rotate_truncated [14:40:29] [PASSED] invalid_option [14:40:29] [PASSED] invalid_tv_option [14:40:29] [PASSED] truncated_tv_option [14:40:29] ============ [PASSED] drm_test_cmdline_invalid ============= [14:40:29] =============== drm_test_cmdline_tv_options =============== [14:40:29] [PASSED] NTSC [14:40:29] [PASSED] NTSC_443 [14:40:29] [PASSED] NTSC_J [14:40:29] [PASSED] PAL [14:40:29] [PASSED] PAL_M [14:40:29] [PASSED] PAL_N [14:40:29] [PASSED] SECAM [14:40:29] [PASSED] MONO_525 [14:40:29] [PASSED] MONO_625 [14:40:29] =========== [PASSED] drm_test_cmdline_tv_options =========== [14:40:29] =============== [PASSED] drm_cmdline_parser ================ [14:40:29] ========== drmm_connector_hdmi_init (19 subtests) ========== [14:40:29] [PASSED] drm_test_connector_hdmi_init_valid [14:40:29] [PASSED] drm_test_connector_hdmi_init_bpc_8 [14:40:29] [PASSED] drm_test_connector_hdmi_init_bpc_10 [14:40:29] [PASSED] drm_test_connector_hdmi_init_bpc_12 [14:40:29] [PASSED] drm_test_connector_hdmi_init_bpc_invalid [14:40:29] [PASSED] drm_test_connector_hdmi_init_bpc_null [14:40:29] [PASSED] drm_test_connector_hdmi_init_formats_empty [14:40:29] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb [14:40:29] [PASSED] drm_test_connector_hdmi_init_null_ddc [14:40:29] [PASSED] drm_test_connector_hdmi_init_null_product [14:40:29] [PASSED] drm_test_connector_hdmi_init_null_vendor [14:40:29] [PASSED] drm_test_connector_hdmi_init_product_length_exact [14:40:29] [PASSED] drm_test_connector_hdmi_init_product_length_too_long [14:40:29] [PASSED] drm_test_connector_hdmi_init_product_valid [14:40:29] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact [14:40:29] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long [14:40:29] [PASSED] drm_test_connector_hdmi_init_vendor_valid [14:40:29] ========= drm_test_connector_hdmi_init_type_valid ========= [14:40:29] [PASSED] HDMI-A [14:40:29] [PASSED] HDMI-B [14:40:29] ===== [PASSED] drm_test_connector_hdmi_init_type_valid ===== [14:40:29] ======== drm_test_connector_hdmi_init_type_invalid ======== [14:40:29] [PASSED] Unknown [14:40:29] [PASSED] VGA [14:40:29] [PASSED] DVI-I [14:40:29] [PASSED] DVI-D [14:40:29] [PASSED] DVI-A [14:40:29] [PASSED] Composite [14:40:29] [PASSED] SVIDEO [14:40:29] [PASSED] LVDS [14:40:29] [PASSED] Component [14:40:29] [PASSED] DIN [14:40:29] [PASSED] DP [14:40:29] [PASSED] TV [14:40:29] [PASSED] eDP [14:40:29] [PASSED] Virtual [14:40:29] [PASSED] DSI [14:40:29] [PASSED] DPI [14:40:29] [PASSED] Writeback [14:40:29] [PASSED] SPI [14:40:29] [PASSED] USB [14:40:29] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ==== [14:40:29] ============ [PASSED] drmm_connector_hdmi_init ============= [14:40:29] ============= drmm_connector_init (3 subtests) ============= [14:40:29] [PASSED] drm_test_drmm_connector_init [14:40:29] [PASSED] drm_test_drmm_connector_init_null_ddc [14:40:29] ========= drm_test_drmm_connector_init_type_valid ========= [14:40:29] [PASSED] Unknown [14:40:29] [PASSED] VGA [14:40:29] [PASSED] DVI-I [14:40:29] [PASSED] DVI-D [14:40:29] [PASSED] DVI-A [14:40:29] [PASSED] Composite [14:40:29] [PASSED] SVIDEO [14:40:29] [PASSED] LVDS [14:40:29] [PASSED] Component [14:40:29] [PASSED] DIN [14:40:29] [PASSED] DP [14:40:29] [PASSED] HDMI-A [14:40:29] [PASSED] HDMI-B [14:40:29] [PASSED] TV [14:40:29] [PASSED] eDP [14:40:29] [PASSED] Virtual [14:40:29] [PASSED] DSI [14:40:29] [PASSED] DPI [14:40:29] [PASSED] Writeback [14:40:29] [PASSED] SPI [14:40:29] [PASSED] USB [14:40:29] ===== [PASSED] drm_test_drmm_connector_init_type_valid ===== [14:40:29] =============== [PASSED] drmm_connector_init =============== [14:40:29] = drm_connector_attach_broadcast_rgb_property (2 subtests) = [14:40:29] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property [14:40:29] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector [14:40:29] === [PASSED] drm_connector_attach_broadcast_rgb_property === [14:40:29] ========== drm_get_tv_mode_from_name (2 subtests) ========== [14:40:29] ========== drm_test_get_tv_mode_from_name_valid =========== [14:40:29] [PASSED] NTSC [14:40:29] [PASSED] NTSC-443 [14:40:29] [PASSED] NTSC-J [14:40:29] [PASSED] PAL [14:40:29] [PASSED] PAL-M [14:40:29] [PASSED] PAL-N [14:40:29] [PASSED] SECAM [14:40:29] [PASSED] Mono [14:40:29] ====== [PASSED] drm_test_get_tv_mode_from_name_valid ======= [14:40:29] [PASSED] drm_test_get_tv_mode_from_name_truncated [14:40:29] ============ [PASSED] drm_get_tv_mode_from_name ============ [14:40:29] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) = [14:40:29] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb [14:40:29] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc [14:40:29] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1 [14:40:29] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc [14:40:29] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1 [14:40:29] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double [14:40:29] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid = [14:40:29] [PASSED] VIC 96 [14:40:29] [PASSED] VIC 97 [14:40:29] [PASSED] VIC 101 [14:40:29] [PASSED] VIC 102 [14:40:29] [PASSED] VIC 106 [14:40:29] [PASSED] VIC 107 [14:40:29] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid === [14:40:29] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc [14:40:29] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc [14:40:29] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc [14:40:29] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc [14:40:29] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc [14:40:29] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ==== [14:40:29] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) == [14:40:29] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ==== [14:40:29] [PASSED] Automatic [14:40:29] [PASSED] Full [14:40:29] [PASSED] Limited 16:235 [14:40:29] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name === [14:40:29] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid [14:40:29] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ==== [14:40:29] == drm_hdmi_connector_get_output_format_name (2 subtests) == [14:40:29] === drm_test_drm_hdmi_connector_get_output_format_name ==== [14:40:29] [PASSED] RGB [14:40:29] [PASSED] YUV 4:2:0 [14:40:29] [PASSED] YUV 4:2:2 [14:40:29] [PASSED] YUV 4:4:4 [14:40:29] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name === [14:40:29] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid [14:40:29] ==== [PASSED] drm_hdmi_connector_get_output_format_name ==== [14:40:29] ============= drm_damage_helper (21 subtests) ============== [14:40:29] [PASSED] drm_test_damage_iter_no_damage [14:40:29] [PASSED] drm_test_damage_iter_no_damage_fractional_src [14:40:29] [PASSED] drm_test_damage_iter_no_damage_src_moved [14:40:29] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved [14:40:29] [PASSED] drm_test_damage_iter_no_damage_not_visible [14:40:29] [PASSED] drm_test_damage_iter_no_damage_no_crtc [14:40:29] [PASSED] drm_test_damage_iter_no_damage_no_fb [14:40:29] [PASSED] drm_test_damage_iter_simple_damage [14:40:29] [PASSED] drm_test_damage_iter_single_damage [14:40:29] [PASSED] drm_test_damage_iter_single_damage_intersect_src [14:40:29] [PASSED] drm_test_damage_iter_single_damage_outside_src [14:40:29] [PASSED] drm_test_damage_iter_single_damage_fractional_src [14:40:29] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src [14:40:29] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src [14:40:29] [PASSED] drm_test_damage_iter_single_damage_src_moved [14:40:29] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved [14:40:29] [PASSED] drm_test_damage_iter_damage [14:40:29] [PASSED] drm_test_damage_iter_damage_one_intersect [14:40:29] [PASSED] drm_test_damage_iter_damage_one_outside [14:40:29] [PASSED] drm_test_damage_iter_damage_src_moved [14:40:29] [PASSED] drm_test_damage_iter_damage_not_visible [14:40:29] ================ [PASSED] drm_damage_helper ================ [14:40:29] ============== drm_dp_mst_helper (3 subtests) ============== [14:40:29] ============== drm_test_dp_mst_calc_pbn_mode ============== [14:40:29] [PASSED] Clock 154000 BPP 30 DSC disabled [14:40:29] [PASSED] Clock 234000 BPP 30 DSC disabled [14:40:29] [PASSED] Clock 297000 BPP 24 DSC disabled [14:40:29] [PASSED] Clock 332880 BPP 24 DSC enabled [14:40:29] [PASSED] Clock 324540 BPP 24 DSC enabled [14:40:29] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ========== [14:40:29] ============== drm_test_dp_mst_calc_pbn_div =============== [14:40:29] [PASSED] Link rate 2000000 lane count 4 [14:40:29] [PASSED] Link rate 2000000 lane count 2 [14:40:29] [PASSED] Link rate 2000000 lane count 1 [14:40:29] [PASSED] Link rate 1350000 lane count 4 [14:40:29] [PASSED] Link rate 1350000 lane count 2 [14:40:29] [PASSED] Link rate 1350000 lane count 1 [14:40:29] [PASSED] Link rate 1000000 lane count 4 [14:40:29] [PASSED] Link rate 1000000 lane count 2 [14:40:29] [PASSED] Link rate 1000000 lane count 1 [14:40:29] [PASSED] Link rate 810000 lane count 4 [14:40:29] [PASSED] Link rate 810000 lane count 2 [14:40:29] [PASSED] Link rate 810000 lane count 1 [14:40:29] [PASSED] Link rate 540000 lane count 4 [14:40:29] [PASSED] Link rate 540000 lane count 2 [14:40:29] [PASSED] Link rate 540000 lane count 1 [14:40:29] [PASSED] Link rate 270000 lane count 4 [14:40:29] [PASSED] Link rate 270000 lane count 2 [14:40:29] [PASSED] Link rate 270000 lane count 1 [14:40:29] [PASSED] Link rate 162000 lane count 4 [14:40:29] [PASSED] Link rate 162000 lane count 2 [14:40:29] [PASSED] Link rate 162000 lane count 1 [14:40:29] ========== [PASSED] drm_test_dp_mst_calc_pbn_div =========== [14:40:29] ========= drm_test_dp_mst_sideband_msg_req_decode ========= [14:40:29] [PASSED] DP_ENUM_PATH_RESOURCES with port number [14:40:29] [PASSED] DP_POWER_UP_PHY with port number [14:40:29] [PASSED] DP_POWER_DOWN_PHY with port number [14:40:29] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks [14:40:29] [PASSED] DP_ALLOCATE_PAYLOAD with port number [14:40:29] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI [14:40:29] [PASSED] DP_ALLOCATE_PAYLOAD with PBN [14:40:29] [PASSED] DP_QUERY_PAYLOAD with port number [14:40:29] [PASSED] DP_QUERY_PAYLOAD with VCPI [14:40:29] [PASSED] DP_REMOTE_DPCD_READ with port number [14:40:29] [PASSED] DP_REMOTE_DPCD_READ with DPCD address [14:40:29] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes [14:40:29] [PASSED] DP_REMOTE_DPCD_WRITE with port number [14:40:29] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address [14:40:29] [PASSED] DP_REMOTE_DPCD_WRITE with data array [14:40:29] [PASSED] DP_REMOTE_I2C_READ with port number [14:40:29] [PASSED] DP_REMOTE_I2C_READ with I2C device ID [14:40:29] [PASSED] DP_REMOTE_I2C_READ with transactions array [14:40:29] [PASSED] DP_REMOTE_I2C_WRITE with port number [14:40:29] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID [14:40:29] [PASSED] DP_REMOTE_I2C_WRITE with data array [14:40:29] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID [14:40:29] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID [14:40:29] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event [14:40:29] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event [14:40:29] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior [14:40:29] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior [14:40:29] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode ===== [14:40:29] ================ [PASSED] drm_dp_mst_helper ================ [14:40:29] ================== drm_exec (7 subtests) =================== [14:40:29] [PASSED] sanitycheck [14:40:29] [PASSED] test_lock [14:40:29] [PASSED] test_lock_unlock [14:40:29] [PASSED] test_duplicates [14:40:29] [PASSED] test_prepare [14:40:29] [PASSED] test_prepare_array [14:40:29] [PASSED] test_multiple_loops [14:40:29] ==================== [PASSED] drm_exec ===================== [14:40:29] =========== drm_format_helper_test (17 subtests) =========== [14:40:29] ============== drm_test_fb_xrgb8888_to_gray8 ============== [14:40:29] [PASSED] single_pixel_source_buffer [14:40:29] [PASSED] single_pixel_clip_rectangle [14:40:29] [PASSED] well_known_colors [14:40:29] [PASSED] destination_pitch [14:40:29] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ========== [14:40:29] ============= drm_test_fb_xrgb8888_to_rgb332 ============== [14:40:29] [PASSED] single_pixel_source_buffer [14:40:29] [PASSED] single_pixel_clip_rectangle [14:40:29] [PASSED] well_known_colors [14:40:29] [PASSED] destination_pitch [14:40:29] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ========== [14:40:29] ============= drm_test_fb_xrgb8888_to_rgb565 ============== [14:40:29] [PASSED] single_pixel_source_buffer [14:40:29] [PASSED] single_pixel_clip_rectangle [14:40:29] [PASSED] well_known_colors [14:40:29] [PASSED] destination_pitch [14:40:29] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ========== [14:40:29] ============ drm_test_fb_xrgb8888_to_xrgb1555 ============= [14:40:29] [PASSED] single_pixel_source_buffer [14:40:29] [PASSED] single_pixel_clip_rectangle [14:40:29] [PASSED] well_known_colors [14:40:29] [PASSED] destination_pitch [14:40:29] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 ========= [14:40:29] ============ drm_test_fb_xrgb8888_to_argb1555 ============= [14:40:29] [PASSED] single_pixel_source_buffer [14:40:29] [PASSED] single_pixel_clip_rectangle [14:40:29] [PASSED] well_known_colors [14:40:29] [PASSED] destination_pitch [14:40:29] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 ========= [14:40:29] ============ drm_test_fb_xrgb8888_to_rgba5551 ============= [14:40:29] [PASSED] single_pixel_source_buffer [14:40:29] [PASSED] single_pixel_clip_rectangle [14:40:29] [PASSED] well_known_colors [14:40:29] [PASSED] destination_pitch [14:40:29] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 ========= [14:40:29] ============= drm_test_fb_xrgb8888_to_rgb888 ============== [14:40:29] [PASSED] single_pixel_source_buffer [14:40:29] [PASSED] single_pixel_clip_rectangle [14:40:29] [PASSED] well_known_colors [14:40:29] [PASSED] destination_pitch [14:40:29] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ========== [14:40:29] ============ drm_test_fb_xrgb8888_to_argb8888 ============= [14:40:29] [PASSED] single_pixel_source_buffer [14:40:29] [PASSED] single_pixel_clip_rectangle [14:40:29] [PASSED] well_known_colors [14:40:29] [PASSED] destination_pitch [14:40:29] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 ========= [14:40:29] =========== drm_test_fb_xrgb8888_to_xrgb2101010 =========== [14:40:29] [PASSED] single_pixel_source_buffer [14:40:29] [PASSED] single_pixel_clip_rectangle [14:40:29] [PASSED] well_known_colors [14:40:29] [PASSED] destination_pitch [14:40:29] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 ======= [14:40:29] =========== drm_test_fb_xrgb8888_to_argb2101010 =========== [14:40:29] [PASSED] single_pixel_source_buffer [14:40:29] [PASSED] single_pixel_clip_rectangle [14:40:29] [PASSED] well_known_colors [14:40:29] [PASSED] destination_pitch [14:40:29] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 ======= [14:40:29] ============== drm_test_fb_xrgb8888_to_mono =============== [14:40:29] [PASSED] single_pixel_source_buffer [14:40:29] [PASSED] single_pixel_clip_rectangle [14:40:29] [PASSED] well_known_colors [14:40:29] [PASSED] destination_pitch [14:40:29] ========== [PASSED] drm_test_fb_xrgb8888_to_mono =========== [14:40:29] ==================== drm_test_fb_swab ===================== [14:40:29] [PASSED] single_pixel_source_buffer [14:40:29] [PASSED] single_pixel_clip_rectangle [14:40:29] [PASSED] well_known_colors [14:40:29] [PASSED] destination_pitch [14:40:29] ================ [PASSED] drm_test_fb_swab ================= [14:40:29] ============ drm_test_fb_xrgb8888_to_xbgr8888 ============= [14:40:29] [PASSED] single_pixel_source_buffer [14:40:29] [PASSED] single_pixel_clip_rectangle [14:40:29] [PASSED] well_known_colors [14:40:29] [PASSED] destination_pitch [14:40:29] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 ========= [14:40:29] ============ drm_test_fb_xrgb8888_to_abgr8888 ============= [14:40:29] [PASSED] single_pixel_source_buffer [14:40:29] [PASSED] single_pixel_clip_rectangle [14:40:29] [PASSED] well_known_colors [14:40:29] [PASSED] destination_pitch [14:40:29] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 ========= [14:40:29] ================= drm_test_fb_clip_offset ================= [14:40:29] [PASSED] pass through [14:40:29] [PASSED] horizontal offset [14:40:29] [PASSED] vertical offset [14:40:29] [PASSED] horizontal and vertical offset [14:40:29] [PASSED] horizontal offset (custom pitch) [14:40:29] [PASSED] vertical offset (custom pitch) [14:40:29] [PASSED] horizontal and vertical offset (custom pitch) [14:40:29] ============= [PASSED] drm_test_fb_clip_offset ============= [14:40:29] ============== drm_test_fb_build_fourcc_list ============== [14:40:29] [PASSED] no native formats [14:40:29] [PASSED] XRGB8888 as native format [14:40:29] [PASSED] remove duplicates [14:40:29] [PASSED] convert alpha formats [14:40:29] [PASSED] random formats [14:40:29] ========== [PASSED] drm_test_fb_build_fourcc_list ========== [14:40:29] =================== drm_test_fb_memcpy ==================== [14:40:29] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258) [14:40:29] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258) [14:40:29] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559) [14:40:29] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258) [14:40:29] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258) [14:40:29] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559) [14:40:29] [PASSED] well_known_colors: XB24 little-endian (0x34324258) [14:40:29] [PASSED] well_known_colors: XRA8 little-endian (0x38415258) [14:40:29] [PASSED] well_known_colors: YU24 little-endian (0x34325559) [14:40:29] [PASSED] destination_pitch: XB24 little-endian (0x34324258) [14:40:29] [PASSED] destination_pitch: XRA8 little-endian (0x38415258) [14:40:29] [PASSED] destination_pitch: YU24 little-endian (0x34325559) [14:40:29] =============== [PASSED] drm_test_fb_memcpy ================ [14:40:29] ============= [PASSED] drm_format_helper_test ============== [14:40:29] ================= drm_format (18 subtests) ================= [14:40:29] [PASSED] drm_test_format_block_width_invalid [14:40:29] [PASSED] drm_test_format_block_width_one_plane [14:40:29] [PASSED] drm_test_format_block_width_two_plane [14:40:29] [PASSED] drm_test_format_block_width_three_plane [14:40:29] [PASSED] drm_test_format_block_width_tiled [14:40:29] [PASSED] drm_test_format_block_height_invalid [14:40:29] [PASSED] drm_test_format_block_height_one_plane [14:40:29] [PASSED] drm_test_format_block_height_two_plane [14:40:29] [PASSED] drm_test_format_block_height_three_plane [14:40:29] [PASSED] drm_test_format_block_height_tiled [14:40:29] [PASSED] drm_test_format_min_pitch_invalid [14:40:29] [PASSED] drm_test_format_min_pitch_one_plane_8bpp [14:40:29] [PASSED] drm_test_format_min_pitch_one_plane_16bpp [14:40:29] [PASSED] drm_test_format_min_pitch_one_plane_24bpp [14:40:29] [PASSED] drm_test_format_min_pitch_one_plane_32bpp [14:40:29] [PASSED] drm_test_format_min_pitch_two_plane [14:40:29] [PASSED] drm_test_format_min_pitch_three_plane_8bpp [14:40:29] [PASSED] drm_test_format_min_pitch_tiled [14:40:29] =================== [PASSED] drm_format ==================== [14:40:29] =============== drm_framebuffer (1 subtest) ================ [14:40:29] =============== drm_test_framebuffer_create =============== [14:40:29] [PASSED] ABGR8888 normal sizes [14:40:29] [PASSED] ABGR8888 max sizes [14:40:29] [PASSED] ABGR8888 pitch greater than min required [14:40:29] [PASSED] ABGR8888 pitch less than min required [14:40:29] [PASSED] ABGR8888 Invalid width [14:40:29] [PASSED] ABGR8888 Invalid buffer handle [14:40:29] [PASSED] No pixel format [14:40:29] [PASSED] ABGR8888 Width 0 [14:40:29] [PASSED] ABGR8888 Height 0 [14:40:29] [PASSED] ABGR8888 Out of bound height * pitch combination [14:40:29] [PASSED] ABGR8888 Large buffer offset [14:40:29] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers [14:40:29] [PASSED] ABGR8888 Valid buffer modifier [14:40:29] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE) [14:40:29] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS [14:40:29] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS [14:40:29] [PASSED] NV12 Normal sizes [14:40:29] [PASSED] NV12 Max sizes [14:40:29] [PASSED] NV12 Invalid pitch [14:40:29] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag [14:40:29] [PASSED] NV12 different modifier per-plane [14:40:29] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE [14:40:29] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS [14:40:29] [PASSED] NV12 Modifier for inexistent plane [14:40:29] [PASSED] NV12 Handle for inexistent plane [14:40:29] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS [14:40:29] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier [14:40:29] [PASSED] YVU420 Normal sizes [14:40:29] [PASSED] YVU420 Max sizes [14:40:29] [PASSED] YVU420 Invalid pitch [14:40:29] [PASSED] YVU420 Different pitches [14:40:29] [PASSED] YVU420 Different buffer offsets/pitches [14:40:29] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS [14:40:29] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS [14:40:29] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS [14:40:29] [PASSED] YVU420 Valid modifier [14:40:29] [PASSED] YVU420 Different modifiers per plane [14:40:29] [PASSED] YVU420 Modifier for inexistent plane [14:40:29] [PASSED] X0L2 Normal sizes [14:40:29] [PASSED] X0L2 Max sizes [14:40:29] [PASSED] X0L2 Invalid pitch [14:40:29] [PASSED] X0L2 Pitch greater than minimum required [14:40:29] [PASSED] X0L2 Handle for inexistent plane [14:40:29] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set [14:40:29] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set [14:40:29] [PASSED] X0L2 Valid modifier [14:40:29] [PASSED] X0L2 Modifier for inexistent plane [14:40:29] =========== [PASSED] drm_test_framebuffer_create =========== [14:40:29] ================= [PASSED] drm_framebuffer ================= [14:40:29] ================ drm_gem_shmem (8 subtests) ================ [14:40:29] [PASSED] drm_gem_shmem_test_obj_create [14:40:29] [PASSED] drm_gem_shmem_test_obj_create_private [14:40:29] [PASSED] drm_gem_shmem_test_pin_pages [14:40:29] [PASSED] drm_gem_shmem_test_vmap [14:40:29] [PASSED] drm_gem_shmem_test_get_pages_sgt [14:40:29] [PASSED] drm_gem_shmem_test_get_sg_table [14:40:29] [PASSED] drm_gem_shmem_test_madvise [14:40:29] [PASSED] drm_gem_shmem_test_purge [14:40:29] ================== [PASSED] drm_gem_shmem ================== [14:40:29] === drm_atomic_helper_connector_hdmi_check (22 subtests) === [14:40:29] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode [14:40:29] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1 [14:40:29] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode [14:40:29] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1 [14:40:29] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode [14:40:29] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1 [14:40:29] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed [14:40:29] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed [14:40:29] [PASSED] drm_test_check_hdmi_funcs_reject_rate [14:40:29] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback [14:40:29] [PASSED] drm_test_check_max_tmds_rate_format_fallback [14:40:29] [PASSED] drm_test_check_output_bpc_crtc_mode_changed [14:40:29] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed [14:40:29] [PASSED] drm_test_check_output_bpc_dvi [14:40:29] [PASSED] drm_test_check_output_bpc_format_vic_1 [14:40:29] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only [14:40:29] [PASSED] drm_test_check_output_bpc_format_display_rgb_only [14:40:29] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only [14:40:29] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only [14:40:29] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc [14:40:29] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc [14:40:29] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc [14:40:29] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ====== [14:40:29] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ==== [14:40:29] [PASSED] drm_test_check_broadcast_rgb_value [14:40:29] [PASSED] drm_test_check_bpc_8_value [14:40:29] [PASSED] drm_test_check_bpc_10_value [14:40:29] [PASSED] drm_test_check_bpc_12_value [14:40:29] [PASSED] drm_test_check_format_value [14:40:29] [PASSED] drm_test_check_tmds_char_value [14:40:29] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ====== [14:40:29] ================= drm_managed (2 subtests) ================= [14:40:29] [PASSED] drm_test_managed_release_action [14:40:29] [PASSED] drm_test_managed_run_action [14:40:29] =================== [PASSED] drm_managed =================== [14:40:29] =================== drm_mm (6 subtests) ==================== [14:40:29] [PASSED] drm_test_mm_init [14:40:29] [PASSED] drm_test_mm_debug [14:40:29] [PASSED] drm_test_mm_align32 [14:40:29] [PASSED] drm_test_mm_align64 [14:40:29] [PASSED] drm_test_mm_lowest [14:40:29] [PASSED] drm_test_mm_highest [14:40:29] ===================== [PASSED] drm_mm ====================== [14:40:29] ============= drm_modes_analog_tv (5 subtests) ============= [14:40:29] [PASSED] drm_test_modes_analog_tv_mono_576i [14:40:29] [PASSED] drm_test_modes_analog_tv_ntsc_480i [14:40:29] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined [14:40:29] [PASSED] drm_test_modes_analog_tv_pal_576i [14:40:29] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined [14:40:29] =============== [PASSED] drm_modes_analog_tv =============== [14:40:29] ============== drm_plane_helper (2 subtests) =============== [14:40:29] =============== drm_test_check_plane_state ================ [14:40:29] [PASSED] clipping_simple [14:40:29] [PASSED] clipping_rotate_reflect [14:40:29] [PASSED] positioning_simple [14:40:29] [PASSED] upscaling [14:40:29] [PASSED] downscaling [14:40:29] [PASSED] rounding1 [14:40:29] [PASSED] rounding2 [14:40:29] [PASSED] rounding3 [14:40:29] [PASSED] rounding4 [14:40:29] =========== [PASSED] drm_test_check_plane_state ============ [14:40:29] =========== drm_test_check_invalid_plane_state ============ [14:40:29] [PASSED] positioning_invalid [14:40:29] [PASSED] upscaling_invalid stty: 'standard input': Inappropriate ioctl for device [14:40:29] [PASSED] downscaling_invalid [14:40:29] ======= [PASSED] drm_test_check_invalid_plane_state ======== [14:40:29] ================ [PASSED] drm_plane_helper ================= [14:40:29] ====== drm_connector_helper_tv_get_modes (1 subtest) ======= [14:40:29] ====== drm_test_connector_helper_tv_get_modes_check ======= [14:40:29] [PASSED] None [14:40:29] [PASSED] PAL [14:40:29] [PASSED] NTSC [14:40:29] [PASSED] Both, NTSC Default [14:40:29] [PASSED] Both, PAL Default [14:40:29] [PASSED] Both, NTSC Default, with PAL on command-line [14:40:29] [PASSED] Both, PAL Default, with NTSC on command-line [14:40:29] == [PASSED] drm_test_connector_helper_tv_get_modes_check === [14:40:29] ======== [PASSED] drm_connector_helper_tv_get_modes ======== [14:40:29] ================== drm_rect (9 subtests) =================== [14:40:29] [PASSED] drm_test_rect_clip_scaled_div_by_zero [14:40:29] [PASSED] drm_test_rect_clip_scaled_not_clipped [14:40:29] [PASSED] drm_test_rect_clip_scaled_clipped [14:40:29] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned [14:40:29] ================= drm_test_rect_intersect ================= [14:40:29] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0 [14:40:29] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1 [14:40:29] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0 [14:40:29] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1 [14:40:29] [PASSED] right x left: 2x1+0+0 x 3x1+1+0 [14:40:29] [PASSED] left x right: 3x1+1+0 x 2x1+0+0 [14:40:29] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1 [14:40:29] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0 [14:40:29] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1 [14:40:29] [PASSED] touching side: 1x1+0+0 x 1x1+1+0 [14:40:29] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0 [14:40:29] [PASSED] inside another: 2x2+0+0 x 1x1+1+1 [14:40:29] [PASSED] far away: 1x1+0+0 x 1x1+3+6 [14:40:29] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10 [14:40:29] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10 [14:40:29] ============= [PASSED] drm_test_rect_intersect ============= [14:40:29] ================ drm_test_rect_calc_hscale ================ [14:40:29] [PASSED] normal use [14:40:29] [PASSED] out of max range [14:40:29] [PASSED] out of min range [14:40:29] [PASSED] zero dst [14:40:29] [PASSED] negative src [14:40:29] [PASSED] negative dst [14:40:29] ============ [PASSED] drm_test_rect_calc_hscale ============ [14:40:29] ================ drm_test_rect_calc_vscale ================ [14:40:29] [PASSED] normal use [14:40:29] [PASSED] out of max range [14:40:29] [PASSED] out of min range [14:40:29] [PASSED] zero dst [14:40:29] [PASSED] negative src [14:40:29] [PASSED] negative dst [14:40:29] ============ [PASSED] drm_test_rect_calc_vscale ============ [14:40:29] ================== drm_test_rect_rotate =================== [14:40:29] [PASSED] reflect-x [14:40:29] [PASSED] reflect-y [14:40:29] [PASSED] rotate-0 [14:40:29] [PASSED] rotate-90 [14:40:29] [PASSED] rotate-180 [14:40:29] [PASSED] rotate-270 [14:40:29] ============== [PASSED] drm_test_rect_rotate =============== [14:40:29] ================ drm_test_rect_rotate_inv ================= [14:40:29] [PASSED] reflect-x [14:40:29] [PASSED] reflect-y [14:40:29] [PASSED] rotate-0 [14:40:29] [PASSED] rotate-90 [14:40:29] [PASSED] rotate-180 [14:40:29] [PASSED] rotate-270 [14:40:29] ============ [PASSED] drm_test_rect_rotate_inv ============= [14:40:29] ==================== [PASSED] drm_rect ===================== [14:40:29] ============================================================ [14:40:29] Testing complete. Ran 515 tests: passed: 515 [14:40:29] Elapsed time: 24.860s total, 2.264s configuring, 22.375s building, 0.203s running + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig [14:40:30] Configuring KUnit Kernel ... Regenerating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [14:40:31] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make ARCH=um O=.kunit --jobs=48 [14:40:41] Starting KUnit Kernel (1/1)... [14:40:41] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [14:40:41] ================= ttm_device (5 subtests) ================== [14:40:41] [PASSED] ttm_device_init_basic [14:40:41] [PASSED] ttm_device_init_multiple [14:40:41] [PASSED] ttm_device_fini_basic [14:40:41] [PASSED] ttm_device_init_no_vma_man [14:40:41] ================== ttm_device_init_pools ================== [14:40:41] [PASSED] No DMA allocations, no DMA32 required [14:40:41] [PASSED] DMA allocations, DMA32 required [14:40:41] [PASSED] No DMA allocations, DMA32 required [14:40:41] [PASSED] DMA allocations, no DMA32 required [14:40:41] ============== [PASSED] ttm_device_init_pools ============== [14:40:41] =================== [PASSED] ttm_device ==================== [14:40:41] ================== ttm_pool (8 subtests) =================== [14:40:41] ================== ttm_pool_alloc_basic =================== [14:40:41] [PASSED] One page [14:40:41] [PASSED] More than one page [14:40:41] [PASSED] Above the allocation limit [14:40:41] [PASSED] One page, with coherent DMA mappings enabled [14:40:41] [PASSED] Above the allocation limit, with coherent DMA mappings enabled [14:40:41] ============== [PASSED] ttm_pool_alloc_basic =============== [14:40:41] ============== ttm_pool_alloc_basic_dma_addr ============== [14:40:41] [PASSED] One page [14:40:41] [PASSED] More than one page [14:40:41] [PASSED] Above the allocation limit [14:40:41] [PASSED] One page, with coherent DMA mappings enabled [14:40:41] [PASSED] Above the allocation limit, with coherent DMA mappings enabled [14:40:41] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ========== [14:40:41] [PASSED] ttm_pool_alloc_order_caching_match [14:40:41] [PASSED] ttm_pool_alloc_caching_mismatch [14:40:41] [PASSED] ttm_pool_alloc_order_mismatch [14:40:41] [PASSED] ttm_pool_free_dma_alloc [14:40:41] [PASSED] ttm_pool_free_no_dma_alloc [14:40:41] [PASSED] ttm_pool_fini_basic [14:40:41] ==================== [PASSED] ttm_pool ===================== [14:40:41] ================ ttm_resource (8 subtests) ================= [14:40:41] ================= ttm_resource_init_basic ================= [14:40:41] [PASSED] Init resource in TTM_PL_SYSTEM [14:40:41] [PASSED] Init resource in TTM_PL_VRAM [14:40:41] [PASSED] Init resource in a private placement [14:40:41] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags [14:40:41] ============= [PASSED] ttm_resource_init_basic ============= [14:40:41] [PASSED] ttm_resource_init_pinned [14:40:41] [PASSED] ttm_resource_fini_basic [14:40:41] [PASSED] ttm_resource_manager_init_basic [14:40:41] [PASSED] ttm_resource_manager_usage_basic [14:40:41] [PASSED] ttm_resource_manager_set_used_basic [14:40:41] [PASSED] ttm_sys_man_alloc_basic [14:40:41] [PASSED] ttm_sys_man_free_basic [14:40:41] ================== [PASSED] ttm_resource =================== [14:40:41] =================== ttm_tt (15 subtests) =================== [14:40:41] ==================== ttm_tt_init_basic ==================== [14:40:41] [PASSED] Page-aligned size [14:40:41] [PASSED] Extra pages requested [14:40:41] ================ [PASSED] ttm_tt_init_basic ================ [14:40:41] [PASSED] ttm_tt_init_misaligned [14:40:41] [PASSED] ttm_tt_fini_basic [14:40:41] [PASSED] ttm_tt_fini_sg [14:40:41] [PASSED] ttm_tt_fini_shmem [14:40:41] [PASSED] ttm_tt_create_basic [14:40:41] [PASSED] ttm_tt_create_invalid_bo_type [14:40:41] [PASSED] ttm_tt_create_ttm_exists [14:40:41] [PASSED] ttm_tt_create_failed [14:40:41] [PASSED] ttm_tt_destroy_basic [14:40:41] [PASSED] ttm_tt_populate_null_ttm [14:40:41] [PASSED] ttm_tt_populate_populated_ttm [14:40:41] [PASSED] ttm_tt_unpopulate_basic [14:40:41] [PASSED] ttm_tt_unpopulate_empty_ttm [14:40:41] [PASSED] ttm_tt_swapin_basic [14:40:41] ===================== [PASSED] ttm_tt ====================== [14:40:41] =================== ttm_bo (14 subtests) =================== [14:40:41] =========== ttm_bo_reserve_optimistic_no_ticket =========== [14:40:41] [PASSED] Cannot be interrupted and sleeps [14:40:41] [PASSED] Cannot be interrupted, locks straight away [14:40:41] [PASSED] Can be interrupted, sleeps [14:40:41] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket ======= [14:40:41] [PASSED] ttm_bo_reserve_locked_no_sleep [14:40:41] [PASSED] ttm_bo_reserve_no_wait_ticket [14:40:41] [PASSED] ttm_bo_reserve_double_resv [14:40:41] [PASSED] ttm_bo_reserve_interrupted [14:40:41] [PASSED] ttm_bo_reserve_deadlock [14:40:41] [PASSED] ttm_bo_unreserve_basic [14:40:41] [PASSED] ttm_bo_unreserve_pinned [14:40:41] [PASSED] ttm_bo_unreserve_bulk [14:40:41] [PASSED] ttm_bo_put_basic [14:40:41] [PASSED] ttm_bo_put_shared_resv [14:40:41] [PASSED] ttm_bo_pin_basic [14:40:41] [PASSED] ttm_bo_pin_unpin_resource [14:40:41] [PASSED] ttm_bo_multiple_pin_one_unpin [14:40:41] ===================== [PASSED] ttm_bo ====================== [14:40:41] ============== ttm_bo_validate (22 subtests) =============== [14:40:41] ============== ttm_bo_init_reserved_sys_man =============== [14:40:41] [PASSED] Buffer object for userspace [14:40:41] [PASSED] Kernel buffer object [14:40:41] [PASSED] Shared buffer object [14:40:41] ========== [PASSED] ttm_bo_init_reserved_sys_man =========== [14:40:41] ============== ttm_bo_init_reserved_mock_man ============== [14:40:41] [PASSED] Buffer object for userspace [14:40:41] [PASSED] Kernel buffer object [14:40:41] [PASSED] Shared buffer object [14:40:41] ========== [PASSED] ttm_bo_init_reserved_mock_man ========== [14:40:41] [PASSED] ttm_bo_init_reserved_resv [14:40:41] ================== ttm_bo_validate_basic ================== [14:40:41] [PASSED] Buffer object for userspace [14:40:41] [PASSED] Kernel buffer object [14:40:41] [PASSED] Shared buffer object [14:40:41] ============== [PASSED] ttm_bo_validate_basic ============== [14:40:41] [PASSED] ttm_bo_validate_invalid_placement [14:40:41] ============= ttm_bo_validate_same_placement ============== [14:40:41] [PASSED] System manager [14:40:41] [PASSED] VRAM manager [14:40:41] ========= [PASSED] ttm_bo_validate_same_placement ========== [14:40:41] [PASSED] ttm_bo_validate_failed_alloc [14:40:41] [PASSED] ttm_bo_validate_pinned [14:40:41] [PASSED] ttm_bo_validate_busy_placement [14:40:41] ================ ttm_bo_validate_multihop ================= [14:40:41] [PASSED] Buffer object for userspace [14:40:41] [PASSED] Kernel buffer object [14:40:41] [PASSED] Shared buffer object [14:40:41] ============ [PASSED] ttm_bo_validate_multihop ============= [14:40:41] ========== ttm_bo_validate_no_placement_signaled ========== [14:40:41] [PASSED] Buffer object in system domain, no page vector [14:40:41] [PASSED] Buffer object in system domain with an existing page vector [14:40:41] ====== [PASSED] ttm_bo_validate_no_placement_signaled ====== [14:40:41] ======== ttm_bo_validate_no_placement_not_signaled ======== [14:40:41] [PASSED] Buffer object for userspace [14:40:41] [PASSED] Kernel buffer object [14:40:41] [PASSED] Shared buffer object [14:40:41] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ==== [14:40:41] [PASSED] ttm_bo_validate_move_fence_signaled [14:40:41] ========= ttm_bo_validate_move_fence_not_signaled ========= [14:40:41] [PASSED] Waits for GPU [14:40:41] [PASSED] Tries to lock straight away [14:40:41] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled ===== [14:40:41] [PASSED] ttm_bo_validate_swapout [14:40:41] [PASSED] ttm_bo_validate_happy_evict [14:40:41] [PASSED] ttm_bo_validate_all_pinned_evict [14:40:41] [PASSED] ttm_bo_validate_allowed_only_evict [14:40:41] [PASSED] ttm_bo_validate_deleted_evict [14:40:41] [PASSED] ttm_bo_validate_busy_domain_evict [14:40:41] [PASSED] ttm_bo_validate_evict_gutting [14:40:41] [PASSED] ttm_bo_validate_recrusive_evict stty: 'standard input': Inappropriate ioctl for device [14:40:41] ================= [PASSED] ttm_bo_validate ================= [14:40:41] ============================================================ [14:40:41] Testing complete. Ran 102 tests: passed: 102 [14:40:42] Elapsed time: 12.020s total, 1.707s configuring, 9.644s building, 0.581s running + cleanup ++ stat -c %u:%g /kernel + chown -R 1003:1003 /kernel ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ CI.Build: success for drm/i915: Some intel_display conversions 2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala ` (8 preceding siblings ...) 2024-09-06 14:40 ` ✓ CI.KUnit: success " Patchwork @ 2024-09-06 14:57 ` Patchwork 2024-09-06 15:02 ` ✓ CI.Hooks: " Patchwork ` (3 subsequent siblings) 13 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2024-09-06 14:57 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-xe == Series Details == Series: drm/i915: Some intel_display conversions URL : https://patchwork.freedesktop.org/series/138332/ State : success == Summary == lib/modules/6.11.0-rc6-xe/kernel/sound/core/seq/ lib/modules/6.11.0-rc6-xe/kernel/sound/core/seq/snd-seq.ko lib/modules/6.11.0-rc6-xe/kernel/sound/core/snd-seq-device.ko lib/modules/6.11.0-rc6-xe/kernel/sound/core/snd-hwdep.ko lib/modules/6.11.0-rc6-xe/kernel/sound/core/snd.ko lib/modules/6.11.0-rc6-xe/kernel/sound/core/snd-pcm.ko lib/modules/6.11.0-rc6-xe/kernel/sound/core/snd-compress.ko lib/modules/6.11.0-rc6-xe/kernel/sound/core/snd-timer.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soundcore.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/ lib/modules/6.11.0-rc6-xe/kernel/sound/soc/intel/ lib/modules/6.11.0-rc6-xe/kernel/sound/soc/intel/atom/ lib/modules/6.11.0-rc6-xe/kernel/sound/soc/intel/atom/snd-soc-sst-atom-hifi2-platform.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/intel/atom/sst/ lib/modules/6.11.0-rc6-xe/kernel/sound/soc/intel/atom/sst/snd-intel-sst-acpi.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/intel/atom/sst/snd-intel-sst-core.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/intel/common/ lib/modules/6.11.0-rc6-xe/kernel/sound/soc/intel/common/snd-soc-acpi-intel-match.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/amd/ lib/modules/6.11.0-rc6-xe/kernel/sound/soc/amd/snd-acp-config.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/ lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/ lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-tgl.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-mlink.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-cnl.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-lnl.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-common.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-generic.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-mtl.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/amd/ lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/amd/snd-sof-amd-renoir.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/amd/snd-sof-amd-acp.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/snd-sof-utils.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/snd-sof-pci.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/snd-sof.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/snd-sof-probes.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/xtensa/ lib/modules/6.11.0-rc6-xe/kernel/sound/soc/sof/xtensa/snd-sof-xtensa-dsp.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/snd-soc-core.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/snd-soc-acpi.ko lib/modules/6.11.0-rc6-xe/kernel/sound/soc/codecs/ lib/modules/6.11.0-rc6-xe/kernel/sound/soc/codecs/snd-soc-hdac-hda.ko lib/modules/6.11.0-rc6-xe/kernel/sound/hda/ lib/modules/6.11.0-rc6-xe/kernel/sound/hda/snd-intel-sdw-acpi.ko lib/modules/6.11.0-rc6-xe/kernel/sound/hda/ext/ lib/modules/6.11.0-rc6-xe/kernel/sound/hda/ext/snd-hda-ext-core.ko lib/modules/6.11.0-rc6-xe/kernel/sound/hda/snd-intel-dspcfg.ko lib/modules/6.11.0-rc6-xe/kernel/sound/hda/snd-hda-core.ko lib/modules/6.11.0-rc6-xe/kernel/arch/ lib/modules/6.11.0-rc6-xe/kernel/arch/x86/ lib/modules/6.11.0-rc6-xe/kernel/arch/x86/kernel/ lib/modules/6.11.0-rc6-xe/kernel/arch/x86/kernel/msr.ko lib/modules/6.11.0-rc6-xe/kernel/arch/x86/kernel/cpuid.ko lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/ lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/sha512-ssse3.ko lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/crct10dif-pclmul.ko lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/ghash-clmulni-intel.ko lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/sha1-ssse3.ko lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/crc32-pclmul.ko lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/sha256-ssse3.ko lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/aesni-intel.ko lib/modules/6.11.0-rc6-xe/kernel/arch/x86/crypto/polyval-clmulni.ko lib/modules/6.11.0-rc6-xe/kernel/arch/x86/events/ lib/modules/6.11.0-rc6-xe/kernel/arch/x86/events/intel/ lib/modules/6.11.0-rc6-xe/kernel/arch/x86/events/intel/intel-cstate.ko lib/modules/6.11.0-rc6-xe/kernel/arch/x86/events/rapl.ko lib/modules/6.11.0-rc6-xe/kernel/arch/x86/kvm/ lib/modules/6.11.0-rc6-xe/kernel/arch/x86/kvm/kvm.ko lib/modules/6.11.0-rc6-xe/kernel/arch/x86/kvm/kvm-intel.ko lib/modules/6.11.0-rc6-xe/kernel/crypto/ lib/modules/6.11.0-rc6-xe/kernel/crypto/crypto_simd.ko lib/modules/6.11.0-rc6-xe/kernel/crypto/cmac.ko lib/modules/6.11.0-rc6-xe/kernel/crypto/ccm.ko lib/modules/6.11.0-rc6-xe/kernel/crypto/cryptd.ko lib/modules/6.11.0-rc6-xe/kernel/crypto/polyval-generic.ko lib/modules/6.11.0-rc6-xe/kernel/crypto/async_tx/ lib/modules/6.11.0-rc6-xe/kernel/crypto/async_tx/async_xor.ko lib/modules/6.11.0-rc6-xe/kernel/crypto/async_tx/async_tx.ko lib/modules/6.11.0-rc6-xe/kernel/crypto/async_tx/async_memcpy.ko lib/modules/6.11.0-rc6-xe/kernel/crypto/async_tx/async_pq.ko lib/modules/6.11.0-rc6-xe/kernel/crypto/async_tx/async_raid6_recov.ko lib/modules/6.11.0-rc6-xe/build lib/modules/6.11.0-rc6-xe/modules.alias.bin lib/modules/6.11.0-rc6-xe/modules.builtin lib/modules/6.11.0-rc6-xe/modules.softdep lib/modules/6.11.0-rc6-xe/modules.alias lib/modules/6.11.0-rc6-xe/modules.order lib/modules/6.11.0-rc6-xe/modules.symbols lib/modules/6.11.0-rc6-xe/modules.dep.bin + mv kernel-nodebug.tar.gz .. + cd .. + rm -rf archive ++ date +%s + echo -e '\e[0Ksection_end:1725634646:package_x86_64_nodebug\r\e[0K' + sync ^[[0Ksection_end:1725634646:package_x86_64_nodebug ^[[0K + cleanup ++ stat -c %u:%g /kernel + chown -R 1003:1003 /kernel ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ CI.Hooks: success for drm/i915: Some intel_display conversions 2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala ` (9 preceding siblings ...) 2024-09-06 14:57 ` ✓ CI.Build: " Patchwork @ 2024-09-06 15:02 ` Patchwork 2024-09-06 15:03 ` ✗ CI.checksparse: warning " Patchwork ` (2 subsequent siblings) 13 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2024-09-06 15:02 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-xe == Series Details == Series: drm/i915: Some intel_display conversions URL : https://patchwork.freedesktop.org/series/138332/ State : success == Summary == run-parts: executing /workspace/ci/hooks/00-showenv + export + grep -Ei '(^|\W)CI_' declare -x CI_KERNEL_BUILD_DIR="/workspace/kernel/build64-default" declare -x CI_KERNEL_SRC_DIR="/workspace/kernel" declare -x CI_TOOLS_SRC_DIR="/workspace/ci" declare -x CI_WORKSPACE_DIR="/workspace" run-parts: executing /workspace/ci/hooks/10-build-W1 + SRC_DIR=/workspace/kernel + RESTORE_DISPLAY_CONFIG=0 + '[' -n /workspace/kernel/build64-default ']' + BUILD_DIR=/workspace/kernel/build64-default + cd /workspace/kernel ++ nproc + make -j48 O=/workspace/kernel/build64-default modules_prepare make[1]: Entering directory '/workspace/kernel/build64-default' GEN Makefile UPD include/config/kernel.release UPD include/generated/compile.h UPD include/generated/utsrelease.h mkdir -p /workspace/kernel/build64-default/tools/objtool && make O=/workspace/kernel/build64-default subdir=tools/objtool --no-print-directory -C objtool CALL ../scripts/checksyscalls.sh HOSTCC /workspace/kernel/build64-default/tools/objtool/fixdep.o HOSTLD /workspace/kernel/build64-default/tools/objtool/fixdep-in.o LINK /workspace/kernel/build64-default/tools/objtool/fixdep INSTALL libsubcmd_headers CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/exec-cmd.o CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/help.o CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/pager.o CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/parse-options.o CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/run-command.o CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/sigchain.o CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/subcmd-config.o LD /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd-in.o AR /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd.a CC /workspace/kernel/build64-default/tools/objtool/weak.o CC /workspace/kernel/build64-default/tools/objtool/arch/x86/special.o CC /workspace/kernel/build64-default/tools/objtool/check.o CC /workspace/kernel/build64-default/tools/objtool/arch/x86/decode.o CC /workspace/kernel/build64-default/tools/objtool/special.o CC /workspace/kernel/build64-default/tools/objtool/builtin-check.o CC /workspace/kernel/build64-default/tools/objtool/arch/x86/orc.o CC /workspace/kernel/build64-default/tools/objtool/elf.o CC /workspace/kernel/build64-default/tools/objtool/objtool.o CC /workspace/kernel/build64-default/tools/objtool/orc_gen.o CC /workspace/kernel/build64-default/tools/objtool/orc_dump.o CC /workspace/kernel/build64-default/tools/objtool/libstring.o CC /workspace/kernel/build64-default/tools/objtool/libctype.o CC /workspace/kernel/build64-default/tools/objtool/str_error_r.o CC /workspace/kernel/build64-default/tools/objtool/librbtree.o LD /workspace/kernel/build64-default/tools/objtool/arch/x86/objtool-in.o LD /workspace/kernel/build64-default/tools/objtool/objtool-in.o LINK /workspace/kernel/build64-default/tools/objtool/objtool make[1]: Leaving directory '/workspace/kernel/build64-default' ++ nproc + make -j48 O=/workspace/kernel/build64-default W=1 drivers/gpu/drm/xe make[1]: Entering directory '/workspace/kernel/build64-default' make[2]: Nothing to be done for 'drivers/gpu/drm/xe'. make[1]: Leaving directory '/workspace/kernel/build64-default' run-parts: executing /workspace/ci/hooks/11-build-32b +++ realpath /workspace/ci/hooks/11-build-32b ++ dirname /workspace/ci/hooks/11-build-32b + THIS_SCRIPT_DIR=/workspace/ci/hooks + SRC_DIR=/workspace/kernel + TOOLS_SRC_DIR=/workspace/ci + '[' -n /workspace/kernel/build64-default ']' + BUILD_DIR=/workspace/kernel/build64-default + BUILD_DIR=/workspace/kernel/build64-default/build32 + cd /workspace/kernel + mkdir -p /workspace/kernel/build64-default/build32 ++ nproc + make -j48 ARCH=i386 O=/workspace/kernel/build64-default/build32 defconfig make[1]: Entering directory '/workspace/kernel/build64-default/build32' GEN Makefile HOSTCC scripts/basic/fixdep HOSTCC scripts/kconfig/conf.o HOSTCC scripts/kconfig/confdata.o HOSTCC scripts/kconfig/expr.o LEX scripts/kconfig/lexer.lex.c YACC scripts/kconfig/parser.tab.[ch] HOSTCC scripts/kconfig/menu.o HOSTCC scripts/kconfig/preprocess.o HOSTCC scripts/kconfig/symbol.o HOSTCC scripts/kconfig/util.o HOSTCC scripts/kconfig/lexer.lex.o HOSTCC scripts/kconfig/parser.tab.o HOSTLD scripts/kconfig/conf *** Default configuration is based on 'i386_defconfig' # # configuration written to .config # make[1]: Leaving directory '/workspace/kernel/build64-default/build32' + cd /workspace/kernel/build64-default/build32 + /workspace/kernel/scripts/kconfig/merge_config.sh .config /workspace/ci/kernel/10-xe.fragment Using .config as base Merging /workspace/ci/kernel/10-xe.fragment Value of CONFIG_DRM_XE is redefined by fragment /workspace/ci/kernel/10-xe.fragment: Previous value: # CONFIG_DRM_XE is not set New value: CONFIG_DRM_XE=m Value of CONFIG_SND_DEBUG is redefined by fragment /workspace/ci/kernel/10-xe.fragment: Previous value: # CONFIG_SND_DEBUG is not set New value: CONFIG_SND_DEBUG=y Value of CONFIG_SND_HDA_INTEL is redefined by fragment /workspace/ci/kernel/10-xe.fragment: Previous value: CONFIG_SND_HDA_INTEL=y New value: CONFIG_SND_HDA_INTEL=m Value of CONFIG_SND_HDA_CODEC_HDMI is redefined by fragment /workspace/ci/kernel/10-xe.fragment: Previous value: # CONFIG_SND_HDA_CODEC_HDMI is not set New value: CONFIG_SND_HDA_CODEC_HDMI=m GEN Makefile WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n] Selected by [m]: - DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] # # configuration written to .config # Value requested for CONFIG_HAVE_UID16 not in final .config Requested value: CONFIG_HAVE_UID16=y Actual value: Value requested for CONFIG_UID16 not in final .config Requested value: CONFIG_UID16=y Actual value: Value requested for CONFIG_X86_32 not in final .config Requested value: CONFIG_X86_32=y Actual value: Value requested for CONFIG_OUTPUT_FORMAT not in final .config Requested value: CONFIG_OUTPUT_FORMAT="elf32-i386" Actual value: CONFIG_OUTPUT_FORMAT="elf64-x86-64" Value requested for CONFIG_ARCH_MMAP_RND_BITS_MIN not in final .config Requested value: CONFIG_ARCH_MMAP_RND_BITS_MIN=8 Actual value: CONFIG_ARCH_MMAP_RND_BITS_MIN=28 Value requested for CONFIG_ARCH_MMAP_RND_BITS_MAX not in final .config Requested value: CONFIG_ARCH_MMAP_RND_BITS_MAX=16 Actual value: CONFIG_ARCH_MMAP_RND_BITS_MAX=32 Value requested for CONFIG_PGTABLE_LEVELS not in final .config Requested value: CONFIG_PGTABLE_LEVELS=2 Actual value: CONFIG_PGTABLE_LEVELS=5 Value requested for CONFIG_X86_BIGSMP not in final .config Requested value: # CONFIG_X86_BIGSMP is not set Actual value: Value requested for CONFIG_X86_INTEL_QUARK not in final .config Requested value: # CONFIG_X86_INTEL_QUARK is not set Actual value: Value requested for CONFIG_X86_RDC321X not in final .config Requested value: # CONFIG_X86_RDC321X is not set Actual value: Value requested for CONFIG_X86_32_NON_STANDARD not in final .config Requested value: # CONFIG_X86_32_NON_STANDARD is not set Actual value: Value requested for CONFIG_X86_32_IRIS not in final .config Requested value: # CONFIG_X86_32_IRIS is not set Actual value: Value requested for CONFIG_M486SX not in final .config Requested value: # CONFIG_M486SX is not set Actual value: Value requested for CONFIG_M486 not in final .config Requested value: # CONFIG_M486 is not set Actual value: Value requested for CONFIG_M586 not in final .config Requested value: # CONFIG_M586 is not set Actual value: Value requested for CONFIG_M586TSC not in final .config Requested value: # CONFIG_M586TSC is not set Actual value: Value requested for CONFIG_M586MMX not in final .config Requested value: # CONFIG_M586MMX is not set Actual value: Value requested for CONFIG_M686 not in final .config Requested value: CONFIG_M686=y Actual value: Value requested for CONFIG_MPENTIUMII not in final .config Requested value: # CONFIG_MPENTIUMII is not set Actual value: Value requested for CONFIG_MPENTIUMIII not in final .config Requested value: # CONFIG_MPENTIUMIII is not set Actual value: Value requested for CONFIG_MPENTIUMM not in final .config Requested value: # CONFIG_MPENTIUMM is not set Actual value: Value requested for CONFIG_MPENTIUM4 not in final .config Requested value: # CONFIG_MPENTIUM4 is not set Actual value: Value requested for CONFIG_MK6 not in final .config Requested value: # CONFIG_MK6 is not set Actual value: Value requested for CONFIG_MK7 not in final .config Requested value: # CONFIG_MK7 is not set Actual value: Value requested for CONFIG_MCRUSOE not in final .config Requested value: # CONFIG_MCRUSOE is not set Actual value: Value requested for CONFIG_MEFFICEON not in final .config Requested value: # CONFIG_MEFFICEON is not set Actual value: Value requested for CONFIG_MWINCHIPC6 not in final .config Requested value: # CONFIG_MWINCHIPC6 is not set Actual value: Value requested for CONFIG_MWINCHIP3D not in final .config Requested value: # CONFIG_MWINCHIP3D is not set Actual value: Value requested for CONFIG_MELAN not in final .config Requested value: # CONFIG_MELAN is not set Actual value: Value requested for CONFIG_MGEODEGX1 not in final .config Requested value: # CONFIG_MGEODEGX1 is not set Actual value: Value requested for CONFIG_MGEODE_LX not in final .config Requested value: # CONFIG_MGEODE_LX is not set Actual value: Value requested for CONFIG_MCYRIXIII not in final .config Requested value: # CONFIG_MCYRIXIII is not set Actual value: Value requested for CONFIG_MVIAC3_2 not in final .config Requested value: # CONFIG_MVIAC3_2 is not set Actual value: Value requested for CONFIG_MVIAC7 not in final .config Requested value: # CONFIG_MVIAC7 is not set Actual value: Value requested for CONFIG_X86_GENERIC not in final .config Requested value: # CONFIG_X86_GENERIC is not set Actual value: Value requested for CONFIG_X86_INTERNODE_CACHE_SHIFT not in final .config Requested value: CONFIG_X86_INTERNODE_CACHE_SHIFT=5 Actual value: CONFIG_X86_INTERNODE_CACHE_SHIFT=6 Value requested for CONFIG_X86_L1_CACHE_SHIFT not in final .config Requested value: CONFIG_X86_L1_CACHE_SHIFT=5 Actual value: CONFIG_X86_L1_CACHE_SHIFT=6 Value requested for CONFIG_X86_USE_PPRO_CHECKSUM not in final .config Requested value: CONFIG_X86_USE_PPRO_CHECKSUM=y Actual value: Value requested for CONFIG_X86_MINIMUM_CPU_FAMILY not in final .config Requested value: CONFIG_X86_MINIMUM_CPU_FAMILY=6 Actual value: CONFIG_X86_MINIMUM_CPU_FAMILY=64 Value requested for CONFIG_CPU_SUP_TRANSMETA_32 not in final .config Requested value: CONFIG_CPU_SUP_TRANSMETA_32=y Actual value: Value requested for CONFIG_CPU_SUP_VORTEX_32 not in final .config Requested value: CONFIG_CPU_SUP_VORTEX_32=y Actual value: Value requested for CONFIG_HPET_TIMER not in final .config Requested value: # CONFIG_HPET_TIMER is not set Actual value: CONFIG_HPET_TIMER=y Value requested for CONFIG_NR_CPUS_RANGE_END not in final .config Requested value: CONFIG_NR_CPUS_RANGE_END=8 Actual value: CONFIG_NR_CPUS_RANGE_END=512 Value requested for CONFIG_NR_CPUS_DEFAULT not in final .config Requested value: CONFIG_NR_CPUS_DEFAULT=8 Actual value: CONFIG_NR_CPUS_DEFAULT=64 Value requested for CONFIG_X86_ANCIENT_MCE not in final .config Requested value: # CONFIG_X86_ANCIENT_MCE is not set Actual value: Value requested for CONFIG_X86_LEGACY_VM86 not in final .config Requested value: # CONFIG_X86_LEGACY_VM86 is not set Actual value: Value requested for CONFIG_X86_ESPFIX32 not in final .config Requested value: CONFIG_X86_ESPFIX32=y Actual value: Value requested for CONFIG_TOSHIBA not in final .config Requested value: # CONFIG_TOSHIBA is not set Actual value: Value requested for CONFIG_X86_REBOOTFIXUPS not in final .config Requested value: # CONFIG_X86_REBOOTFIXUPS is not set Actual value: Value requested for CONFIG_MICROCODE_INITRD32 not in final .config Requested value: CONFIG_MICROCODE_INITRD32=y Actual value: Value requested for CONFIG_NOHIGHMEM not in final .config Requested value: # CONFIG_NOHIGHMEM is not set Actual value: Value requested for CONFIG_HIGHMEM4G not in final .config Requested value: CONFIG_HIGHMEM4G=y Actual value: Value requested for CONFIG_HIGHMEM64G not in final .config Requested value: # CONFIG_HIGHMEM64G is not set Actual value: Value requested for CONFIG_VMSPLIT_3G not in final .config Requested value: CONFIG_VMSPLIT_3G=y Actual value: Value requested for CONFIG_VMSPLIT_3G_OPT not in final .config Requested value: # CONFIG_VMSPLIT_3G_OPT is not set Actual value: Value requested for CONFIG_VMSPLIT_2G not in final .config Requested value: # CONFIG_VMSPLIT_2G is not set Actual value: Value requested for CONFIG_VMSPLIT_2G_OPT not in final .config Requested value: # CONFIG_VMSPLIT_2G_OPT is not set Actual value: Value requested for CONFIG_VMSPLIT_1G not in final .config Requested value: # CONFIG_VMSPLIT_1G is not set Actual value: Value requested for CONFIG_PAGE_OFFSET not in final .config Requested value: CONFIG_PAGE_OFFSET=0xC0000000 Actual value: Value requested for CONFIG_HIGHMEM not in final .config Requested value: CONFIG_HIGHMEM=y Actual value: Value requested for CONFIG_X86_PAE not in final .config Requested value: # CONFIG_X86_PAE is not set Actual value: Value requested for CONFIG_ARCH_FLATMEM_ENABLE not in final .config Requested value: CONFIG_ARCH_FLATMEM_ENABLE=y Actual value: Value requested for CONFIG_ARCH_SELECT_MEMORY_MODEL not in final .config Requested value: CONFIG_ARCH_SELECT_MEMORY_MODEL=y Actual value: Value requested for CONFIG_ILLEGAL_POINTER_VALUE not in final .config Requested value: CONFIG_ILLEGAL_POINTER_VALUE=0 Actual value: CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 Value requested for CONFIG_HIGHPTE not in final .config Requested value: # CONFIG_HIGHPTE is not set Actual value: Value requested for CONFIG_COMPAT_VDSO not in final .config Requested value: # CONFIG_COMPAT_VDSO is not set Actual value: Value requested for CONFIG_FUNCTION_PADDING_CFI not in final .config Requested value: CONFIG_FUNCTION_PADDING_CFI=0 Actual value: CONFIG_FUNCTION_PADDING_CFI=11 Value requested for CONFIG_FUNCTION_PADDING_BYTES not in final .config Requested value: CONFIG_FUNCTION_PADDING_BYTES=4 Actual value: CONFIG_FUNCTION_PADDING_BYTES=16 Value requested for CONFIG_APM not in final .config Requested value: # CONFIG_APM is not set Actual value: Value requested for CONFIG_X86_POWERNOW_K6 not in final .config Requested value: # CONFIG_X86_POWERNOW_K6 is not set Actual value: Value requested for CONFIG_X86_POWERNOW_K7 not in final .config Requested value: # CONFIG_X86_POWERNOW_K7 is not set Actual value: Value requested for CONFIG_X86_GX_SUSPMOD not in final .config Requested value: # CONFIG_X86_GX_SUSPMOD is not set Actual value: Value requested for CONFIG_X86_SPEEDSTEP_ICH not in final .config Requested value: # CONFIG_X86_SPEEDSTEP_ICH is not set Actual value: Value requested for CONFIG_X86_SPEEDSTEP_SMI not in final .config Requested value: # CONFIG_X86_SPEEDSTEP_SMI is not set Actual value: Value requested for CONFIG_X86_CPUFREQ_NFORCE2 not in final .config Requested value: # CONFIG_X86_CPUFREQ_NFORCE2 is not set Actual value: Value requested for CONFIG_X86_LONGRUN not in final .config Requested value: # CONFIG_X86_LONGRUN is not set Actual value: Value requested for CONFIG_X86_LONGHAUL not in final .config Requested value: # CONFIG_X86_LONGHAUL is not set Actual value: Value requested for CONFIG_X86_E_POWERSAVER not in final .config Requested value: # CONFIG_X86_E_POWERSAVER is not set Actual value: Value requested for CONFIG_PCI_GOBIOS not in final .config Requested value: # CONFIG_PCI_GOBIOS is not set Actual value: Value requested for CONFIG_PCI_GOMMCONFIG not in final .config Requested value: # CONFIG_PCI_GOMMCONFIG is not set Actual value: Value requested for CONFIG_PCI_GODIRECT not in final .config Requested value: # CONFIG_PCI_GODIRECT is not set Actual value: Value requested for CONFIG_PCI_GOANY not in final .config Requested value: CONFIG_PCI_GOANY=y Actual value: Value requested for CONFIG_PCI_BIOS not in final .config Requested value: CONFIG_PCI_BIOS=y Actual value: Value requested for CONFIG_ISA not in final .config Requested value: # CONFIG_ISA is not set Actual value: Value requested for CONFIG_SCx200 not in final .config Requested value: # CONFIG_SCx200 is not set Actual value: Value requested for CONFIG_OLPC not in final .config Requested value: # CONFIG_OLPC is not set Actual value: Value requested for CONFIG_ALIX not in final .config Requested value: # CONFIG_ALIX is not set Actual value: Value requested for CONFIG_NET5501 not in final .config Requested value: # CONFIG_NET5501 is not set Actual value: Value requested for CONFIG_GEOS not in final .config Requested value: # CONFIG_GEOS is not set Actual value: Value requested for CONFIG_COMPAT_32 not in final .config Requested value: CONFIG_COMPAT_32=y Actual value: Value requested for CONFIG_HAVE_ATOMIC_IOMAP not in final .config Requested value: CONFIG_HAVE_ATOMIC_IOMAP=y Actual value: Value requested for CONFIG_ARCH_32BIT_OFF_T not in final .config Requested value: CONFIG_ARCH_32BIT_OFF_T=y Actual value: Value requested for CONFIG_ARCH_WANT_IPC_PARSE_VERSION not in final .config Requested value: CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y Actual value: Value requested for CONFIG_MODULES_USE_ELF_REL not in final .config Requested value: CONFIG_MODULES_USE_ELF_REL=y Actual value: Value requested for CONFIG_ARCH_MMAP_RND_BITS not in final .config Requested value: CONFIG_ARCH_MMAP_RND_BITS=8 Actual value: CONFIG_ARCH_MMAP_RND_BITS=28 Value requested for CONFIG_CLONE_BACKWARDS not in final .config Requested value: CONFIG_CLONE_BACKWARDS=y Actual value: Value requested for CONFIG_OLD_SIGSUSPEND3 not in final .config Requested value: CONFIG_OLD_SIGSUSPEND3=y Actual value: Value requested for CONFIG_OLD_SIGACTION not in final .config Requested value: CONFIG_OLD_SIGACTION=y Actual value: Value requested for CONFIG_ARCH_SPLIT_ARG64 not in final .config Requested value: CONFIG_ARCH_SPLIT_ARG64=y Actual value: Value requested for CONFIG_FUNCTION_ALIGNMENT not in final .config Requested value: CONFIG_FUNCTION_ALIGNMENT=4 Actual value: CONFIG_FUNCTION_ALIGNMENT=16 Value requested for CONFIG_SELECT_MEMORY_MODEL not in final .config Requested value: CONFIG_SELECT_MEMORY_MODEL=y Actual value: Value requested for CONFIG_FLATMEM_MANUAL not in final .config Requested value: CONFIG_FLATMEM_MANUAL=y Actual value: Value requested for CONFIG_SPARSEMEM_MANUAL not in final .config Requested value: # CONFIG_SPARSEMEM_MANUAL is not set Actual value: Value requested for CONFIG_FLATMEM not in final .config Requested value: CONFIG_FLATMEM=y Actual value: Value requested for CONFIG_SPARSEMEM_STATIC not in final .config Requested value: CONFIG_SPARSEMEM_STATIC=y Actual value: Value requested for CONFIG_BOUNCE not in final .config Requested value: CONFIG_BOUNCE=y Actual value: Value requested for CONFIG_KMAP_LOCAL not in final .config Requested value: CONFIG_KMAP_LOCAL=y Actual value: Value requested for CONFIG_HOTPLUG_PCI_COMPAQ not in final .config Requested value: # CONFIG_HOTPLUG_PCI_COMPAQ is not set Actual value: Value requested for CONFIG_HOTPLUG_PCI_IBM not in final .config Requested value: # CONFIG_HOTPLUG_PCI_IBM is not set Actual value: Value requested for CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH not in final .config Requested value: CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH=y Actual value: Value requested for CONFIG_PCH_PHUB not in final .config Requested value: # CONFIG_PCH_PHUB is not set Actual value: Value requested for CONFIG_SCSI_NSP32 not in final .config Requested value: # CONFIG_SCSI_NSP32 is not set Actual value: Value requested for CONFIG_PATA_CS5520 not in final .config Requested value: # CONFIG_PATA_CS5520 is not set Actual value: Value requested for CONFIG_PATA_CS5530 not in final .config Requested value: # CONFIG_PATA_CS5530 is not set Actual value: Value requested for CONFIG_PATA_CS5535 not in final .config Requested value: # CONFIG_PATA_CS5535 is not set Actual value: Value requested for CONFIG_PATA_CS5536 not in final .config Requested value: # CONFIG_PATA_CS5536 is not set Actual value: Value requested for CONFIG_PATA_SC1200 not in final .config Requested value: # CONFIG_PATA_SC1200 is not set Actual value: Value requested for CONFIG_PCH_GBE not in final .config Requested value: # CONFIG_PCH_GBE is not set Actual value: Value requested for CONFIG_INPUT_WISTRON_BTNS not in final .config Requested value: # CONFIG_INPUT_WISTRON_BTNS is not set Actual value: Value requested for CONFIG_SERIAL_TIMBERDALE not in final .config Requested value: # CONFIG_SERIAL_TIMBERDALE is not set Actual value: Value requested for CONFIG_SERIAL_PCH_UART not in final .config Requested value: # CONFIG_SERIAL_PCH_UART is not set Actual value: Value requested for CONFIG_HW_RANDOM_GEODE not in final .config Requested value: CONFIG_HW_RANDOM_GEODE=y Actual value: Value requested for CONFIG_SONYPI not in final .config Requested value: # CONFIG_SONYPI is not set Actual value: Value requested for CONFIG_PC8736x_GPIO not in final .config Requested value: # CONFIG_PC8736x_GPIO is not set Actual value: Value requested for CONFIG_NSC_GPIO not in final .config Requested value: # CONFIG_NSC_GPIO is not set Actual value: Value requested for CONFIG_I2C_EG20T not in final .config Requested value: # CONFIG_I2C_EG20T is not set Actual value: Value requested for CONFIG_SCx200_ACB not in final .config Requested value: # CONFIG_SCx200_ACB is not set Actual value: Value requested for CONFIG_PTP_1588_CLOCK_PCH not in final .config Requested value: # CONFIG_PTP_1588_CLOCK_PCH is not set Actual value: Value requested for CONFIG_SBC8360_WDT not in final .config Requested value: # CONFIG_SBC8360_WDT is not set Actual value: Value requested for CONFIG_SBC7240_WDT not in final .config Requested value: # CONFIG_SBC7240_WDT is not set Actual value: Value requested for CONFIG_MFD_CS5535 not in final .config Requested value: # CONFIG_MFD_CS5535 is not set Actual value: Value requested for CONFIG_AGP_ALI not in final .config Requested value: # CONFIG_AGP_ALI is not set Actual value: Value requested for CONFIG_AGP_ATI not in final .config Requested value: # CONFIG_AGP_ATI is not set Actual value: Value requested for CONFIG_AGP_AMD not in final .config Requested value: # CONFIG_AGP_AMD is not set Actual value: Value requested for CONFIG_AGP_NVIDIA not in final .config Requested value: # CONFIG_AGP_NVIDIA is not set Actual value: Value requested for CONFIG_AGP_SWORKS not in final .config Requested value: # CONFIG_AGP_SWORKS is not set Actual value: Value requested for CONFIG_AGP_EFFICEON not in final .config Requested value: # CONFIG_AGP_EFFICEON is not set Actual value: Value requested for CONFIG_SND_PCM not in final .config Requested value: CONFIG_SND_PCM=y Actual value: CONFIG_SND_PCM=m Value requested for CONFIG_SND_HWDEP not in final .config Requested value: CONFIG_SND_HWDEP=y Actual value: CONFIG_SND_HWDEP=m Value requested for CONFIG_SND_DYNAMIC_MINORS not in final .config Requested value: # CONFIG_SND_DYNAMIC_MINORS is not set Actual value: CONFIG_SND_DYNAMIC_MINORS=y Value requested for CONFIG_SND_CS5530 not in final .config Requested value: # CONFIG_SND_CS5530 is not set Actual value: Value requested for CONFIG_SND_CS5535AUDIO not in final .config Requested value: # CONFIG_SND_CS5535AUDIO is not set Actual value: Value requested for CONFIG_SND_SIS7019 not in final .config Requested value: # CONFIG_SND_SIS7019 is not set Actual value: Value requested for CONFIG_SND_HDA not in final .config Requested value: CONFIG_SND_HDA=y Actual value: CONFIG_SND_HDA=m Value requested for CONFIG_SND_HDA_CORE not in final .config Requested value: CONFIG_SND_HDA_CORE=y Actual value: CONFIG_SND_HDA_CORE=m Value requested for CONFIG_SND_INTEL_DSP_CONFIG not in final .config Requested value: CONFIG_SND_INTEL_DSP_CONFIG=y Actual value: CONFIG_SND_INTEL_DSP_CONFIG=m Value requested for CONFIG_SND_INTEL_SOUNDWIRE_ACPI not in final .config Requested value: CONFIG_SND_INTEL_SOUNDWIRE_ACPI=y Actual value: CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m Value requested for CONFIG_LEDS_OT200 not in final .config Requested value: # CONFIG_LEDS_OT200 is not set Actual value: Value requested for CONFIG_PCH_DMA not in final .config Requested value: # CONFIG_PCH_DMA is not set Actual value: Value requested for CONFIG_CLKSRC_I8253 not in final .config Requested value: CONFIG_CLKSRC_I8253=y Actual value: Value requested for CONFIG_MAILBOX not in final .config Requested value: # CONFIG_MAILBOX is not set Actual value: CONFIG_MAILBOX=y Value requested for CONFIG_CRYPTO_SERPENT_SSE2_586 not in final .config Requested value: # CONFIG_CRYPTO_SERPENT_SSE2_586 is not set Actual value: Value requested for CONFIG_CRYPTO_TWOFISH_586 not in final .config Requested value: # CONFIG_CRYPTO_TWOFISH_586 is not set Actual value: Value requested for CONFIG_CRYPTO_DEV_GEODE not in final .config Requested value: # CONFIG_CRYPTO_DEV_GEODE is not set Actual value: Value requested for CONFIG_CRYPTO_DEV_HIFN_795X not in final .config Requested value: # CONFIG_CRYPTO_DEV_HIFN_795X is not set Actual value: Value requested for CONFIG_CRYPTO_LIB_POLY1305_RSIZE not in final .config Requested value: CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1 Actual value: CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 Value requested for CONFIG_AUDIT_GENERIC not in final .config Requested value: CONFIG_AUDIT_GENERIC=y Actual value: Value requested for CONFIG_GENERIC_VDSO_32 not in final .config Requested value: CONFIG_GENERIC_VDSO_32=y Actual value: Value requested for CONFIG_DEBUG_KMAP_LOCAL not in final .config Requested value: # CONFIG_DEBUG_KMAP_LOCAL is not set Actual value: Value requested for CONFIG_DEBUG_HIGHMEM not in final .config Requested value: # CONFIG_DEBUG_HIGHMEM is not set Actual value: Value requested for CONFIG_HAVE_DEBUG_STACKOVERFLOW not in final .config Requested value: CONFIG_HAVE_DEBUG_STACKOVERFLOW=y Actual value: Value requested for CONFIG_DEBUG_STACKOVERFLOW not in final .config Requested value: # CONFIG_DEBUG_STACKOVERFLOW is not set Actual value: Value requested for CONFIG_HAVE_FUNCTION_GRAPH_TRACER not in final .config Requested value: CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y Actual value: Value requested for CONFIG_HAVE_FUNCTION_GRAPH_RETVAL not in final .config Requested value: CONFIG_HAVE_FUNCTION_GRAPH_RETVAL=y Actual value: Value requested for CONFIG_DRM_KUNIT_TEST not in final .config Requested value: CONFIG_DRM_KUNIT_TEST=m Actual value: Value requested for CONFIG_DRM_XE_WERROR not in final .config Requested value: CONFIG_DRM_XE_WERROR=y Actual value: Value requested for CONFIG_DRM_XE_DEBUG not in final .config Requested value: CONFIG_DRM_XE_DEBUG=y Actual value: Value requested for CONFIG_DRM_XE_DEBUG_MEM not in final .config Requested value: CONFIG_DRM_XE_DEBUG_MEM=y Actual value: Value requested for CONFIG_DRM_XE_KUNIT_TEST not in final .config Requested value: CONFIG_DRM_XE_KUNIT_TEST=m Actual value: ++ nproc + make -j48 ARCH=i386 olddefconfig GEN Makefile WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n] Selected by [m]: - DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] # # configuration written to .config # ++ nproc + make -j48 ARCH=i386 SYNC include/config/auto.conf.cmd GEN Makefile WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n] Selected by [m]: - DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n] Selected by [m]: - DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n] Selected by [m]: - DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] GEN Makefile SYSHDR arch/x86/include/generated/uapi/asm/unistd_32.h SYSHDR arch/x86/include/generated/uapi/asm/unistd_64.h SYSHDR arch/x86/include/generated/uapi/asm/unistd_x32.h WRAP arch/x86/include/generated/uapi/asm/bpf_perf_event.h SYSTBL arch/x86/include/generated/asm/syscalls_32.h WRAP arch/x86/include/generated/uapi/asm/errno.h WRAP arch/x86/include/generated/uapi/asm/fcntl.h WRAP arch/x86/include/generated/uapi/asm/ioctl.h WRAP arch/x86/include/generated/uapi/asm/ioctls.h HOSTCC arch/x86/tools/relocs_32.o WRAP arch/x86/include/generated/uapi/asm/ipcbuf.h HOSTCC arch/x86/tools/relocs_64.o UPD include/generated/uapi/linux/version.h WRAP arch/x86/include/generated/uapi/asm/param.h HOSTCC arch/x86/tools/relocs_common.o WRAP arch/x86/include/generated/uapi/asm/poll.h WRAP arch/x86/include/generated/uapi/asm/resource.h WRAP arch/x86/include/generated/uapi/asm/socket.h WRAP arch/x86/include/generated/uapi/asm/sockios.h WRAP arch/x86/include/generated/uapi/asm/termbits.h WRAP arch/x86/include/generated/uapi/asm/termios.h HOSTCC scripts/kallsyms WRAP arch/x86/include/generated/uapi/asm/types.h HOSTCC scripts/sorttable HOSTCC scripts/selinux/mdp/mdp HOSTCC scripts/selinux/genheaders/genheaders WRAP arch/x86/include/generated/asm/early_ioremap.h HOSTCC scripts/asn1_compiler WRAP arch/x86/include/generated/asm/mcs_spinlock.h UPD include/generated/compile.h WRAP arch/x86/include/generated/asm/irq_regs.h WRAP arch/x86/include/generated/asm/kmap_size.h WRAP arch/x86/include/generated/asm/local64.h WRAP arch/x86/include/generated/asm/mmiowb.h WRAP arch/x86/include/generated/asm/module.lds.h WRAP arch/x86/include/generated/asm/rwonce.h WRAP arch/x86/include/generated/asm/unaligned.h HOSTLD arch/x86/tools/relocs UPD include/config/kernel.release UPD include/generated/utsrelease.h CC scripts/mod/empty.o HOSTCC scripts/mod/mk_elfconfig CC scripts/mod/devicetable-offsets.s UPD scripts/mod/devicetable-offsets.h MKELF scripts/mod/elfconfig.h HOSTCC scripts/mod/modpost.o HOSTCC scripts/mod/file2alias.o HOSTCC scripts/mod/sumversion.o HOSTCC scripts/mod/symsearch.o HOSTLD scripts/mod/modpost CC kernel/bounds.s CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-arch-fallback.h CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-instrumented.h UPD include/generated/timeconst.h CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-long.h UPD include/generated/bounds.h CC arch/x86/kernel/asm-offsets.s UPD include/generated/asm-offsets.h CALL /workspace/kernel/scripts/checksyscalls.sh LDS scripts/module.lds CC init/main.o HOSTCC usr/gen_init_cpio CC init/do_mounts.o CC init/do_mounts_initrd.o UPD init/utsversion-tmp.h CC certs/system_keyring.o CC init/initramfs.o CC arch/x86/realmode/init.o CC init/calibrate.o CC arch/x86/events/amd/core.o CC arch/x86/events/core.o CC init/init_task.o AS arch/x86/entry/entry.o CC mm/filemap.o AS arch/x86/entry/entry_32.o CC arch/x86/events/amd/lbr.o CC arch/x86/events/probe.o CC arch/x86/entry/syscall_32.o CC arch/x86/events/amd/ibs.o CC arch/x86/entry/common.o AR arch/x86/crypto/built-in.a AR arch/x86/entry/vsyscall/built-in.a CC arch/x86/events/intel/core.o AS arch/x86/entry/thunk.o CC arch/x86/events/amd/uncore.o CC arch/x86/events/intel/bts.o CC init/version.o CC arch/x86/mm/init.o CC arch/x86/events/utils.o CC arch/x86/events/rapl.o CC mm/mempool.o CC arch/x86/events/msr.o CC arch/x86/mm/pat/set_memory.o CC ipc/util.o AS arch/x86/realmode/rm/header.o CC arch/x86/events/zhaoxin/core.o CC arch/x86/kernel/fpu/init.o AR arch/x86/platform/atom/built-in.a AR arch/x86/net/built-in.a AS arch/x86/realmode/rm/trampoline_32.o CC security/keys/gc.o CC security/keys/key.o CC fs/notify/dnotify/dnotify.o CC arch/x86/entry/vdso/vma.o CC io_uring/io_uring.o CC fs/notify/inotify/inotify_fsnotify.o CC block/partitions/core.o AR fs/notify/fanotify/built-in.a AR arch/x86/virt/svm/built-in.a CC arch/x86/kernel/acpi/boot.o CC arch/x86/kernel/acpi/sleep.o CC arch/x86/kernel/cpu/mce/core.o AS arch/x86/realmode/rm/stack.o AR arch/x86/platform/ce4100/built-in.a AR arch/x86/virt/vmx/built-in.a AS arch/x86/kernel/acpi/wakeup_32.o GEN security/selinux/flask.h security/selinux/av_permissions.h CC kernel/sched/core.o CC arch/x86/kernel/acpi/cstate.o AR arch/x86/virt/built-in.a AS arch/x86/realmode/rm/reboot.o CC arch/x86/platform/efi/memmap.o CC security/selinux/avc.o CC arch/x86/kernel/apic/apic.o CC block/partitions/msdos.o AS arch/x86/realmode/rm/wakeup_asm.o CC arch/x86/kernel/fpu/bugs.o CC crypto/asymmetric_keys/asymmetric_type.o GEN usr/initramfs_data.cpio CC kernel/sched/fair.o CC arch/x86/realmode/rm/wakemain.o COPY usr/initramfs_inc_data AS usr/initramfs_data.o CC arch/x86/kernel/fpu/core.o AR usr/built-in.a CC arch/x86/kernel/fpu/regset.o HOSTCC certs/extract-cert CC arch/x86/realmode/rm/video-mode.o CC crypto/asymmetric_keys/restrict.o CC security/selinux/hooks.o CC ipc/msgutil.o CC arch/x86/kernel/apic/apic_common.o CC fs/notify/inotify/inotify_user.o CC arch/x86/events/intel/ds.o AS arch/x86/realmode/rm/copy.o CC arch/x86/kernel/kprobes/core.o CC arch/x86/platform/efi/quirks.o CC mm/oom_kill.o AS arch/x86/realmode/rm/bioscall.o AR arch/x86/events/zhaoxin/built-in.a CERT certs/x509_certificate_list CC arch/x86/kernel/cpu/mce/severity.o CERT certs/signing_key.x509 CC arch/x86/realmode/rm/regs.o CC arch/x86/kernel/cpu/mce/genpool.o AS certs/system_certificates.o CC arch/x86/realmode/rm/video-vga.o CC arch/x86/kernel/cpu/mce/intel.o AR certs/built-in.a CC ipc/msg.o CC arch/x86/kernel/cpu/mtrr/mtrr.o CC arch/x86/kernel/cpu/microcode/core.o CC crypto/asymmetric_keys/signature.o CC block/partitions/efi.o CC arch/x86/entry/vdso/extable.o LDS arch/x86/entry/vdso/vdso32/vdso32.lds CC crypto/asymmetric_keys/public_key.o CC arch/x86/kernel/cpu/cacheinfo.o CC arch/x86/mm/pat/memtype.o CC arch/x86/realmode/rm/video-vesa.o ASN.1 crypto/asymmetric_keys/x509.asn1.[ch] CC mm/fadvise.o CC arch/x86/kernel/cpu/microcode/intel.o CC arch/x86/kernel/cpu/microcode/amd.o ASN.1 crypto/asymmetric_keys/x509_akid.asn1.[ch] CC crypto/api.o CC kernel/sched/build_policy.o CC mm/maccess.o CC crypto/asymmetric_keys/x509_loader.o CC arch/x86/realmode/rm/video-bios.o CC crypto/cipher.o AR arch/x86/platform/geode/built-in.a CC arch/x86/kernel/fpu/signal.o CC io_uring/opdef.o PASYMS arch/x86/realmode/rm/pasyms.h CC arch/x86/kernel/apic/apic_noop.o LDS arch/x86/realmode/rm/realmode.lds AR fs/notify/dnotify/built-in.a LD arch/x86/realmode/rm/realmode.elf AR arch/x86/events/amd/built-in.a RELOCS arch/x86/realmode/rm/realmode.relocs OBJCOPY arch/x86/realmode/rm/realmode.bin CC fs/nfs_common/nfsacl.o CC arch/x86/events/intel/knc.o CC ipc/sem.o CC arch/x86/kernel/kprobes/opt.o CC ipc/shm.o AS arch/x86/realmode/rmpiggy.o CC security/keys/keyring.o AR arch/x86/realmode/built-in.a CC arch/x86/kernel/cpu/mtrr/if.o CC arch/x86/kernel/fpu/xstate.o CC ipc/syscall.o AR arch/x86/kernel/acpi/built-in.a CC arch/x86/platform/efi/efi.o CC arch/x86/kernel/apic/ipi.o CC security/integrity/iint.o CC security/integrity/integrity_audit.o AS arch/x86/entry/vdso/vdso32/note.o CC crypto/asymmetric_keys/x509_public_key.o CC kernel/sched/build_utility.o CC arch/x86/mm/pat/memtype_interval.o AS arch/x86/entry/vdso/vdso32/system_call.o CC ipc/ipc_sysctl.o CC ipc/mqueue.o CC arch/x86/kernel/apic/vector.o CC arch/x86/events/intel/lbr.o CC arch/x86/platform/efi/efi_32.o AR fs/notify/inotify/built-in.a AS arch/x86/entry/vdso/vdso32/sigreturn.o CC fs/notify/fsnotify.o CC fs/quota/dquot.o CC fs/iomap/trace.o AR block/partitions/built-in.a CC fs/notify/notification.o CC arch/x86/entry/vdso/vdso32/vclock_gettime.o CC block/bdev.o CC fs/notify/group.o AR arch/x86/kernel/cpu/microcode/built-in.a CC fs/notify/mark.o CC fs/notify/fdinfo.o CC arch/x86/kernel/apic/init.o CC arch/x86/kernel/apic/hw_nmi.o AR arch/x86/kernel/kprobes/built-in.a CC ipc/namespace.o CC arch/x86/kernel/cpu/mce/amd.o AR init/built-in.a CC fs/proc/task_mmu.o CC fs/proc/inode.o ASN.1 crypto/asymmetric_keys/pkcs7.asn1.[ch] CC crypto/asymmetric_keys/pkcs7_trust.o AR arch/x86/platform/iris/built-in.a CC arch/x86/events/intel/p4.o CC arch/x86/platform/intel/iosf_mbi.o CC arch/x86/kernel/cpu/mtrr/generic.o CC arch/x86/kernel/cpu/scattered.o AS arch/x86/platform/efi/efi_stub_32.o CC fs/iomap/iter.o CC ipc/mq_sysctl.o CC fs/nfs_common/grace.o CC fs/proc/root.o CC security/keys/keyctl.o CC fs/iomap/buffered-io.o CC arch/x86/mm/init_32.o CC crypto/asymmetric_keys/pkcs7_verify.o AR arch/x86/mm/pat/built-in.a CC lib/math/div64.o AS arch/x86/lib/atomic64_cx8_32.o AR drivers/cache/built-in.a AR drivers/irqchip/built-in.a AS arch/x86/lib/checksum_32.o AR security/integrity/built-in.a CC sound/core/seq/seq.o CC arch/x86/lib/cmdline.o CC arch/x86/kernel/apic/io_apic.o AR drivers/bus/mhi/built-in.a CC mm/page-writeback.o CC arch/x86/kernel/apic/msi.o CC arch/x86/kernel/cpu/topology_common.o AR drivers/bus/built-in.a CC arch/x86/kernel/cpu/topology_ext.o CC arch/x86/platform/efi/runtime-map.o CC sound/core/seq/seq_lock.o CC arch/x86/events/intel/p6.o CC lib/math/gcd.o AR drivers/pwm/built-in.a CC arch/x86/mm/fault.o CC sound/core/seq/seq_clientmgr.o CC arch/x86/events/intel/pt.o CC drivers/pci/msi/pcidev_msi.o CC drivers/pci/pcie/portdrv.o AS arch/x86/lib/cmpxchg8b_emu.o AR arch/x86/kernel/fpu/built-in.a CC lib/math/lcm.o CC security/commoncap.o CC arch/x86/lib/cpu.o CC net/core/sock.o LDS arch/x86/kernel/vmlinux.lds CC io_uring/kbuf.o CC lib/math/int_log.o CC lib/math/int_pow.o CC lib/math/int_sqrt.o AR fs/notify/built-in.a CC net/core/request_sock.o CC arch/x86/entry/vdso/vdso32/vgetcpu.o CC arch/x86/mm/ioremap.o CC net/core/skbuff.o CC net/ethernet/eth.o CC lib/math/reciprocal_div.o CC security/keys/permission.o HOSTCC arch/x86/entry/vdso/vdso2c CC fs/iomap/direct-io.o CC net/core/datagram.o CC block/fops.o CC crypto/asymmetric_keys/x509.asn1.o CC arch/x86/kernel/cpu/mtrr/cleanup.o CC drivers/pci/msi/api.o AR arch/x86/platform/efi/built-in.a CC drivers/pci/msi/msi.o CC drivers/video/console/dummycon.o CC arch/x86/kernel/cpu/topology_amd.o CC arch/x86/lib/delay.o AR fs/nfs_common/built-in.a CC lib/math/rational.o CC crypto/asymmetric_keys/x509_akid.asn1.o AR drivers/idle/built-in.a CC drivers/video/backlight/backlight.o AR arch/x86/platform/intel/built-in.a CC fs/iomap/fiemap.o CC arch/x86/events/intel/uncore.o CC crypto/asymmetric_keys/x509_cert_parser.o AR sound/i2c/other/built-in.a AR arch/x86/platform/intel-mid/built-in.a CC lib/crypto/mpi/generic_mpih-lshift.o AR sound/i2c/built-in.a AR arch/x86/platform/intel-quark/built-in.a CC lib/crypto/mpi/generic_mpih-mul1.o AR arch/x86/platform/olpc/built-in.a CC arch/x86/entry/vdso/vdso32-setup.o CC drivers/pci/pcie/rcec.o AR arch/x86/platform/scx200/built-in.a AR arch/x86/platform/ts5500/built-in.a AR lib/math/built-in.a CC lib/crypto/memneq.o CC lib/crypto/mpi/generic_mpih-mul2.o AR ipc/built-in.a CC security/lsm_syscalls.o CC arch/x86/mm/extable.o CC lib/crypto/mpi/generic_mpih-mul3.o AR arch/x86/platform/uv/built-in.a CC fs/quota/quota_v2.o AS arch/x86/lib/getuser.o AR arch/x86/platform/built-in.a CC lib/crypto/utils.o CC io_uring/rsrc.o CC arch/x86/events/intel/uncore_nhmex.o GEN arch/x86/lib/inat-tables.c CC arch/x86/lib/insn-eval.o AR drivers/char/ipmi/built-in.a CC security/selinux/selinuxfs.o CC security/keys/process_keys.o AR virt/lib/built-in.a CC drivers/acpi/acpica/dsargs.o AR virt/built-in.a CC drivers/video/console/vgacon.o CC drivers/acpi/acpica/dscontrol.o CC crypto/asymmetric_keys/pkcs7.asn1.o CC crypto/compress.o VDSO arch/x86/entry/vdso/vdso32.so.dbg CC arch/x86/kernel/cpu/mtrr/amd.o CC sound/core/seq/seq_memory.o CC arch/x86/kernel/cpu/mtrr/cyrix.o OBJCOPY arch/x86/entry/vdso/vdso32.so CC arch/x86/kernel/cpu/mce/threshold.o CC arch/x86/lib/insn.o VDSO2C arch/x86/entry/vdso/vdso-image-32.c CC crypto/asymmetric_keys/pkcs7_parser.o CC arch/x86/entry/vdso/vdso-image-32.o CC arch/x86/kernel/cpu/mtrr/centaur.o CC net/core/stream.o CC fs/proc/base.o AR net/802/built-in.a CC net/core/scm.o CC block/bio.o CC mm/folio-compat.o CC mm/readahead.o CC fs/quota/quota_tree.o CC mm/swap.o CC security/keys/request_key.o CC net/sched/sch_generic.o CC net/sched/sch_mq.o CC drivers/acpi/acpica/dsdebug.o CC crypto/algapi.o CC drivers/acpi/acpica/dsfield.o CC drivers/pci/pcie/aspm.o CC net/sched/sch_frag.o CC drivers/acpi/acpica/dsinit.o CC net/netlink/af_netlink.o CC arch/x86/kernel/apic/probe_32.o AR arch/x86/entry/vdso/built-in.a CC drivers/pci/msi/irqdomain.o CC lib/crypto/mpi/generic_mpih-rshift.o AR drivers/video/backlight/built-in.a AR arch/x86/entry/built-in.a CC block/elevator.o CC sound/core/seq/seq_queue.o AS arch/x86/kernel/head_32.o CC sound/core/seq/seq_fifo.o AR net/ethernet/built-in.a AR drivers/pci/pwrctl/built-in.a CC drivers/pci/hotplug/pci_hotplug_core.o CC fs/quota/quota.o CC fs/quota/kqid.o AR drivers/acpi/pmic/built-in.a CC fs/quota/netlink.o AR crypto/asymmetric_keys/built-in.a CC io_uring/notif.o CC fs/kernfs/mount.o AR arch/x86/kernel/apic/built-in.a CC arch/x86/kernel/head32.o CC fs/iomap/seek.o CC net/sched/sch_api.o CC crypto/scatterwalk.o CC arch/x86/mm/mmap.o CC arch/x86/lib/kaslr.o AR drivers/pci/controller/dwc/built-in.a CC net/sched/sch_blackhole.o CC drivers/acpi/acpica/dsmethod.o AR drivers/pci/controller/mobiveil/built-in.a CC arch/x86/lib/memcpy_32.o CC lib/crypto/mpi/generic_mpih-sub1.o CC arch/x86/kernel/cpu/mtrr/legacy.o AR drivers/pci/controller/plda/built-in.a CC lib/crypto/mpi/generic_mpih-add1.o AR drivers/video/console/built-in.a AR drivers/pci/controller/built-in.a CC lib/crypto/mpi/ec.o AR drivers/video/fbdev/core/built-in.a CC arch/x86/mm/pgtable.o CC drivers/acpi/acpica/dsmthdat.o CC security/keys/request_key_auth.o AR drivers/video/fbdev/omap/built-in.a CC crypto/proc.o AS arch/x86/lib/memmove_32.o AR drivers/pci/switch/built-in.a AR drivers/video/fbdev/omap2/omapfb/dss/built-in.a CC arch/x86/lib/misc.o CC drivers/pci/access.o AR drivers/video/fbdev/omap2/omapfb/displays/built-in.a CC arch/x86/pci/i386.o CC crypto/aead.o CC drivers/pci/bus.o CC sound/core/sound.o CC fs/sysfs/file.o AR arch/x86/kernel/cpu/mtrr/built-in.a AR drivers/video/fbdev/omap2/omapfb/built-in.a CC block/blk-core.o CC arch/x86/lib/pc-conf-reg.o CC fs/kernfs/inode.o CC net/core/gen_stats.o AR drivers/video/fbdev/omap2/built-in.a CC sound/core/seq/seq_prioq.o CC arch/x86/events/intel/uncore_snb.o AR drivers/video/fbdev/built-in.a CC security/min_addr.o CC arch/x86/pci/init.o CC kernel/locking/mutex.o AR drivers/pci/msi/built-in.a CC crypto/geniv.o CC drivers/video/aperture.o CC drivers/pci/hotplug/acpi_pcihp.o CC drivers/video/cmdline.o CC drivers/video/nomodeset.o CC mm/truncate.o CC crypto/lskcipher.o CC lib/crypto/mpi/mpicoder.o CC security/selinux/netlink.o CC fs/iomap/swapfile.o CC drivers/pci/pcie/pme.o CC drivers/acpi/acpica/dsobject.o CC security/selinux/nlmsgtab.o CC fs/devpts/inode.o AR arch/x86/kernel/cpu/mce/built-in.a CC io_uring/tctx.o AS arch/x86/lib/putuser.o CC io_uring/filetable.o CC arch/x86/kernel/cpu/common.o AS arch/x86/lib/retpoline.o AR net/bpf/built-in.a CC mm/vmscan.o CC drivers/video/hdmi.o CC arch/x86/lib/string_32.o CC net/ethtool/ioctl.o AR fs/quota/built-in.a CC net/ethtool/common.o CC security/keys/user_defined.o CC net/ethtool/netlink.o CC arch/x86/mm/physaddr.o CC arch/x86/lib/strstr_32.o CC lib/crypto/chacha.o AR kernel/sched/built-in.a CC crypto/skcipher.o CC security/security.o CC fs/sysfs/dir.o CC block/blk-sysfs.o CC arch/x86/lib/usercopy.o CC net/netfilter/core.o CC sound/core/seq/seq_timer.o CC net/core/gen_estimator.o CC block/blk-flush.o CC lib/crypto/aes.o CC arch/x86/pci/pcbios.o CC net/ethtool/bitset.o CC drivers/acpi/acpica/dsopcode.o CC net/core/net_namespace.o CC arch/x86/power/cpu.o CC net/core/secure_seq.o CC fs/kernfs/dir.o CC net/core/flow_dissector.o CC arch/x86/video/video-common.o CC lib/crypto/mpi/mpi-add.o CC lib/crypto/mpi/mpi-bit.o AR drivers/pci/pcie/built-in.a CC net/ethtool/strset.o CC arch/x86/mm/tlb.o CC fs/kernfs/file.o CC fs/proc/generic.o AR fs/iomap/built-in.a CC fs/kernfs/symlink.o CC security/keys/proc.o CC fs/sysfs/symlink.o CC fs/sysfs/mount.o CC io_uring/rw.o CC arch/x86/lib/usercopy_32.o CC net/netlink/genetlink.o CC net/netlink/policy.o CC crypto/seqiv.o AR drivers/pci/hotplug/built-in.a CC io_uring/net.o CC drivers/pci/probe.o CC io_uring/poll.o CC drivers/acpi/acpica/dspkginit.o CC drivers/acpi/acpica/dsutils.o AR drivers/video/built-in.a CC fs/sysfs/group.o AR fs/devpts/built-in.a CC arch/x86/events/intel/uncore_snbep.o CC arch/x86/events/intel/uncore_discovery.o CC drivers/pnp/pnpacpi/core.o CC arch/x86/power/hibernate_32.o CC arch/x86/lib/msr-smp.o AR arch/x86/video/built-in.a CC kernel/locking/semaphore.o AS arch/x86/power/hibernate_asm_32.o CC arch/x86/power/hibernate.o CC security/selinux/netif.o CC arch/x86/lib/cache-smp.o CC arch/x86/lib/msr.o CC arch/x86/events/intel/cstate.o CC sound/core/seq/seq_system.o CC net/ethtool/linkinfo.o CC security/keys/sysctl.o CC drivers/acpi/acpica/dswexec.o CC security/keys/keyctl_pkey.o CC net/netfilter/nf_log.o CC fs/netfs/buffered_read.o CC kernel/power/qos.o CC fs/proc/array.o CC crypto/echainiv.o CC drivers/pnp/pnpacpi/rsparser.o CC lib/crypto/mpi/mpi-cmp.o CC lib/crypto/mpi/mpi-sub-ui.o CC drivers/pnp/core.o AR drivers/amba/built-in.a CC drivers/pnp/card.o AR drivers/clk/actions/built-in.a CC drivers/pnp/driver.o CC lib/crypto/mpi/mpi-div.o CC kernel/locking/rwsem.o CC drivers/dma/dw/core.o CC drivers/dma/dw/dw.o AR drivers/clk/analogbits/built-in.a CC arch/x86/mm/cpu_entry_area.o CC arch/x86/pci/mmconfig_32.o CC security/selinux/netnode.o AR drivers/clk/bcm/built-in.a CC net/ethtool/linkmodes.o AR drivers/clk/imgtec/built-in.a AR fs/kernfs/built-in.a CC arch/x86/kernel/cpu/rdrand.o CC net/ethtool/rss.o AR fs/sysfs/built-in.a AR drivers/clk/imx/built-in.a CC fs/ext4/balloc.o CC drivers/dma/dw/idma32.o CC lib/crypto/mpi/mpi-inv.o CC crypto/ahash.o CC kernel/printk/printk.o AR security/keys/built-in.a CC sound/core/seq/seq_ports.o AR drivers/clk/ingenic/built-in.a AR arch/x86/power/built-in.a AR drivers/clk/mediatek/built-in.a CC net/core/sysctl_net_core.o CC arch/x86/kernel/cpu/match.o CC net/sched/cls_api.o CC drivers/dma/dw/acpi.o AR drivers/clk/microchip/built-in.a CC drivers/acpi/acpica/dswload.o AR drivers/clk/mstar/built-in.a AR drivers/clk/mvebu/built-in.a CC net/core/dev.o CC kernel/irq/irqdesc.o AR net/netlink/built-in.a CC fs/jbd2/transaction.o AR drivers/clk/ralink/built-in.a AR drivers/clk/renesas/built-in.a CC sound/core/init.o CC fs/ext4/bitmap.o CC block/blk-settings.o CC block/blk-ioc.o AR drivers/clk/socfpga/built-in.a CC block/blk-map.o CC kernel/locking/percpu-rwsem.o CC arch/x86/kernel/cpu/bugs.o AR drivers/clk/sophgo/built-in.a CC drivers/acpi/acpica/dswload2.o AR drivers/clk/sprd/built-in.a CC kernel/power/main.o CC io_uring/eventfd.o CC block/blk-merge.o CC fs/proc/fd.o AR drivers/clk/starfive/built-in.a AS arch/x86/lib/msr-reg.o AR drivers/clk/sunxi-ng/built-in.a CC lib/crypto/mpi/mpi-mod.o CC arch/x86/lib/msr-reg-export.o CC io_uring/uring_cmd.o AR drivers/clk/ti/built-in.a CC block/blk-timeout.o CC arch/x86/pci/direct.o CC block/blk-lib.o AR drivers/clk/versatile/built-in.a CC mm/shrinker.o CC net/netfilter/nf_queue.o CC mm/shmem.o CC net/netfilter/nf_sockopt.o CC arch/x86/mm/maccess.o AR drivers/pnp/pnpacpi/built-in.a AR drivers/clk/xilinx/built-in.a CC drivers/pnp/resource.o AR drivers/clk/built-in.a CC net/netfilter/utils.o CC security/lsm_audit.o CC net/netfilter/nfnetlink.o CC drivers/pci/host-bridge.o CC net/netfilter/nfnetlink_log.o CC sound/core/seq/seq_info.o CC net/netfilter/nf_conntrack_core.o AS arch/x86/lib/hweight.o CC fs/ext4/block_validity.o CC drivers/acpi/acpica/dswscope.o CC fs/netfs/buffered_write.o CC crypto/shash.o CC arch/x86/mm/pgprot.o CC drivers/acpi/acpica/dswstate.o CC block/blk-mq.o CC kernel/locking/spinlock.o CC arch/x86/lib/iomem.o AR drivers/dma/dw/built-in.a CC arch/x86/lib/atomic64_32.o CC kernel/irq/handle.o CC drivers/dma/hsu/hsu.o AR drivers/dma/idxd/built-in.a CC arch/x86/pci/mmconfig-shared.o CC security/selinux/netport.o AR drivers/soc/apple/built-in.a CC security/selinux/status.o CC block/blk-mq-tag.o CC net/ethtool/linkstate.o AR drivers/soc/aspeed/built-in.a CC block/blk-stat.o CC lib/crypto/mpi/mpi-mul.o CC io_uring/openclose.o AR drivers/soc/bcm/built-in.a CC fs/jbd2/commit.o AR drivers/soc/fsl/built-in.a CC kernel/printk/printk_safe.o CC kernel/locking/osq_lock.o CC io_uring/sqpoll.o AR drivers/soc/fujitsu/built-in.a CC kernel/locking/qspinlock.o CC drivers/acpi/acpica/evevent.o CC arch/x86/mm/pgtable_32.o CC arch/x86/kernel/ebda.o AR drivers/soc/hisilicon/built-in.a CC kernel/irq/manage.o CC sound/core/seq/seq_dummy.o CC arch/x86/pci/fixup.o CC net/ethtool/debug.o AR drivers/soc/imx/built-in.a CC arch/x86/lib/inat.o CC fs/proc/proc_tty.o AR drivers/soc/ixp4xx/built-in.a AR arch/x86/lib/built-in.a AR drivers/soc/loongson/built-in.a CC arch/x86/kernel/platform-quirks.o CC io_uring/xattr.o AR drivers/soc/mediatek/built-in.a CC kernel/power/console.o CC arch/x86/kernel/cpu/aperfmperf.o AR arch/x86/events/intel/built-in.a CC crypto/akcipher.o AR arch/x86/lib/lib.a AR drivers/soc/microchip/built-in.a AR arch/x86/events/built-in.a CC lib/crypto/mpi/mpih-cmp.o CC crypto/sig.o CC arch/x86/mm/iomap_32.o CC drivers/pci/remove.o AR drivers/soc/nuvoton/built-in.a AR drivers/soc/pxa/built-in.a CC kernel/locking/rtmutex_api.o CC arch/x86/pci/acpi.o AR drivers/soc/amlogic/built-in.a CC drivers/pnp/manager.o AR drivers/soc/qcom/built-in.a CC arch/x86/kernel/cpu/cpuid-deps.o CC drivers/acpi/acpica/evgpe.o AR drivers/soc/rockchip/built-in.a AR drivers/soc/renesas/built-in.a CC drivers/acpi/acpica/evgpeblk.o AR drivers/soc/sunxi/built-in.a CC arch/x86/mm/hugetlbpage.o CC drivers/pnp/support.o CC crypto/kpp.o CC arch/x86/kernel/process_32.o CC fs/ext4/dir.o CC arch/x86/mm/dump_pagetables.o CC drivers/acpi/dptf/int340x_thermal.o AR drivers/soc/ti/built-in.a AR sound/core/seq/built-in.a AR drivers/dma/mediatek/built-in.a CC fs/ext4/ext4_jbd2.o CC sound/core/memory.o CC lib/zlib_inflate/inffast.o AR drivers/soc/xilinx/built-in.a CC fs/netfs/direct_read.o CC fs/proc/cmdline.o CC lib/zlib_deflate/deflate.o CC fs/netfs/direct_write.o AR drivers/soc/built-in.a CC kernel/printk/nbcon.o CC lib/zlib_inflate/inflate.o AR drivers/dma/hsu/built-in.a CC lib/zlib_inflate/infutil.o CC lib/crypto/mpi/mpih-div.o CC net/sched/act_api.o CC lib/zlib_inflate/inftrees.o AR drivers/dma/qcom/built-in.a CC security/selinux/ss/ebitmap.o AR drivers/dma/stm32/built-in.a CC arch/x86/kernel/signal.o CC lib/zlib_inflate/inflate_syms.o CC arch/x86/pci/legacy.o CC arch/x86/pci/irq.o AR drivers/dma/ti/built-in.a CC net/ethtool/wol.o CC net/ethtool/features.o AR drivers/dma/xilinx/built-in.a CC net/sched/sch_fifo.o CC drivers/dma/dmaengine.o CC arch/x86/mm/highmem_32.o CC fs/netfs/io.o CC drivers/pci/pci.o CC kernel/power/process.o CC lib/lzo/lzo1x_compress.o CC block/blk-mq-sysfs.o CC net/sched/cls_cgroup.o CC fs/proc/consoles.o CC lib/lzo/lzo1x_decompress_safe.o CC net/netfilter/nf_conntrack_standalone.o CC fs/jbd2/recovery.o CC arch/x86/kernel/cpu/umwait.o CC fs/proc/cpuinfo.o CC drivers/acpi/acpica/evgpeinit.o CC kernel/printk/printk_ringbuffer.o CC fs/proc/devices.o AR drivers/acpi/dptf/built-in.a CC net/ethtool/privflags.o CC kernel/locking/qrwlock.o CC lib/zlib_deflate/deftree.o CC arch/x86/pci/common.o CC block/blk-mq-cpumap.o AR lib/zlib_inflate/built-in.a CC io_uring/nop.o CC drivers/pnp/interface.o CC sound/core/control.o CC fs/jbd2/checkpoint.o CC mm/util.o CC fs/jbd2/revoke.o CC security/device_cgroup.o CC io_uring/fs.o CC lib/crypto/mpi/mpih-mul.o ASN.1 crypto/rsapubkey.asn1.[ch] ASN.1 crypto/rsaprivkey.asn1.[ch] CC crypto/rsa.o CC drivers/pci/pci-driver.o CC fs/proc/interrupts.o CC fs/ext4/extents.o CC fs/proc/loadavg.o CC drivers/acpi/acpica/evgpeutil.o AR lib/lzo/built-in.a CC kernel/irq/spurious.o CC fs/netfs/iterator.o AR arch/x86/mm/built-in.a CC lib/lz4/lz4_decompress.o CC fs/netfs/locking.o AR kernel/locking/built-in.a MKCAP arch/x86/kernel/cpu/capflags.c CC arch/x86/kernel/cpu/powerflags.o CC drivers/pci/search.o CC lib/zlib_deflate/deflate_syms.o CC arch/x86/kernel/cpu/topology.o CC sound/core/misc.o CC fs/proc/meminfo.o CC kernel/irq/resend.o CC crypto/rsa_helper.o CC kernel/irq/chip.o CC kernel/printk/sysctl.o CC drivers/pnp/quirks.o CC drivers/acpi/acpica/evglock.o CC security/selinux/ss/hashtab.o CC kernel/irq/dummychip.o CC drivers/acpi/acpica/evhandler.o CC drivers/pnp/system.o CC drivers/dma/virt-dma.o CC crypto/rsa-pkcs1pad.o CC net/ipv4/netfilter/nf_defrag_ipv4.o CC block/blk-mq-sched.o CC fs/ramfs/inode.o CC fs/hugetlbfs/inode.o CC arch/x86/pci/early.o CC block/ioctl.o CC fs/fat/cache.o AR kernel/printk/built-in.a CC block/genhd.o CC sound/core/device.o AR lib/zlib_deflate/built-in.a CC sound/core/info.o CC sound/core/isadma.o CC net/ethtool/rings.o CC net/ethtool/channels.o CC net/ethtool/coalesce.o CC drivers/acpi/x86/apple.o CC fs/proc/stat.o CC drivers/acpi/x86/cmos_rtc.o CC kernel/power/suspend.o CC fs/fat/dir.o CC net/netfilter/nf_conntrack_expect.o CC io_uring/splice.o AR sound/drivers/opl3/built-in.a CC net/ethtool/pause.o CC fs/proc/uptime.o CC lib/crypto/mpi/mpi-pow.o CC drivers/acpi/acpica/evmisc.o CC security/selinux/ss/symtab.o AR sound/drivers/opl4/built-in.a CC sound/core/vmaster.o CC net/sched/ematch.o CC drivers/acpi/acpica/evregion.o CC security/selinux/ss/sidtab.o CC crypto/acompress.o CC fs/isofs/namei.o AR sound/drivers/mpu401/built-in.a CC fs/jbd2/journal.o CC sound/core/ctljack.o AR sound/drivers/vx/built-in.a CC drivers/dma/acpi-dma.o AR drivers/pnp/built-in.a CC fs/fat/fatent.o AR sound/drivers/pcsp/built-in.a CC fs/nfs/client.o CC fs/nfs/dir.o CC kernel/irq/devres.o CC mm/mmzone.o CC fs/isofs/inode.o AR sound/drivers/built-in.a CC arch/x86/pci/bus_numa.o CC drivers/acpi/x86/lpss.o CC fs/isofs/dir.o CC fs/nfs/file.o CC fs/fat/file.o AR fs/hugetlbfs/built-in.a CC fs/netfs/main.o CC fs/nfs/getroot.o AR lib/lz4/built-in.a CC fs/exportfs/expfs.o CC fs/nfs/inode.o CC fs/ramfs/file-mmu.o CC block/ioprio.o CC kernel/irq/autoprobe.o CC block/badblocks.o CC lib/zstd/zstd_decompress_module.o CC drivers/acpi/acpica/evrgnini.o CC lib/xz/xz_dec_syms.o CC lib/zstd/decompress/huf_decompress.o CC fs/proc/util.o AR sound/isa/ad1816a/built-in.a CC lib/zstd/decompress/zstd_ddict.o CC lib/crypto/mpi/mpiutil.o CC sound/core/jack.o CC fs/netfs/misc.o AR sound/isa/ad1848/built-in.a CC net/ipv4/netfilter/nf_reject_ipv4.o CC drivers/virtio/virtio.o CC arch/x86/kernel/cpu/proc.o AR sound/isa/cs423x/built-in.a CC crypto/scompress.o CC io_uring/sync.o CC mm/vmstat.o CC net/ethtool/eee.o CC fs/ext4/extents_status.o CC net/netfilter/nf_conntrack_helper.o CC kernel/irq/irqdomain.o AR sound/isa/es1688/built-in.a AR sound/isa/galaxy/built-in.a CC arch/x86/pci/amd_bus.o AR sound/isa/gus/built-in.a AR drivers/dma/built-in.a CC drivers/acpi/x86/s2idle.o CC net/netfilter/nf_conntrack_proto.o CC fs/proc/version.o CC kernel/rcu/update.o AR sound/isa/msnd/built-in.a AR sound/isa/opti9xx/built-in.a CC net/ethtool/tsinfo.o AR kernel/livepatch/built-in.a AR sound/isa/sb/built-in.a AR net/sched/built-in.a CC arch/x86/kernel/cpu/feat_ctl.o CC drivers/pci/rom.o AR sound/isa/wavefront/built-in.a CC drivers/acpi/tables.o CC drivers/acpi/acpica/evsci.o AR fs/exportfs/built-in.a CC lib/xz/xz_dec_stream.o CC drivers/acpi/osi.o AR sound/isa/wss/built-in.a CC net/core/dev_addr_lists.o AR sound/isa/built-in.a CC security/selinux/ss/avtab.o CC kernel/power/hibernate.o CC lib/xz/xz_dec_lzma2.o CC fs/nfs/super.o AR lib/crypto/mpi/built-in.a CC block/blk-rq-qos.o AR fs/ramfs/built-in.a CC fs/fat/inode.o CC lib/crypto/arc4.o CC drivers/acpi/acpica/evxface.o CC lib/crypto/gf128mul.o CC kernel/power/snapshot.o CC fs/nfs/io.o CC fs/proc/softirqs.o CC sound/core/timer.o CC net/netfilter/nf_conntrack_proto_generic.o CC net/ethtool/cabletest.o CC mm/backing-dev.o CC lib/zstd/decompress/zstd_decompress.o AR arch/x86/pci/built-in.a CC net/netfilter/nf_conntrack_proto_tcp.o CC kernel/power/swap.o CC mm/mm_init.o CC kernel/power/user.o CC crypto/algboss.o CC net/ipv4/netfilter/ip_tables.o CC crypto/testmgr.o CC kernel/dma/mapping.o CC net/netfilter/nf_conntrack_proto_udp.o CC kernel/dma/direct.o CC kernel/irq/proc.o CC drivers/acpi/osl.o CC fs/isofs/util.o CC drivers/virtio/virtio_ring.o CC drivers/acpi/utils.o CC lib/xz/xz_dec_bcj.o CC lib/crypto/blake2s.o CC drivers/pci/setup-res.o CC fs/proc/namespaces.o CC drivers/pci/irq.o CC io_uring/msg_ring.o CC fs/netfs/objects.o CC drivers/acpi/x86/utils.o CC drivers/acpi/x86/blacklist.o CC fs/nfs/direct.o CC drivers/acpi/acpica/evxfevnt.o CC drivers/acpi/acpica/evxfgpe.o CC drivers/acpi/reboot.o CC mm/percpu.o CC fs/ext4/file.o CC lib/crypto/blake2s-generic.o AR lib/xz/built-in.a CC kernel/rcu/sync.o CC fs/lockd/clntlock.o CC kernel/rcu/srcutree.o CC io_uring/advise.o CC fs/proc/self.o CC block/disk-events.o CC mm/slab_common.o CC lib/zstd/decompress/zstd_decompress_block.o AR fs/jbd2/built-in.a CC security/selinux/ss/policydb.o CC mm/compaction.o CC kernel/irq/migration.o CC mm/show_mem.o CC mm/shmem_quota.o CC net/core/dst.o CC kernel/irq/cpuhotplug.o CC net/core/netevent.o CC drivers/tty/vt/vt_ioctl.o CC drivers/pci/vpd.o CC net/ethtool/tunnels.o CC drivers/acpi/acpica/evxfregn.o CC kernel/entry/common.o CC crypto/cmac.o CC kernel/entry/syscall_user_dispatch.o CC kernel/dma/ops_helpers.o CC fs/netfs/write_collect.o CC drivers/acpi/acpica/exconcat.o CC io_uring/epoll.o AR drivers/acpi/x86/built-in.a CC fs/nls/nls_base.o CC fs/nls/nls_cp437.o CC fs/nls/nls_ascii.o CC fs/isofs/rock.o CC fs/nls/nls_iso8859-1.o CC lib/crypto/sha1.o CC lib/crypto/sha256.o CC fs/proc/thread_self.o CC net/netfilter/nf_conntrack_proto_icmp.o CC arch/x86/kernel/signal_32.o CC arch/x86/kernel/traps.o CC arch/x86/kernel/idt.o CC fs/fat/misc.o CC net/ipv4/route.o CC block/blk-ia-ranges.o CC block/early-lookup.o CC block/bounce.o CC drivers/virtio/virtio_anchor.o CC block/bsg.o CC block/blk-cgroup.o CC drivers/acpi/acpica/exconfig.o CC crypto/hmac.o CC fs/ext4/fsmap.o CC kernel/dma/dummy.o CC crypto/crypto_null.o CC net/ipv4/netfilter/iptable_filter.o CC drivers/char/hw_random/core.o CC kernel/dma/remap.o CC drivers/virtio/virtio_pci_modern_dev.o CC sound/core/hrtimer.o CC kernel/rcu/tree.o CC fs/nls/nls_utf8.o AR lib/crypto/built-in.a CC mm/interval_tree.o CC fs/lockd/clntproc.o CC drivers/acpi/acpica/exconvrt.o CC fs/lockd/clntxdr.o CC drivers/acpi/acpica/excreate.o CC fs/proc/proc_sysctl.o CC drivers/pci/setup-bus.o CC drivers/acpi/acpica/exdebug.o CC io_uring/statx.o CC drivers/acpi/acpica/exdump.o CC kernel/irq/pm.o CC drivers/acpi/acpica/exfield.o CC net/netfilter/nf_conntrack_extend.o CC drivers/tty/vt/vc_screen.o CC fs/fat/nfs.o CC kernel/power/poweroff.o CC net/ethtool/fec.o CC net/core/neighbour.o AR kernel/entry/built-in.a CC net/ipv4/inetpeer.o CC net/ipv4/protocol.o CC drivers/virtio/virtio_pci_legacy_dev.o CC arch/x86/kernel/cpu/intel.o CC drivers/virtio/virtio_pci_modern.o CC arch/x86/kernel/cpu/tsx.o AR kernel/dma/built-in.a CC crypto/md5.o CC drivers/char/hw_random/intel-rng.o CC arch/x86/kernel/irq.o CC arch/x86/kernel/irq_32.o CC sound/core/seq_device.o CC kernel/module/main.o AR fs/nls/built-in.a CC kernel/irq/msi.o CC net/ipv4/netfilter/iptable_mangle.o CC kernel/irq/affinity.o CC fs/ext4/fsync.o CC io_uring/timeout.o CC security/selinux/ss/services.o AR kernel/power/built-in.a CC drivers/acpi/acpica/exfldio.o CC drivers/acpi/acpica/exmisc.o CC fs/isofs/export.o CC net/xfrm/xfrm_policy.o CC drivers/virtio/virtio_pci_common.o CC fs/netfs/write_issue.o CC lib/zstd/zstd_common_module.o CC drivers/tty/vt/selection.o CC security/selinux/ss/conditional.o CC security/selinux/ss/mls.o CC net/unix/af_unix.o CC crypto/sha256_generic.o CC net/unix/garbage.o CC net/unix/sysctl_net_unix.o CC drivers/tty/vt/keyboard.o CC [M] sound/core/hwdep.o CC drivers/char/hw_random/amd-rng.o CC kernel/irq/matrix.o CC security/selinux/ss/context.o CC drivers/tty/vt/vt.o CC fs/lockd/host.o COPY drivers/tty/vt/defkeymap.c CC arch/x86/kernel/dumpstack_32.o CC arch/x86/kernel/time.o CC mm/list_lru.o CC drivers/acpi/acpica/exmutex.o CC fs/fat/namei_vfat.o CC block/blk-ioprio.o CC mm/workingset.o CC fs/nfs/pagelist.o CC net/netfilter/nf_conntrack_acct.o CC net/ethtool/eeprom.o CC lib/zstd/common/debug.o CC net/ethtool/stats.o CC lib/zstd/common/entropy_common.o CC drivers/tty/hvc/hvc_console.o CC drivers/pci/vc.o CC security/selinux/netlabel.o CC fs/isofs/joliet.o CC fs/proc/proc_net.o CC fs/isofs/compress.o CC fs/ext4/hash.o CC lib/zstd/common/error_private.o CC kernel/rcu/rcu_segcblist.o CC drivers/acpi/acpica/exnames.o CC net/netfilter/nf_conntrack_seqadj.o CC net/ethtool/phc_vclocks.o CC net/ipv6/netfilter/ip6_tables.o CC crypto/sha512_generic.o CC lib/zstd/common/fse_decompress.o CC kernel/time/time.o CC [M] sound/core/pcm.o CC net/ipv4/netfilter/ipt_REJECT.o CC [M] net/ipv4/netfilter/iptable_nat.o CC drivers/char/hw_random/geode-rng.o CC io_uring/fdinfo.o CC arch/x86/kernel/ioport.o CC arch/x86/kernel/dumpstack.o CC drivers/virtio/virtio_pci_legacy.o CC crypto/sha3_generic.o AR drivers/tty/hvc/built-in.a CC crypto/ecb.o CC lib/zstd/common/zstd_common.o CC crypto/cbc.o CC net/netfilter/nf_conntrack_proto_icmpv6.o CC net/packet/af_packet.o CC drivers/acpi/acpica/exoparg1.o CC mm/debug.o CC drivers/acpi/acpica/exoparg2.o CC drivers/acpi/acpica/exoparg3.o AR fs/netfs/built-in.a CC [M] sound/core/pcm_native.o CC block/blk-iolatency.o CC crypto/ctr.o CC block/blk-iocost.o CC drivers/pci/mmap.o CC fs/ext4/ialloc.o CC fs/fat/namei_msdos.o CC fs/proc/kcore.o CC crypto/gcm.o CC net/xfrm/xfrm_state.o CC net/xfrm/xfrm_hash.o AR lib/zstd/built-in.a CC drivers/acpi/acpica/exoparg6.o CC lib/dim/dim.o CC lib/fonts/fonts.o CC lib/argv_split.o CC crypto/ccm.o CC drivers/acpi/acpica/exprep.o CC crypto/aes_generic.o CC lib/bug.o CC fs/lockd/svc.o CC kernel/module/strict_rwx.o CC fs/lockd/svclock.o CC drivers/char/hw_random/via-rng.o AR kernel/irq/built-in.a AR fs/isofs/built-in.a CC crypto/crc32c_generic.o CC fs/nfs/read.o CC crypto/authenc.o CC drivers/pci/devres.o CC drivers/pci/proc.o CC drivers/virtio/virtio_pci_admin_legacy_io.o CC net/ipv6/netfilter/ip6table_filter.o CC fs/nfs/symlink.o CC drivers/tty/vt/consolemap.o CC net/core/rtnetlink.o CC mm/gup.o CC fs/ext4/indirect.o CC drivers/virtio/virtio_input.o CC block/mq-deadline.o CC lib/fonts/font_8x16.o CC kernel/time/timer.o CC lib/dim/net_dim.o AR fs/fat/built-in.a AR net/unix/built-in.a CC kernel/time/hrtimer.o CC crypto/authencesn.o CC crypto/lzo.o CC kernel/futex/core.o CC io_uring/cancel.o AR security/selinux/built-in.a CC drivers/acpi/acpica/exregion.o AR drivers/char/hw_random/built-in.a AR security/built-in.a CC net/ethtool/mm.o CC drivers/char/agp/backend.o AR net/ipv4/netfilter/built-in.a CC net/ipv4/ip_input.o CC drivers/char/mem.o CC drivers/char/random.o HOSTCC drivers/tty/vt/conmakehash CC drivers/char/agp/generic.o CC kernel/module/kmod.o CC drivers/char/agp/isoch.o CC lib/buildid.o CC io_uring/waitid.o CC lib/clz_tab.o CC net/netfilter/nf_conntrack_netlink.o CC lib/dim/rdma_dim.o AR fs/unicode/built-in.a CC fs/proc/vmcore.o AR lib/fonts/built-in.a CC net/ethtool/module.o CC fs/ext4/inline.o CC net/ethtool/cmis_fw_update.o CC drivers/char/agp/amd64-agp.o CC drivers/tty/vt/defkeymap.o CC drivers/acpi/acpica/exresnte.o CC drivers/pci/pci-sysfs.o CC arch/x86/kernel/cpu/intel_epb.o CC kernel/module/tree_lookup.o CC net/ipv6/netfilter/ip6table_mangle.o CC fs/autofs/init.o CC drivers/virtio/virtio_dma_buf.o CC fs/nfs/unlink.o CC block/kyber-iosched.o CONMK drivers/tty/vt/consolemap_deftbl.c CC fs/9p/vfs_super.o CC fs/ext4/inode.o CC drivers/tty/vt/consolemap_deftbl.o CC fs/lockd/svcshare.o CC fs/9p/vfs_inode.o CC drivers/acpi/acpica/exresolv.o AR drivers/tty/vt/built-in.a CC crypto/lzo-rle.o AR drivers/iommu/amd/built-in.a CC drivers/tty/serial/8250/8250_core.o CC drivers/tty/serial/8250/8250_platform.o AR drivers/gpu/host1x/built-in.a AR drivers/iommu/intel/built-in.a CC kernel/futex/syscalls.o CC drivers/tty/serial/serial_core.o AR drivers/iommu/arm/arm-smmu/built-in.a CC drivers/acpi/acpica/exresop.o AR drivers/iommu/arm/arm-smmu-v3/built-in.a AR drivers/iommu/arm/built-in.a AR drivers/iommu/iommufd/built-in.a CC drivers/iommu/iommu.o CC drivers/tty/serial/serial_base_bus.o CC arch/x86/kernel/nmi.o CC fs/ext4/ioctl.o CC net/ipv4/ip_fragment.o CC fs/autofs/inode.o CC net/ipv4/ip_forward.o CC drivers/char/agp/intel-agp.o CC kernel/module/kallsyms.o CC kernel/cgroup/cgroup.o AR drivers/gpu/drm/tests/built-in.a CC drivers/acpi/nvs.o CC [M] sound/core/pcm_lib.o CC crypto/rng.o CC fs/proc/kmsg.o AR drivers/gpu/drm/arm/built-in.a CC net/xfrm/xfrm_input.o AR lib/dim/built-in.a CC net/ipv6/netfilter/nf_defrag_ipv6_hooks.o CC io_uring/register.o AR drivers/virtio/built-in.a CC block/blk-mq-pci.o CC drivers/gpu/drm/display/drm_display_helper_mod.o CC net/ipv4/ip_options.o CC lib/cmdline.o CC mm/mmap_lock.o CC mm/highmem.o CC drivers/pci/slot.o CC block/blk-mq-virtio.o CC mm/memory.o CC drivers/acpi/acpica/exserial.o CC drivers/tty/serial/8250/8250_pnp.o CC net/ethtool/cmis_cdb.o CC lib/cpumask.o CC fs/nfs/write.o CC fs/nfs/namespace.o CC fs/lockd/svcproc.o AR net/packet/built-in.a AR kernel/rcu/built-in.a CC fs/lockd/svcsubs.o CC fs/9p/vfs_inode_dotl.o CC fs/lockd/mon.o CC kernel/module/procfs.o CC drivers/gpu/drm/display/drm_dp_dual_mode_helper.o CC fs/autofs/root.o CC arch/x86/kernel/ldt.o CC drivers/char/agp/intel-gtt.o CC drivers/acpi/acpica/exstore.o CC fs/proc/page.o CC kernel/futex/pi.o CC net/ipv4/ip_output.o CC drivers/pci/pci-acpi.o CC drivers/pci/iomap.o CC fs/lockd/trace.o CC net/ipv4/ip_sockglue.o CC drivers/tty/serial/8250/8250_rsa.o CC [M] sound/core/pcm_misc.o CC drivers/acpi/acpica/exstoren.o CC [M] sound/core/pcm_memory.o CC kernel/time/timekeeping.o CC drivers/gpu/drm/ttm/ttm_tt.o CC drivers/gpu/drm/ttm/ttm_bo.o CC drivers/gpu/drm/ttm/ttm_bo_util.o CC drivers/gpu/drm/ttm/ttm_bo_vm.o CC crypto/drbg.o CC drivers/gpu/drm/ttm/ttm_module.o CC lib/ctype.o CC drivers/gpu/drm/display/drm_dp_helper.o CC kernel/module/sysfs.o CC lib/dec_and_lock.o CC lib/decompress.o CC io_uring/truncate.o CC block/blk-mq-debugfs.o AR fs/hostfs/built-in.a CC block/blk-pm.o CC drivers/gpu/drm/ttm/ttm_execbuf_util.o CC fs/debugfs/inode.o CC drivers/acpi/acpica/exstorob.o CC fs/tracefs/inode.o AR fs/proc/built-in.a CC net/core/utils.o CC fs/9p/vfs_addr.o CC crypto/jitterentropy.o CC crypto/jitterentropy-kcapi.o CC kernel/futex/requeue.o AR drivers/char/agp/built-in.a CC block/holder.o CC fs/autofs/symlink.o CC drivers/char/misc.o CC lib/decompress_bunzip2.o CC net/ipv6/netfilter/nf_conntrack_reasm.o CC [M] sound/core/memalloc.o CC net/netfilter/nf_conntrack_ftp.o CC lib/decompress_inflate.o AR kernel/module/built-in.a CC net/xfrm/xfrm_output.o CC [M] sound/core/pcm_timer.o CC [M] fs/efivarfs/inode.o CC fs/tracefs/event_inode.o CC drivers/gpu/drm/ttm/ttm_range_manager.o CC drivers/acpi/acpica/exsystem.o CC drivers/acpi/acpica/extrace.o CC drivers/gpu/drm/ttm/ttm_resource.o CC net/ethtool/pse-pd.o CC net/ipv6/netfilter/nf_reject_ipv6.o CC drivers/gpu/drm/ttm/ttm_pool.o CC drivers/gpu/drm/ttm/ttm_device.o CC drivers/pci/quirks.o CC drivers/char/virtio_console.o CC fs/debugfs/file.o CC drivers/tty/serial/8250/8250_port.o CC kernel/time/ntp.o CC drivers/pci/pci-label.o AR drivers/tty/ipwireless/built-in.a CC drivers/tty/tty_io.o CC drivers/tty/n_tty.o CC drivers/gpu/drm/ttm/ttm_sys_manager.o CC net/ipv4/inet_hashtables.o CC crypto/ghash-generic.o LD [M] sound/core/snd-hwdep.o CC fs/nfs/mount_clnt.o CC drivers/tty/tty_ioctl.o CC fs/nfs/nfstrace.o CC io_uring/memmap.o CC io_uring/io-wq.o CC io_uring/futex.o CC drivers/acpi/acpica/exutils.o CC drivers/tty/serial/8250/8250_dma.o CC fs/nfs/export.o AR fs/tracefs/built-in.a CC drivers/iommu/iommu-traces.o AR block/built-in.a CC drivers/iommu/iommu-sysfs.o CC lib/decompress_unlz4.o CC [M] fs/efivarfs/file.o CC lib/decompress_unlzma.o CC net/netfilter/nf_conntrack_irc.o CC drivers/iommu/dma-iommu.o CC crypto/hash_info.o CC fs/lockd/xdr.o CC net/xfrm/xfrm_sysctl.o CC net/xfrm/xfrm_replay.o CC kernel/time/clocksource.o CC crypto/rsapubkey.asn1.o CC fs/autofs/waitq.o CC crypto/rsaprivkey.asn1.o CC net/core/link_watch.o CC net/ipv6/af_inet6.o CC mm/mincore.o CC fs/9p/vfs_file.o CC net/netfilter/nf_conntrack_sip.o CC drivers/acpi/acpica/hwacpi.o CC kernel/futex/waitwake.o CC fs/9p/vfs_dir.o AR crypto/built-in.a AR sound/core/built-in.a CC drivers/acpi/acpica/hwesleep.o CC drivers/connector/cn_queue.o LD [M] sound/core/snd-pcm.o CC drivers/gpu/drm/ttm/ttm_agp_backend.o AR sound/pci/ac97/built-in.a AR sound/ppc/built-in.a CC io_uring/napi.o CC fs/ext4/mballoc.o CC net/netfilter/nf_nat_core.o AR sound/pci/ali5451/built-in.a CC fs/ext4/migrate.o CC drivers/connector/connector.o CC drivers/acpi/acpica/hwgpe.o AR sound/pci/asihpi/built-in.a CC drivers/tty/tty_ldisc.o CC drivers/tty/tty_buffer.o AR sound/pci/au88x0/built-in.a AR sound/pci/aw2/built-in.a AR sound/pci/ctxfi/built-in.a CC net/ipv6/netfilter/ip6t_ipv6header.o CC net/ipv6/netfilter/ip6t_REJECT.o AR sound/pci/ca0106/built-in.a CC drivers/tty/tty_port.o AR sound/pci/cs46xx/built-in.a CC drivers/tty/tty_mutex.o AR drivers/gpu/drm/ttm/built-in.a CC fs/ext4/mmp.o CC fs/ext4/move_extent.o AR sound/pci/cs5535audio/built-in.a CC fs/ext4/namei.o AR sound/pci/lola/built-in.a AR fs/debugfs/built-in.a AR sound/pci/lx6464es/built-in.a CC drivers/tty/serial/8250/8250_dwlib.o CC drivers/gpu/drm/display/drm_dp_mst_topology.o CC lib/decompress_unlzo.o CC drivers/char/hpet.o CC fs/autofs/expire.o AR sound/pci/echoaudio/built-in.a CC net/ethtool/plca.o CC drivers/acpi/acpica/hwregs.o CC [M] fs/efivarfs/super.o CC drivers/acpi/acpica/hwsleep.o AR sound/pci/emu10k1/built-in.a CC net/xfrm/xfrm_device.o AR drivers/gpu/drm/renesas/rcar-du/built-in.a CC mm/mlock.o AR sound/pci/hda/built-in.a CC [M] sound/pci/hda/hda_bind.o AR drivers/gpu/drm/renesas/rz-du/built-in.a CC drivers/gpu/drm/i915/i915_config.o CC kernel/time/jiffies.o AR drivers/gpu/drm/renesas/built-in.a AR sound/pci/ice1712/built-in.a CC drivers/pci/vgaarb.o CC fs/ext4/page-io.o CC fs/ext4/readpage.o AR kernel/futex/built-in.a CC fs/ext4/resize.o CC fs/autofs/dev-ioctl.o CC net/ipv4/inet_timewait_sock.o CC kernel/cgroup/rstat.o CC net/core/filter.o CC drivers/acpi/acpica/hwvalid.o CC drivers/iommu/iova.o CC net/ipv4/inet_connection_sock.o CC drivers/connector/cn_proc.o CC fs/9p/vfs_dentry.o CC arch/x86/kernel/setup.o CC lib/decompress_unxz.o CC arch/x86/kernel/x86_init.o CC drivers/gpu/drm/i915/i915_driver.o CC net/netfilter/nf_nat_proto.o CC net/netfilter/nf_nat_helper.o CC net/netfilter/nf_nat_masquerade.o CC drivers/tty/serial/8250/8250_pcilib.o CC drivers/acpi/wakeup.o CC drivers/char/nvram.o CC net/core/sock_diag.o AR io_uring/built-in.a CC drivers/gpu/drm/display/drm_dsc_helper.o CC net/core/dev_ioctl.o CC kernel/time/timer_list.o CC [M] fs/efivarfs/vars.o CC drivers/acpi/acpica/hwxface.o CC fs/nfs/sysfs.o CC fs/lockd/clnt4xdr.o CC lib/decompress_unzstd.o CC kernel/trace/trace_clock.o CC fs/nfs/fs_context.o CC mm/mmap.o CC [M] sound/pci/hda/hda_codec.o CC mm/mmu_gather.o AR drivers/gpu/vga/built-in.a AR net/ipv6/netfilter/built-in.a CC kernel/cgroup/namespace.o CC kernel/cgroup/cgroup-v1.o CC lib/dump_stack.o CC net/ipv6/anycast.o CC lib/earlycpio.o AR drivers/pci/built-in.a CC fs/ext4/super.o CC fs/9p/v9fs.o CC fs/9p/fid.o CC fs/nfs/nfsroot.o AR net/ethtool/built-in.a CC drivers/base/power/sysfs.o CC fs/9p/xattr.o CC drivers/base/power/generic_ops.o AR fs/autofs/built-in.a CC drivers/base/firmware_loader/builtin/main.o CC drivers/tty/serial/8250/8250_early.o CC drivers/base/power/common.o CC kernel/trace/ring_buffer.o CC net/ipv6/ip6_output.o AR drivers/iommu/built-in.a CC fs/nfs/sysctl.o CC net/xfrm/xfrm_nat_keepalive.o CC drivers/acpi/acpica/hwxfsleep.o CC drivers/base/firmware_loader/main.o CC kernel/time/timeconv.o CC drivers/tty/tty_ldsem.o AR drivers/connector/built-in.a AR sound/arm/built-in.a CC kernel/time/timecounter.o CC drivers/tty/serial/8250/8250_exar.o AR drivers/char/built-in.a AR drivers/base/firmware_loader/builtin/built-in.a CC arch/x86/kernel/i8259.o CC drivers/tty/tty_baudrate.o CC arch/x86/kernel/irqinit.o CC arch/x86/kernel/jump_label.o CC [M] sound/pci/hda/hda_jack.o LD [M] fs/efivarfs/efivarfs.o CC kernel/trace/trace.o AR net/dsa/built-in.a CC net/xfrm/xfrm_algo.o CC drivers/base/power/qos.o CC drivers/base/power/runtime.o CC fs/open.o CC arch/x86/kernel/irq_work.o CC kernel/trace/trace_output.o CC lib/extable.o CC net/core/tso.o CC fs/lockd/xdr4.o CC net/core/sock_reuseport.o CC fs/lockd/svc4proc.o CC drivers/acpi/acpica/hwpci.o AR drivers/gpu/drm/omapdrm/built-in.a AR fs/9p/built-in.a CC drivers/base/regmap/regmap.o CC net/core/fib_notifier.o CC drivers/acpi/sleep.o CC kernel/time/alarmtimer.o AR drivers/gpu/drm/tilcdc/built-in.a CC arch/x86/kernel/cpu/amd.o CC kernel/time/posix-timers.o CC kernel/trace/trace_seq.o CC kernel/time/posix-cpu-timers.o CC drivers/acpi/acpica/nsaccess.o CC lib/flex_proportions.o CC kernel/trace/trace_stat.o CC net/netfilter/nf_nat_ftp.o CC fs/ext4/symlink.o CC drivers/acpi/acpica/nsalloc.o CC kernel/cgroup/freezer.o CC net/ipv4/tcp.o CC net/netfilter/nf_nat_irc.o CC arch/x86/kernel/probe_roms.o CC net/netfilter/nf_nat_sip.o CC net/ipv4/tcp_input.o CC drivers/tty/serial/8250/8250_lpss.o AR drivers/base/firmware_loader/built-in.a CC kernel/cgroup/legacy_freezer.o CC kernel/fork.o CC kernel/events/core.o CC kernel/bpf/core.o CC net/xfrm/xfrm_user.o CC lib/idr.o AR drivers/base/test/built-in.a CC drivers/acpi/acpica/nsarguments.o CC drivers/tty/serial/serial_ctrl.o CC drivers/acpi/acpica/nsconvert.o CC net/ipv4/tcp_output.o CC arch/x86/kernel/sys_ia32.o CC drivers/gpu/drm/i915/i915_drm_client.o CC arch/x86/kernel/ksysfs.o CC arch/x86/kernel/bootflag.o CC drivers/gpu/drm/display/drm_hdcp_helper.o CC kernel/events/ring_buffer.o CC mm/mprotect.o CC kernel/trace/trace_printk.o CC drivers/tty/tty_jobctrl.o CC net/sunrpc/auth_gss/auth_gss.o CC fs/nfs/nfs3super.o CC fs/lockd/procfs.o CC drivers/tty/n_null.o CC drivers/tty/serial/8250/8250_mid.o CC drivers/base/power/wakeirq.o CC fs/nfs/nfs3client.o CC net/netfilter/x_tables.o CC drivers/tty/pty.o CC net/core/xdp.o CC drivers/acpi/acpica/nsdump.o CC net/ipv4/tcp_timer.o CC drivers/acpi/acpica/nseval.o CC lib/irq_regs.o CC drivers/acpi/acpica/nsinit.o CC net/sunrpc/auth_gss/gss_generic_token.o CC kernel/exec_domain.o CC drivers/tty/serial/serial_port.o CC drivers/tty/serial/earlycon.o AR sound/sh/built-in.a CC kernel/time/posix-clock.o CC drivers/gpu/drm/display/drm_hdmi_helper.o CC drivers/block/loop.o CC kernel/time/itimer.o CC [M] sound/pci/hda/hda_auto_parser.o AR drivers/misc/eeprom/built-in.a CC kernel/cgroup/pids.o AR fs/lockd/built-in.a CC drivers/base/regmap/regcache.o CC lib/is_single_threaded.o AR drivers/misc/cb710/built-in.a CC kernel/cgroup/rdma.o CC net/ipv6/ip6_input.o CC mm/mremap.o CC kernel/cgroup/cpuset.o CC arch/x86/kernel/cpu/hygon.o CC kernel/cgroup/misc.o AR drivers/misc/ti-st/built-in.a CC arch/x86/kernel/e820.o CC kernel/events/callchain.o CC drivers/tty/serial/8250/8250_pci.o AR drivers/mfd/built-in.a CC drivers/base/power/main.o AR drivers/misc/lis3lv02d/built-in.a CC drivers/base/regmap/regcache-rbtree.o CC drivers/tty/serial/8250/8250_pericom.o AR drivers/misc/cardreader/built-in.a CC drivers/base/regmap/regcache-flat.o AR drivers/misc/keba/built-in.a CC [M] sound/pci/hda/hda_sysfs.o AR drivers/misc/built-in.a CC drivers/tty/tty_audit.o CC drivers/acpi/acpica/nsload.o CC kernel/events/hw_breakpoint.o CC drivers/gpu/drm/display/drm_scdc_helper.o CC drivers/base/power/wakeup.o CC fs/nfs/nfs3proc.o CC lib/klist.o CC drivers/base/regmap/regcache-maple.o CC kernel/time/clockevents.o CC drivers/gpu/drm/i915/i915_getparam.o CC kernel/cgroup/debug.o CC drivers/base/regmap/regmap-debugfs.o CC drivers/tty/sysrq.o CC fs/nfs/nfs3xdr.o CC kernel/time/tick-common.o CC drivers/base/component.o CC mm/msync.o CC drivers/acpi/acpica/nsnames.o CC kernel/panic.o CC drivers/gpu/drm/virtio/virtgpu_drv.o AR net/xfrm/built-in.a CC drivers/gpu/drm/virtio/virtgpu_kms.o CC lib/kobject.o AR sound/pci/korg1212/built-in.a CC drivers/gpu/drm/virtio/virtgpu_gem.o CC arch/x86/kernel/pci-dma.o CC lib/kobject_uevent.o CC net/core/flow_offload.o CC mm/page_vma_mapped.o CC kernel/trace/pid_list.o CC drivers/gpu/drm/i915/i915_ioctl.o CC net/sunrpc/auth_gss/gss_mech_switch.o CC kernel/cpu.o CC mm/pagewalk.o CC drivers/acpi/acpica/nsobject.o CC mm/pgtable-generic.o AR drivers/gpu/drm/display/built-in.a CC drivers/acpi/acpica/nsparse.o CC kernel/trace/trace_sched_switch.o AR drivers/base/regmap/built-in.a CC net/sunrpc/clnt.o CC drivers/gpu/drm/i915/i915_irq.o CC drivers/block/virtio_blk.o CC kernel/trace/trace_nop.o CC lib/logic_pio.o CC [M] sound/pci/hda/hda_controller.o CC drivers/gpu/drm/virtio/virtgpu_vram.o AR drivers/gpu/drm/imx/built-in.a CC kernel/exit.o AR kernel/bpf/built-in.a CC fs/read_write.o CC drivers/gpu/drm/i915/i915_mitigations.o AR drivers/gpu/drm/i2c/built-in.a CC net/netfilter/xt_tcpudp.o CC lib/maple_tree.o CC net/netfilter/xt_CONNSECMARK.o CC kernel/trace/blktrace.o CC net/netfilter/xt_NFLOG.o AR drivers/tty/serial/8250/built-in.a CC fs/file_table.o AR drivers/tty/serial/built-in.a CC drivers/acpi/acpica/nspredef.o CC mm/rmap.o CC drivers/base/core.o AR drivers/tty/built-in.a CC drivers/base/bus.o CC net/ipv6/addrconf.o CC net/ipv6/addrlabel.o CC kernel/time/tick-broadcast.o CC mm/vmalloc.o CC mm/process_vm_access.o CC mm/page_alloc.o CC drivers/base/power/wakeup_stats.o CC kernel/softirq.o CC fs/ext4/sysfs.o CC net/sunrpc/auth_gss/svcauth_gss.o CC mm/init-mm.o CC drivers/base/power/trace.o CC fs/nfs/nfs3acl.o CC fs/ext4/xattr.o CC fs/ext4/xattr_hurd.o CC fs/ext4/xattr_trusted.o AR kernel/cgroup/built-in.a CC fs/ext4/xattr_user.o CC fs/ext4/fast_commit.o CC kernel/resource.o CC drivers/gpu/drm/virtio/virtgpu_display.o CC fs/nfs/nfs4proc.o CC fs/ext4/orphan.o CC drivers/acpi/acpica/nsprepkg.o CC drivers/base/dd.o CC arch/x86/kernel/cpu/centaur.o CC kernel/events/uprobes.o CC kernel/trace/trace_events.o CC [M] sound/pci/hda/hda_proc.o AR sound/pci/mixart/built-in.a AR sound/pci/nm256/built-in.a CC [M] sound/pci/hda/hda_hwdep.o CC kernel/time/tick-broadcast-hrtimer.o CC net/sunrpc/auth_gss/gss_rpc_upcall.o AR sound/synth/emux/built-in.a AR sound/synth/built-in.a CC arch/x86/kernel/quirks.o CC drivers/gpu/drm/i915/i915_module.o CC arch/x86/kernel/kdebugfs.o CC net/sunrpc/xprt.o CC arch/x86/kernel/alternative.o AR net/wireless/tests/built-in.a CC net/netfilter/xt_SECMARK.o CC net/wireless/core.o CC net/netfilter/xt_TCPMSS.o CC net/ipv4/tcp_ipv4.o AR drivers/block/built-in.a CC net/netfilter/xt_conntrack.o AR drivers/gpu/drm/panel/built-in.a CC net/netfilter/xt_policy.o CC net/netfilter/xt_state.o CC lib/memcat_p.o CC drivers/gpu/drm/virtio/virtgpu_vq.o CC drivers/acpi/acpica/nsrepair.o CC kernel/time/tick-oneshot.o CC drivers/acpi/acpica/nsrepair2.o AR drivers/base/power/built-in.a CC drivers/acpi/acpica/nssearch.o CC kernel/trace/trace_export.o CC kernel/trace/trace_event_perf.o CC kernel/trace/trace_events_filter.o CC fs/nfs/nfs4xdr.o CC arch/x86/kernel/cpu/transmeta.o CC net/ipv4/tcp_minisocks.o CC fs/super.o CC drivers/acpi/device_sysfs.o CC fs/ext4/acl.o CC [M] net/netfilter/nf_log_syslog.o CC mm/memblock.o AR sound/pci/oxygen/built-in.a CC net/sunrpc/socklib.o CC arch/x86/kernel/i8253.o AR drivers/gpu/drm/hisilicon/built-in.a AR drivers/gpu/drm/bridge/analogix/built-in.a CC arch/x86/kernel/hw_breakpoint.o AR drivers/gpu/drm/bridge/cadence/built-in.a CC lib/nmi_backtrace.o AR drivers/gpu/drm/bridge/imx/built-in.a CC net/wireless/sysfs.o CC net/ipv6/route.o CC kernel/time/tick-sched.o AR drivers/gpu/drm/bridge/synopsys/built-in.a AR sound/usb/misc/built-in.a CC drivers/acpi/acpica/nsutils.o AR drivers/gpu/drm/bridge/built-in.a CC [M] sound/pci/hda/patch_hdmi.o AR sound/usb/usx2y/built-in.a CC mm/slub.o AR sound/usb/caiaq/built-in.a CC lib/objpool.o AR sound/usb/6fire/built-in.a CC lib/plist.o CC lib/radix-tree.o CC fs/char_dev.o AR sound/usb/hiface/built-in.a CC fs/stat.o CC lib/ratelimit.o CC arch/x86/kernel/tsc.o AR sound/usb/bcd2000/built-in.a CC drivers/acpi/device_pm.o CC arch/x86/kernel/tsc_msr.o CC drivers/gpu/drm/i915/i915_params.o AR sound/usb/built-in.a CC drivers/acpi/proc.o CC net/sunrpc/xprtsock.o CC net/sunrpc/auth_gss/gss_rpc_xdr.o CC kernel/time/timer_migration.o CC kernel/time/vsyscall.o AR sound/pci/pcxhr/built-in.a CC [M] net/netfilter/xt_mark.o CC net/sunrpc/auth_gss/trace.o CC [M] net/netfilter/xt_nat.o CC mm/madvise.o CC net/sunrpc/auth_gss/gss_krb5_mech.o AR net/mac80211/tests/built-in.a CC net/wireless/radiotap.o CC net/mac80211/main.o CC net/mac80211/status.o CC drivers/gpu/drm/virtio/virtgpu_fence.o CC drivers/acpi/acpica/nswalk.o CC lib/rbtree.o CC kernel/trace/trace_events_trigger.o CC arch/x86/kernel/cpu/zhaoxin.o CC drivers/base/syscore.o CC arch/x86/kernel/cpu/vortex.o CC net/ipv6/ip6_fib.o CC arch/x86/kernel/cpu/perfctr-watchdog.o AR kernel/events/built-in.a CC net/mac80211/driver-ops.o CC drivers/acpi/bus.o CC fs/nfs/nfs4state.o CC drivers/acpi/acpica/nsxfeval.o CC fs/exec.o CC net/core/gro.o CC drivers/gpu/drm/virtio/virtgpu_object.o CC fs/ext4/xattr_security.o CC arch/x86/kernel/io_delay.o CC fs/nfs/nfs4renewd.o CC fs/nfs/nfs4super.o CC arch/x86/kernel/rtc.o CC fs/nfs/nfs4file.o CC drivers/acpi/acpica/nsxfname.o CC fs/nfs/delegation.o CC net/sunrpc/auth_gss/gss_krb5_seal.o CC net/netlabel/netlabel_user.o CC drivers/gpu/drm/i915/i915_pci.o CC drivers/acpi/acpica/nsxfobj.o CC net/netlabel/netlabel_kapi.o CC arch/x86/kernel/cpu/vmware.o CC fs/nfs/nfs4idmap.o CC net/netlabel/netlabel_domainhash.o CC net/rfkill/core.o CC drivers/acpi/acpica/psargs.o CC [M] net/netfilter/xt_LOG.o CC net/9p/mod.o CC net/dns_resolver/dns_key.o AR drivers/nfc/built-in.a CC net/ipv6/ipv6_sockglue.o CC net/ipv6/ndisc.o CC kernel/trace/trace_eprobe.o CC net/ipv6/udp.o CC drivers/base/driver.o CC mm/page_io.o CC drivers/base/class.o AR sound/firewire/built-in.a CC drivers/gpu/drm/virtio/virtgpu_debugfs.o CC arch/x86/kernel/cpu/hypervisor.o CC net/9p/client.o CC net/ipv4/tcp_cong.o CC arch/x86/kernel/cpu/mshyperv.o CC kernel/time/timekeeping_debug.o CC net/sunrpc/auth_gss/gss_krb5_unseal.o CC net/ipv4/tcp_metrics.o CC drivers/acpi/acpica/psloop.o CC net/core/netdev-genl.o CC drivers/acpi/acpica/psobject.o CC net/9p/error.o CC drivers/gpu/drm/virtio/virtgpu_plane.o CC fs/nfs/callback.o CC drivers/gpu/drm/i915/i915_scatterlist.o CC net/core/netdev-genl-gen.o CC net/rfkill/input.o CC net/netlabel/netlabel_addrlist.o CC net/dns_resolver/dns_query.o CC [M] sound/pci/hda/hda_eld.o AR fs/ext4/built-in.a AR drivers/dax/hmem/built-in.a AR drivers/dax/built-in.a CC drivers/dma-buf/dma-buf.o CC net/core/gso.o CC net/ipv4/tcp_fastopen.o CC [M] net/netfilter/xt_MASQUERADE.o CC net/ipv4/tcp_rate.o CC net/ipv4/tcp_recovery.o CC drivers/acpi/acpica/psopcode.o CC net/ipv4/tcp_ulp.o CC lib/seq_buf.o CC fs/pipe.o CC net/ipv4/tcp_offload.o CC drivers/base/platform.o CC drivers/acpi/acpica/psopinfo.o CC fs/namei.o CC fs/fcntl.o CC kernel/time/namespace.o CC net/wireless/util.o AR net/rfkill/built-in.a CC net/sunrpc/auth_gss/gss_krb5_wrap.o AR net/dns_resolver/built-in.a CC net/core/net-sysfs.o CC net/core/hotdata.o AR sound/sparc/built-in.a CC drivers/gpu/drm/i915/i915_suspend.o CC net/handshake/alert.o CC net/sunrpc/auth_gss/gss_krb5_crypto.o CC net/9p/protocol.o CC drivers/gpu/drm/virtio/virtgpu_ioctl.o CC kernel/trace/trace_kprobe.o CC drivers/gpu/drm/i915/i915_switcheroo.o CC net/sunrpc/auth_gss/gss_krb5_keys.o CC kernel/sysctl.o CC drivers/acpi/acpica/psparse.o CC kernel/capability.o AR kernel/time/built-in.a CC net/netlabel/netlabel_mgmt.o CC net/mac80211/sta_info.o CC drivers/gpu/drm/virtio/virtgpu_prime.o CC mm/swap_state.o CC lib/siphash.o CC fs/ioctl.o CC lib/string.o CC [M] sound/pci/hda/hda_intel.o CC kernel/ptrace.o CC drivers/acpi/acpica/psscope.o CC net/handshake/genl.o CC net/9p/trans_common.o CC arch/x86/kernel/resource.o CC kernel/user.o CC net/ipv6/udplite.o CC net/mac80211/wep.o LD [M] sound/pci/hda/snd-hda-codec.o CC drivers/dma-buf/dma-fence.o CC drivers/base/cpu.o CC drivers/dma-buf/dma-fence-array.o CC drivers/dma-buf/dma-fence-chain.o CC drivers/acpi/glue.o AR drivers/gpu/drm/mxsfb/built-in.a CC fs/nfs/callback_xdr.o CC fs/readdir.o CC drivers/gpu/drm/virtio/virtgpu_trace_points.o AS arch/x86/kernel/irqflags.o CC fs/nfs/callback_proc.o CC [M] net/netfilter/xt_addrtype.o CC fs/nfs/nfs4namespace.o CC fs/nfs/nfs4getroot.o CC fs/nfs/nfs4client.o CC fs/select.o CC net/mac80211/aead_api.o CC drivers/acpi/scan.o CC net/mac80211/wpa.o CC drivers/acpi/acpica/pstree.o CC drivers/dma-buf/dma-fence-unwrap.o CC net/netlabel/netlabel_unlabeled.o CC net/netlabel/netlabel_cipso_v4.o CC drivers/acpi/mipi-disco-img.o CC drivers/acpi/resource.o CC lib/timerqueue.o AR drivers/gpu/drm/tiny/built-in.a CC net/9p/trans_fd.o CC fs/nfs/nfs4session.o CC arch/x86/kernel/cpu/debugfs.o CC kernel/trace/error_report-traces.o CC fs/nfs/dns_resolve.o CC drivers/gpu/drm/i915/i915_sysfs.o CC net/ipv4/tcp_plb.o CC drivers/acpi/acpica/psutils.o CC drivers/acpi/acpica/pswalk.o CC fs/nfs/nfs4trace.o CC net/handshake/netlink.o CC net/ipv6/raw.o CC fs/nfs/nfs4sysctl.o CC lib/vsprintf.o CC drivers/gpu/drm/virtio/virtgpu_submit.o CC net/core/net-procfs.o CC lib/win_minmax.o CC net/core/netpoll.o AR drivers/gpu/drm/xlnx/built-in.a CC net/wireless/reg.o AR net/sunrpc/auth_gss/built-in.a AR sound/spi/built-in.a CC net/sunrpc/sched.o CC net/core/fib_rules.o CC net/core/net-traces.o AR sound/parisc/built-in.a CC net/core/selftests.o CC net/ipv4/datagram.o CC drivers/dma-buf/dma-resv.o CC drivers/base/firmware.o CC drivers/acpi/acpica/psxface.o AR drivers/cxl/core/built-in.a AR drivers/cxl/built-in.a CC mm/swapfile.o CC fs/dcache.o CC fs/inode.o CC kernel/trace/power-traces.o CC fs/attr.o CC net/mac80211/scan.o AR sound/pcmcia/vx/built-in.a CC drivers/gpu/drm/i915/i915_utils.o AR sound/pcmcia/pdaudiocf/built-in.a CC drivers/dma-buf/sync_file.o CC drivers/gpu/drm/i915/intel_clock_gating.o AR sound/pcmcia/built-in.a CC drivers/gpu/drm/i915/intel_device_info.o CC net/sunrpc/auth.o CC fs/bad_inode.o CC drivers/acpi/acpica/rsaddr.o CC drivers/acpi/acpi_processor.o CC drivers/base/init.o CC drivers/base/map.o CC drivers/base/devres.o CC net/netlabel/netlabel_calipso.o CC fs/file.o AR net/netfilter/built-in.a CC fs/filesystems.o CC fs/namespace.o CC net/9p/trans_virtio.o CC fs/seq_file.o CC net/mac80211/offchannel.o AR drivers/gpu/drm/virtio/built-in.a CC mm/swap_slots.o LD [M] sound/pci/hda/snd-hda-codec-hdmi.o CC net/devres.o LD [M] sound/pci/hda/snd-hda-intel.o AR sound/pci/riptide/built-in.a CC drivers/macintosh/mac_hid.o CC drivers/acpi/acpica/rscalc.o CC net/mac80211/ht.o AR sound/pci/rme9652/built-in.a CC drivers/acpi/acpica/rscreate.o AR sound/pci/trident/built-in.a CC drivers/acpi/acpica/rsdumpinfo.o CC kernel/trace/rpm-traces.o AR drivers/dma-buf/built-in.a CC mm/dmapool.o CC net/handshake/request.o AR sound/pci/vx222/built-in.a AR sound/pci/ymfpci/built-in.a CC kernel/signal.o CC kernel/sys.o AR sound/pci/built-in.a CC kernel/umh.o CC mm/hugetlb.o CC net/socket.o CC net/core/ptp_classifier.o CC net/mac80211/agg-tx.o CC drivers/base/attribute_container.o AR sound/mips/built-in.a AR drivers/macintosh/built-in.a AR sound/soc/built-in.a CC net/wireless/scan.o CC net/mac80211/agg-rx.o CC net/ipv4/raw.o AR sound/atmel/built-in.a CC fs/xattr.o AR sound/x86/built-in.a AR sound/hda/built-in.a CC kernel/trace/trace_dynevent.o AR drivers/scsi/pcmcia/built-in.a CC [M] sound/hda/hda_bus_type.o AR drivers/nvme/common/built-in.a CC drivers/scsi/scsi.o AR drivers/nvme/host/built-in.a CC drivers/acpi/acpica/rsinfo.o CC drivers/scsi/hosts.o CC net/ipv6/icmp.o CC drivers/acpi/processor_core.o CC kernel/trace/trace_probe.o AR drivers/nvme/target/built-in.a CC drivers/gpu/drm/i915/intel_memory_region.o CC kernel/trace/trace_uprobe.o AR drivers/nvme/built-in.a CC drivers/acpi/processor_pdc.o CC drivers/acpi/ec.o CC drivers/acpi/dock.o CC arch/x86/kernel/static_call.o CC drivers/acpi/pci_root.o CC drivers/base/transport_class.o CC drivers/acpi/acpica/rsio.o CC arch/x86/kernel/process.o AR net/9p/built-in.a CC drivers/ata/libata-core.o CC drivers/base/topology.o AR net/netlabel/built-in.a CC net/handshake/tlshd.o CC drivers/base/container.o CC lib/xarray.o AR drivers/net/phy/qcom/built-in.a CC drivers/net/phy/mdio-boardinfo.o CC net/sysctl_net.o CC drivers/base/property.o CC net/ipv6/mcast.o CC [M] sound/hda/hdac_bus.o CC net/ipv6/reassembly.o CC net/handshake/trace.o CC drivers/acpi/acpica/rsirq.o CC drivers/acpi/pci_link.o CC drivers/acpi/acpica/rslist.o CC lib/lockref.o AR drivers/net/pse-pd/built-in.a CC lib/bcd.o CC lib/sort.o CC net/ipv6/tcp_ipv6.o CC net/ipv6/ping.o CC lib/parser.o CC fs/libfs.o CC [M] sound/hda/hdac_device.o CC drivers/net/phy/stubs.o CC drivers/gpu/drm/i915/intel_pcode.o CC drivers/acpi/pci_irq.o CC arch/x86/kernel/cpu/capflags.o CC drivers/ata/libata-scsi.o CC drivers/ata/libata-eh.o AR sound/xen/built-in.a CC [M] sound/hda/hdac_sysfs.o CC kernel/trace/rethook.o CC net/wireless/nl80211.o AR arch/x86/kernel/cpu/built-in.a CC sound/sound_core.o AR sound/virtio/built-in.a CC drivers/net/mdio/acpi_mdio.o CC arch/x86/kernel/ptrace.o CC drivers/base/cacheinfo.o CC drivers/base/swnode.o CC drivers/acpi/acpica/rsmemory.o CC drivers/net/mdio/fwnode_mdio.o CC drivers/scsi/scsi_ioctl.o CC sound/last.o CC net/ipv4/udp.o CC drivers/firewire/init_ohci1394_dma.o CC mm/mmu_notifier.o CC drivers/acpi/acpica/rsmisc.o CC mm/migrate.o CC mm/page_counter.o CC mm/hugetlb_cgroup.o CC drivers/base/auxiliary.o CC lib/debug_locks.o AR drivers/gpu/drm/gud/built-in.a AR fs/nfs/built-in.a CC net/sunrpc/auth_null.o CC fs/fs-writeback.o CC net/core/netprio_cgroup.o CC net/sunrpc/auth_tls.o CC drivers/net/phy/mdio_devres.o CC drivers/net/phy/phy.o CC drivers/net/phy/phy-c45.o CC net/ipv4/udplite.o CC drivers/net/phy/phy-core.o CC net/sunrpc/auth_unix.o AR net/handshake/built-in.a CC net/sunrpc/svc.o CC drivers/scsi/scsicam.o AR kernel/trace/built-in.a CC kernel/workqueue.o CC arch/x86/kernel/tls.o AR drivers/net/pcs/built-in.a CC lib/random32.o CC arch/x86/kernel/step.o CC drivers/gpu/drm/i915/intel_region_ttm.o CC arch/x86/kernel/i8237.o CC drivers/scsi/scsi_error.o CC drivers/gpu/drm/i915/intel_runtime_pm.o CC drivers/net/phy/phy_device.o CC drivers/acpi/acpica/rsserial.o CC [M] sound/hda/hdac_regmap.o CC net/ipv6/exthdrs.o CC drivers/base/devtmpfs.o CC drivers/base/module.o AR drivers/firewire/built-in.a AR drivers/net/mdio/built-in.a AR drivers/net/ethernet/3com/built-in.a AR drivers/net/wireless/admtek/built-in.a CC drivers/ata/libata-transport.o AR drivers/net/wireless/ath/built-in.a CC drivers/net/ethernet/8390/ne2k-pci.o CC drivers/cdrom/cdrom.o AR drivers/net/wireless/atmel/built-in.a CC drivers/ata/libata-trace.o AR drivers/net/wireless/broadcom/built-in.a CC drivers/ata/libata-sata.o CC lib/bust_spinlocks.o CC drivers/ata/libata-sff.o AR drivers/net/ethernet/adaptec/built-in.a AR drivers/net/wireless/intel/built-in.a AR drivers/net/wireless/intersil/built-in.a CC drivers/ata/libata-pmp.o CC lib/kasprintf.o CC net/mac80211/vht.o AR drivers/net/wireless/marvell/built-in.a CC lib/bitmap.o CC net/ipv6/datagram.o CC net/ipv6/ip6_flowlabel.o CC lib/scatterlist.o AR drivers/net/wireless/mediatek/built-in.a CC drivers/acpi/acpica/rsutils.o AR drivers/net/wireless/microchip/built-in.a CC drivers/acpi/acpica/rsxface.o CC net/mac80211/he.o CC drivers/acpi/acpica/tbdata.o AR drivers/net/wireless/purelifi/built-in.a CC net/ipv4/udp_offload.o CC net/ipv4/arp.o AR drivers/net/wireless/quantenna/built-in.a AR drivers/net/ethernet/agere/built-in.a CC net/core/netclassid_cgroup.o AR drivers/net/wireless/ralink/built-in.a CC net/wireless/mlme.o AR drivers/net/wireless/realtek/built-in.a CC drivers/base/auxiliary_sysfs.o CC drivers/base/devcoredump.o AR drivers/net/wireless/rsi/built-in.a CC net/ipv6/inet6_connection_sock.o CC drivers/ata/libata-acpi.o AR drivers/net/wireless/silabs/built-in.a CC drivers/ata/libata-pata-timings.o CC kernel/pid.o AR drivers/net/ethernet/alacritech/built-in.a CC mm/early_ioremap.o CC arch/x86/kernel/stacktrace.o CC arch/x86/kernel/reboot.o AR drivers/net/wireless/st/built-in.a AR drivers/net/wireless/ti/built-in.a CC arch/x86/kernel/msr.o CC [M] sound/hda/hdac_controller.o AR drivers/net/wireless/zydas/built-in.a AR drivers/net/wireless/virtual/built-in.a CC drivers/gpu/drm/i915/intel_sbi.o AR drivers/net/wireless/built-in.a CC arch/x86/kernel/cpuid.o CC mm/secretmem.o CC kernel/task_work.o CC drivers/base/platform-msi.o CC drivers/base/physical_location.o CC drivers/base/trace.o CC drivers/net/phy/linkmode.o CC drivers/scsi/scsi_lib.o CC drivers/acpi/acpica/tbfadt.o CC drivers/ata/ahci.o CC [M] sound/hda/hdac_stream.o CC drivers/net/phy/mdio_bus.o CC drivers/scsi/constants.o AR drivers/gpu/drm/solomon/built-in.a CC drivers/net/ethernet/8390/8390.o CC drivers/scsi/scsi_lib_dma.o CC drivers/scsi/scsi_scan.o GEN drivers/scsi/scsi_devinfo_tbl.c CC net/ipv6/udp_offload.o CC drivers/scsi/scsi_devinfo.o AR drivers/net/usb/built-in.a CC kernel/extable.o CC net/wireless/ibss.o CC kernel/params.o CC kernel/kthread.o CC drivers/acpi/acpica/tbfind.o CC kernel/sys_ni.o CC [M] drivers/gpu/drm/scheduler/sched_main.o CC net/sunrpc/svcsock.o CC lib/list_sort.o CC lib/uuid.o CC drivers/net/phy/mdio_device.o CC [M] sound/hda/array.o CC net/core/dst_cache.o AR drivers/base/built-in.a CC drivers/net/phy/swphy.o CC drivers/net/mii.o CC drivers/net/loopback.o CC drivers/gpu/drm/i915/intel_step.o CC lib/iov_iter.o CC drivers/gpu/drm/i915/intel_uncore.o CC lib/clz_ctz.o AR drivers/cdrom/built-in.a CC drivers/gpu/drm/i915/intel_wakeref.o CC lib/bsearch.o CC drivers/scsi/scsi_sysctl.o CC mm/hmm.o CC drivers/scsi/scsi_proc.o CC lib/find_bit.o CC net/sunrpc/svcauth.o CC arch/x86/kernel/early-quirks.o AR drivers/net/ethernet/8390/built-in.a HOSTCC drivers/gpu/drm/xe/xe_gen_wa_oob AR drivers/net/ethernet/alteon/built-in.a CC drivers/acpi/acpi_apd.o CC drivers/acpi/acpica/tbinstal.o CC [M] drivers/gpu/drm/scheduler/sched_fence.o CC drivers/net/phy/fixed_phy.o AR drivers/net/ethernet/amazon/built-in.a CC drivers/net/phy/realtek.o AR drivers/net/ethernet/amd/built-in.a CC drivers/ata/libahci.o AR drivers/net/ethernet/aquantia/built-in.a GEN xe_wa_oob.c xe_wa_oob.h AR drivers/net/ethernet/arc/built-in.a CC net/core/gro_cells.o CC [M] drivers/gpu/drm/xe/xe_bb.o AR drivers/auxdisplay/built-in.a CC [M] drivers/gpu/drm/xe/xe_bo.o CC drivers/pcmcia/cs.o CC fs/pnode.o CC lib/llist.o AR drivers/net/ethernet/asix/built-in.a CC drivers/acpi/acpi_platform.o CC drivers/acpi/acpi_pnp.o CC drivers/scsi/scsi_debugfs.o CC net/mac80211/s1g.o CC drivers/scsi/scsi_trace.o AR drivers/net/ethernet/atheros/built-in.a CC drivers/usb/common/common.o CC lib/lwq.o CC [M] sound/hda/hdmi_chmap.o AR drivers/net/ethernet/cadence/built-in.a CC net/sunrpc/svcauth_unix.o CC net/sunrpc/addr.o CC drivers/ata/ata_piix.o CC drivers/net/ethernet/broadcom/bnx2.o CC [M] drivers/gpu/drm/scheduler/sched_entity.o CC [M] sound/hda/trace.o CC [M] sound/hda/hdac_component.o CC [M] sound/hda/hdac_i915.o CC mm/memfd.o CC drivers/ata/pata_amd.o CC drivers/pcmcia/socket_sysfs.o CC drivers/acpi/acpica/tbprint.o CC drivers/ata/pata_oldpiix.o CC net/mac80211/ibss.o CC drivers/gpu/drm/i915/vlv_sideband.o CC drivers/net/netconsole.o CC drivers/usb/common/debug.o CC net/mac80211/iface.o CC net/ipv6/seg6.o AR drivers/usb/common/built-in.a CC drivers/usb/core/usb.o CC drivers/scsi/scsi_logging.o CC drivers/acpi/acpica/tbutils.o CC net/ipv4/icmp.o CC [M] sound/hda/intel-dsp-config.o CC drivers/scsi/scsi_pm.o CC drivers/net/ethernet/broadcom/tg3.o CC arch/x86/kernel/smp.o CC [M] drivers/gpu/drm/xe/xe_bo_evict.o CC drivers/scsi/scsi_bsg.o CC drivers/scsi/scsi_common.o CC lib/memweight.o CC drivers/scsi/scsi_transport_spi.o LD [M] drivers/gpu/drm/scheduler/gpu-sched.o CC [M] drivers/gpu/drm/xe/xe_devcoredump.o CC kernel/nsproxy.o CC [M] drivers/gpu/drm/xe/xe_device.o CC net/core/failover.o CC net/ipv6/fib6_notifier.o CC net/wireless/sme.o CC fs/splice.o CC drivers/usb/core/hub.o CC drivers/usb/core/hcd.o CC arch/x86/kernel/smpboot.o AR drivers/net/phy/built-in.a CC drivers/usb/core/urb.o CC drivers/pcmcia/cardbus.o CC mm/ptdump.o CC drivers/acpi/acpica/tbxface.o AR drivers/usb/phy/built-in.a CC net/sunrpc/rpcb_clnt.o CC drivers/input/serio/serio.o CC drivers/input/serio/i8042.o CC mm/execmem.o CC drivers/input/serio/serport.o CC drivers/gpu/drm/i915/vlv_suspend.o CC drivers/acpi/acpica/tbxfload.o CC net/ipv6/rpl.o CC kernel/notifier.o CC [M] sound/hda/intel-nhlt.o CC drivers/input/serio/libps2.o CC drivers/scsi/virtio_scsi.o CC drivers/gpu/drm/i915/soc/intel_dram.o CC net/ipv4/devinet.o CC net/ipv4/af_inet.o CC net/ipv4/igmp.o CC lib/kfifo.o CC drivers/ata/pata_sch.o CC lib/percpu-refcount.o CC net/sunrpc/timer.o CC [M] drivers/gpu/drm/xe/xe_device_sysfs.o CC net/sunrpc/xdr.o CC drivers/pcmcia/ds.o CC [M] drivers/gpu/drm/xe/xe_dma_buf.o CC [M] sound/hda/intel-sdw-acpi.o CC [M] drivers/gpu/drm/xe/xe_drm_client.o AR mm/built-in.a CC [M] drivers/gpu/drm/xe/xe_exec.o CC drivers/usb/core/message.o CC drivers/usb/core/driver.o CC [M] drivers/gpu/drm/xe/xe_execlist.o CC drivers/acpi/acpica/tbxfroot.o CC arch/x86/kernel/tsc_sync.o CC [M] drivers/gpu/drm/xe/xe_exec_queue.o CC net/mac80211/link.o LD [M] sound/hda/snd-hda-core.o CC [M] drivers/gpu/drm/xe/xe_force_wake.o AR drivers/net/ethernet/brocade/built-in.a AR net/core/built-in.a CC drivers/usb/mon/mon_main.o CC drivers/usb/mon/mon_stat.o CC net/wireless/chan.o CC drivers/ata/pata_mpiix.o CC arch/x86/kernel/setup_percpu.o CC drivers/acpi/acpica/utaddress.o AR drivers/input/serio/built-in.a CC drivers/usb/mon/mon_text.o LD [M] sound/hda/snd-intel-dspcfg.o CC drivers/net/virtio_net.o CC drivers/net/net_failover.o LD [M] sound/hda/snd-intel-sdw-acpi.o AR sound/built-in.a CC drivers/gpu/drm/i915/soc/intel_gmch.o CC lib/rhashtable.o CC drivers/usb/host/pci-quirks.o CC drivers/pcmcia/pcmcia_resource.o CC drivers/pcmcia/cistpl.o CC drivers/pcmcia/pcmcia_cis.o CC net/ipv6/ioam6.o CC kernel/ksysfs.o CC drivers/usb/host/ehci-hcd.o CC drivers/acpi/acpica/utalloc.o CC drivers/usb/host/ehci-pci.o CC drivers/acpi/acpica/utascii.o CC lib/base64.o CC drivers/scsi/sd.o CC drivers/scsi/sr.o CC drivers/usb/host/ohci-hcd.o CC kernel/cred.o CC drivers/acpi/acpica/utbuffer.o CC drivers/usb/host/ohci-pci.o CC net/wireless/ethtool.o CC net/ipv6/sysctl_net_ipv6.o CC drivers/pcmcia/rsrc_mgr.o CC lib/once.o CC lib/refcount.o CC lib/rcuref.o CC drivers/ata/ata_generic.o CC lib/usercopy.o CC fs/sync.o CC drivers/usb/core/config.o CC drivers/usb/host/uhci-hcd.o CC drivers/usb/host/xhci.o CC drivers/usb/host/xhci-mem.o CC arch/x86/kernel/mpparse.o CC arch/x86/kernel/trace_clock.o CC drivers/usb/mon/mon_bin.o CC drivers/usb/host/xhci-ext-caps.o CC drivers/acpi/acpica/utcksum.o CC [M] drivers/gpu/drm/xe/xe_ggtt.o CC drivers/usb/class/usblp.o CC drivers/gpu/drm/drm_aperture.o CC drivers/pcmcia/rsrc_nonstatic.o CC drivers/gpu/drm/drm_atomic.o CC net/wireless/mesh.o CC drivers/rtc/lib.o CC drivers/input/keyboard/atkbd.o CC lib/errseq.o CC kernel/reboot.o CC drivers/i2c/algos/i2c-algo-bit.o CC drivers/usb/host/xhci-ring.o CC drivers/gpu/drm/i915/soc/intel_pch.o CC drivers/input/mouse/psmouse-base.o CC drivers/scsi/sr_ioctl.o CC drivers/rtc/class.o CC drivers/acpi/acpica/utcopy.o CC drivers/rtc/interface.o CC lib/bucket_locks.o CC drivers/i2c/busses/i2c-i801.o CC arch/x86/kernel/trace.o CC drivers/scsi/sr_vendor.o CC drivers/scsi/sg.o CC net/ipv4/fib_frontend.o AR drivers/i2c/muxes/built-in.a CC drivers/gpu/drm/i915/i915_memcpy.o CC drivers/gpu/drm/i915/i915_mm.o CC drivers/gpu/drm/i915/i915_sw_fence.o CC fs/utimes.o CC drivers/usb/core/file.o CC drivers/usb/core/buffer.o CC drivers/gpu/drm/i915/i915_sw_fence_work.o AR drivers/ata/built-in.a CC drivers/acpi/acpica/utexcep.o CC net/sunrpc/sunrpc_syms.o CC fs/d_path.o CC fs/stack.o CC drivers/acpi/acpica/utdebug.o CC fs/fs_struct.o CC lib/generic-radix-tree.o AR drivers/usb/mon/built-in.a CC fs/statfs.o AR drivers/i2c/algos/built-in.a AR drivers/input/joystick/built-in.a CC kernel/async.o CC drivers/gpu/drm/drm_atomic_uapi.o CC drivers/usb/host/xhci-hub.o CC lib/bitmap-str.o CC arch/x86/kernel/rethook.o CC drivers/usb/core/sysfs.o CC arch/x86/kernel/vmcore_info_32.o CC drivers/acpi/acpica/utdecode.o CC drivers/usb/core/endpoint.o AR drivers/usb/class/built-in.a CC drivers/pcmcia/yenta_socket.o CC net/ipv6/xfrm6_policy.o AR drivers/i3c/built-in.a CC net/ipv6/xfrm6_state.o AR drivers/input/tablet/built-in.a CC lib/string_helpers.o CC lib/hexdump.o CC net/mac80211/rate.o CC net/mac80211/michael.o CC drivers/input/mouse/synaptics.o CC fs/fs_pin.o CC net/mac80211/tkip.o CC drivers/gpu/drm/i915/i915_syncmap.o CC drivers/input/mouse/focaltech.o AR drivers/input/keyboard/built-in.a CC net/mac80211/aes_cmac.o CC kernel/range.o CC net/ipv6/xfrm6_input.o CC drivers/rtc/nvmem.o AR drivers/i2c/busses/built-in.a CC drivers/i2c/i2c-boardinfo.o CC fs/nsfs.o CC drivers/i2c/i2c-core-base.o CC drivers/acpi/acpica/utdelete.o CC drivers/acpi/acpica/uterror.o CC arch/x86/kernel/machine_kexec_32.o AS arch/x86/kernel/relocate_kernel_32.o CC [M] drivers/gpu/drm/xe/xe_gpu_scheduler.o CC drivers/rtc/dev.o CC kernel/smpboot.o CC net/sunrpc/cache.o CC drivers/acpi/acpica/uteval.o CC drivers/gpu/drm/i915/i915_user_extensions.o CC lib/kstrtox.o CC drivers/rtc/proc.o CC drivers/acpi/acpica/utglobal.o CC drivers/gpu/drm/i915/i915_debugfs.o CC drivers/gpu/drm/i915/i915_debugfs_params.o CC net/wireless/ap.o CC drivers/gpu/drm/drm_auth.o CC drivers/usb/core/devio.o CC kernel/ucount.o CC drivers/usb/host/xhci-dbg.o CC kernel/regset.o CC kernel/ksyms_common.o CC drivers/acpi/acpica/uthex.o CC drivers/rtc/sysfs.o CC drivers/scsi/scsi_sysfs.o CC [M] drivers/gpu/drm/xe/xe_gsc.o CC net/mac80211/aes_gmac.o CC net/sunrpc/rpc_pipe.o CC drivers/gpu/drm/drm_blend.o CC drivers/usb/storage/scsiglue.o AR drivers/usb/misc/built-in.a CC drivers/input/mouse/alps.o CC drivers/input/mouse/byd.o CC arch/x86/kernel/crash_dump_32.o CC drivers/i2c/i2c-core-smbus.o CC net/sunrpc/sysfs.o AR drivers/input/touchscreen/built-in.a CC drivers/usb/storage/protocol.o CC drivers/gpu/drm/i915/i915_pmu.o CC lib/iomap.o CC net/wireless/trace.o CC lib/iomap_copy.o CC drivers/acpi/acpica/utids.o CC fs/fs_types.o CC drivers/i2c/i2c-core-acpi.o CC [M] drivers/gpu/drm/xe/xe_gsc_debugfs.o CC [M] drivers/gpu/drm/xe/xe_gsc_proxy.o CC drivers/rtc/rtc-mc146818-lib.o CC [M] drivers/gpu/drm/xe/xe_gsc_submit.o CC [M] drivers/gpu/drm/xe/xe_gt.o CC [M] drivers/gpu/drm/xe/xe_gt_ccs_mode.o CC [M] drivers/gpu/drm/xe/xe_gt_clock.o CC net/ipv4/fib_semantics.o CC net/ipv6/xfrm6_output.o CC drivers/rtc/rtc-cmos.o CC lib/devres.o CC arch/x86/kernel/crash.o CC kernel/groups.o CC kernel/kcmp.o CC kernel/freezer.o CC net/ipv4/fib_trie.o AR drivers/input/misc/built-in.a AR drivers/pcmcia/built-in.a CC drivers/gpu/drm/i915/gt/gen2_engine_cs.o CC fs/fs_context.o CC fs/fs_parser.o CC net/sunrpc/svc_xprt.o AR drivers/media/i2c/built-in.a AR drivers/media/tuners/built-in.a CC drivers/gpu/drm/i915/gt/gen6_engine_cs.o CC drivers/acpi/acpica/utinit.o CC drivers/gpu/drm/i915/gt/gen6_ppgtt.o AR drivers/media/rc/keymaps/built-in.a AR drivers/media/rc/built-in.a AR drivers/media/common/b2c2/built-in.a CC lib/check_signature.o CC drivers/usb/storage/transport.o AR drivers/media/common/siano/built-in.a AR drivers/media/common/saa7146/built-in.a CC drivers/input/input.o CC drivers/usb/host/xhci-trace.o CC drivers/usb/host/xhci-debugfs.o AR drivers/media/common/v4l2-tpg/built-in.a AR drivers/scsi/built-in.a CC arch/x86/kernel/module.o CC net/wireless/ocb.o CC lib/interval_tree.o AR drivers/media/common/videobuf2/built-in.a CC net/wireless/pmsr.o CC kernel/profile.o CC net/ipv6/xfrm6_protocol.o GEN net/wireless/shipped-certs.c AR drivers/media/common/built-in.a CC net/mac80211/fils_aead.o CC net/sunrpc/xprtmultipath.o CC net/sunrpc/stats.o AR drivers/media/platform/allegro-dvt/built-in.a CC drivers/acpi/acpica/utlock.o CC drivers/gpu/drm/i915/gt/gen7_renderclear.o CC net/ipv4/fib_notifier.o AR drivers/media/platform/amlogic/meson-ge2d/built-in.a AR drivers/rtc/built-in.a CC drivers/i2c/i2c-smbus.o CC drivers/usb/early/ehci-dbgp.o CC net/sunrpc/sysctl.o AR drivers/media/platform/amlogic/built-in.a CC lib/assoc_array.o CC arch/x86/kernel/doublefault_32.o CC drivers/gpu/drm/i915/gt/gen8_engine_cs.o AR drivers/media/platform/amphion/built-in.a AR drivers/pps/clients/built-in.a AR drivers/pps/generators/built-in.a AR drivers/media/platform/aspeed/built-in.a CC drivers/pps/pps.o AR drivers/media/platform/atmel/built-in.a AR drivers/media/pci/ttpci/built-in.a AR drivers/media/platform/broadcom/built-in.a AR drivers/media/pci/b2c2/built-in.a CC drivers/input/mouse/logips2pp.o AR drivers/media/usb/b2c2/built-in.a AR drivers/media/platform/cadence/built-in.a CC drivers/gpu/drm/i915/gt/gen8_ppgtt.o CC net/ipv4/inet_fragment.o AR drivers/media/usb/dvb-usb/built-in.a AR drivers/media/pci/pluto2/built-in.a AR drivers/media/mmc/siano/built-in.a AR drivers/media/mmc/built-in.a CC drivers/acpi/acpica/utmath.o AR drivers/media/pci/dm1105/built-in.a AR drivers/media/usb/dvb-usb-v2/built-in.a CC [M] drivers/gpu/drm/xe/xe_gt_freq.o AR drivers/media/platform/chips-media/coda/built-in.a CC drivers/acpi/acpica/utmisc.o AR drivers/media/usb/s2255/built-in.a CC drivers/gpu/drm/i915/gt/intel_breadcrumbs.o AR drivers/media/pci/pt1/built-in.a AR drivers/media/firewire/built-in.a AR drivers/media/platform/chips-media/wave5/built-in.a CC drivers/gpu/drm/i915/gt/intel_context.o CC kernel/stacktrace.o CC drivers/input/input-compat.o AR drivers/media/usb/siano/built-in.a CC kernel/dma.o AR drivers/media/platform/chips-media/built-in.a AR drivers/media/pci/pt3/built-in.a AR drivers/media/pci/mantis/built-in.a AR drivers/media/usb/ttusb-budget/built-in.a AR drivers/media/platform/imagination/built-in.a CC drivers/pps/kapi.o AR drivers/media/pci/ngene/built-in.a CC fs/fsopen.o AR drivers/media/usb/ttusb-dec/built-in.a AR drivers/media/platform/intel/built-in.a CC lib/bitrev.o CC lib/crc-ccitt.o CC drivers/usb/host/xhci-pci.o AR drivers/media/pci/ddbridge/built-in.a AR drivers/media/platform/marvell/built-in.a AR drivers/media/usb/built-in.a AR drivers/media/spi/built-in.a CC drivers/usb/core/notify.o AR drivers/media/pci/saa7146/built-in.a CC drivers/gpu/drm/drm_bridge.o CC drivers/ptp/ptp_clock.o CC net/mac80211/cfg.o AR drivers/media/platform/mediatek/mdp/built-in.a CC net/mac80211/ethtool.o AR drivers/media/platform/mediatek/jpeg/built-in.a AR drivers/media/pci/smipcie/built-in.a CC drivers/power/supply/power_supply_core.o AR drivers/i2c/built-in.a CC net/ipv4/ping.o AR drivers/media/pci/netup_unidvb/built-in.a CC drivers/hwmon/hwmon.o CC drivers/gpu/drm/i915/gt/intel_context_sseu.o AR drivers/media/platform/mediatek/vcodec/common/built-in.a CC drivers/gpu/drm/drm_cache.o AR drivers/media/pci/intel/ipu3/built-in.a CC drivers/usb/storage/usb.o AR drivers/media/platform/mediatek/vcodec/encoder/built-in.a CC drivers/input/mouse/lifebook.o AR drivers/media/pci/intel/ivsc/built-in.a AR drivers/media/platform/mediatek/vcodec/decoder/built-in.a CC drivers/usb/storage/initializers.o CC drivers/input/mouse/trackpoint.o AR drivers/media/pci/intel/built-in.a CC drivers/input/mouse/cypress_ps2.o AR drivers/media/platform/mediatek/vcodec/built-in.a CC drivers/acpi/acpica/utmutex.o CC lib/crc16.o AR drivers/usb/early/built-in.a AR drivers/media/pci/built-in.a CC kernel/smp.o AR drivers/thermal/broadcom/built-in.a AR drivers/thermal/renesas/built-in.a AR drivers/media/platform/mediatek/vpu/built-in.a CC kernel/uid16.o CC arch/x86/kernel/early_printk.o CC net/ipv6/netfilter.o AR drivers/thermal/samsung/built-in.a CC kernel/kallsyms.o CC fs/init.o AR drivers/media/platform/mediatek/mdp3/built-in.a AR drivers/media/platform/mediatek/built-in.a CC drivers/thermal/intel/intel_tcc.o HOSTCC lib/gen_crc32table CC drivers/gpu/drm/drm_client.o CC net/mac80211/rx.o CC [M] drivers/gpu/drm/xe/xe_gt_idle.o CC net/ipv4/ip_tunnel_core.o CC drivers/input/input-mt.o CC drivers/input/input-poller.o CC drivers/pps/sysfs.o AR drivers/media/platform/microchip/built-in.a CC drivers/input/ff-core.o CC drivers/usb/core/generic.o AR drivers/media/platform/nuvoton/built-in.a CC drivers/input/touchscreen.o AR drivers/media/platform/nvidia/tegra-vde/built-in.a CC drivers/usb/core/quirks.o AR drivers/media/platform/nvidia/built-in.a CC drivers/thermal/intel/therm_throt.o CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.o CC net/ipv6/proc.o AR drivers/media/platform/nxp/dw100/built-in.a AR drivers/media/platform/nxp/imx-jpeg/built-in.a CC drivers/acpi/acpica/utnonansi.o AR drivers/media/platform/nxp/imx8-isi/built-in.a CC arch/x86/kernel/hpet.o AR drivers/media/platform/nxp/built-in.a AR drivers/thermal/st/built-in.a CC drivers/acpi/acpica/utobject.o CC lib/xxhash.o CC drivers/usb/core/devices.o CC net/ipv6/syncookies.o CC [M] drivers/gpu/drm/xe/xe_gt_mcr.o CC net/ipv4/gre_offload.o AR drivers/media/platform/qcom/camss/built-in.a AR drivers/media/test-drivers/built-in.a CC drivers/input/mouse/psmouse-smbus.o AR drivers/hwmon/built-in.a CC drivers/usb/core/phy.o AR drivers/media/platform/qcom/venus/built-in.a AR drivers/net/ethernet/cavium/common/built-in.a AR drivers/media/platform/qcom/built-in.a AR drivers/pps/built-in.a AR drivers/media/platform/raspberrypi/pisp_be/built-in.a CC arch/x86/kernel/amd_nb.o AR drivers/net/ethernet/cavium/thunder/built-in.a CC kernel/acct.o AR drivers/media/platform/raspberrypi/built-in.a CC fs/kernel_read_file.o CC kernel/vmcore_info.o CC net/ipv4/metrics.o AR drivers/net/ethernet/cavium/liquidio/built-in.a CC drivers/gpu/drm/i915/gt/intel_engine_cs.o CC drivers/gpu/drm/i915/gt/intel_engine_heartbeat.o CC drivers/acpi/acpica/utosi.o CC drivers/input/ff-memless.o AR drivers/net/ethernet/cavium/octeon/built-in.a CC kernel/elfcorehdr.o AR drivers/media/platform/renesas/rcar-vin/built-in.a CC drivers/ptp/ptp_chardev.o AR drivers/net/ethernet/cavium/built-in.a AR drivers/media/platform/renesas/rzg2l-cru/built-in.a CC kernel/crash_reserve.o CC drivers/usb/storage/sierra_ms.o AR drivers/media/platform/renesas/vsp1/built-in.a AR drivers/thermal/qcom/built-in.a AR drivers/media/platform/rockchip/rga/built-in.a AR drivers/media/platform/renesas/built-in.a AR drivers/net/ethernet/chelsio/built-in.a AR drivers/watchdog/built-in.a CC drivers/power/supply/power_supply_sysfs.o AR drivers/media/platform/rockchip/rkisp1/built-in.a CC drivers/usb/core/port.o CC drivers/power/supply/power_supply_leds.o CC drivers/gpu/drm/i915/gt/intel_engine_pm.o CC drivers/gpu/drm/i915/gt/intel_engine_user.o CC drivers/usb/core/hcd-pci.o AR drivers/media/platform/rockchip/built-in.a CC net/ipv4/netlink.o CC fs/mnt_idmapping.o CC drivers/power/supply/power_supply_hwmon.o CC arch/x86/kernel/kvm.o CC drivers/gpu/drm/drm_client_modeset.o CC net/wireless/shipped-certs.o AR drivers/media/platform/samsung/exynos-gsc/built-in.a CC drivers/acpi/power.o AR drivers/input/mouse/built-in.a AR drivers/media/platform/samsung/exynos4-is/built-in.a CC drivers/input/sparse-keymap.o AR drivers/media/platform/samsung/s3c-camif/built-in.a AR drivers/media/platform/samsung/s5p-g2d/built-in.a CC drivers/input/vivaldi-fmap.o CC lib/genalloc.o CC drivers/acpi/event.o CC drivers/acpi/evged.o AR drivers/media/platform/samsung/s5p-jpeg/built-in.a CC drivers/acpi/sysfs.o AR drivers/media/platform/samsung/s5p-mfc/built-in.a CC drivers/acpi/acpica/utownerid.o CC drivers/input/input-leds.o AR drivers/media/platform/samsung/built-in.a AR drivers/usb/host/built-in.a CC drivers/input/evdev.o AR drivers/thermal/tegra/built-in.a AR drivers/media/platform/st/sti/bdisp/built-in.a AR drivers/media/platform/st/sti/c8sectpfe/built-in.a AR drivers/thermal/intel/built-in.a CC drivers/acpi/acpica/utpredef.o CC drivers/acpi/acpica/utresdecode.o AR drivers/thermal/mediatek/built-in.a CC drivers/gpu/drm/drm_color_mgmt.o CC [M] drivers/gpu/drm/xe/xe_gt_pagefault.o CC drivers/md/md.o AR drivers/media/platform/st/sti/delta/built-in.a CC [M] drivers/gpu/drm/xe/xe_gt_sysfs.o CC drivers/thermal/thermal_core.o CC drivers/cpufreq/cpufreq.o AR drivers/media/platform/st/sti/hva/built-in.a CC drivers/cpufreq/freq_table.o CC drivers/usb/storage/option_ms.o CC drivers/thermal/thermal_sysfs.o CC drivers/acpi/property.o AR drivers/media/platform/st/stm32/built-in.a AR drivers/mmc/built-in.a CC fs/remap_range.o CC drivers/cpuidle/governors/menu.o AR drivers/power/supply/built-in.a AR drivers/media/platform/st/built-in.a CC net/ipv6/calipso.o AR net/sunrpc/built-in.a CC lib/percpu_counter.o AR drivers/power/built-in.a CC drivers/acpi/debugfs.o CC fs/pidfs.o CC [M] drivers/gpu/drm/xe/xe_gt_throttle.o AR drivers/net/ethernet/broadcom/built-in.a CC drivers/cpuidle/cpuidle.o AR drivers/media/platform/sunxi/sun4i-csi/built-in.a CC net/ipv6/ah6.o CC kernel/kexec_core.o AR drivers/media/platform/sunxi/sun6i-csi/built-in.a AR drivers/media/platform/sunxi/sun6i-mipi-csi2/built-in.a AR drivers/ufs/built-in.a CC drivers/thermal/thermal_trip.o AR drivers/net/ethernet/cisco/built-in.a AR drivers/leds/trigger/built-in.a AR drivers/leds/blink/built-in.a AR drivers/net/ethernet/cortina/built-in.a AR drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/built-in.a AR drivers/media/platform/sunxi/sun8i-di/built-in.a CC drivers/leds/led-core.o AR drivers/media/platform/sunxi/sun8i-rotate/built-in.a AR drivers/leds/simple/built-in.a CC drivers/cpuidle/driver.o CC drivers/leds/led-class.o CC drivers/acpi/acpica/utresrc.o CC lib/audit.o CC net/mac80211/spectmgmt.o AR drivers/net/ethernet/dec/tulip/built-in.a CC drivers/acpi/acpica/utstate.o CC drivers/leds/led-triggers.o AR drivers/media/platform/sunxi/built-in.a CC drivers/usb/core/usb-acpi.o CC drivers/acpi/acpi_lpat.o AR drivers/net/ethernet/dec/built-in.a CC drivers/cpufreq/cpufreq_performance.o CC drivers/cpuidle/governors/haltpoll.o CC drivers/acpi/acpica/utstring.o CC net/ipv4/nexthop.o CC drivers/cpufreq/cpufreq_userspace.o AR drivers/net/ethernet/dlink/built-in.a CC drivers/ptp/ptp_sysfs.o AR drivers/media/platform/ti/am437x/built-in.a AR drivers/net/ethernet/emulex/built-in.a CC drivers/usb/storage/usual-tables.o AR drivers/media/platform/ti/cal/built-in.a AR drivers/net/ethernet/engleder/built-in.a AR drivers/net/ethernet/ezchip/built-in.a AR drivers/media/platform/ti/vpe/built-in.a CC drivers/cpufreq/cpufreq_ondemand.o AR drivers/media/platform/ti/davinci/built-in.a AR drivers/net/ethernet/fujitsu/built-in.a CC [M] drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o AR drivers/net/ethernet/fungible/built-in.a AR drivers/media/platform/ti/j721e-csi2rx/built-in.a CC [M] drivers/gpu/drm/xe/xe_gt_topology.o CC drivers/cpufreq/cpufreq_governor.o AR drivers/net/ethernet/google/built-in.a CC net/mac80211/tx.o AR drivers/net/ethernet/huawei/built-in.a AR drivers/media/platform/verisilicon/built-in.a CC drivers/cpufreq/cpufreq_governor_attr_set.o AR drivers/media/platform/ti/omap/built-in.a CC drivers/md/md-bitmap.o CC drivers/cpufreq/acpi-cpufreq.o CC drivers/acpi/acpica/utstrsuppt.o CC drivers/md/md-autodetect.o CC [M] drivers/gpu/drm/xe/xe_guc.o AR drivers/media/platform/ti/omap3isp/built-in.a CC drivers/md/dm.o CC drivers/net/ethernet/intel/e1000/e1000_main.o CC drivers/net/ethernet/intel/e1000/e1000_hw.o AR drivers/media/platform/ti/built-in.a CC drivers/thermal/thermal_helpers.o AR drivers/usb/core/built-in.a CC drivers/thermal/thermal_hwmon.o AR drivers/media/platform/via/built-in.a CC arch/x86/kernel/kvmclock.o CC drivers/thermal/gov_step_wise.o CC drivers/md/dm-table.o CC arch/x86/kernel/paravirt.o AR drivers/media/platform/xilinx/built-in.a CC lib/syscall.o CC drivers/gpu/drm/drm_connector.o AR drivers/media/platform/built-in.a AR drivers/usb/storage/built-in.a CC drivers/cpufreq/amd-pstate.o AR drivers/leds/built-in.a AR drivers/usb/built-in.a CC drivers/acpi/acpi_pcc.o AR drivers/input/built-in.a CC kernel/crash_core.o CC drivers/net/ethernet/intel/e1000e/82571.o CC drivers/acpi/ac.o CC drivers/net/ethernet/intel/e100.o CC fs/buffer.o CC drivers/net/ethernet/intel/e1000e/ich8lan.o CC drivers/cpufreq/amd-pstate-trace.o CC drivers/ptp/ptp_vclock.o CC net/mac80211/key.o CC drivers/md/dm-target.o CC net/ipv4/udp_tunnel_stub.o AR drivers/cpuidle/governors/built-in.a CC net/ipv4/ip_tunnel.o CC drivers/acpi/acpica/utstrtoul64.o AR drivers/media/built-in.a CC drivers/net/ethernet/intel/e1000e/80003es2lan.o CC drivers/net/ethernet/intel/e1000e/mac.o CC drivers/gpu/drm/i915/gt/intel_execlists_submission.o CC kernel/kexec.o CC kernel/utsname.o CC drivers/cpuidle/governor.o CC drivers/acpi/button.o CC drivers/md/dm-linear.o CC net/ipv4/sysctl_net_ipv4.o CC drivers/thermal/gov_user_space.o CC net/mac80211/util.o AR drivers/net/ethernet/i825xx/built-in.a CC net/mac80211/parse.o CC net/mac80211/wme.o CC arch/x86/kernel/pvclock.o CC net/mac80211/chan.o CC kernel/pid_namespace.o CC drivers/md/dm-stripe.o CC drivers/gpu/drm/drm_crtc.o CC net/ipv6/esp6.o CC drivers/net/ethernet/intel/e1000/e1000_ethtool.o CC drivers/acpi/acpica/utxface.o CC drivers/md/dm-ioctl.o CC lib/errname.o CC drivers/cpuidle/sysfs.o AR drivers/net/ethernet/microsoft/built-in.a CC drivers/acpi/acpica/utxfinit.o AR drivers/net/ethernet/litex/built-in.a CC lib/nlattr.o AR drivers/net/ethernet/marvell/octeon_ep/built-in.a AR drivers/net/ethernet/marvell/octeon_ep_vf/built-in.a CC drivers/ptp/ptp_kvm_x86.o CC drivers/cpufreq/intel_pstate.o AR drivers/thermal/built-in.a CC [M] drivers/gpu/drm/xe/xe_guc_ads.o AR drivers/net/ethernet/marvell/octeontx2/built-in.a CC lib/cpu_rmap.o CC drivers/acpi/acpica/utxferror.o AR drivers/net/ethernet/marvell/prestera/built-in.a CC drivers/acpi/acpica/utxfmutex.o CC drivers/net/ethernet/marvell/sky2.o CC drivers/gpu/drm/i915/gt/intel_ggtt.o CC net/ipv6/sit.o CC drivers/gpu/drm/drm_displayid.o CC net/ipv4/proc.o CC drivers/cpuidle/poll_state.o CC arch/x86/kernel/pcspeaker.o CC net/ipv6/addrconf_core.o CC net/ipv4/fib_rules.o CC net/ipv4/ipmr.o CC net/ipv4/ipmr_base.o CC kernel/stop_machine.o CC drivers/md/dm-io.o CC drivers/gpu/drm/drm_drv.o AR drivers/net/ethernet/mellanox/built-in.a CC net/ipv4/syncookies.o AR drivers/acpi/acpica/built-in.a CC drivers/md/dm-kcopyd.o CC [M] drivers/gpu/drm/xe/xe_guc_ct.o CC drivers/net/ethernet/intel/e1000/e1000_param.o CC drivers/acpi/fan_core.o CC net/mac80211/trace.o CC net/mac80211/mlme.o CC [M] drivers/gpu/drm/xe/xe_guc_db_mgr.o CC drivers/ptp/ptp_kvm_common.o CC drivers/cpuidle/cpuidle-haltpoll.o AR drivers/net/ethernet/meta/built-in.a CC kernel/audit.o CC arch/x86/kernel/check.o CC kernel/auditfilter.o CC arch/x86/kernel/uprobes.o CC drivers/net/ethernet/intel/e1000e/manage.o CC arch/x86/kernel/perf_regs.o CC arch/x86/kernel/tracepoint.o CC drivers/gpu/drm/drm_dumb_buffers.o CC drivers/net/ethernet/intel/e1000e/nvm.o CC arch/x86/kernel/itmt.o CC arch/x86/kernel/umip.o AR drivers/net/ethernet/micrel/built-in.a AR drivers/cpuidle/built-in.a AR drivers/net/ethernet/microchip/built-in.a CC lib/dynamic_queue_limits.o CC net/mac80211/tdls.o CC drivers/md/dm-sysfs.o CC drivers/md/dm-stats.o CC drivers/acpi/fan_attr.o CC net/ipv6/exthdrs_core.o CC [M] drivers/gpu/drm/xe/xe_guc_hwconfig.o CC net/mac80211/ocb.o CC kernel/auditsc.o CC [M] drivers/gpu/drm/xe/xe_guc_id_mgr.o CC fs/mpage.o CC arch/x86/kernel/unwind_frame.o CC fs/proc_namespace.o CC drivers/net/ethernet/intel/e1000e/phy.o CC drivers/gpu/drm/drm_edid.o CC drivers/acpi/fan_hwmon.o CC lib/glob.o CC net/mac80211/airtime.o CC lib/strncpy_from_user.o CC net/mac80211/eht.o AR drivers/ptp/built-in.a CC drivers/net/ethernet/intel/e1000e/param.o CC drivers/net/ethernet/intel/e1000e/ethtool.o AR drivers/net/ethernet/intel/e1000/built-in.a AR drivers/firmware/arm_ffa/built-in.a CC drivers/net/ethernet/intel/e1000e/netdev.o CC fs/direct-io.o CC net/ipv6/ip6_checksum.o AR drivers/firmware/arm_scmi/built-in.a CC drivers/acpi/acpi_video.o CC drivers/gpu/drm/i915/gt/intel_ggtt_fencing.o AR drivers/firmware/broadcom/built-in.a CC drivers/net/ethernet/intel/e1000e/ptp.o AR drivers/firmware/cirrus/built-in.a CC fs/eventpoll.o CC drivers/acpi/video_detect.o AR drivers/firmware/meson/built-in.a CC drivers/gpu/drm/drm_eld.o AR drivers/crypto/stm32/built-in.a AR drivers/firmware/microchip/built-in.a AR drivers/crypto/xilinx/built-in.a CC drivers/clocksource/acpi_pm.o AR drivers/crypto/hisilicon/built-in.a CC drivers/clocksource/i8253.o CC drivers/hid/usbhid/hid-core.o AR drivers/firmware/imx/built-in.a AR drivers/crypto/intel/keembay/built-in.a AR drivers/platform/x86/amd/built-in.a CC [M] drivers/gpu/drm/xe/xe_guc_klv_helpers.o CC drivers/hid/usbhid/hiddev.o CC [M] drivers/gpu/drm/xe/xe_guc_log.o AR drivers/crypto/starfive/built-in.a AR drivers/platform/x86/intel/built-in.a AR drivers/crypto/intel/ixp4xx/built-in.a CC drivers/platform/x86/wmi.o CC drivers/gpu/drm/drm_encoder.o AR drivers/crypto/intel/built-in.a CC [M] drivers/gpu/drm/xe/xe_guc_pc.o AR arch/x86/kernel/built-in.a AR drivers/crypto/built-in.a CC drivers/firmware/efi/libstub/efi-stub-helper.o AR drivers/cpufreq/built-in.a AR arch/x86/built-in.a CC drivers/gpu/drm/drm_file.o CC drivers/firmware/efi/efi-bgrt.o CC kernel/audit_watch.o CC drivers/gpu/drm/i915/gt/intel_gt.o AR drivers/firmware/psci/built-in.a CC lib/strnlen_user.o CC kernel/audit_fsnotify.o CC lib/net_utils.o CC lib/sg_pool.o CC lib/stackdepot.o CC drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.o CC net/mac80211/led.o CC drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.o CC drivers/gpu/drm/i915/gt/intel_gt_clock_utils.o CC drivers/gpu/drm/i915/gt/intel_gt_debugfs.o CC drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.o CC lib/asn1_decoder.o CC drivers/md/dm-rq.o CC net/mac80211/pm.o AR drivers/firmware/qcom/built-in.a AR drivers/platform/surface/built-in.a CC drivers/firmware/efi/libstub/gop.o AR drivers/net/ethernet/mscc/built-in.a AR drivers/clocksource/built-in.a AR drivers/net/ethernet/marvell/built-in.a CC drivers/hid/hid-core.o CC [M] drivers/gpu/drm/xe/xe_guc_submit.o CC drivers/firmware/efi/libstub/secureboot.o AR drivers/net/ethernet/myricom/built-in.a CC net/ipv6/ip6_icmp.o CC [M] drivers/gpu/drm/xe/xe_heci_gsc.o CC drivers/mailbox/mailbox.o CC drivers/mailbox/pcc.o CC drivers/hid/usbhid/hid-pidff.o AR drivers/perf/built-in.a CC fs/anon_inodes.o CC net/ipv4/tunnel4.o CC drivers/platform/x86/wmi-bmof.o CC net/ipv4/ipconfig.o CC fs/signalfd.o CC fs/timerfd.o CC drivers/acpi/processor_driver.o CC net/ipv4/netfilter.o CC net/ipv4/tcp_cubic.o AR drivers/net/ethernet/natsemi/built-in.a CC net/ipv4/tcp_sigpool.o CC net/ipv4/cipso_ipv4.o CC drivers/platform/x86/eeepc-laptop.o AR drivers/net/ethernet/neterion/built-in.a CC drivers/firmware/efi/libstub/tpm.o CC net/ipv4/xfrm4_policy.o AR drivers/net/ethernet/netronome/built-in.a CC drivers/md/dm-io-rewind.o AR drivers/net/ethernet/ni/built-in.a CC kernel/audit_tree.o GEN lib/oid_registry_data.c CC [M] drivers/gpu/drm/xe/xe_hw_engine.o CC drivers/md/dm-builtin.o CC drivers/net/ethernet/nvidia/forcedeth.o CC lib/ucs2_string.o CC drivers/gpu/drm/i915/gt/intel_gt_irq.o CC [M] drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.o CC net/ipv4/xfrm4_state.o AR drivers/mailbox/built-in.a CC drivers/md/dm-raid1.o CC net/ipv4/xfrm4_input.o AR drivers/hwtracing/intel_th/built-in.a CC drivers/firmware/efi/libstub/file.o AR drivers/android/built-in.a CC drivers/gpu/drm/i915/gt/intel_gt_mcr.o CC drivers/gpu/drm/i915/gt/intel_gt_pm.o AR drivers/nvmem/layouts/built-in.a CC drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.o CC drivers/nvmem/core.o CC kernel/kprobes.o CC net/mac80211/rc80211_minstrel_ht.o CC kernel/seccomp.o CC lib/sbitmap.o CC drivers/acpi/processor_thermal.o CC net/ipv4/xfrm4_output.o CC drivers/platform/x86/p2sb.o CC net/mac80211/wbrf.o CC drivers/gpu/drm/i915/gt/intel_gt_pm_irq.o CC net/ipv6/output_core.o CC fs/eventfd.o CC net/ipv4/xfrm4_protocol.o CC fs/aio.o CC drivers/gpu/drm/drm_fourcc.o CC fs/locks.o CC drivers/gpu/drm/drm_framebuffer.o AR drivers/hid/usbhid/built-in.a CC drivers/gpu/drm/drm_gem.o CC drivers/gpu/drm/drm_ioctl.o CC drivers/gpu/drm/i915/gt/intel_gt_requests.o CC drivers/gpu/drm/drm_lease.o CC drivers/gpu/drm/drm_managed.o CC drivers/gpu/drm/i915/gt/intel_gt_sysfs.o CC net/ipv6/protocol.o CC net/ipv6/ip6_offload.o AR net/wireless/built-in.a CC drivers/md/dm-log.o CC fs/binfmt_misc.o CC drivers/hid/hid-input.o CC fs/binfmt_script.o CC drivers/acpi/processor_idle.o CC drivers/firmware/efi/libstub/mem.o CC fs/binfmt_elf.o CC fs/mbcache.o CC fs/posix_acl.o CC fs/coredump.o CC fs/drop_caches.o AR drivers/platform/x86/built-in.a CC [M] drivers/gpu/drm/xe/xe_hw_engine_group.o CC kernel/relay.o AR drivers/platform/built-in.a CC lib/group_cpus.o AR drivers/nvmem/built-in.a CC fs/sysctls.o CC lib/fw_table.o CC drivers/acpi/processor_throttling.o CC drivers/acpi/processor_perflib.o AR drivers/net/ethernet/oki-semi/built-in.a CC drivers/acpi/container.o CC drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.o AR drivers/firmware/smccc/built-in.a CC drivers/md/dm-region-hash.o AR drivers/net/ethernet/packetengines/built-in.a CC drivers/md/dm-zero.o CC drivers/gpu/drm/drm_mm.o CC fs/fhandle.o CC drivers/gpu/drm/i915/gt/intel_gtt.o AR lib/lib.a CC drivers/firmware/efi/efi.o CC drivers/firmware/efi/vars.o AR net/ipv4/built-in.a CC drivers/firmware/efi/libstub/random.o CC drivers/firmware/efi/reboot.o CC drivers/firmware/efi/memattr.o GEN lib/crc32table.h CC drivers/firmware/efi/tpm.o CC drivers/gpu/drm/drm_mode_config.o CC drivers/firmware/efi/memmap.o CC drivers/gpu/drm/drm_mode_object.o CC drivers/firmware/efi/capsule.o CC drivers/firmware/efi/esrt.o CC drivers/firmware/efi/runtime-wrappers.o CC [M] drivers/gpu/drm/xe/xe_hw_fence.o CC drivers/gpu/drm/drm_modes.o CC drivers/gpu/drm/i915/gt/intel_llc.o CC drivers/gpu/drm/drm_modeset_lock.o CC lib/oid_registry.o AR drivers/firmware/tegra/built-in.a AR drivers/firmware/xilinx/built-in.a CC kernel/utsname_sysctl.o CC drivers/gpu/drm/i915/gt/intel_lrc.o CC drivers/firmware/dmi_scan.o CC [M] drivers/gpu/drm/xe/xe_huc.o AR drivers/net/ethernet/qlogic/built-in.a AR drivers/net/ethernet/nvidia/built-in.a CC drivers/acpi/thermal_lib.o CC drivers/firmware/efi/libstub/randomalloc.o CC drivers/gpu/drm/i915/gt/intel_migrate.o AR drivers/net/ethernet/qualcomm/emac/built-in.a CC drivers/gpu/drm/i915/gt/intel_mocs.o AR drivers/net/ethernet/qualcomm/built-in.a CC drivers/acpi/thermal.o CC drivers/firmware/efi/capsule-loader.o CC drivers/gpu/drm/i915/gt/intel_ppgtt.o CC drivers/firmware/efi/earlycon.o CC drivers/acpi/nhlt.o CC drivers/hid/hid-quirks.o CC kernel/delayacct.o CC drivers/gpu/drm/drm_plane.o CC drivers/firmware/dmi-id.o CC drivers/net/ethernet/realtek/8139too.o CC drivers/acpi/acpi_memhotplug.o CC [M] drivers/gpu/drm/xe/xe_irq.o AR drivers/net/ethernet/renesas/built-in.a CC drivers/firmware/efi/libstub/pci.o CC drivers/hid/hid-debug.o AR drivers/net/ethernet/rdc/built-in.a CC drivers/firmware/efi/libstub/skip_spaces.o CC drivers/hid/hidraw.o AR drivers/net/ethernet/rocker/built-in.a CC kernel/taskstats.o CC kernel/tsacct.o AR drivers/net/ethernet/samsung/built-in.a CC drivers/net/ethernet/realtek/r8169_main.o AR drivers/net/ethernet/seeq/built-in.a AR fs/built-in.a CC lib/crc32.o CC kernel/tracepoint.o CC drivers/acpi/ioapic.o AR drivers/net/ethernet/silan/built-in.a CC drivers/net/ethernet/realtek/r8169_firmware.o CC drivers/net/ethernet/realtek/r8169_phy_config.o CC drivers/gpu/drm/i915/gt/intel_rc6.o CC drivers/acpi/battery.o AR drivers/net/ethernet/sis/built-in.a CC [M] drivers/gpu/drm/xe/xe_lrc.o CC [M] drivers/gpu/drm/xe/xe_migrate.o CC drivers/gpu/drm/drm_prime.o CC kernel/irq_work.o CC drivers/hid/hid-generic.o CC drivers/hid/hid-a4tech.o CC drivers/firmware/memmap.o CC drivers/hid/hid-apple.o CC drivers/hid/hid-belkin.o CC drivers/hid/hid-cherry.o AR drivers/net/ethernet/sfc/built-in.a CC drivers/hid/hid-chicony.o CC drivers/gpu/drm/drm_print.o CC drivers/gpu/drm/drm_property.o CC drivers/hid/hid-cypress.o AR drivers/md/built-in.a CC net/ipv6/tcpv6_offload.o CC kernel/static_call.o CC net/ipv6/exthdrs_offload.o CC drivers/acpi/bgrt.o CC drivers/gpu/drm/i915/gt/intel_region_lmem.o AR drivers/net/ethernet/socionext/built-in.a AR drivers/net/ethernet/smsc/built-in.a CC drivers/acpi/spcr.o CC net/ipv6/inet6_hashtables.o CC drivers/gpu/drm/i915/gt/intel_renderstate.o CC drivers/gpu/drm/i915/gt/intel_reset.o CC drivers/gpu/drm/i915/gt/intel_ring.o CC net/ipv6/mcast_snoop.o AR drivers/net/ethernet/stmicro/built-in.a CC kernel/padata.o CC drivers/gpu/drm/drm_syncobj.o CC drivers/firmware/efi/libstub/lib-cmdline.o CC kernel/jump_label.o AR drivers/net/ethernet/intel/e1000e/built-in.a AR lib/built-in.a CC kernel/context_tracking.o AR drivers/net/ethernet/intel/built-in.a CC kernel/iomem.o CC kernel/rseq.o CC drivers/firmware/efi/libstub/lib-ctype.o CC drivers/firmware/efi/libstub/alignedmem.o CC drivers/firmware/efi/libstub/relocate.o CC [M] drivers/gpu/drm/xe/xe_mmio.o CC drivers/hid/hid-ezkey.o CC drivers/gpu/drm/drm_sysfs.o AR drivers/firmware/efi/built-in.a CC [M] drivers/gpu/drm/xe/xe_mocs.o AR drivers/net/ethernet/sun/built-in.a AR drivers/net/ethernet/tehuti/built-in.a CC drivers/firmware/efi/libstub/printk.o CC drivers/firmware/efi/libstub/vsprintf.o CC drivers/hid/hid-gyration.o AR drivers/net/ethernet/ti/built-in.a CC drivers/firmware/efi/libstub/x86-stub.o CC drivers/gpu/drm/drm_trace_points.o CC drivers/hid/hid-ite.o AR drivers/net/ethernet/vertexcom/built-in.a AR drivers/net/ethernet/via/built-in.a CC drivers/gpu/drm/drm_vblank.o AR drivers/net/ethernet/wangxun/built-in.a CC drivers/gpu/drm/drm_vblank_work.o CC [M] drivers/gpu/drm/xe/xe_module.o CC drivers/hid/hid-kensington.o AR drivers/net/ethernet/wiznet/built-in.a CC [M] drivers/gpu/drm/xe/xe_oa.o CC [M] drivers/gpu/drm/xe/xe_observation.o CC [M] drivers/gpu/drm/xe/xe_pat.o CC [M] drivers/gpu/drm/xe/xe_pci.o CC [M] drivers/gpu/drm/xe/xe_pcode.o CC [M] drivers/gpu/drm/xe/xe_pm.o AR drivers/net/ethernet/xilinx/built-in.a AR drivers/net/ethernet/xircom/built-in.a CC drivers/hid/hid-lg.o AR drivers/net/ethernet/pensando/built-in.a AR drivers/net/ethernet/synopsys/built-in.a CC drivers/hid/hid-lgff.o CC drivers/hid/hid-lg4ff.o CC drivers/gpu/drm/i915/gt/intel_ring_submission.o CC drivers/gpu/drm/i915/gt/intel_rps.o CC drivers/firmware/efi/libstub/smbios.o CC [M] drivers/gpu/drm/xe/xe_preempt_fence.o CC drivers/gpu/drm/i915/gt/intel_sa_media.o CC drivers/gpu/drm/i915/gt/intel_sseu.o CC [M] drivers/gpu/drm/xe/xe_pt.o CC drivers/hid/hid-lg-g15.o CC drivers/gpu/drm/drm_vma_manager.o CC drivers/hid/hid-microsoft.o CC drivers/gpu/drm/drm_writeback.o CC drivers/gpu/drm/i915/gt/intel_sseu_debugfs.o AR drivers/acpi/built-in.a CC drivers/gpu/drm/drm_panel.o STUBCPY drivers/firmware/efi/libstub/alignedmem.stub.o CC drivers/gpu/drm/i915/gt/intel_timeline.o CC drivers/gpu/drm/i915/gt/intel_tlb.o CC drivers/gpu/drm/i915/gt/intel_wopcm.o STUBCPY drivers/firmware/efi/libstub/efi-stub-helper.stub.o AR drivers/net/ethernet/realtek/built-in.a CC drivers/hid/hid-monterey.o CC drivers/gpu/drm/i915/gt/intel_workarounds.o CC drivers/hid/hid-ntrig.o AR drivers/net/ethernet/built-in.a CC [M] drivers/gpu/drm/xe/xe_pt_walk.o STUBCPY drivers/firmware/efi/libstub/file.stub.o CC drivers/gpu/drm/drm_pci.o CC drivers/hid/hid-pl.o CC drivers/gpu/drm/drm_debugfs.o STUBCPY drivers/firmware/efi/libstub/gop.stub.o CC drivers/hid/hid-petalynx.o CC drivers/gpu/drm/drm_debugfs_crc.o STUBCPY drivers/firmware/efi/libstub/lib-cmdline.stub.o CC [M] drivers/gpu/drm/xe/xe_query.o STUBCPY drivers/firmware/efi/libstub/lib-ctype.stub.o CC drivers/gpu/drm/drm_panel_orientation_quirks.o CC [M] drivers/gpu/drm/xe/xe_range_fence.o AR kernel/built-in.a STUBCPY drivers/firmware/efi/libstub/mem.stub.o CC drivers/hid/hid-redragon.o CC drivers/gpu/drm/i915/gt/shmem_utils.o CC [M] drivers/gpu/drm/xe/xe_reg_sr.o STUBCPY drivers/firmware/efi/libstub/pci.stub.o CC [M] drivers/gpu/drm/xe/xe_reg_whitelist.o CC drivers/gpu/drm/i915/gt/sysfs_engines.o CC [M] drivers/gpu/drm/xe/xe_rtp.o CC drivers/gpu/drm/drm_buddy.o CC drivers/gpu/drm/drm_gem_shmem_helper.o CC [M] drivers/gpu/drm/xe/xe_ring_ops.o AR net/mac80211/built-in.a AR net/ipv6/built-in.a CC [M] drivers/gpu/drm/xe/xe_sa.o STUBCPY drivers/firmware/efi/libstub/printk.stub.o AR net/built-in.a STUBCPY drivers/firmware/efi/libstub/random.stub.o STUBCPY drivers/firmware/efi/libstub/randomalloc.stub.o CC [M] drivers/gpu/drm/xe/xe_sched_job.o STUBCPY drivers/firmware/efi/libstub/relocate.stub.o CC [M] drivers/gpu/drm/xe/xe_step.o STUBCPY drivers/firmware/efi/libstub/secureboot.stub.o CC drivers/gpu/drm/i915/gt/intel_ggtt_gmch.o CC drivers/gpu/drm/i915/gt/gen6_renderstate.o STUBCPY drivers/firmware/efi/libstub/skip_spaces.stub.o CC drivers/gpu/drm/drm_atomic_helper.o STUBCPY drivers/firmware/efi/libstub/smbios.stub.o STUBCPY drivers/firmware/efi/libstub/tpm.stub.o CC drivers/gpu/drm/drm_atomic_state_helper.o STUBCPY drivers/firmware/efi/libstub/vsprintf.stub.o STUBCPY drivers/firmware/efi/libstub/x86-stub.stub.o CC drivers/gpu/drm/drm_crtc_helper.o CC [M] drivers/gpu/drm/xe/xe_sync.o CC drivers/hid/hid-samsung.o AR drivers/net/built-in.a CC drivers/hid/hid-sony.o CC drivers/gpu/drm/i915/gt/gen7_renderstate.o AR drivers/firmware/efi/libstub/lib.a CC drivers/gpu/drm/i915/gt/gen8_renderstate.o AR drivers/firmware/built-in.a CC drivers/hid/hid-sunplus.o CC drivers/hid/hid-topseed.o CC drivers/gpu/drm/i915/gt/gen9_renderstate.o CC [M] drivers/gpu/drm/xe/xe_tile.o CC drivers/gpu/drm/drm_damage_helper.o CC drivers/gpu/drm/drm_encoder_slave.o CC drivers/gpu/drm/drm_flip_work.o CC drivers/gpu/drm/drm_format_helper.o CC drivers/gpu/drm/drm_gem_atomic_helper.o CC [M] drivers/gpu/drm/xe/xe_tile_sysfs.o CC [M] drivers/gpu/drm/xe/xe_trace.o CC [M] drivers/gpu/drm/xe/xe_trace_bo.o CC drivers/gpu/drm/drm_gem_framebuffer_helper.o CC [M] drivers/gpu/drm/xe/xe_trace_guc.o CC [M] drivers/gpu/drm/xe/xe_ttm_sys_mgr.o CC drivers/gpu/drm/drm_kms_helper_common.o CC drivers/gpu/drm/i915/gem/i915_gem_busy.o CC [M] drivers/gpu/drm/xe/xe_ttm_stolen_mgr.o CC drivers/gpu/drm/drm_modeset_helper.o CC drivers/gpu/drm/drm_plane_helper.o CC drivers/gpu/drm/i915/gem/i915_gem_clflush.o CC drivers/gpu/drm/i915/gem/i915_gem_context.o CC drivers/gpu/drm/i915/gem/i915_gem_create.o CC drivers/gpu/drm/drm_probe_helper.o CC drivers/gpu/drm/i915/gem/i915_gem_dmabuf.o CC drivers/gpu/drm/drm_rect.o CC drivers/gpu/drm/i915/gem/i915_gem_domain.o CC drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o CC [M] drivers/gpu/drm/xe/xe_ttm_vram_mgr.o CC [M] drivers/gpu/drm/xe/xe_tuning.o CC [M] drivers/gpu/drm/xe/xe_uc.o CC drivers/gpu/drm/i915/gem/i915_gem_internal.o CC [M] drivers/gpu/drm/xe/xe_uc_fw.o CC drivers/gpu/drm/drm_self_refresh_helper.o CC [M] drivers/gpu/drm/xe/xe_vm.o CC drivers/gpu/drm/drm_simple_kms_helper.o CC [M] drivers/gpu/drm/xe/xe_vram.o CC drivers/gpu/drm/bridge/panel.o CC [M] drivers/gpu/drm/xe/xe_vram_freq.o CC [M] drivers/gpu/drm/xe/xe_wait_user_fence.o CC drivers/gpu/drm/drm_mipi_dsi.o CC drivers/gpu/drm/i915/gem/i915_gem_lmem.o CC [M] drivers/gpu/drm/drm_exec.o CC [M] drivers/gpu/drm/xe/xe_wa.o CC drivers/gpu/drm/i915/gem/i915_gem_mman.o CC [M] drivers/gpu/drm/xe/xe_wopcm.o CC [M] drivers/gpu/drm/drm_gpuvm.o CC [M] drivers/gpu/drm/xe/xe_hmm.o CC drivers/gpu/drm/i915/gem/i915_gem_object.o CC [M] drivers/gpu/drm/xe/xe_hwmon.o CC [M] drivers/gpu/drm/xe/xe_gt_sriov_vf.o CC [M] drivers/gpu/drm/xe/xe_guc_relay.o CC [M] drivers/gpu/drm/drm_suballoc.o CC [M] drivers/gpu/drm/drm_gem_ttm_helper.o CC drivers/gpu/drm/i915/gem/i915_gem_pages.o CC drivers/gpu/drm/i915/gem/i915_gem_phys.o CC drivers/gpu/drm/i915/gem/i915_gem_pm.o CC drivers/gpu/drm/i915/gem/i915_gem_region.o CC drivers/gpu/drm/i915/gem/i915_gem_shmem.o CC drivers/gpu/drm/i915/gem/i915_gem_shrinker.o CC drivers/gpu/drm/i915/gem/i915_gem_stolen.o CC drivers/gpu/drm/i915/gem/i915_gem_throttle.o CC drivers/gpu/drm/i915/gem/i915_gem_tiling.o CC drivers/gpu/drm/i915/gem/i915_gem_ttm.o CC drivers/gpu/drm/i915/gem/i915_gem_ttm_move.o CC [M] drivers/gpu/drm/xe/xe_memirq.o CC [M] drivers/gpu/drm/xe/xe_sriov.o CC [M] drivers/gpu/drm/xe/display/ext/i915_irq.o AR drivers/hid/built-in.a CC [M] drivers/gpu/drm/xe/display/ext/i915_utils.o CC drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.o CC [M] drivers/gpu/drm/xe/display/intel_fb_bo.o CC drivers/gpu/drm/i915/gem/i915_gem_userptr.o CC drivers/gpu/drm/i915/gem/i915_gem_wait.o CC drivers/gpu/drm/i915/gem/i915_gemfs.o CC drivers/gpu/drm/i915/i915_active.o CC drivers/gpu/drm/i915/i915_cmd_parser.o CC [M] drivers/gpu/drm/xe/display/intel_fbdev_fb.o LD [M] drivers/gpu/drm/drm_suballoc_helper.o CC drivers/gpu/drm/i915/i915_deps.o CC [M] drivers/gpu/drm/xe/display/xe_display.o CC drivers/gpu/drm/i915/i915_gem.o CC [M] drivers/gpu/drm/xe/display/xe_display_misc.o CC [M] drivers/gpu/drm/xe/display/xe_display_rps.o CC drivers/gpu/drm/i915/i915_gem_evict.o CC [M] drivers/gpu/drm/xe/display/xe_display_wa.o CC drivers/gpu/drm/i915/i915_gem_gtt.o CC [M] drivers/gpu/drm/xe/display/xe_dsb_buffer.o CC [M] drivers/gpu/drm/xe/display/xe_fb_pin.o CC drivers/gpu/drm/i915/i915_gem_ww.o CC drivers/gpu/drm/i915/i915_query.o LD [M] drivers/gpu/drm/drm_ttm_helper.o CC [M] drivers/gpu/drm/xe/display/xe_hdcp_gsc.o CC [M] drivers/gpu/drm/xe/display/xe_plane_initial.o CC [M] drivers/gpu/drm/xe/display/xe_tdf.o CC [M] drivers/gpu/drm/xe/i915-soc/intel_dram.o CC drivers/gpu/drm/i915/i915_request.o CC [M] drivers/gpu/drm/xe/i915-soc/intel_pch.o CC [M] drivers/gpu/drm/xe/i915-display/icl_dsi.o CC [M] drivers/gpu/drm/xe/i915-display/intel_alpm.o CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic.o CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic_plane.o CC drivers/gpu/drm/i915/i915_scheduler.o CC [M] drivers/gpu/drm/xe/i915-display/intel_audio.o CC drivers/gpu/drm/i915/i915_trace_points.o CC drivers/gpu/drm/i915/i915_ttm_buddy_manager.o CC [M] drivers/gpu/drm/xe/i915-display/intel_backlight.o CC [M] drivers/gpu/drm/xe/i915-display/intel_bios.o CC drivers/gpu/drm/i915/i915_vma.o CC drivers/gpu/drm/i915/i915_vma_resource.o CC drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.o CC [M] drivers/gpu/drm/xe/i915-display/intel_bw.o CC drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.o CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.o CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.o CC [M] drivers/gpu/drm/xe/i915-display/intel_cdclk.o CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.o CC drivers/gpu/drm/i915/gt/uc/intel_guc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_color.o CC [M] drivers/gpu/drm/xe/i915-display/intel_combo_phy.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_capture.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_ct.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_fw.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.o CC [M] drivers/gpu/drm/xe/i915-display/intel_connector.o CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_log.o CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc_state_dump.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.o CC [M] drivers/gpu/drm/xe/i915-display/intel_cursor.o CC [M] drivers/gpu/drm/xe/i915-display/intel_cx0_phy.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_rc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.o CC drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi_buf_trans.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_device.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_driver.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_irq.o CC drivers/gpu/drm/i915/gt/uc/intel_huc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_params.o CC drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.o CC drivers/gpu/drm/i915/gt/uc/intel_huc_fw.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power.o CC drivers/gpu/drm/i915/gt/uc/intel_uc.o CC drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.o CC drivers/gpu/drm/i915/gt/uc/intel_uc_fw.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_map.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_well.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_trace.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_wa.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dkl_phy.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dmc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp.o CC drivers/gpu/drm/i915/gt/intel_gsc.o CC drivers/gpu/drm/i915/i915_hwmon.o CC drivers/gpu/drm/i915/display/hsw_ips.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux.o CC drivers/gpu/drm/i915/display/i9xx_plane.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux_backlight.o CC drivers/gpu/drm/i915/display/i9xx_wm.o CC drivers/gpu/drm/i915/display/intel_alpm.o CC drivers/gpu/drm/i915/display/intel_atomic.o CC drivers/gpu/drm/i915/display/intel_atomic_plane.o CC drivers/gpu/drm/i915/display/intel_audio.o CC drivers/gpu/drm/i915/display/intel_bios.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_hdcp.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_link_training.o CC drivers/gpu/drm/i915/display/intel_bw.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_mst.o CC drivers/gpu/drm/i915/display/intel_cdclk.o CC drivers/gpu/drm/i915/display/intel_color.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll_mgr.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dpt_common.o CC [M] drivers/gpu/drm/xe/i915-display/intel_drrs.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dsb.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi.o CC drivers/gpu/drm/i915/display/intel_combo_phy.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_dcs_backlight.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_vbt.o CC [M] drivers/gpu/drm/xe/i915-display/intel_encoder.o CC drivers/gpu/drm/i915/display/intel_connector.o CC [M] drivers/gpu/drm/xe/i915-display/intel_fb.o CC [M] drivers/gpu/drm/xe/i915-display/intel_fbc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_fdi.o CC drivers/gpu/drm/i915/display/intel_crtc.o CC drivers/gpu/drm/i915/display/intel_crtc_state_dump.o CC [M] drivers/gpu/drm/xe/i915-display/intel_fifo_underrun.o CC [M] drivers/gpu/drm/xe/i915-display/intel_frontbuffer.o CC [M] drivers/gpu/drm/xe/i915-display/intel_global_state.o CC [M] drivers/gpu/drm/xe/i915-display/intel_gmbus.o CC drivers/gpu/drm/i915/display/intel_cursor.o CC [M] drivers/gpu/drm/xe/i915-display/intel_hdcp.o CC drivers/gpu/drm/i915/display/intel_display.o CC [M] drivers/gpu/drm/xe/i915-display/intel_hdcp_gsc_message.o CC [M] drivers/gpu/drm/xe/i915-display/intel_hdmi.o CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug.o CC drivers/gpu/drm/i915/display/intel_display_driver.o CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug_irq.o CC drivers/gpu/drm/i915/display/intel_display_irq.o CC [M] drivers/gpu/drm/xe/i915-display/intel_hti.o CC [M] drivers/gpu/drm/xe/i915-display/intel_link_bw.o CC drivers/gpu/drm/i915/display/intel_display_params.o CC [M] drivers/gpu/drm/xe/i915-display/intel_lspcon.o CC drivers/gpu/drm/i915/display/intel_display_power.o CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_lock.o CC drivers/gpu/drm/i915/display/intel_display_power_map.o CC drivers/gpu/drm/i915/display/intel_display_power_well.o CC drivers/gpu/drm/i915/display/intel_display_reset.o CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_setup.o CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_verify.o CC drivers/gpu/drm/i915/display/intel_display_rps.o CC [M] drivers/gpu/drm/xe/i915-display/intel_panel.o CC [M] drivers/gpu/drm/xe/i915-display/intel_pmdemand.o CC drivers/gpu/drm/i915/display/intel_display_wa.o CC [M] drivers/gpu/drm/xe/i915-display/intel_pps.o CC [M] drivers/gpu/drm/xe/i915-display/intel_psr.o CC [M] drivers/gpu/drm/xe/i915-display/intel_qp_tables.o CC drivers/gpu/drm/i915/display/intel_dmc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_quirks.o CC drivers/gpu/drm/i915/display/intel_dmc_wl.o CC [M] drivers/gpu/drm/xe/i915-display/intel_snps_phy.o CC [M] drivers/gpu/drm/xe/i915-display/intel_tc.o CC drivers/gpu/drm/i915/display/intel_dpio_phy.o CC [M] drivers/gpu/drm/xe/i915-display/intel_vblank.o CC drivers/gpu/drm/i915/display/intel_dpll.o CC [M] drivers/gpu/drm/xe/i915-display/intel_vdsc.o CC drivers/gpu/drm/i915/display/intel_dpll_mgr.o CC [M] drivers/gpu/drm/xe/i915-display/intel_vga.o CC [M] drivers/gpu/drm/xe/i915-display/intel_vrr.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dmc_wl.o CC drivers/gpu/drm/i915/display/intel_dpt.o CC [M] drivers/gpu/drm/xe/i915-display/intel_wm.o CC drivers/gpu/drm/i915/display/intel_dpt_common.o CC [M] drivers/gpu/drm/xe/i915-display/skl_scaler.o CC [M] drivers/gpu/drm/xe/i915-display/skl_universal_plane.o CC [M] drivers/gpu/drm/xe/i915-display/skl_watermark.o CC drivers/gpu/drm/i915/display/intel_drrs.o CC [M] drivers/gpu/drm/xe/i915-display/intel_acpi.o CC [M] drivers/gpu/drm/xe/i915-display/intel_opregion.o CC [M] drivers/gpu/drm/xe/xe_debugfs.o CC [M] drivers/gpu/drm/xe/xe_gt_debugfs.o CC [M] drivers/gpu/drm/xe/xe_gt_sriov_vf_debugfs.o CC drivers/gpu/drm/i915/display/intel_dsb.o CC drivers/gpu/drm/i915/display/intel_dsb_buffer.o CC [M] drivers/gpu/drm/xe/xe_gt_stats.o CC drivers/gpu/drm/i915/display/intel_fb.o CC [M] drivers/gpu/drm/xe/xe_guc_debugfs.o CC drivers/gpu/drm/i915/display/intel_fb_bo.o CC [M] drivers/gpu/drm/xe/xe_huc_debugfs.o CC [M] drivers/gpu/drm/xe/xe_uc_debugfs.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_debugfs.o CC drivers/gpu/drm/i915/display/intel_fb_pin.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_debugfs_params.o CC [M] drivers/gpu/drm/xe/i915-display/intel_pipe_crc.o CC drivers/gpu/drm/i915/display/intel_fbc.o CC drivers/gpu/drm/i915/display/intel_fdi.o CC drivers/gpu/drm/i915/display/intel_fifo_underrun.o CC drivers/gpu/drm/i915/display/intel_frontbuffer.o CC drivers/gpu/drm/i915/display/intel_global_state.o CC drivers/gpu/drm/i915/display/intel_hdcp.o CC drivers/gpu/drm/i915/display/intel_hdcp_gsc.o CC drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.o CC drivers/gpu/drm/i915/display/intel_hotplug.o CC drivers/gpu/drm/i915/display/intel_hotplug_irq.o CC drivers/gpu/drm/i915/display/intel_hti.o CC drivers/gpu/drm/i915/display/intel_link_bw.o CC drivers/gpu/drm/i915/display/intel_load_detect.o CC drivers/gpu/drm/i915/display/intel_lpe_audio.o CC drivers/gpu/drm/i915/display/intel_modeset_lock.o CC drivers/gpu/drm/i915/display/intel_modeset_setup.o CC drivers/gpu/drm/i915/display/intel_modeset_verify.o CC drivers/gpu/drm/i915/display/intel_overlay.o CC drivers/gpu/drm/i915/display/intel_pch_display.o CC drivers/gpu/drm/i915/display/intel_pch_refclk.o CC drivers/gpu/drm/i915/display/intel_plane_initial.o CC drivers/gpu/drm/i915/display/intel_pmdemand.o CC drivers/gpu/drm/i915/display/intel_psr.o CC drivers/gpu/drm/i915/display/intel_quirks.o CC drivers/gpu/drm/i915/display/intel_sprite.o CC drivers/gpu/drm/i915/display/intel_sprite_uapi.o CC drivers/gpu/drm/i915/display/intel_tc.o CC drivers/gpu/drm/i915/display/intel_vblank.o CC drivers/gpu/drm/i915/display/intel_vga.o CC drivers/gpu/drm/i915/display/intel_wm.o CC drivers/gpu/drm/i915/display/skl_scaler.o CC drivers/gpu/drm/i915/display/skl_universal_plane.o CC drivers/gpu/drm/i915/display/skl_watermark.o CC drivers/gpu/drm/i915/display/intel_acpi.o CC drivers/gpu/drm/i915/display/intel_opregion.o CC drivers/gpu/drm/i915/display/intel_display_debugfs.o CC drivers/gpu/drm/i915/display/intel_display_debugfs_params.o CC drivers/gpu/drm/i915/display/intel_pipe_crc.o CC drivers/gpu/drm/i915/display/dvo_ch7017.o CC drivers/gpu/drm/i915/display/dvo_ch7xxx.o CC drivers/gpu/drm/i915/display/dvo_ivch.o CC drivers/gpu/drm/i915/display/dvo_ns2501.o CC drivers/gpu/drm/i915/display/dvo_sil164.o CC drivers/gpu/drm/i915/display/dvo_tfp410.o CC drivers/gpu/drm/i915/display/g4x_dp.o CC drivers/gpu/drm/i915/display/g4x_hdmi.o CC drivers/gpu/drm/i915/display/icl_dsi.o CC drivers/gpu/drm/i915/display/intel_backlight.o CC drivers/gpu/drm/i915/display/intel_crt.o CC drivers/gpu/drm/i915/display/intel_cx0_phy.o CC drivers/gpu/drm/i915/display/intel_ddi.o CC drivers/gpu/drm/i915/display/intel_ddi_buf_trans.o CC drivers/gpu/drm/i915/display/intel_display_device.o CC drivers/gpu/drm/i915/display/intel_display_trace.o CC drivers/gpu/drm/i915/display/intel_dkl_phy.o CC drivers/gpu/drm/i915/display/intel_dp.o CC drivers/gpu/drm/i915/display/intel_dp_aux.o CC drivers/gpu/drm/i915/display/intel_dp_aux_backlight.o CC drivers/gpu/drm/i915/display/intel_dp_hdcp.o CC drivers/gpu/drm/i915/display/intel_dp_link_training.o CC drivers/gpu/drm/i915/display/intel_dp_mst.o CC drivers/gpu/drm/i915/display/intel_dsi.o CC drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.o CC drivers/gpu/drm/i915/display/intel_dsi_vbt.o CC drivers/gpu/drm/i915/display/intel_dvo.o CC drivers/gpu/drm/i915/display/intel_encoder.o CC drivers/gpu/drm/i915/display/intel_gmbus.o CC drivers/gpu/drm/i915/display/intel_hdmi.o CC drivers/gpu/drm/i915/display/intel_lspcon.o CC drivers/gpu/drm/i915/display/intel_lvds.o CC drivers/gpu/drm/i915/display/intel_panel.o CC drivers/gpu/drm/i915/display/intel_pps.o CC drivers/gpu/drm/i915/display/intel_qp_tables.o CC drivers/gpu/drm/i915/display/intel_sdvo.o CC drivers/gpu/drm/i915/display/intel_snps_phy.o CC drivers/gpu/drm/i915/display/intel_tv.o CC drivers/gpu/drm/i915/display/intel_vdsc.o CC drivers/gpu/drm/i915/display/intel_vrr.o CC drivers/gpu/drm/i915/display/vlv_dsi.o LD [M] drivers/gpu/drm/xe/xe.o CC drivers/gpu/drm/i915/display/vlv_dsi_pll.o CC drivers/gpu/drm/i915/i915_perf.o CC drivers/gpu/drm/i915/pxp/intel_pxp.o CC drivers/gpu/drm/i915/pxp/intel_pxp_huc.o CC drivers/gpu/drm/i915/pxp/intel_pxp_tee.o CC drivers/gpu/drm/i915/i915_gpu_error.o CC drivers/gpu/drm/i915/i915_vgpu.o AR drivers/gpu/drm/i915/built-in.a AR drivers/gpu/drm/built-in.a AR drivers/gpu/built-in.a AR drivers/built-in.a AR built-in.a AR vmlinux.a LD vmlinux.o OBJCOPY modules.builtin.modinfo GEN modules.builtin MODPOST Module.symvers CC [M] fs/efivarfs/efivarfs.mod.o CC .vmlinux.export.o CC [M] drivers/gpu/drm/drm_exec.mod.o CC [M] drivers/gpu/drm/drm_gpuvm.mod.o CC [M] drivers/gpu/drm/drm_suballoc_helper.mod.o CC [M] drivers/gpu/drm/drm_ttm_helper.mod.o CC [M] drivers/gpu/drm/scheduler/gpu-sched.mod.o CC [M] drivers/gpu/drm/xe/xe.mod.o CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.mod.o CC [M] sound/core/snd-hwdep.mod.o CC [M] sound/core/snd-pcm.mod.o CC [M] sound/pci/hda/snd-hda-codec.mod.o CC [M] sound/pci/hda/snd-hda-codec-hdmi.mod.o CC [M] sound/pci/hda/snd-hda-intel.mod.o CC [M] sound/hda/snd-hda-core.mod.o CC [M] sound/hda/snd-intel-dspcfg.mod.o CC [M] net/netfilter/nf_log_syslog.mod.o CC [M] sound/hda/snd-intel-sdw-acpi.mod.o CC [M] net/netfilter/xt_mark.mod.o CC [M] net/netfilter/xt_nat.mod.o CC [M] net/netfilter/xt_LOG.mod.o CC [M] net/netfilter/xt_MASQUERADE.mod.o CC [M] net/netfilter/xt_addrtype.mod.o CC [M] net/ipv4/netfilter/iptable_nat.mod.o LD [M] drivers/gpu/drm/drm_exec.ko LD [M] net/netfilter/xt_LOG.ko LD [M] drivers/thermal/intel/x86_pkg_temp_thermal.ko LD [M] net/ipv4/netfilter/iptable_nat.ko LD [M] drivers/gpu/drm/drm_gpuvm.ko LD [M] sound/hda/snd-intel-sdw-acpi.ko LD [M] drivers/gpu/drm/drm_ttm_helper.ko LD [M] sound/hda/snd-intel-dspcfg.ko LD [M] drivers/gpu/drm/scheduler/gpu-sched.ko LD [M] drivers/gpu/drm/xe/xe.ko LD [M] sound/core/snd-hwdep.ko LD [M] net/netfilter/nf_log_syslog.ko LD [M] sound/core/snd-pcm.ko LD [M] net/netfilter/xt_MASQUERADE.ko LD [M] fs/efivarfs/efivarfs.ko LD [M] sound/hda/snd-hda-core.ko LD [M] drivers/gpu/drm/drm_suballoc_helper.ko LD [M] net/netfilter/xt_mark.ko LD [M] net/netfilter/xt_nat.ko LD [M] sound/pci/hda/snd-hda-codec-hdmi.ko LD [M] sound/pci/hda/snd-hda-codec.ko LD [M] net/netfilter/xt_addrtype.ko LD [M] sound/pci/hda/snd-hda-intel.ko UPD include/generated/utsversion.h CC init/version-timestamp.o KSYMS .tmp_vmlinux0.kallsyms.S AS .tmp_vmlinux0.kallsyms.o LD .tmp_vmlinux1 NM .tmp_vmlinux1.syms KSYMS .tmp_vmlinux1.kallsyms.S AS .tmp_vmlinux1.kallsyms.o LD .tmp_vmlinux2 NM .tmp_vmlinux2.syms KSYMS .tmp_vmlinux2.kallsyms.S AS .tmp_vmlinux2.kallsyms.o LD vmlinux NM System.map SORTTAB vmlinux RELOCS arch/x86/boot/compressed/vmlinux.relocs RSTRIP vmlinux CC arch/x86/boot/a20.o AS arch/x86/boot/bioscall.o CC arch/x86/boot/cmdline.o AS arch/x86/boot/copy.o HOSTCC arch/x86/boot/mkcpustr CC arch/x86/boot/cpuflags.o CC arch/x86/boot/cpucheck.o CC arch/x86/boot/early_serial_console.o CC arch/x86/boot/edd.o CC arch/x86/boot/main.o CC arch/x86/boot/memory.o CC arch/x86/boot/pm.o AS arch/x86/boot/pmjump.o CC arch/x86/boot/printf.o CC arch/x86/boot/regs.o CC arch/x86/boot/string.o CC arch/x86/boot/tty.o CC arch/x86/boot/video.o CC arch/x86/boot/video-mode.o CC arch/x86/boot/version.o CC arch/x86/boot/video-vga.o CC arch/x86/boot/video-vesa.o CC arch/x86/boot/video-bios.o HOSTCC arch/x86/boot/tools/build CPUSTR arch/x86/boot/cpustr.h CC arch/x86/boot/cpu.o LDS arch/x86/boot/compressed/vmlinux.lds AS arch/x86/boot/compressed/kernel_info.o AS arch/x86/boot/compressed/head_32.o VOFFSET arch/x86/boot/compressed/../voffset.h CC arch/x86/boot/compressed/string.o CC arch/x86/boot/compressed/cmdline.o CC arch/x86/boot/compressed/error.o OBJCOPY arch/x86/boot/compressed/vmlinux.bin HOSTCC arch/x86/boot/compressed/mkpiggy CC arch/x86/boot/compressed/cpuflags.o CC arch/x86/boot/compressed/early_serial_console.o CC arch/x86/boot/compressed/kaslr.o CC arch/x86/boot/compressed/acpi.o CC arch/x86/boot/compressed/efi.o GZIP arch/x86/boot/compressed/vmlinux.bin.gz CC arch/x86/boot/compressed/misc.o MKPIGGY arch/x86/boot/compressed/piggy.S AS arch/x86/boot/compressed/piggy.o LD arch/x86/boot/compressed/vmlinux ZOFFSET arch/x86/boot/zoffset.h OBJCOPY arch/x86/boot/vmlinux.bin AS arch/x86/boot/header.o LD arch/x86/boot/setup.elf OBJCOPY arch/x86/boot/setup.bin BUILD arch/x86/boot/bzImage Kernel: arch/x86/boot/bzImage is ready (#1) run-parts: executing /workspace/ci/hooks/20-kernel-doc + SRC_DIR=/workspace/kernel + cd /workspace/kernel + find drivers/gpu/drm/xe/ -name '*.[ch]' -not -path 'drivers/gpu/drm/xe/display/*' + xargs ./scripts/kernel-doc -Werror -none include/uapi/drm/xe_drm.h All hooks done ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✗ CI.checksparse: warning for drm/i915: Some intel_display conversions 2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala ` (10 preceding siblings ...) 2024-09-06 15:02 ` ✓ CI.Hooks: " Patchwork @ 2024-09-06 15:03 ` Patchwork 2024-09-06 15:45 ` ✓ CI.BAT: success " Patchwork 2024-09-09 10:12 ` ✗ CI.FULL: failure " Patchwork 13 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2024-09-06 15:03 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-xe == Series Details == Series: drm/i915: Some intel_display conversions URL : https://patchwork.freedesktop.org/series/138332/ State : warning == Summary == + trap cleanup EXIT + KERNEL=/kernel + MT=/root/linux/maintainer-tools + git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools Cloning into '/root/linux/maintainer-tools'... warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/ + make -C /root/linux/maintainer-tools make: Entering directory '/root/linux/maintainer-tools' cc -O2 -g -Wextra -o remap-log remap-log.c make: Leaving directory '/root/linux/maintainer-tools' + cd /kernel + git config --global --add safe.directory /kernel + /root/linux/maintainer-tools/dim sparse --fast 6094a8d70f8599700297da58bcf80d5b1915adff Sparse version: 0.6.1 (Ubuntu: 0.6.1-2build1) Fast mode used, each commit won't be checked separately. + cleanup ++ stat -c %u:%g /kernel + chown -R 1003:1003 /kernel ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✓ CI.BAT: success for drm/i915: Some intel_display conversions 2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala ` (11 preceding siblings ...) 2024-09-06 15:03 ` ✗ CI.checksparse: warning " Patchwork @ 2024-09-06 15:45 ` Patchwork 2024-09-09 10:12 ` ✗ CI.FULL: failure " Patchwork 13 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2024-09-06 15:45 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-xe [-- Attachment #1: Type: text/plain, Size: 1460 bytes --] == Series Details == Series: drm/i915: Some intel_display conversions URL : https://patchwork.freedesktop.org/series/138332/ State : success == Summary == CI Bug Log - changes from xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2_BAT -> xe-pw-138332v1_BAT ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (8 -> 8) ------------------------------ No changes in participating hosts Known issues ------------ Here are the changes found in xe-pw-138332v1_BAT that come from known issues: ### IGT changes ### #### Possible fixes #### * igt@xe_exec_queue_property@invalid-property: - bat-lnl-1: [DMESG-WARN][1] -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/bat-lnl-1/igt@xe_exec_queue_property@invalid-property.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/bat-lnl-1/igt@xe_exec_queue_property@invalid-property.html Build changes ------------- * Linux: xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2 -> xe-pw-138332v1 IGT_8007: 8f9900c288f4cf1244d66baa71bc6d9355747cbd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2: c60c8a9f80f13dfdeed45927a71d65b0250e17d2 xe-pw-138332v1: 138332v1 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/index.html [-- Attachment #2: Type: text/html, Size: 2032 bytes --] ^ permalink raw reply [flat|nested] 24+ messages in thread
* ✗ CI.FULL: failure for drm/i915: Some intel_display conversions 2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala ` (12 preceding siblings ...) 2024-09-06 15:45 ` ✓ CI.BAT: success " Patchwork @ 2024-09-09 10:12 ` Patchwork 13 siblings, 0 replies; 24+ messages in thread From: Patchwork @ 2024-09-09 10:12 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-xe [-- Attachment #1: Type: text/plain, Size: 70695 bytes --] == Series Details == Series: drm/i915: Some intel_display conversions URL : https://patchwork.freedesktop.org/series/138332/ State : failure == Summary == CI Bug Log - changes from xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2_full -> xe-pw-138332v1_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with xe-pw-138332v1_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in xe-pw-138332v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (4 -> 4) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in xe-pw-138332v1_full: ### IGT changes ### #### Possible regressions #### * igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue: - shard-lnl: [PASS][1] -> [FAIL][2] +1 other test fail [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-lnl-7/igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue.html [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-3/igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue.html * igt@xe_evict@evict-mixed-threads-small: - shard-dg2-set2: [PASS][3] -> [DMESG-WARN][4] [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-434/igt@xe_evict@evict-mixed-threads-small.html [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@xe_evict@evict-mixed-threads-small.html * igt@xe_exec_reset@gt-reset-stress: - shard-lnl: [PASS][5] -> [DMESG-WARN][6] [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-lnl-7/igt@xe_exec_reset@gt-reset-stress.html [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-3/igt@xe_exec_reset@gt-reset-stress.html * igt@xe_wedged@wedged-at-any-timeout: - shard-dg2-set2: [PASS][7] -> [FAIL][8] [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-466/igt@xe_wedged@wedged-at-any-timeout.html [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-436/igt@xe_wedged@wedged-at-any-timeout.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@xe_evict@evict-mixed-many-threads-small: - {shard-bmg}: [PASS][9] -> [INCOMPLETE][10] [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-bmg-8/igt@xe_evict@evict-mixed-many-threads-small.html [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-bmg-7/igt@xe_evict@evict-mixed-many-threads-small.html Known issues ------------ Here are the changes found in xe-pw-138332v1_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-1-x: - shard-adlp: [PASS][11] -> [DMESG-WARN][12] ([Intel XE#324]) [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-adlp-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-1-x.html [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-adlp-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-1-x.html * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1: - shard-lnl: [PASS][13] -> [FAIL][14] ([Intel XE#1426]) +1 other test fail [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-lnl-8/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-7/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-edp-1.html * igt@kms_big_fb@4-tiled-64bpp-rotate-270: - shard-lnl: NOTRUN -> [SKIP][15] ([Intel XE#1407]) [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html * igt@kms_big_fb@4-tiled-8bpp-rotate-270: - shard-dg2-set2: NOTRUN -> [SKIP][16] ([Intel XE#1201] / [Intel XE#316]) +1 other test skip [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html * igt@kms_big_fb@y-tiled-16bpp-rotate-180: - shard-lnl: NOTRUN -> [SKIP][17] ([Intel XE#1124]) +1 other test skip [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip: - shard-dg2-set2: NOTRUN -> [SKIP][18] ([Intel XE#1124] / [Intel XE#1201]) +1 other test skip [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html * igt@kms_big_fb@yf-tiled-addfb: - shard-lnl: NOTRUN -> [SKIP][19] ([Intel XE#1467]) [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@kms_big_fb@yf-tiled-addfb.html * igt@kms_bw@linear-tiling-1-displays-2160x1440p: - shard-dg2-set2: NOTRUN -> [SKIP][20] ([Intel XE#1201] / [Intel XE#367]) [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_bw@linear-tiling-1-displays-2160x1440p.html * igt@kms_bw@linear-tiling-2-displays-2560x1440p: - shard-lnl: NOTRUN -> [SKIP][21] ([Intel XE#367]) [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs: - shard-lnl: NOTRUN -> [SKIP][22] ([Intel XE#1399]) +2 other tests skip [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-mc-ccs.html * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs: - shard-dg2-set2: NOTRUN -> [SKIP][23] ([Intel XE#1201] / [Intel XE#1252]) [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-c-dp-4: - shard-dg2-set2: NOTRUN -> [SKIP][24] ([Intel XE#1201] / [Intel XE#787]) +13 other tests skip [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-c-dp-4.html * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4: - shard-dg2-set2: NOTRUN -> [SKIP][25] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +3 other tests skip [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html * igt@kms_chamelium_color@ctm-blue-to-red: - shard-dg2-set2: NOTRUN -> [SKIP][26] ([Intel XE#1201] / [Intel XE#306]) [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_chamelium_color@ctm-blue-to-red.html * igt@kms_chamelium_edid@dp-edid-stress-resolution-4k: - shard-dg2-set2: NOTRUN -> [SKIP][27] ([Intel XE#1201] / [Intel XE#373]) +2 other tests skip [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html * igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k: - shard-lnl: NOTRUN -> [SKIP][28] ([Intel XE#373]) [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@kms_chamelium_edid@dp-edid-stress-resolution-non-4k.html * igt@kms_cursor_crc@cursor-random-512x170: - shard-lnl: NOTRUN -> [SKIP][29] ([Intel XE#1413]) [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@kms_cursor_crc@cursor-random-512x170.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - shard-dg2-set2: NOTRUN -> [SKIP][30] ([Intel XE#1201] / [Intel XE#323]) [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt@kms_flip@2x-plain-flip-ts-check: - shard-lnl: NOTRUN -> [SKIP][31] ([Intel XE#1421]) [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@kms_flip@2x-plain-flip-ts-check.html * igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1: - shard-lnl: [PASS][32] -> [FAIL][33] ([Intel XE#886]) +1 other test fail [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-lnl-4/igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1.html [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-2/igt@kms_flip@flip-vs-blocking-wf-vblank@c-edp1.html * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling: - shard-lnl: NOTRUN -> [SKIP][34] ([Intel XE#1401] / [Intel XE#1745]) +1 other test skip [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode: - shard-lnl: NOTRUN -> [SKIP][35] ([Intel XE#1401]) +1 other test skip [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode.html * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-x: - shard-adlp: [PASS][36] -> [FAIL][37] ([Intel XE#1874]) +2 other tests fail [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-x.html [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-x.html * igt@kms_force_connector_basic@prune-stale-modes: - shard-dg2-set2: NOTRUN -> [SKIP][38] ([Intel XE#1201] / [i915#5274]) [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_force_connector_basic@prune-stale-modes.html * igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-mmap-wc: - shard-lnl: NOTRUN -> [SKIP][39] ([Intel XE#651]) +2 other tests skip [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@kms_frontbuffer_tracking@drrs-1p-offscren-pri-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render: - shard-dg2-set2: NOTRUN -> [SKIP][40] ([Intel XE#1201] / [Intel XE#651]) +6 other tests skip [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-onoff: - shard-lnl: NOTRUN -> [SKIP][41] ([Intel XE#656]) +10 other tests skip [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-onoff.html * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt: - shard-dg2-set2: NOTRUN -> [SKIP][42] ([Intel XE#1201] / [Intel XE#653]) +5 other tests skip [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html * igt@kms_getfb@getfb-reject-ccs: - shard-dg2-set2: NOTRUN -> [SKIP][43] ([Intel XE#1201] / [Intel XE#605]) [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_getfb@getfb-reject-ccs.html * igt@kms_hdr@invalid-hdr: - shard-dg2-set2: [PASS][44] -> [SKIP][45] ([Intel XE#455]) [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_hdr@invalid-hdr.html [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_hdr@invalid-hdr.html * igt@kms_plane@plane-position-hole: - shard-lnl: [PASS][46] -> [DMESG-FAIL][47] ([Intel XE#324]) +1 other test dmesg-fail [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-lnl-7/igt@kms_plane@plane-position-hole.html [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-3/igt@kms_plane@plane-position-hole.html * igt@kms_plane@plane-position-hole-dpms@pipe-b-plane-3: - shard-lnl: [PASS][48] -> [DMESG-WARN][49] ([Intel XE#324]) +4 other tests dmesg-warn [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-lnl-1/igt@kms_plane@plane-position-hole-dpms@pipe-b-plane-3.html [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@kms_plane@plane-position-hole-dpms@pipe-b-plane-3.html * igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256: - shard-dg2-set2: NOTRUN -> [FAIL][50] ([Intel XE#616]) +3 other tests fail [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256.html * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5: - shard-lnl: NOTRUN -> [SKIP][51] ([Intel XE#2318]) +7 other tests skip [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html * igt@kms_psr@fbc-pr-no-drrs: - shard-lnl: NOTRUN -> [SKIP][52] ([Intel XE#1406]) [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@kms_psr@fbc-pr-no-drrs.html * igt@kms_psr@pr-primary-page-flip: - shard-dg2-set2: NOTRUN -> [SKIP][53] ([Intel XE#1201] / [Intel XE#929]) +3 other tests skip [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_psr@pr-primary-page-flip.html * igt@kms_scaling_modes@scaling-mode-full: - shard-dg2-set2: NOTRUN -> [SKIP][54] ([Intel XE#1201] / [Intel XE#455]) +1 other test skip [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_scaling_modes@scaling-mode-full.html * igt@kms_universal_plane@cursor-fb-leak: - shard-lnl: [PASS][55] -> [FAIL][56] ([Intel XE#899]) +1 other test fail [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-lnl-5/igt@kms_universal_plane@cursor-fb-leak.html [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-6/igt@kms_universal_plane@cursor-fb-leak.html * igt@kms_writeback@writeback-check-output-xrgb2101010: - shard-lnl: NOTRUN -> [SKIP][57] ([Intel XE#756]) [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@kms_writeback@writeback-check-output-xrgb2101010.html * igt@kms_writeback@writeback-fb-id-xrgb2101010: - shard-dg2-set2: NOTRUN -> [SKIP][58] ([Intel XE#1201] / [Intel XE#756]) [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_writeback@writeback-fb-id-xrgb2101010.html * igt@xe_evict@evict-beng-mixed-many-threads-small: - shard-lnl: NOTRUN -> [SKIP][59] ([Intel XE#688]) +1 other test skip [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@xe_evict@evict-beng-mixed-many-threads-small.html * igt@xe_evict@evict-mixed-threads-large: - shard-dg2-set2: [PASS][60] -> [TIMEOUT][61] ([Intel XE#1473]) [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@xe_evict@evict-mixed-threads-large.html [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@xe_evict@evict-mixed-threads-large.html * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr: - shard-lnl: NOTRUN -> [SKIP][62] ([Intel XE#1392]) +1 other test skip [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr.html * igt@xe_exec_fault_mode@many-execqueues-invalid-userptr-fault: - shard-dg2-set2: NOTRUN -> [SKIP][63] ([Intel XE#1201] / [Intel XE#288]) +5 other tests skip [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@xe_exec_fault_mode@many-execqueues-invalid-userptr-fault.html * igt@xe_oa@oa-unit-exclusive-stream-sample-oa: - shard-dg2-set2: NOTRUN -> [SKIP][64] ([Intel XE#1201] / [Intel XE#2541]) +1 other test skip [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html * igt@xe_pm@d3cold-mmap-system: - shard-dg2-set2: NOTRUN -> [SKIP][65] ([Intel XE#1201] / [Intel XE#2284] / [Intel XE#366]) [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@xe_pm@d3cold-mmap-system.html * igt@xe_pm@d3hot-mmap-vram: - shard-lnl: NOTRUN -> [SKIP][66] ([Intel XE#1948]) [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@xe_pm@d3hot-mmap-vram.html * igt@xe_pm@s3-mocs: - shard-lnl: NOTRUN -> [SKIP][67] ([Intel XE#584]) [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@xe_pm@s3-mocs.html * igt@xe_pm@s4-basic: - shard-adlp: [PASS][68] -> [ABORT][69] ([Intel XE#1358] / [Intel XE#1607]) [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-adlp-1/igt@xe_pm@s4-basic.html [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-adlp-9/igt@xe_pm@s4-basic.html * igt@xe_pm@s4-vm-bind-unbind-all: - shard-lnl: [PASS][70] -> [ABORT][71] ([Intel XE#1794]) [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-lnl-8/igt@xe_pm@s4-vm-bind-unbind-all.html [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-2/igt@xe_pm@s4-vm-bind-unbind-all.html * igt@xe_query@multigpu-query-oa-units: - shard-lnl: NOTRUN -> [SKIP][72] ([Intel XE#944]) [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@xe_query@multigpu-query-oa-units.html #### Possible fixes #### * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-1-y: - shard-adlp: [DMESG-WARN][73] ([Intel XE#324]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-adlp-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-1-y.html [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-adlp-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-1-y.html * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-dp-2: - {shard-bmg}: [FAIL][75] ([Intel XE#1426]) -> [PASS][76] +1 other test pass [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-bmg-2/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-dp-2.html [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-bmg-4/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-dp-2.html * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1: - shard-adlp: [FAIL][77] ([Intel XE#1426]) -> [PASS][78] +1 other test pass [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-adlp-6/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-adlp-8/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0: - shard-lnl: [FAIL][79] ([Intel XE#1659]) -> [PASS][80] [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-lnl-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs@pipe-c-hdmi-a-3: - {shard-bmg}: [DMESG-WARN][81] ([Intel XE#877]) -> [PASS][82] +8 other tests pass [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-bmg-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs@pipe-c-hdmi-a-3.html [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-bmg-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs@pipe-c-hdmi-a-3.html * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-a-hdmi-a-3: - {shard-bmg}: [FAIL][83] ([Intel XE#2436]) -> [PASS][84] [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-bmg-2/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-a-hdmi-a-3.html [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-bmg-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-a-hdmi-a-3.html * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-d-hdmi-a-3: - {shard-bmg}: [DMESG-FAIL][85] ([Intel XE#877]) -> [PASS][86] [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-bmg-2/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-d-hdmi-a-3.html [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-bmg-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs@pipe-d-hdmi-a-3.html * igt@kms_cursor_legacy@single-bo: - shard-dg2-set2: [DMESG-WARN][87] ([Intel XE#877]) -> [PASS][88] +1 other test pass [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_cursor_legacy@single-bo.html [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_cursor_legacy@single-bo.html * igt@kms_cursor_legacy@torture-move@pipe-b: - {shard-bmg}: [DMESG-WARN][89] -> [PASS][90] [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-bmg-3/igt@kms_cursor_legacy@torture-move@pipe-b.html [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-bmg-4/igt@kms_cursor_legacy@torture-move@pipe-b.html * igt@kms_flip@2x-flip-vs-suspend@ac-hdmi-a6-dp4: - shard-dg2-set2: [FAIL][91] -> [PASS][92] [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-466/igt@kms_flip@2x-flip-vs-suspend@ac-hdmi-a6-dp4.html [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_flip@2x-flip-vs-suspend@ac-hdmi-a6-dp4.html * igt@kms_flip@2x-flip-vs-suspend@ad-hdmi-a6-dp4: - shard-dg2-set2: [TIMEOUT][93] -> [PASS][94] +1 other test pass [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-466/igt@kms_flip@2x-flip-vs-suspend@ad-hdmi-a6-dp4.html [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_flip@2x-flip-vs-suspend@ad-hdmi-a6-dp4.html * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y: - shard-adlp: [FAIL][95] ([Intel XE#1874]) -> [PASS][96] +3 other tests pass [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html * igt@kms_pm_dc@dc6-dpms: - shard-lnl: [FAIL][97] ([Intel XE#1430]) -> [PASS][98] [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-lnl-4/igt@kms_pm_dc@dc6-dpms.html [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-3/igt@kms_pm_dc@dc6-dpms.html * igt@kms_universal_plane@cursor-fb-leak@pipe-c-dp-2: - {shard-bmg}: [FAIL][99] ([Intel XE#899]) -> [PASS][100] [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-bmg-7/igt@kms_universal_plane@cursor-fb-leak@pipe-c-dp-2.html [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-bmg-3/igt@kms_universal_plane@cursor-fb-leak@pipe-c-dp-2.html * igt@xe_drm_fdinfo@utilization-others-idle: - shard-dg2-set2: [INCOMPLETE][101] ([Intel XE#1195]) -> [PASS][102] [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-466/igt@xe_drm_fdinfo@utilization-others-idle.html [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@xe_drm_fdinfo@utilization-others-idle.html * igt@xe_evict@evict-beng-large-multi-vm-cm: - {shard-bmg}: [FAIL][103] ([Intel XE#2364]) -> [PASS][104] [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-bmg-5/igt@xe_evict@evict-beng-large-multi-vm-cm.html [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-bmg-8/igt@xe_evict@evict-beng-large-multi-vm-cm.html * igt@xe_evict@evict-beng-mixed-many-threads-small: - shard-dg2-set2: [TIMEOUT][105] ([Intel XE#1473] / [Intel XE#402]) -> [PASS][106] [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-435/igt@xe_evict@evict-beng-mixed-many-threads-small.html [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-434/igt@xe_evict@evict-beng-mixed-many-threads-small.html * igt@xe_evict@evict-large-multi-vm-cm: - shard-dg2-set2: [FAIL][107] ([Intel XE#1600]) -> [PASS][108] [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-466/igt@xe_evict@evict-large-multi-vm-cm.html [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-436/igt@xe_evict@evict-large-multi-vm-cm.html * igt@xe_gt_freq@freq_reset_multiple: - shard-lnl: [FAIL][109] ([Intel XE#2711]) -> [PASS][110] [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-lnl-7/igt@xe_gt_freq@freq_reset_multiple.html [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-1/igt@xe_gt_freq@freq_reset_multiple.html * igt@xe_pm@s4-vm-bind-userptr: - shard-lnl: [ABORT][111] ([Intel XE#1794]) -> [PASS][112] [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-lnl-2/igt@xe_pm@s4-vm-bind-userptr.html [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-lnl-4/igt@xe_pm@s4-vm-bind-userptr.html * igt@xe_wedged@wedged-at-any-timeout: - {shard-bmg}: [DMESG-WARN][113] ([Intel XE#1760]) -> [PASS][114] [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-bmg-8/igt@xe_wedged@wedged-at-any-timeout.html [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-bmg-2/igt@xe_wedged@wedged-at-any-timeout.html #### Warnings #### * igt@kms_async_flips@invalid-async-flip: - shard-dg2-set2: [SKIP][115] ([Intel XE#873]) -> [SKIP][116] ([Intel XE#1201] / [Intel XE#873]) [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_async_flips@invalid-async-flip.html [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_async_flips@invalid-async-flip.html * igt@kms_big_fb@4-tiled-64bpp-rotate-90: - shard-dg2-set2: [SKIP][117] ([Intel XE#1201] / [Intel XE#316]) -> [SKIP][118] ([Intel XE#316]) +2 other tests skip [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-436/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html * igt@kms_big_fb@linear-16bpp-rotate-90: - shard-dg2-set2: [SKIP][119] ([Intel XE#316]) -> [SKIP][120] ([Intel XE#1201] / [Intel XE#316]) +3 other tests skip [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_big_fb@linear-16bpp-rotate-90.html [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_big_fb@linear-16bpp-rotate-90.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip: - shard-adlp: [FAIL][121] ([Intel XE#1231]) -> [DMESG-FAIL][122] ([Intel XE#324]) [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-adlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-adlp-1/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html * igt@kms_big_fb@y-tiled-addfb-size-overflow: - shard-dg2-set2: [SKIP][123] ([Intel XE#610]) -> [SKIP][124] ([Intel XE#1201] / [Intel XE#610]) [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_big_fb@y-tiled-addfb-size-overflow.html [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_big_fb@y-tiled-addfb-size-overflow.html * igt@kms_big_fb@yf-tiled-16bpp-rotate-0: - shard-dg2-set2: [SKIP][125] ([Intel XE#1124]) -> [SKIP][126] ([Intel XE#1124] / [Intel XE#1201]) +8 other tests skip [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html * igt@kms_big_fb@yf-tiled-32bpp-rotate-180: - shard-dg2-set2: [SKIP][127] ([Intel XE#1124] / [Intel XE#1201]) -> [SKIP][128] ([Intel XE#1124]) +11 other tests skip [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-436/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html * igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p: - shard-dg2-set2: [SKIP][129] ([Intel XE#2191]) -> [SKIP][130] ([Intel XE#1201] / [Intel XE#2191]) +1 other test skip [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html * igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p: - shard-dg2-set2: [SKIP][131] ([Intel XE#1201] / [Intel XE#2191]) -> [SKIP][132] ([Intel XE#2191]) +1 other test skip [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-436/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_bw@connected-linear-tiling-4-displays-2560x1440p.html * igt@kms_bw@linear-tiling-1-displays-1920x1080p: - shard-dg2-set2: [SKIP][133] ([Intel XE#367]) -> [SKIP][134] ([Intel XE#1201] / [Intel XE#367]) +3 other tests skip [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_bw@linear-tiling-1-displays-1920x1080p.html * igt@kms_bw@linear-tiling-3-displays-2160x1440p: - shard-dg2-set2: [SKIP][135] ([Intel XE#1201] / [Intel XE#367]) -> [SKIP][136] ([Intel XE#367]) +3 other tests skip [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-6: - shard-dg2-set2: [SKIP][137] ([Intel XE#1201] / [Intel XE#787]) -> [SKIP][138] ([Intel XE#787]) +69 other tests skip [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-6.html [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs@pipe-c-hdmi-a-6.html * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs: - shard-dg2-set2: [SKIP][139] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) -> [SKIP][140] ([Intel XE#455] / [Intel XE#787]) +19 other tests skip [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs: - shard-dg2-set2: [SKIP][141] ([Intel XE#1252]) -> [SKIP][142] ([Intel XE#1201] / [Intel XE#1252]) [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-dp-4: - shard-dg2-set2: [SKIP][143] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][144] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#787]) +23 other tests skip [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-dp-4.html [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-dp-4.html * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4: - shard-dg2-set2: [SKIP][145] ([Intel XE#787]) -> [SKIP][146] ([Intel XE#1201] / [Intel XE#787]) +83 other tests skip [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4.html [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-dp-4.html * igt@kms_chamelium_color@ctm-0-50: - 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shard-dg2-set2: [SKIP][153] ([Intel XE#1201] / [Intel XE#373]) -> [SKIP][154] ([Intel XE#373]) +8 other tests skip [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html * igt@kms_cursor_crc@cursor-offscreen-512x170: - shard-dg2-set2: [SKIP][155] ([Intel XE#308]) -> [SKIP][156] ([Intel XE#1201] / [Intel XE#308]) +1 other test skip [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_cursor_crc@cursor-offscreen-512x170.html [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_cursor_crc@cursor-offscreen-512x170.html * igt@kms_cursor_crc@cursor-onscreen-512x170: - shard-dg2-set2: [SKIP][157] ([Intel XE#1201] / [Intel XE#308]) -> [SKIP][158] ([Intel XE#308]) +1 other test skip [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-436/igt@kms_cursor_crc@cursor-onscreen-512x170.html [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_cursor_crc@cursor-onscreen-512x170.html * igt@kms_cursor_crc@cursor-random-max-size: - shard-dg2-set2: [SKIP][159] ([Intel XE#455]) -> [SKIP][160] ([Intel XE#1201] / [Intel XE#455]) +10 other tests skip [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_cursor_crc@cursor-random-max-size.html [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_cursor_crc@cursor-random-max-size.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size: - shard-dg2-set2: [SKIP][161] ([Intel XE#1201] / [Intel XE#323]) -> [SKIP][162] ([Intel XE#323]) [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size: - shard-dg2-set2: [SKIP][163] ([Intel XE#323]) -> [SKIP][164] ([Intel XE#1201] / [Intel XE#323]) [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html * igt@kms_feature_discovery@chamelium: - shard-dg2-set2: [SKIP][165] ([Intel XE#701]) -> [SKIP][166] ([Intel XE#1201] / [Intel XE#701]) [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_feature_discovery@chamelium.html [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_feature_discovery@chamelium.html * igt@kms_feature_discovery@display-3x: - shard-dg2-set2: [SKIP][167] ([Intel XE#703]) -> [SKIP][168] ([Intel XE#1201] / [Intel XE#703]) [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_feature_discovery@display-3x.html [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_feature_discovery@display-3x.html * igt@kms_feature_discovery@display-4x: - shard-dg2-set2: [SKIP][169] ([Intel XE#1138]) -> [SKIP][170] ([Intel XE#1138] / [Intel XE#1201]) [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_feature_discovery@display-4x.html [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_feature_discovery@display-4x.html * igt@kms_feature_discovery@psr2: - shard-dg2-set2: [SKIP][171] ([Intel XE#1135] / [Intel XE#1201]) -> [SKIP][172] ([Intel XE#1135]) [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_feature_discovery@psr2.html [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_feature_discovery@psr2.html * igt@kms_frontbuffer_tracking@fbc-tiling-y: - shard-dg2-set2: [SKIP][173] ([Intel XE#658]) -> [SKIP][174] ([Intel XE#1201] / [Intel XE#658]) [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_frontbuffer_tracking@fbc-tiling-y.html [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-tiling-y.html * igt@kms_frontbuffer_tracking@fbcdrrs-1p-rte: - shard-dg2-set2: [SKIP][175] ([Intel XE#651]) -> [SKIP][176] ([Intel XE#1201] / [Intel XE#651]) +27 other tests skip [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-1p-rte.html [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_frontbuffer_tracking@fbcdrrs-1p-rte.html * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-pgflip-blt: - shard-dg2-set2: [SKIP][177] ([Intel XE#1201] / [Intel XE#651]) -> [SKIP][178] ([Intel XE#651]) +29 other tests skip [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-pgflip-blt.html [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-pgflip-blt.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt: - shard-dg2-set2: [SKIP][179] ([Intel XE#1201] / [Intel XE#653]) -> [SKIP][180] ([Intel XE#653]) +30 other tests skip [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html * igt@kms_frontbuffer_tracking@psr-slowdraw: - shard-dg2-set2: [SKIP][181] ([Intel XE#653]) -> [SKIP][182] ([Intel XE#1201] / [Intel XE#653]) +28 other tests skip [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_frontbuffer_tracking@psr-slowdraw.html [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_frontbuffer_tracking@psr-slowdraw.html * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation: - shard-dg2-set2: [SKIP][183] ([Intel XE#1201] / [Intel XE#455] / [Intel XE#498]) -> [SKIP][184] ([Intel XE#455] / [Intel XE#498]) +1 other test skip [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation.html [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation.html * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-6: - shard-dg2-set2: [SKIP][185] ([Intel XE#1201] / [Intel XE#498]) -> [SKIP][186] ([Intel XE#498]) +2 other tests skip [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-6.html [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-b-hdmi-a-6.html * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-a-hdmi-a-6: - shard-dg2-set2: [SKIP][187] ([Intel XE#2318]) -> [SKIP][188] ([Intel XE#1201] / [Intel XE#2318]) +2 other tests skip [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-a-hdmi-a-6.html [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-a-hdmi-a-6.html * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-6: - 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shard-dg2-set2: [SKIP][193] ([Intel XE#1201] / [Intel XE#2318]) -> [SKIP][194] ([Intel XE#2318]) +8 other tests skip [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-hdmi-a-6.html [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c-hdmi-a-6.html * igt@kms_pm_backlight@bad-brightness: - shard-dg2-set2: [SKIP][195] ([Intel XE#870]) -> [SKIP][196] ([Intel XE#1201] / [Intel XE#870]) [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_pm_backlight@bad-brightness.html [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_pm_backlight@bad-brightness.html * igt@kms_pm_backlight@fade: - shard-dg2-set2: [SKIP][197] ([Intel XE#1201] / [Intel XE#870]) -> [SKIP][198] ([Intel XE#870]) [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-436/igt@kms_pm_backlight@fade.html [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_pm_backlight@fade.html * igt@kms_pm_dc@dc6-psr: - shard-dg2-set2: [SKIP][199] ([Intel XE#1129]) -> [SKIP][200] ([Intel XE#1129] / [Intel XE#1201]) [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_pm_dc@dc6-psr.html [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_pm_dc@dc6-psr.html * igt@kms_pm_dc@deep-pkgc: - shard-dg2-set2: [SKIP][201] ([Intel XE#1201] / [Intel XE#908]) -> [SKIP][202] ([Intel XE#908]) [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_pm_dc@deep-pkgc.html [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_pm_dc@deep-pkgc.html * igt@kms_psr2_sf@overlay-plane-update-continuous-sf: - shard-dg2-set2: [SKIP][203] ([Intel XE#1201] / [Intel XE#1489]) -> [SKIP][204] ([Intel XE#1489]) +2 other tests skip [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area: - shard-dg2-set2: [SKIP][205] ([Intel XE#1489]) -> [SKIP][206] ([Intel XE#1201] / [Intel XE#1489]) +4 other tests skip [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html * igt@kms_psr2_su@page_flip-xrgb8888: - shard-dg2-set2: [SKIP][207] ([Intel XE#1122] / [Intel XE#1201]) -> [SKIP][208] ([Intel XE#1122]) +1 other test skip [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_psr2_su@page_flip-xrgb8888.html [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_psr2_su@page_flip-xrgb8888.html * igt@kms_psr@fbc-psr-sprite-render: - shard-dg2-set2: [SKIP][209] ([Intel XE#1201] / [Intel XE#929]) -> [SKIP][210] ([Intel XE#929]) +12 other tests skip [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_psr@fbc-psr-sprite-render.html [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_psr@fbc-psr-sprite-render.html * igt@kms_psr@psr2-basic: - shard-dg2-set2: [SKIP][211] ([Intel XE#929]) -> [SKIP][212] ([Intel XE#1201] / [Intel XE#929]) +13 other tests skip [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_psr@psr2-basic.html [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_psr@psr2-basic.html * igt@kms_psr_stress_test@invalidate-primary-flip-overlay: - shard-dg2-set2: [SKIP][213] ([Intel XE#1149] / [Intel XE#1201]) -> [SKIP][214] ([Intel XE#1149]) [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0: - shard-dg2-set2: [SKIP][215] ([Intel XE#1127] / [Intel XE#1201]) -> [SKIP][216] ([Intel XE#1127]) [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90: - shard-dg2-set2: [SKIP][217] ([Intel XE#327]) -> [SKIP][218] ([Intel XE#1201] / [Intel XE#327]) +3 other tests skip [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html * igt@kms_rotation_crc@sprite-rotation-270: - shard-dg2-set2: [SKIP][219] ([Intel XE#1201] / [Intel XE#327]) -> [SKIP][220] ([Intel XE#327]) +3 other tests skip [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-436/igt@kms_rotation_crc@sprite-rotation-270.html [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_rotation_crc@sprite-rotation-270.html * igt@kms_tiled_display@basic-test-pattern-with-chamelium: - shard-dg2-set2: [SKIP][221] ([Intel XE#1201] / [Intel XE#1500]) -> [SKIP][222] ([Intel XE#1201] / [Intel XE#362]) [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-434/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html * igt@kms_tv_load_detect@load-detect: - shard-dg2-set2: [SKIP][223] ([Intel XE#1201] / [Intel XE#330]) -> [SKIP][224] ([Intel XE#330]) [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_tv_load_detect@load-detect.html [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_tv_load_detect@load-detect.html * igt@kms_vrr@flip-dpms: - shard-dg2-set2: [SKIP][225] ([Intel XE#1201] / [Intel XE#455]) -> [SKIP][226] ([Intel XE#455]) +18 other tests skip [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@kms_vrr@flip-dpms.html [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@kms_vrr@flip-dpms.html * igt@kms_writeback@writeback-fb-id: - shard-dg2-set2: [SKIP][227] ([Intel XE#756]) -> [SKIP][228] ([Intel XE#1201] / [Intel XE#756]) [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@kms_writeback@writeback-fb-id.html [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@kms_writeback@writeback-fb-id.html * igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute: - shard-dg2-set2: [SKIP][229] ([Intel XE#1280] / [Intel XE#455]) -> [SKIP][230] ([Intel XE#1201] / [Intel XE#1280] / [Intel XE#455]) +1 other test skip [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute.html [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute.html * igt@xe_copy_basic@mem-copy-linear-0x3fff: - shard-dg2-set2: [SKIP][231] ([Intel XE#1123] / [Intel XE#1201]) -> [SKIP][232] ([Intel XE#1123]) [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@xe_copy_basic@mem-copy-linear-0x3fff.html [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@xe_copy_basic@mem-copy-linear-0x3fff.html * igt@xe_evict@evict-mixed-many-threads-large: - shard-dg2-set2: [FAIL][233] ([Intel XE#1000]) -> [TIMEOUT][234] ([Intel XE#1473]) [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-436/igt@xe_evict@evict-mixed-many-threads-large.html [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-434/igt@xe_evict@evict-mixed-many-threads-large.html * igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind-prefetch: - shard-dg2-set2: [SKIP][235] ([Intel XE#288]) -> [SKIP][236] ([Intel XE#1201] / [Intel XE#288]) +24 other tests skip [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind-prefetch.html [236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-rebind-prefetch.html * igt@xe_exec_fault_mode@twice-userptr-invalidate-race: - shard-dg2-set2: [SKIP][237] ([Intel XE#1201] / [Intel XE#288]) -> [SKIP][238] ([Intel XE#288]) +26 other tests skip [237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@xe_exec_fault_mode@twice-userptr-invalidate-race.html [238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@xe_exec_fault_mode@twice-userptr-invalidate-race.html * igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence: - shard-dg2-set2: [SKIP][239] ([Intel XE#1201] / [Intel XE#2360]) -> [SKIP][240] ([Intel XE#2360]) [239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-436/igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence.html [240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@xe_exec_mix_modes@exec-simple-batch-store-dma-fence.html * igt@xe_exec_mix_modes@exec-spinner-interrupted-lr: - shard-dg2-set2: [SKIP][241] ([Intel XE#2360]) -> [SKIP][242] ([Intel XE#1201] / [Intel XE#2360]) [241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@xe_exec_mix_modes@exec-spinner-interrupted-lr.html [242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@xe_exec_mix_modes@exec-spinner-interrupted-lr.html * igt@xe_huc_copy@huc_copy: - shard-dg2-set2: [SKIP][243] ([Intel XE#1201] / [Intel XE#255]) -> [SKIP][244] ([Intel XE#255]) [243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-436/igt@xe_huc_copy@huc_copy.html [244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@xe_huc_copy@huc_copy.html * igt@xe_media_fill@media-fill: - shard-dg2-set2: [SKIP][245] ([Intel XE#560]) -> [SKIP][246] ([Intel XE#1201] / [Intel XE#560]) [245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@xe_media_fill@media-fill.html [246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@xe_media_fill@media-fill.html * igt@xe_module_load@force-load: - shard-dg2-set2: [SKIP][247] ([Intel XE#378]) -> [SKIP][248] ([Intel XE#1201] / [Intel XE#378]) [247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@xe_module_load@force-load.html [248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@xe_module_load@force-load.html * igt@xe_module_load@load: - shard-dg2-set2: [SKIP][249] ([Intel XE#1201] / [Intel XE#378]) -> [SKIP][250] ([Intel XE#378]) [249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@xe_module_load@load.html [250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@xe_module_load@load.html * igt@xe_oa@closed-fd-and-unmapped-access: - shard-dg2-set2: [SKIP][251] ([Intel XE#1201] / [Intel XE#2541]) -> [SKIP][252] ([Intel XE#2541]) +6 other tests skip [251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@xe_oa@closed-fd-and-unmapped-access.html [252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@xe_oa@closed-fd-and-unmapped-access.html * igt@xe_oa@privileged-forked-access-vaddr: - shard-dg2-set2: [SKIP][253] ([Intel XE#2541]) -> [SKIP][254] ([Intel XE#1201] / [Intel XE#2541]) +5 other tests skip [253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@xe_oa@privileged-forked-access-vaddr.html [254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-466/igt@xe_oa@privileged-forked-access-vaddr.html * igt@xe_pat@pat-index-xelpg: - shard-dg2-set2: [SKIP][255] ([Intel XE#1201] / [Intel XE#979]) -> [SKIP][256] ([Intel XE#979]) +1 other test skip [255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@xe_pat@pat-index-xelpg.html [256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@xe_pat@pat-index-xelpg.html * igt@xe_pm@s2idle-d3cold-basic-exec: - shard-dg2-set2: [SKIP][257] ([Intel XE#1201] / [Intel XE#2284] / [Intel XE#366]) -> [SKIP][258] ([Intel XE#2284] / [Intel XE#366]) +1 other test skip [257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@xe_pm@s2idle-d3cold-basic-exec.html [258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@xe_pm@s2idle-d3cold-basic-exec.html * igt@xe_pm@vram-d3cold-threshold: - shard-dg2-set2: [SKIP][259] ([Intel XE#1201] / [Intel XE#579]) -> [SKIP][260] ([Intel XE#579]) [259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@xe_pm@vram-d3cold-threshold.html [260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@xe_pm@vram-d3cold-threshold.html * igt@xe_query@multigpu-query-hwconfig: - shard-dg2-set2: [SKIP][261] ([Intel XE#944]) -> [SKIP][262] ([Intel XE#1201] / [Intel XE#944]) [261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-432/igt@xe_query@multigpu-query-hwconfig.html [262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-433/igt@xe_query@multigpu-query-hwconfig.html * igt@xe_query@multigpu-query-uc-fw-version-guc: - shard-dg2-set2: [SKIP][263] ([Intel XE#1201] / [Intel XE#944]) -> [SKIP][264] ([Intel XE#944]) +4 other tests skip [263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2/shard-dg2-463/igt@xe_query@multigpu-query-uc-fw-version-guc.html [264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/shard-dg2-432/igt@xe_query@multigpu-query-uc-fw-version-guc.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [Intel XE#1000]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1000 [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122 [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123 [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124 [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127 [Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129 [Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135 [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138 [Intel XE#1149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1149 [Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195 [Intel XE#1201]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1201 [Intel XE#1231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1231 [Intel XE#1252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1252 [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280 [Intel XE#1358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1358 [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392 [Intel XE#1399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1399 [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401 [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406 [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407 [Intel XE#1413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1413 [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421 [Intel XE#1426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1426 [Intel XE#1430]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1430 [Intel XE#1467]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1467 [Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473 [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489 [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500 [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503 [Intel XE#1600]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1600 [Intel XE#1607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1607 [Intel XE#1659]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1659 [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745 [Intel XE#1760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1760 [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794 [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874 [Intel XE#1948]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1948 [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191 [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284 [Intel XE#2318]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2318 [Intel XE#2333]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2333 [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360 [Intel XE#2364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2364 [Intel XE#2436]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2436 [Intel XE#2472]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2472 [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541 [Intel XE#255]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/255 [Intel XE#2711]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2711 [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288 [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306 [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308 [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316 [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323 [Intel XE#324]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/324 [Intel XE#327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/327 [Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330 [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362 [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366 [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367 [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373 [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378 [Intel XE#402]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/402 [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455 [Intel XE#498]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/498 [Intel XE#560]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/560 [Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579 [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584 [Intel XE#605]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/605 [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610 [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616 [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651 [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653 [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656 [Intel XE#658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/658 [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688 [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701 [Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703 [Intel XE#756]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/756 [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787 [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870 [Intel XE#873]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/873 [Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877 [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886 [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899 [Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908 [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929 [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944 [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979 [i915#5274]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5274 Build changes ------------- * Linux: xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2 -> xe-pw-138332v1 IGT_8007: 8f9900c288f4cf1244d66baa71bc6d9355747cbd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git xe-1904-c60c8a9f80f13dfdeed45927a71d65b0250e17d2: c60c8a9f80f13dfdeed45927a71d65b0250e17d2 xe-pw-138332v1: 138332v1 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-138332v1/index.html [-- Attachment #2: Type: text/html, Size: 91287 bytes --] ^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2024-09-09 10:12 UTC | newest] Thread overview: 24+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-09-06 14:33 [PATCH 0/6] drm/i915: Some intel_display conversions Ville Syrjala 2024-09-06 14:33 ` [PATCH 1/6] drm/i915/cdclk: Add missing braces Ville Syrjala 2024-09-06 15:10 ` Rodrigo Vivi 2024-09-06 15:19 ` Jani Nikula 2024-09-06 14:33 ` [PATCH 2/6] drm/i915/cdclk: Convert CDCLK code to intel_display Ville Syrjala 2024-09-06 15:09 ` Rodrigo Vivi 2024-09-06 15:18 ` Jani Nikula 2024-09-06 16:17 ` Ville Syrjälä 2024-09-06 14:33 ` [PATCH 3/6] drm/i915/power: Convert low level DC state " Ville Syrjala 2024-09-06 15:10 ` Rodrigo Vivi 2024-09-06 14:33 ` [PATCH 4/6] drm/i915/vga: Convert VGA " Ville Syrjala 2024-09-06 15:12 ` Rodrigo Vivi 2024-09-06 14:33 ` [PATCH 5/6] drm/i915/power: Convert "i830 power well" " Ville Syrjala 2024-09-06 15:13 ` Rodrigo Vivi 2024-09-06 14:33 ` [PATCH 6/6] drm/i915/dmc: Convert DMC " Ville Syrjala 2024-09-06 15:16 ` Rodrigo Vivi 2024-09-06 14:38 ` ✓ CI.Patch_applied: success for drm/i915: Some intel_display conversions Patchwork 2024-09-06 14:39 ` ✗ CI.checkpatch: warning " Patchwork 2024-09-06 14:40 ` ✓ CI.KUnit: success " Patchwork 2024-09-06 14:57 ` ✓ CI.Build: " Patchwork 2024-09-06 15:02 ` ✓ CI.Hooks: " Patchwork 2024-09-06 15:03 ` ✗ CI.checksparse: warning " Patchwork 2024-09-06 15:45 ` ✓ CI.BAT: success " Patchwork 2024-09-09 10:12 ` ✗ CI.FULL: failure " Patchwork
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