From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: [PATCH 8/9] drm/i915/dsc: Account for Odd pixel removal
Date: Mon, 14 Oct 2024 12:32:25 +0530 [thread overview]
Message-ID: <20241014070226.2729008-9-ankit.k.nautiyal@intel.com> (raw)
In-Reply-To: <20241014070226.2729008-1-ankit.k.nautiyal@intel.com>
With 3 DSC engines we can support 12 slices. With ultra joiner
usecase while dividing the width into 12 slices, we might
end up having odd number of pixels per pipe.
As per Bspec, pipe src size should be even, so an extra pixel is added
in each pipe. For Pipe A and C the odd pixel is added at the end of
pipe and for Pipe B and D it is added at the beginning of the pipe.
This extra pixel needs to be dropped in Splitter hardware.
So account for odd pixel removal while programming DSS CTL.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 26 +++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index f58dac630bb8..d2d712545450 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -768,6 +768,26 @@ void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state)
}
}
+/*
+ * With 12 slices, there can be a case where the src width is odd.
+ * As per Bspec the src width should be even, so an extra Odd Pixel is
+ * programmed in Pipe in such cases. This extra pixel needs to be
+ * dropped in Splitter HW.
+ */
+static
+bool intel_dsc_need_odd_pixel_removal(const struct intel_crtc_state *crtc_state)
+{
+ int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
+
+ if (intel_crtc_num_joined_pipes(crtc_state) != 4)
+ return false;
+
+ if ((pipe_src_w + crtc_state->dsc.pixel_replication_count) % 4)
+ return true;
+
+ return false;
+}
+
void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -806,6 +826,12 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state)
dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE;
}
+ if (intel_dsc_need_odd_pixel_removal(crtc_state)) {
+ dss_ctl2_val |= ODD_PIXEL_REMOVAL;
+ if (crtc->pipe == PIPE_A || crtc->pipe == PIPE_C)
+ dss_ctl2_val |= ODD_PIXEL_REMOVAL_CONFIG_EOL;
+ }
+
if (crtc_state->dsc.pixel_replication_count)
dss_ctl3_val = DSC_PIXEL_REPLICATION(crtc_state->dsc.pixel_replication_count);
--
2.45.2
next prev parent reply other threads:[~2024-10-14 7:00 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-14 7:02 [PATCH 0/9] Add support for 3 VDSC engines 12 slices Ankit Nautiyal
2024-10-14 7:02 ` [PATCH 1/9] drm/i915/display: Prepare for dsc 3 stream splitter Ankit Nautiyal
2024-10-14 7:02 ` [PATCH 2/9] drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine Ankit Nautiyal
2024-10-14 7:02 ` [PATCH 3/9] drm/i915/vdsc: Add register bits for VDSC2 engine Ankit Nautiyal
2024-10-14 7:02 ` [PATCH 4/9] drm/i915/vdsc: Add support for read/write PPS for DSC3 Ankit Nautiyal
2024-10-14 7:02 ` [PATCH 5/9] drm/i915/dp: Add check for hdisplay divisible by slice count Ankit Nautiyal
2024-10-14 7:02 ` [PATCH 6/9] drm/i915/display: Add DSC pixel replication Ankit Nautiyal
2024-10-14 7:02 ` [PATCH 7/9] drm/i915/dp: Compute pixel replication count for DSC 12 slices case Ankit Nautiyal
2024-10-14 7:02 ` Ankit Nautiyal [this message]
2024-10-14 7:02 ` [PATCH 9/9] drm/i915/dp: Add support for 3 vdsc engines and 12 slices Ankit Nautiyal
2024-10-14 7:07 ` ✗ CI.Patch_applied: failure for Add support for 3 VDSC engines " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2024-10-14 8:09 [PATCH 0/9] " Ankit Nautiyal
2024-10-14 8:09 ` [PATCH 8/9] drm/i915/dsc: Account for Odd pixel removal Ankit Nautiyal
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