[PATCH 0/3] drm/i915/dmc_wl: Track pipe interrupt registers

[Gustavo Sousa <gustavo.sousa@intel.com>]

Pipe interrupt registers live in their respective pipes' power wells,
which are below PG0. That means that they must also be tracked as
registers that are powered-off during dynamic DC states.

For that, we first convert the display IRQ code to use display-specific
MMIO functions so that DMC wakelock checks are properly done and then
add the range for pipe interrupts in the table checked by the DMC
wakelock code.

This series fixes vblank timeouts that were happening due to PIPE
interrupt registers being accessed without the DMC wakelock.

Gustavo Sousa (3):
  drm/i915/display: Use display MMIO functions in intel_display_irq.c
  drm/i915/display: Wrap IRQ-specific uncore functions
  drm/i915/dmc_wl: Track pipe interrupt registers

 drivers/gpu/drm/i915/display/intel_de.h       |  43 +++
 .../gpu/drm/i915/display/intel_display_irq.c  | 307 +++++++++---------
 drivers/gpu/drm/i915/display/intel_dmc_wl.c   |   1 +
 3 files changed, 205 insertions(+), 146 deletions(-)

-- 
2.47.1