From: Suraj Kandpal <suraj.kandpal@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com,
Suraj Kandpal <suraj.kandpal@intel.com>
Subject: [PATCH 0/2] SSC enablement in port clock programming
Date: Mon, 6 Jan 2025 09:38:19 +0530 [thread overview]
Message-ID: <20250106040821.251114-1-suraj.kandpal@intel.com> (raw)
According to specs SSC is enabled during port clock programming based on
below conditions:
-if uhbr 10 or uhbr 20 enable ssc regardless of what display controller
asks of us
-if ubhr 13.5 or legacy rates enable ssc if required.
Currently these conditions are not exactly followed this patch series
fixes that.
One more thing this patch addresses is how SSC was not enabled for c20
PHY at all because ssc_enabled variable is never set for c20 PHY.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Suraj Kandpal (2):
drm/i915/cx0: Fix SSC enablement in PORT_CLOCK_CTL
drm/i915/cx0: Set ssc_enabled for c20 too
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
--
2.34.1
next reply other threads:[~2025-01-06 4:08 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-06 4:08 Suraj Kandpal [this message]
2025-01-06 4:08 ` [PATCH 1/2] drm/i915/cx0: Fix SSC enablement in PORT_CLOCK_CTL Suraj Kandpal
2025-01-07 15:02 ` Imre Deak
2025-01-08 6:04 ` Kandpal, Suraj
2025-01-08 17:05 ` Imre Deak
2025-01-16 5:14 ` Kandpal, Suraj
2025-01-06 4:08 ` [PATCH 2/2] drm/i915/cx0: Set ssc_enabled for c20 too Suraj Kandpal
2025-01-06 4:37 ` ✓ CI.Patch_applied: success for SSC enablement in port clock programming Patchwork
2025-01-06 4:37 ` ✓ CI.checkpatch: " Patchwork
2025-01-06 4:38 ` ✓ CI.KUnit: " Patchwork
2025-01-06 4:57 ` ✓ CI.Build: " Patchwork
2025-01-06 4:59 ` ✓ CI.Hooks: " Patchwork
2025-01-06 5:01 ` ✓ CI.checksparse: " Patchwork
2025-01-06 5:28 ` ✓ Xe.CI.BAT: " Patchwork
2025-01-06 7:41 ` ✗ Xe.CI.Full: failure " Patchwork
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