From: Suraj Kandpal <suraj.kandpal@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: ankit.k.nautiyal@intel.com, uma.shankar@intel.com,
Suraj Kandpal <suraj.kandpal@intel.com>
Subject: [PATCH 1/2] drm/i915/cx0: Fix SSC enablement in PORT_CLOCK_CTL
Date: Mon, 6 Jan 2025 09:38:20 +0530 [thread overview]
Message-ID: <20250106040821.251114-2-suraj.kandpal@intel.com> (raw)
In-Reply-To: <20250106040821.251114-1-suraj.kandpal@intel.com>
SSC for PLL_A is enabled for UHBR10 or UHBR20 regardless of the
need for SSC. This means the ssc_enabled variable had no say
to determine enablement of SSC on PLL A.
Bspec: 64568, 74165, 74489, 74491
Fixes: 237e7be0bf57 ("drm/i915/mtl: For DP2.0 10G and 20G rates use MPLLA")
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index e768dc6a15b3..3fd959a2773c 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2747,7 +2747,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
/* TODO: HDMI FRL */
/* DP2.0 10G and 20G rates enable MPLLA*/
if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000)
- val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0;
+ val |= XELPDP_SSC_ENABLE_PLLA;
else
val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
--
2.34.1
next prev parent reply other threads:[~2025-01-06 4:08 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-06 4:08 [PATCH 0/2] SSC enablement in port clock programming Suraj Kandpal
2025-01-06 4:08 ` Suraj Kandpal [this message]
2025-01-07 15:02 ` [PATCH 1/2] drm/i915/cx0: Fix SSC enablement in PORT_CLOCK_CTL Imre Deak
2025-01-08 6:04 ` Kandpal, Suraj
2025-01-08 17:05 ` Imre Deak
2025-01-16 5:14 ` Kandpal, Suraj
2025-01-06 4:08 ` [PATCH 2/2] drm/i915/cx0: Set ssc_enabled for c20 too Suraj Kandpal
2025-01-06 4:37 ` ✓ CI.Patch_applied: success for SSC enablement in port clock programming Patchwork
2025-01-06 4:37 ` ✓ CI.checkpatch: " Patchwork
2025-01-06 4:38 ` ✓ CI.KUnit: " Patchwork
2025-01-06 4:57 ` ✓ CI.Build: " Patchwork
2025-01-06 4:59 ` ✓ CI.Hooks: " Patchwork
2025-01-06 5:01 ` ✓ CI.checksparse: " Patchwork
2025-01-06 5:28 ` ✓ Xe.CI.BAT: " Patchwork
2025-01-06 7:41 ` ✗ Xe.CI.Full: failure " Patchwork
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