From: Maarten Lankhorst <dev@lankhorst.se>
To: intel-xe@lists.freedesktop.org
Cc: Maarten Lankhorst <dev@lankhorst.se>
Subject: [CI 06/13] drm/xe/display: Dont poke into GGTT internals to fill a DPT
Date: Fri, 4 Apr 2025 22:51:31 +0200 [thread overview]
Message-ID: <20250404205138.620455-7-dev@lankhorst.se> (raw)
In-Reply-To: <20250404205138.620455-1-dev@lankhorst.se>
For DPT, it is sufficient to get the GGTT encode flags to fill the DPT.
Create a function to return the encode flags, and then encode using the
BO address.
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 20 +++++++++-----------
drivers/gpu/drm/xe/xe_ggtt.c | 15 +++++++++++++++
drivers/gpu/drm/xe/xe_ggtt.h | 2 ++
3 files changed, 26 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index d509def82b134..5392e46a3a134 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -23,6 +23,7 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32 bo_
struct xe_device *xe = xe_bo_device(bo);
struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
u32 column, row;
+ u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]);
/* TODO: Maybe rewrite so we can traverse the bo addresses sequentially,
* by writing dpt/ggtt in a different order?
@@ -32,10 +33,9 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32 bo_
u32 src_idx = src_stride * (height - 1) + column + bo_ofs;
for (row = 0; row < height; row++) {
- u64 pte = ggtt->pt_ops->pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
- xe->pat.idx[XE_CACHE_NONE]);
+ u64 addr = xe_bo_addr(bo, src_idx * XE_PAGE_SIZE, XE_PAGE_SIZE);
- iosys_map_wr(map, *dpt_ofs, u64, pte);
+ iosys_map_wr(map, *dpt_ofs, u64, pte | addr);
*dpt_ofs += 8;
src_idx -= src_stride;
}
@@ -55,17 +55,15 @@ write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs,
{
struct xe_device *xe = xe_bo_device(bo);
struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
- u64 (*pte_encode_bo)(struct xe_bo *bo, u64 bo_offset, u16 pat_index)
- = ggtt->pt_ops->pte_encode_bo;
u32 column, row;
+ u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]);
for (row = 0; row < height; row++) {
u32 src_idx = src_stride * row + bo_ofs;
for (column = 0; column < width; column++) {
- iosys_map_wr(map, *dpt_ofs, u64,
- pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
- xe->pat.idx[XE_CACHE_NONE]));
+ u64 addr = xe_bo_addr(bo, src_idx * XE_PAGE_SIZE, XE_PAGE_SIZE);
+ iosys_map_wr(map, *dpt_ofs, u64, pte | addr);
*dpt_ofs += 8;
src_idx++;
@@ -129,13 +127,13 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
return PTR_ERR(dpt);
if (view->type == I915_GTT_VIEW_NORMAL) {
+ u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]);
u32 x;
for (x = 0; x < size / XE_PAGE_SIZE; x++) {
- u64 pte = ggtt->pt_ops->pte_encode_bo(bo, x * XE_PAGE_SIZE,
- xe->pat.idx[XE_CACHE_NONE]);
+ u64 addr = xe_bo_addr(bo, x * XE_PAGE_SIZE, XE_PAGE_SIZE);
- iosys_map_wr(&dpt->vmap, x * 8, u64, pte);
+ iosys_map_wr(&dpt->vmap, x * 8, u64, pte | addr);
}
} else if (view->type == I915_GTT_VIEW_REMAPPED) {
const struct intel_remapped_info *remap_info = &view->remapped;
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index 8e1976bceb44f..5ea2f9fac85d4 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -918,3 +918,18 @@ u64 xe_ggtt_print_holes(struct xe_ggtt *ggtt, u64 alignment, struct drm_printer
return total;
}
+
+/**
+ * xe_ggtt_encode_pte_flags - Get PTE encoding flags for BO
+ * @ggtt: &xe_ggtt
+ * @bo: &xe_bo
+ * @pat_index: The pat_index for the PTE.
+ *
+ * This function returns the pte_flags for a given BO, without address.
+ * It's used for DPT to fill a GGTT mapped BO with a linear lookup table.
+ */
+u64 xe_ggtt_encode_pte_flags(struct xe_ggtt *ggtt,
+ struct xe_bo *bo, u16 pat_index)
+{
+ return ggtt->pt_ops->pte_encode_flags(bo, pat_index);
+}
diff --git a/drivers/gpu/drm/xe/xe_ggtt.h b/drivers/gpu/drm/xe/xe_ggtt.h
index c48da99908848..437ba65f33860 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.h
+++ b/drivers/gpu/drm/xe/xe_ggtt.h
@@ -49,4 +49,6 @@ static inline void xe_ggtt_might_lock(struct xe_ggtt *ggtt)
void xe_ggtt_might_lock(struct xe_ggtt *ggtt);
#endif
+u64 xe_ggtt_encode_pte_flags(struct xe_ggtt *ggtt, struct xe_bo *bo, u16 pat_index);
+
#endif
--
2.45.2
next prev parent reply other threads:[~2025-04-04 20:51 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-04 20:51 [CI 00/13] Offload GGTT binding to migration engine Maarten Lankhorst
2025-04-04 20:51 ` [CI 01/13] drm/xe: Use xe_ggtt_map_bo_unlocked for resume Maarten Lankhorst
2025-04-04 20:51 ` [CI 02/13] drm/xe: Add xe_ggtt_might_lock Maarten Lankhorst
2025-04-04 20:51 ` [CI 03/13] drm/xe: Add xe_ggtt_alloc Maarten Lankhorst
2025-04-04 20:51 ` [CI 04/13] drm/xe/display: Remove dereferences of ggtt for tile id Maarten Lankhorst
2025-04-04 20:51 ` [CI 05/13] drm/xe/ggtt: Seperate flags and address in PTE encoding Maarten Lankhorst
2025-04-04 20:51 ` Maarten Lankhorst [this message]
2025-04-04 20:51 ` [CI 07/13] drm/xe/display: Convert GGTT mapping to use pte_encode_flags Maarten Lankhorst
2025-04-04 20:51 ` [CI 08/13] drm/xe: Remove pte_encode_bo callback Maarten Lankhorst
2025-04-04 20:51 ` [CI 09/13] drm/xe: Implement a helper for reading out a GGTT PTE at a specified offset Maarten Lankhorst
2025-04-04 20:51 ` [CI 10/13] drm/xe: Add GGTT updates to migration engine Maarten Lankhorst
2025-04-04 20:51 ` [CI 11/13] drm/xe: Convert xe_fb_pin to use a callback for insertion into GGTT Maarten Lankhorst
2025-04-04 20:51 ` [CI 12/13] drm/xe: Allow for optimization of xe_ggtt_map_bo Maarten Lankhorst
2025-04-04 20:51 ` [CI 13/13] drm/xe: Move struct xe_ggtt to xe_ggtt.c Maarten Lankhorst
2025-04-04 22:20 ` ✓ CI.Patch_applied: success for Offload GGTT binding to migration engine Patchwork
2025-04-04 22:20 ` ✗ CI.checkpatch: warning " Patchwork
2025-04-04 22:21 ` ✗ CI.KUnit: failure " Patchwork
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