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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: [PATCH v4 06/21] drm/i915/dsb: Disable the GOSUB interrupt
Date: Mon,  9 Jun 2025 17:10:31 +0300	[thread overview]
Message-ID: <20250609141046.6244-7-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20250609141046.6244-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Current DSB hardware is apparently a bit borked and likes to signal
spurious GOSUB errors. We already have most for the workarounds for
this in place, but the last part is simply not enabling the corresponding
interrupt.

While at it polish up the w/a comments with the w/a number,
and consistently take the short blurp from the w/a page.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 6fdd324615e2..f60a6698419c 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -555,8 +555,8 @@ static void intel_dsb_gosub_align(struct intel_dsb *dsb)
 	aligned_tail = ALIGN(tail, CACHELINE_BYTES);
 
 	/*
-	 * "The GOSUB instruction cannot be placed in
-	 *  cacheline QW slot 6 or 7 (numbered 0-7)"
+	 * Wa_16024917128
+	 * "Ensure GOSUB is not placed in cacheline QW slot 6 or 7 (numbered 0-7)"
 	 */
 	if (aligned_tail - tail <= 2 * 8)
 		intel_dsb_buffer_memset(&dsb->dsb_buf, dsb->free_pos, 0,
@@ -619,8 +619,8 @@ void intel_dsb_gosub_finish(struct intel_dsb *dsb)
 	intel_dsb_align_tail(dsb);
 
 	/*
-	 * "All subroutines called by the GOSUB instruction
-	 *  must end with a cacheline of NOPs"
+	 * Wa_16024917128
+	 * "Ensure that all subroutines called by GOSUB end with a cacheline of NOPs"
 	 */
 	intel_dsb_noop(dsb, 8);
 
@@ -668,7 +668,11 @@ static u32 dsb_error_int_en(struct intel_display *display)
 	if (DISPLAY_VER(display) >= 14)
 		errors |= DSB_ATS_FAULT_INT_EN;
 
-	if (DISPLAY_VER(display) >= 30)
+	/*
+	 * Wa_16024917128
+	 * "Disable nested GOSUB interrupt (DSB_INTERRUPT bit 21)"
+	 */
+	if (0 && DISPLAY_VER(display) >= 30)
 		errors |= DSB_GOSUB_INT_EN;
 
 	return errors;
-- 
2.49.0


  parent reply	other threads:[~2025-06-09 14:11 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-09 14:10 [PATCH v4 00/21] drm/i915/flipq: Rough flip queue implementation Ville Syrjala
2025-06-09 14:10 ` [PATCH v4 01/21] drm/i915/dsb: Use intel_dsb_ins_align() in intel_dsb_align_tail() Ville Syrjala
2025-06-10 21:24   ` Shankar, Uma
2025-06-09 14:10 ` [PATCH v4 02/21] drm/i915/dsb: Provide intel_dsb_head() and intel_dsb_size() Ville Syrjala
2025-06-10 21:28   ` Shankar, Uma
2025-06-09 14:10 ` [PATCH v4 03/21] drm/i915/dsb: Introduce intel_dsb_exec_time_us() Ville Syrjala
2025-06-10 21:32   ` Shankar, Uma
2025-06-09 14:10 ` [PATCH v4 04/21] drm/i915/dsb: Garbage collect the MMIO DEwake stuff Ville Syrjala
2025-06-10 21:41   ` Shankar, Uma
2025-06-09 14:10 ` [PATCH v4 05/21] drm/i915/dsb: Move the DSB_PMCTRL* reset out of intel_dsb_finish() Ville Syrjala
2025-06-10 21:50   ` Shankar, Uma
2025-06-09 14:10 ` Ville Syrjala [this message]
2025-06-10 21:53   ` [PATCH v4 06/21] drm/i915/dsb: Disable the GOSUB interrupt Shankar, Uma
2025-06-09 14:10 ` [PATCH v4 07/21] drm/i915/dmc: Limit PIPEDMC clock gating w/a to just ADL/DG2/MTL Ville Syrjala
2025-06-10 22:06   ` Shankar, Uma
2025-06-11 13:30     ` Ville Syrjälä
2025-06-12  5:12       ` Shankar, Uma
2025-06-09 14:10 ` [PATCH v4 08/21] drm/i915/dmc: Parametrize MTL_PIPEDMC_GATING_DIS Ville Syrjala
2025-06-10 22:07   ` Shankar, Uma
2025-06-09 14:10 ` [PATCH v4 09/21] drm/i915: Set PKG_C_LATENCY.added_wake_time to 0 Ville Syrjala
2025-06-10 22:18   ` Shankar, Uma
2025-06-09 14:10 ` [PATCH v4 10/21] drm/i915: Try to program PKG_C_LATENCY more correctly Ville Syrjala
2025-06-09 14:10 ` [PATCH v4 11/21] drm/i915/dmc: Shuffle code around Ville Syrjala
2025-06-10 22:20   ` Shankar, Uma
2025-06-09 14:10 ` [PATCH v4 12/21] drm/i915/dmc: Reload PIPEDMC MMIO registers for pipe C/D on PTL+ Ville Syrjala
2025-06-10 23:24   ` Shankar, Uma
2025-06-11 14:25     ` Ville Syrjälä
2025-06-12  5:05       ` Shankar, Uma
2025-06-09 14:10 ` [PATCH v4 13/21] drm/i915/dmc: Assert DMC is loaded harder Ville Syrjala
2025-06-09 14:10 ` [PATCH v4 14/21] drm/i915/dmc: Define flip queue related PIPEDMC registers Ville Syrjala
2025-06-19  7:29   ` Shankar, Uma
2025-06-09 14:10 ` [PATCH v4 15/21] drm/i915/flipq: Provide the nuts and bolts code for flip queue Ville Syrjala
2025-06-23 19:54   ` Shankar, Uma
2025-06-09 14:10 ` [PATCH v4 16/21] drm/i915/flipq: Implement flip queue based commit path Ville Syrjala
2025-06-23 19:58   ` Shankar, Uma
2025-06-09 14:10 ` [PATCH v4 17/21] drm/i915/flipq: Implement Wa_18034343758 Ville Syrjala
2025-06-23 20:05   ` Shankar, Uma
2025-06-09 14:10 ` [PATCH v4 18/21] drm/i915/flipq: Implement Wa_16018781658 for LNL-A0 Ville Syrjala
2025-06-23 20:08   ` Shankar, Uma
2025-06-09 14:10 ` [PATCH v4 19/21] drm/i915/flipq: Add intel_flipq_dump() Ville Syrjala
2025-06-23 20:09   ` Shankar, Uma
2025-06-09 14:10 ` [PATCH v4 20/21] drm/i915/flipq: Enable flipq by default for testing Ville Syrjala
2025-06-09 14:10 ` [PATCH v4 21/21] drm/i915/flipq: Disable PSR for extra flip queue coverage Ville Syrjala
2025-06-09 19:22 ` ✓ CI.Patch_applied: success for drm/i915/flipq: Rough flip queue implementation (rev6) Patchwork
2025-06-09 19:23 ` ✗ CI.checkpatch: warning " Patchwork
2025-06-09 19:24 ` ✓ CI.KUnit: success " Patchwork
2025-06-09 19:35 ` ✓ CI.Build: " Patchwork
2025-06-09 19:37 ` ✓ CI.Hooks: " Patchwork
2025-06-09 19:39 ` ✗ CI.checksparse: warning " Patchwork
2025-06-09 20:01 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-06-09 21:50 ` ✗ Xe.CI.Full: " Patchwork

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