From: Matt Roper <matthew.d.roper@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: matthew.d.roper@intel.com
Subject: [PATCH 0/5] Future-proof for multi-tile + multi-GT cases
Date: Thu, 12 Jun 2025 17:14:39 -0700 [thread overview]
Message-ID: <20250613001438.678728-7-matthew.d.roper@intel.com> (raw)
Today all of our platforms fall into one of three cases:
* Single tile platforms with a single (primary) GT
* Single tile platforms with two GTs (primary + media)
* Two-tile platforms with a single GT (primary) in each
Our numbering of GTs has been a bit inconsistent between platforms
(e.g., GT1 is the media GT on some platforms, but the second tile's
primary GT on others). In the future we'll likely have platforms that
are both multi-tile and multi-GT, which will make the situation more
confusing. We could also wind up with more than just two types of GTs
at some point in the future.
Going forward we should standardize the way we assign uapi GT IDs to
internal GT structures. Let's declare that for userspace GT ID n,
GT[n]'s tile = n / (max gt per tile)
GT[n]'s slot within tile = n % (max gt per tile)
If we allow 'max gt per tile' to vary by platform, we can support any
possible future tile/GT combinations (even if new types of GTs show up)
without changing any behavior of our existing platforms.
Matt Roper (5):
drm/xe: Export xe_step_name for kunit tests
drm/xe: Track maximum GTs per tile on a per-platform basis
drm/xe/tests/pci: Ensure all platforms have a valid GT/tile count
drm/xe: Assign GT IDs properly on multi-tile + multi-GT platforms
drm/xe: Don't compare GT ID to GT count when determining valid GTs
drivers/gpu/drm/xe/tests/xe_pci.c | 24 +++++++++
drivers/gpu/drm/xe/tests/xe_pci_test.c | 15 ++++++
drivers/gpu/drm/xe/tests/xe_pci_test.h | 3 ++
drivers/gpu/drm/xe/xe_device.h | 47 ++++++++----------
drivers/gpu/drm/xe/xe_device_types.h | 2 +
drivers/gpu/drm/xe/xe_eu_stall.c | 6 ++-
drivers/gpu/drm/xe/xe_exec_queue.c | 2 +-
drivers/gpu/drm/xe/xe_hw_engine.c | 3 +-
drivers/gpu/drm/xe/xe_mmio.c | 8 ---
drivers/gpu/drm/xe/xe_pci.c | 68 ++++++++------------------
drivers/gpu/drm/xe/xe_pci_types.h | 40 +++++++++++++++
drivers/gpu/drm/xe/xe_pmu.c | 4 +-
drivers/gpu/drm/xe/xe_query.c | 2 +-
drivers/gpu/drm/xe/xe_step.c | 2 +
14 files changed, 138 insertions(+), 88 deletions(-)
--
2.49.0
next reply other threads:[~2025-06-13 0:14 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-13 0:14 Matt Roper [this message]
2025-06-13 0:14 ` [PATCH 1/5] drm/xe: Export xe_step_name for kunit tests Matt Roper
2025-06-13 15:52 ` Michal Wajdeczko
2025-06-13 0:14 ` [PATCH 2/5] drm/xe: Track maximum GTs per tile on a per-platform basis Matt Roper
2025-06-13 20:32 ` Lucas De Marchi
2025-06-13 0:14 ` [PATCH 3/5] drm/xe/tests/pci: Ensure all platforms have a valid GT/tile count Matt Roper
2025-06-13 17:59 ` Michal Wajdeczko
2025-06-13 19:21 ` Michal Wajdeczko
2025-06-13 0:14 ` [PATCH 4/5] drm/xe: Assign GT IDs properly on multi-tile + multi-GT platforms Matt Roper
2025-06-13 0:14 ` [PATCH 5/5] drm/xe: Don't compare GT ID to GT count when determining valid GTs Matt Roper
2025-06-13 7:36 ` ✗ CI.checkpatch: warning for Future-proof for multi-tile + multi-GT cases Patchwork
2025-06-13 7:37 ` ✗ CI.KUnit: failure " Patchwork
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