[PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target

[PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

The GuC has an option to write log data via NPK. This is basically a
magic IO address that GuC writes arbitrary data to and which can be
logged by a suitable hardware logger. This can allow retrieval of the
GuC log in hardware debug environments even when the system as a whole
dies horribly.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 drivers/gpu/drm/xe/xe_guc.c    | 4 ++++
 drivers/gpu/drm/xe/xe_module.c | 4 ++++
 drivers/gpu/drm/xe/xe_module.h | 1 +
 3 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index e16d19b44bcc..9c0e3113f7d5 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -35,6 +35,7 @@
 #include "xe_guc_submit.h"
 #include "xe_memirq.h"
 #include "xe_mmio.h"
+#include "xe_module.h"
 #include "xe_platform_types.h"
 #include "xe_sriov.h"
 #include "xe_uc.h"
@@ -74,6 +75,9 @@ static u32 guc_ctl_debug_flags(struct xe_guc *guc)
 	else
 		flags |= FIELD_PREP(GUC_LOG_VERBOSITY, GUC_LOG_LEVEL_TO_VERBOSITY(level));
 
+	if (xe_modparam.guc_log_target)
+		flags |= FIELD_PREP(GUC_LOG_DESTINATION, xe_modparam.guc_log_target);
+
 	return flags;
 }
 
diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
index 1c4dfafbcd0b..fc8c681819b9 100644
--- a/drivers/gpu/drm/xe/xe_module.c
+++ b/drivers/gpu/drm/xe/xe_module.c
@@ -21,6 +21,7 @@
 struct xe_modparam xe_modparam = {
 	.probe_display = true,
 	.guc_log_level = 3,
+	.guc_log_target = 0,
 	.force_probe = CONFIG_DRM_XE_FORCE_PROBE,
 #ifdef CONFIG_PCI_IOV
 	.max_vfs = IS_ENABLED(CONFIG_DRM_XE_DEBUG) ? ~0 : 0,
@@ -45,6 +46,9 @@ MODULE_PARM_DESC(vram_bar_size, "Set the vram bar size (in MiB) - <0=disable-res
 module_param_named(guc_log_level, xe_modparam.guc_log_level, int, 0600);
 MODULE_PARM_DESC(guc_log_level, "GuC firmware logging level (0=disable, 1..5=enable with verbosity min..max)");
 
+module_param_named(guc_log_target, xe_modparam.guc_log_target, int, 0600);
+MODULE_PARM_DESC(guc_log_target, "GuC firmware logging target (0=memory [default], 1 = NPK, 2 = memory + NPK)");
+
 module_param_named_unsafe(guc_firmware_path, xe_modparam.guc_firmware_path, charp, 0400);
 MODULE_PARM_DESC(guc_firmware_path,
 		 "GuC firmware path to use instead of the default one");
diff --git a/drivers/gpu/drm/xe/xe_module.h b/drivers/gpu/drm/xe/xe_module.h
index 5a3bfea8b7b4..4d978f6f26b6 100644
--- a/drivers/gpu/drm/xe/xe_module.h
+++ b/drivers/gpu/drm/xe/xe_module.h
@@ -14,6 +14,7 @@ struct xe_modparam {
 	bool probe_display;
 	u32 force_vram_bar_size;
 	int guc_log_level;
+	int guc_log_target;
 	char *guc_firmware_path;
 	char *huc_firmware_path;
 	char *gsc_firmware_path;
-- 
2.49.0

Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target

[Lucas De Marchi]

On Wed, Jun 11, 2025 at 02:05:53PM -0700, John.C.Harrison@Intel.com wrote:
>From: John Harrison <John.C.Harrison@Intel.com>
>
>The GuC has an option to write log data via NPK. This is basically a
>magic IO address that GuC writes arbitrary data to and which can be
>logged by a suitable hardware logger. This can allow retrieval of the
>GuC log in hardware debug environments even when the system as a whole
>dies horribly.
>
>Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>---
> drivers/gpu/drm/xe/xe_guc.c    | 4 ++++
> drivers/gpu/drm/xe/xe_module.c | 4 ++++
> drivers/gpu/drm/xe/xe_module.h | 1 +
> 3 files changed, 9 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>index e16d19b44bcc..9c0e3113f7d5 100644
>--- a/drivers/gpu/drm/xe/xe_guc.c
>+++ b/drivers/gpu/drm/xe/xe_guc.c
>@@ -35,6 +35,7 @@
> #include "xe_guc_submit.h"
> #include "xe_memirq.h"
> #include "xe_mmio.h"
>+#include "xe_module.h"
> #include "xe_platform_types.h"
> #include "xe_sriov.h"
> #include "xe_uc.h"
>@@ -74,6 +75,9 @@ static u32 guc_ctl_debug_flags(struct xe_guc *guc)
> 	else
> 		flags |= FIELD_PREP(GUC_LOG_VERBOSITY, GUC_LOG_LEVEL_TO_VERBOSITY(level));
>
>+	if (xe_modparam.guc_log_target)
>+		flags |= FIELD_PREP(GUC_LOG_DESTINATION, xe_modparam.guc_log_target);

is this supported across the board for all platforms and firmware
versions? Otherwise, what'd happen if you have and old igfx and you are
debugging a new dgfx? or vice-versa.

We should probably need to sanitize the user input here?

Lucas De Marchi

>+
> 	return flags;
> }
>
>diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
>index 1c4dfafbcd0b..fc8c681819b9 100644
>--- a/drivers/gpu/drm/xe/xe_module.c
>+++ b/drivers/gpu/drm/xe/xe_module.c
>@@ -21,6 +21,7 @@
> struct xe_modparam xe_modparam = {
> 	.probe_display = true,
> 	.guc_log_level = 3,
>+	.guc_log_target = 0,
> 	.force_probe = CONFIG_DRM_XE_FORCE_PROBE,
> #ifdef CONFIG_PCI_IOV
> 	.max_vfs = IS_ENABLED(CONFIG_DRM_XE_DEBUG) ? ~0 : 0,
>@@ -45,6 +46,9 @@ MODULE_PARM_DESC(vram_bar_size, "Set the vram bar size (in MiB) - <0=disable-res
> module_param_named(guc_log_level, xe_modparam.guc_log_level, int, 0600);
> MODULE_PARM_DESC(guc_log_level, "GuC firmware logging level (0=disable, 1..5=enable with verbosity min..max)");
>
>+module_param_named(guc_log_target, xe_modparam.guc_log_target, int, 0600);
>+MODULE_PARM_DESC(guc_log_target, "GuC firmware logging target (0=memory [default], 1 = NPK, 2 = memory + NPK)");
>+
> module_param_named_unsafe(guc_firmware_path, xe_modparam.guc_firmware_path, charp, 0400);
> MODULE_PARM_DESC(guc_firmware_path,
> 		 "GuC firmware path to use instead of the default one");
>diff --git a/drivers/gpu/drm/xe/xe_module.h b/drivers/gpu/drm/xe/xe_module.h
>index 5a3bfea8b7b4..4d978f6f26b6 100644
>--- a/drivers/gpu/drm/xe/xe_module.h
>+++ b/drivers/gpu/drm/xe/xe_module.h
>@@ -14,6 +14,7 @@ struct xe_modparam {
> 	bool probe_display;
> 	u32 force_vram_bar_size;
> 	int guc_log_level;
>+	int guc_log_target;
> 	char *guc_firmware_path;
> 	char *huc_firmware_path;
> 	char *gsc_firmware_path;
>-- 
>2.49.0
>

RE: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target

[Cavitt, Jonathan]

-----Original Message-----
From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of John.C.Harrison@Intel.com
Sent: Wednesday, June 11, 2025 2:06 PM
To: Intel-Xe@Lists.FreeDesktop.Org
Cc: Harrison, John C <john.c.harrison@intel.com>
Subject: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target
> 
> From: John Harrison <John.C.Harrison@Intel.com>
> 
> The GuC has an option to write log data via NPK. This is basically a
> magic IO address that GuC writes arbitrary data to and which can be
> logged by a suitable hardware logger. This can allow retrieval of the
> GuC log in hardware debug environments even when the system as a whole
> dies horribly.
> 
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>

So, this is basically a new modparam value that redirects GuC logs to
a specific IO address?  I take it guc_log_target = 2 is the default value, and
guc_log_target = 1 would print the logs to stdout, then?  I'd ask why we
use 0 as a default value and not just default to 2 all the time, but I think I
already know why (we need to guard against guc_log_target = 0 anyways
to prevent printing to stdin).

I also take it this is modified on boot by, for example, writing
"xe.guc_log_target=1" to CMDLINE_LINUX_DEFAULT as a part of the grub file.

Yeah, seems good.
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
-Jonathan Cavitt

> ---
>  drivers/gpu/drm/xe/xe_guc.c    | 4 ++++
>  drivers/gpu/drm/xe/xe_module.c | 4 ++++
>  drivers/gpu/drm/xe/xe_module.h | 1 +
>  3 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index e16d19b44bcc..9c0e3113f7d5 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -35,6 +35,7 @@
>  #include "xe_guc_submit.h"
>  #include "xe_memirq.h"
>  #include "xe_mmio.h"
> +#include "xe_module.h"
>  #include "xe_platform_types.h"
>  #include "xe_sriov.h"
>  #include "xe_uc.h"
> @@ -74,6 +75,9 @@ static u32 guc_ctl_debug_flags(struct xe_guc *guc)
>  	else
>  		flags |= FIELD_PREP(GUC_LOG_VERBOSITY, GUC_LOG_LEVEL_TO_VERBOSITY(level));
>  
> +	if (xe_modparam.guc_log_target)
> +		flags |= FIELD_PREP(GUC_LOG_DESTINATION, xe_modparam.guc_log_target);
> +
>  	return flags;
>  }
>  
> diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
> index 1c4dfafbcd0b..fc8c681819b9 100644
> --- a/drivers/gpu/drm/xe/xe_module.c
> +++ b/drivers/gpu/drm/xe/xe_module.c
> @@ -21,6 +21,7 @@
>  struct xe_modparam xe_modparam = {
>  	.probe_display = true,
>  	.guc_log_level = 3,
> +	.guc_log_target = 0,
>  	.force_probe = CONFIG_DRM_XE_FORCE_PROBE,
>  #ifdef CONFIG_PCI_IOV
>  	.max_vfs = IS_ENABLED(CONFIG_DRM_XE_DEBUG) ? ~0 : 0,
> @@ -45,6 +46,9 @@ MODULE_PARM_DESC(vram_bar_size, "Set the vram bar size (in MiB) - <0=disable-res
>  module_param_named(guc_log_level, xe_modparam.guc_log_level, int, 0600);
>  MODULE_PARM_DESC(guc_log_level, "GuC firmware logging level (0=disable, 1..5=enable with verbosity min..max)");
>  
> +module_param_named(guc_log_target, xe_modparam.guc_log_target, int, 0600);
> +MODULE_PARM_DESC(guc_log_target, "GuC firmware logging target (0=memory [default], 1 = NPK, 2 = memory + NPK)");
> +
>  module_param_named_unsafe(guc_firmware_path, xe_modparam.guc_firmware_path, charp, 0400);
>  MODULE_PARM_DESC(guc_firmware_path,
>  		 "GuC firmware path to use instead of the default one");
> diff --git a/drivers/gpu/drm/xe/xe_module.h b/drivers/gpu/drm/xe/xe_module.h
> index 5a3bfea8b7b4..4d978f6f26b6 100644
> --- a/drivers/gpu/drm/xe/xe_module.h
> +++ b/drivers/gpu/drm/xe/xe_module.h
> @@ -14,6 +14,7 @@ struct xe_modparam {
>  	bool probe_display;
>  	u32 force_vram_bar_size;
>  	int guc_log_level;
> +	int guc_log_target;
>  	char *guc_firmware_path;
>  	char *huc_firmware_path;
>  	char *gsc_firmware_path;
> -- 
> 2.49.0
> 
> 

Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target

[John Harrison]

On 6/11/2025 2:49 PM, Lucas De Marchi wrote:
> On Wed, Jun 11, 2025 at 02:05:53PM -0700, John.C.Harrison@Intel.com 
> wrote:
>> From: John Harrison <John.C.Harrison@Intel.com>
>>
>> The GuC has an option to write log data via NPK. This is basically a
>> magic IO address that GuC writes arbitrary data to and which can be
>> logged by a suitable hardware logger. This can allow retrieval of the
>> GuC log in hardware debug environments even when the system as a whole
>> dies horribly.
>>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_guc.c    | 4 ++++
>> drivers/gpu/drm/xe/xe_module.c | 4 ++++
>> drivers/gpu/drm/xe/xe_module.h | 1 +
>> 3 files changed, 9 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>> index e16d19b44bcc..9c0e3113f7d5 100644
>> --- a/drivers/gpu/drm/xe/xe_guc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>> @@ -35,6 +35,7 @@
>> #include "xe_guc_submit.h"
>> #include "xe_memirq.h"
>> #include "xe_mmio.h"
>> +#include "xe_module.h"
>> #include "xe_platform_types.h"
>> #include "xe_sriov.h"
>> #include "xe_uc.h"
>> @@ -74,6 +75,9 @@ static u32 guc_ctl_debug_flags(struct xe_guc *guc)
>>     else
>>         flags |= FIELD_PREP(GUC_LOG_VERBOSITY, 
>> GUC_LOG_LEVEL_TO_VERBOSITY(level));
>>
>> +    if (xe_modparam.guc_log_target)
>> +        flags |= FIELD_PREP(GUC_LOG_DESTINATION, 
>> xe_modparam.guc_log_target);
>
> is this supported across the board for all platforms and firmware
> versions? Otherwise, what'd happen if you have and old igfx and you are
> debugging a new dgfx? or vice-versa.
All platforms that have a GuC and all firmware builds that have been 
supported under Linux. North PeaK is part of the host chipset not the 
GuC or GT.

>
> We should probably need to sanitize the user input here?
Doesn't FIELD_PREP do that already? It will ensure the value written 
does not overflow the field. And if the user is setting a dumb value 
then that's their problem. It will have no effect beyond where the GuC 
log goes.

John.

>
> Lucas De Marchi
>
>> +
>>     return flags;
>> }
>>
>> diff --git a/drivers/gpu/drm/xe/xe_module.c 
>> b/drivers/gpu/drm/xe/xe_module.c
>> index 1c4dfafbcd0b..fc8c681819b9 100644
>> --- a/drivers/gpu/drm/xe/xe_module.c
>> +++ b/drivers/gpu/drm/xe/xe_module.c
>> @@ -21,6 +21,7 @@
>> struct xe_modparam xe_modparam = {
>>     .probe_display = true,
>>     .guc_log_level = 3,
>> +    .guc_log_target = 0,
>>     .force_probe = CONFIG_DRM_XE_FORCE_PROBE,
>> #ifdef CONFIG_PCI_IOV
>>     .max_vfs = IS_ENABLED(CONFIG_DRM_XE_DEBUG) ? ~0 : 0,
>> @@ -45,6 +46,9 @@ MODULE_PARM_DESC(vram_bar_size, "Set the vram bar 
>> size (in MiB) - <0=disable-res
>> module_param_named(guc_log_level, xe_modparam.guc_log_level, int, 0600);
>> MODULE_PARM_DESC(guc_log_level, "GuC firmware logging level 
>> (0=disable, 1..5=enable with verbosity min..max)");
>>
>> +module_param_named(guc_log_target, xe_modparam.guc_log_target, int, 
>> 0600);
>> +MODULE_PARM_DESC(guc_log_target, "GuC firmware logging target 
>> (0=memory [default], 1 = NPK, 2 = memory + NPK)");
>> +
>> module_param_named_unsafe(guc_firmware_path, 
>> xe_modparam.guc_firmware_path, charp, 0400);
>> MODULE_PARM_DESC(guc_firmware_path,
>>          "GuC firmware path to use instead of the default one");
>> diff --git a/drivers/gpu/drm/xe/xe_module.h 
>> b/drivers/gpu/drm/xe/xe_module.h
>> index 5a3bfea8b7b4..4d978f6f26b6 100644
>> --- a/drivers/gpu/drm/xe/xe_module.h
>> +++ b/drivers/gpu/drm/xe/xe_module.h
>> @@ -14,6 +14,7 @@ struct xe_modparam {
>>     bool probe_display;
>>     u32 force_vram_bar_size;
>>     int guc_log_level;
>> +    int guc_log_target;
>>     char *guc_firmware_path;
>>     char *huc_firmware_path;
>>     char *gsc_firmware_path;
>> -- 
>> 2.49.0
>>

Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target

[John Harrison]

On 6/11/2025 3:04 PM, Cavitt, Jonathan wrote:
> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of John.C.Harrison@Intel.com
> Sent: Wednesday, June 11, 2025 2:06 PM
> To: Intel-Xe@Lists.FreeDesktop.Org
> Cc: Harrison, John C <john.c.harrison@intel.com>
> Subject: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target
>> From: John Harrison <John.C.Harrison@Intel.com>
>>
>> The GuC has an option to write log data via NPK. This is basically a
>> magic IO address that GuC writes arbitrary data to and which can be
>> logged by a suitable hardware logger. This can allow retrieval of the
>> GuC log in hardware debug environments even when the system as a whole
>> dies horribly.
>>
>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> So, this is basically a new modparam value that redirects GuC logs to
> a specific IO address?  I take it guc_log_target = 2 is the default value, and
> guc_log_target = 1 would print the logs to stdout, then?  I'd ask why we
> use 0 as a default value and not just default to 2 all the time, but I think I
> already know why (we need to guard against guc_log_target = 0 anyways
> to prevent printing to stdin).
Um, read the patch - "(0=memory [default], 1 = NPK, 2 = memory + NPK)". 
The default is zero. And no, nothing prints to stdout. This is about 
hardware level debugging. It has nothing to do with stdin/stdout/stderr. 
Those concepts do not exist in hardware nor in the KMD. If you send the 
GuC log to the NPK target then you need a hardware debugger (JTAG, etc.) 
to read it, as described in the commit message.

>
> I also take it this is modified on boot by, for example, writing
> "xe.guc_log_target=1" to CMDLINE_LINUX_DEFAULT as a part of the grub file.
That is generally how module parameters work. You can also set via 
modprobe.conf files as long as the Xe driver is a module and not 
compiled in.

John.

>
> Yeah, seems good.
> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> -Jonathan Cavitt
>
>> ---
>>   drivers/gpu/drm/xe/xe_guc.c    | 4 ++++
>>   drivers/gpu/drm/xe/xe_module.c | 4 ++++
>>   drivers/gpu/drm/xe/xe_module.h | 1 +
>>   3 files changed, 9 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>> index e16d19b44bcc..9c0e3113f7d5 100644
>> --- a/drivers/gpu/drm/xe/xe_guc.c
>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>> @@ -35,6 +35,7 @@
>>   #include "xe_guc_submit.h"
>>   #include "xe_memirq.h"
>>   #include "xe_mmio.h"
>> +#include "xe_module.h"
>>   #include "xe_platform_types.h"
>>   #include "xe_sriov.h"
>>   #include "xe_uc.h"
>> @@ -74,6 +75,9 @@ static u32 guc_ctl_debug_flags(struct xe_guc *guc)
>>   	else
>>   		flags |= FIELD_PREP(GUC_LOG_VERBOSITY, GUC_LOG_LEVEL_TO_VERBOSITY(level));
>>   
>> +	if (xe_modparam.guc_log_target)
>> +		flags |= FIELD_PREP(GUC_LOG_DESTINATION, xe_modparam.guc_log_target);
>> +
>>   	return flags;
>>   }
>>   
>> diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
>> index 1c4dfafbcd0b..fc8c681819b9 100644
>> --- a/drivers/gpu/drm/xe/xe_module.c
>> +++ b/drivers/gpu/drm/xe/xe_module.c
>> @@ -21,6 +21,7 @@
>>   struct xe_modparam xe_modparam = {
>>   	.probe_display = true,
>>   	.guc_log_level = 3,
>> +	.guc_log_target = 0,
>>   	.force_probe = CONFIG_DRM_XE_FORCE_PROBE,
>>   #ifdef CONFIG_PCI_IOV
>>   	.max_vfs = IS_ENABLED(CONFIG_DRM_XE_DEBUG) ? ~0 : 0,
>> @@ -45,6 +46,9 @@ MODULE_PARM_DESC(vram_bar_size, "Set the vram bar size (in MiB) - <0=disable-res
>>   module_param_named(guc_log_level, xe_modparam.guc_log_level, int, 0600);
>>   MODULE_PARM_DESC(guc_log_level, "GuC firmware logging level (0=disable, 1..5=enable with verbosity min..max)");
>>   
>> +module_param_named(guc_log_target, xe_modparam.guc_log_target, int, 0600);
>> +MODULE_PARM_DESC(guc_log_target, "GuC firmware logging target (0=memory [default], 1 = NPK, 2 = memory + NPK)");
>> +
>>   module_param_named_unsafe(guc_firmware_path, xe_modparam.guc_firmware_path, charp, 0400);
>>   MODULE_PARM_DESC(guc_firmware_path,
>>   		 "GuC firmware path to use instead of the default one");
>> diff --git a/drivers/gpu/drm/xe/xe_module.h b/drivers/gpu/drm/xe/xe_module.h
>> index 5a3bfea8b7b4..4d978f6f26b6 100644
>> --- a/drivers/gpu/drm/xe/xe_module.h
>> +++ b/drivers/gpu/drm/xe/xe_module.h
>> @@ -14,6 +14,7 @@ struct xe_modparam {
>>   	bool probe_display;
>>   	u32 force_vram_bar_size;
>>   	int guc_log_level;
>> +	int guc_log_target;
>>   	char *guc_firmware_path;
>>   	char *huc_firmware_path;
>>   	char *gsc_firmware_path;
>> -- 
>> 2.49.0
>>
>>

RE: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target

[Cavitt, Jonathan]

-----Original Message-----
From: Harrison, John C <john.c.harrison@intel.com> 
Sent: Wednesday, June 11, 2025 4:57 PM
To: Cavitt, Jonathan <jonathan.cavitt@intel.com>; Intel-Xe@Lists.FreeDesktop.Org
Subject: Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target
> 
> On 6/11/2025 3:04 PM, Cavitt, Jonathan wrote:
> > -----Original Message-----
> > From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of John.C.Harrison@Intel.com
> > Sent: Wednesday, June 11, 2025 2:06 PM
> > To: Intel-Xe@Lists.FreeDesktop.Org
> > Cc: Harrison, John C <john.c.harrison@intel.com>
> > Subject: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target
> >> From: John Harrison <John.C.Harrison@Intel.com>
> >>
> >> The GuC has an option to write log data via NPK. This is basically a
> >> magic IO address that GuC writes arbitrary data to and which can be
> >> logged by a suitable hardware logger. This can allow retrieval of the
> >> GuC log in hardware debug environments even when the system as a whole
> >> dies horribly.
> >>
> >> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> > So, this is basically a new modparam value that redirects GuC logs to
> > a specific IO address?  I take it guc_log_target = 2 is the default value, and
> > guc_log_target = 1 would print the logs to stdout, then?  I'd ask why we
> > use 0 as a default value and not just default to 2 all the time, but I think I
> > already know why (we need to guard against guc_log_target = 0 anyways
> > to prevent printing to stdin).
> Um, read the patch - "(0=memory [default], 1 = NPK, 2 = memory + NPK)". 
> The default is zero. And no, nothing prints to stdout. This is about 
> hardware level debugging. It has nothing to do with stdin/stdout/stderr. 
> Those concepts do not exist in hardware nor in the KMD. If you send the 
> GuC log to the NPK target then you need a hardware debugger (JTAG, etc.) 
> to read it, as described in the commit message.

Ah, okay.  When I read "This is basically a magic IO address that GuC writes
arbitrary data to", I thought that was indicating that we're writing to the
in/out/err IO addresses, and that the data being logged "by a suitable
hardware logger" was occurring separately.  I guess I also thought NPK
was a writing protocol and not a hardware address.

It didn't occur to me that we'd need to directly write the logs to the
hardware logger in cases of catastrophic failure because we already have
methods of streaming the logs directly via the serial ports.  Though I
suppose that we're talking about different "logs" at this point?

The reviewed-by still stands.
-Jonathan Cavitt

> 
> >
> > I also take it this is modified on boot by, for example, writing
> > "xe.guc_log_target=1" to CMDLINE_LINUX_DEFAULT as a part of the grub file.
> That is generally how module parameters work. You can also set via 
> modprobe.conf files as long as the Xe driver is a module and not 
> compiled in.
> 
> John.
> 
> >
> > Yeah, seems good.
> > Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> > -Jonathan Cavitt
> >
> >> ---
> >>   drivers/gpu/drm/xe/xe_guc.c    | 4 ++++
> >>   drivers/gpu/drm/xe/xe_module.c | 4 ++++
> >>   drivers/gpu/drm/xe/xe_module.h | 1 +
> >>   3 files changed, 9 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> >> index e16d19b44bcc..9c0e3113f7d5 100644
> >> --- a/drivers/gpu/drm/xe/xe_guc.c
> >> +++ b/drivers/gpu/drm/xe/xe_guc.c
> >> @@ -35,6 +35,7 @@
> >>   #include "xe_guc_submit.h"
> >>   #include "xe_memirq.h"
> >>   #include "xe_mmio.h"
> >> +#include "xe_module.h"
> >>   #include "xe_platform_types.h"
> >>   #include "xe_sriov.h"
> >>   #include "xe_uc.h"
> >> @@ -74,6 +75,9 @@ static u32 guc_ctl_debug_flags(struct xe_guc *guc)
> >>   	else
> >>   		flags |= FIELD_PREP(GUC_LOG_VERBOSITY, GUC_LOG_LEVEL_TO_VERBOSITY(level));
> >>   
> >> +	if (xe_modparam.guc_log_target)
> >> +		flags |= FIELD_PREP(GUC_LOG_DESTINATION, xe_modparam.guc_log_target);
> >> +
> >>   	return flags;
> >>   }
> >>   
> >> diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
> >> index 1c4dfafbcd0b..fc8c681819b9 100644
> >> --- a/drivers/gpu/drm/xe/xe_module.c
> >> +++ b/drivers/gpu/drm/xe/xe_module.c
> >> @@ -21,6 +21,7 @@
> >>   struct xe_modparam xe_modparam = {
> >>   	.probe_display = true,
> >>   	.guc_log_level = 3,
> >> +	.guc_log_target = 0,
> >>   	.force_probe = CONFIG_DRM_XE_FORCE_PROBE,
> >>   #ifdef CONFIG_PCI_IOV
> >>   	.max_vfs = IS_ENABLED(CONFIG_DRM_XE_DEBUG) ? ~0 : 0,
> >> @@ -45,6 +46,9 @@ MODULE_PARM_DESC(vram_bar_size, "Set the vram bar size (in MiB) - <0=disable-res
> >>   module_param_named(guc_log_level, xe_modparam.guc_log_level, int, 0600);
> >>   MODULE_PARM_DESC(guc_log_level, "GuC firmware logging level (0=disable, 1..5=enable with verbosity min..max)");
> >>   
> >> +module_param_named(guc_log_target, xe_modparam.guc_log_target, int, 0600);
> >> +MODULE_PARM_DESC(guc_log_target, "GuC firmware logging target (0=memory [default], 1 = NPK, 2 = memory + NPK)");
> >> +
> >>   module_param_named_unsafe(guc_firmware_path, xe_modparam.guc_firmware_path, charp, 0400);
> >>   MODULE_PARM_DESC(guc_firmware_path,
> >>   		 "GuC firmware path to use instead of the default one");
> >> diff --git a/drivers/gpu/drm/xe/xe_module.h b/drivers/gpu/drm/xe/xe_module.h
> >> index 5a3bfea8b7b4..4d978f6f26b6 100644
> >> --- a/drivers/gpu/drm/xe/xe_module.h
> >> +++ b/drivers/gpu/drm/xe/xe_module.h
> >> @@ -14,6 +14,7 @@ struct xe_modparam {
> >>   	bool probe_display;
> >>   	u32 force_vram_bar_size;
> >>   	int guc_log_level;
> >> +	int guc_log_target;
> >>   	char *guc_firmware_path;
> >>   	char *huc_firmware_path;
> >>   	char *gsc_firmware_path;
> >> -- 
> >> 2.49.0
> >>
> >>
> 
> 

Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target

[John Harrison]

On 6/12/2025 7:32 AM, Cavitt, Jonathan wrote:
> -----Original Message-----
> From: Harrison, John C <john.c.harrison@intel.com>
> Sent: Wednesday, June 11, 2025 4:57 PM
> To: Cavitt, Jonathan <jonathan.cavitt@intel.com>; Intel-Xe@Lists.FreeDesktop.Org
> Subject: Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target
>> On 6/11/2025 3:04 PM, Cavitt, Jonathan wrote:
>>> -----Original Message-----
>>> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of John.C.Harrison@Intel.com
>>> Sent: Wednesday, June 11, 2025 2:06 PM
>>> To: Intel-Xe@Lists.FreeDesktop.Org
>>> Cc: Harrison, John C <john.c.harrison@intel.com>
>>> Subject: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target
>>>> From: John Harrison <John.C.Harrison@Intel.com>
>>>>
>>>> The GuC has an option to write log data via NPK. This is basically a
>>>> magic IO address that GuC writes arbitrary data to and which can be
>>>> logged by a suitable hardware logger. This can allow retrieval of the
>>>> GuC log in hardware debug environments even when the system as a whole
>>>> dies horribly.
>>>>
>>>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>> So, this is basically a new modparam value that redirects GuC logs to
>>> a specific IO address?  I take it guc_log_target = 2 is the default value, and
>>> guc_log_target = 1 would print the logs to stdout, then?  I'd ask why we
>>> use 0 as a default value and not just default to 2 all the time, but I think I
>>> already know why (we need to guard against guc_log_target = 0 anyways
>>> to prevent printing to stdin).
>> Um, read the patch - "(0=memory [default], 1 = NPK, 2 = memory + NPK)".
>> The default is zero. And no, nothing prints to stdout. This is about
>> hardware level debugging. It has nothing to do with stdin/stdout/stderr.
>> Those concepts do not exist in hardware nor in the KMD. If you send the
>> GuC log to the NPK target then you need a hardware debugger (JTAG, etc.)
>> to read it, as described in the commit message.
> Ah, okay.  When I read "This is basically a magic IO address that GuC writes
> arbitrary data to", I thought that was indicating that we're writing to the
> in/out/err IO addresses, and that the data being logged "by a suitable
You say "the in/out/err IO addresses" like there is such a thing. 
In/out/err generally refers to stdin/stdout/stderr, being the default 
first three file handles of a unix process. File handles are not IO 
addresses. Such file handles also do not exist in the kernel. And they 
absolutely do not exist inside the GT hardware. My comment was referring 
to memory mapped IO addresses, i.e. hardware registers. On a normal 
system, there is nothing connected to said hardware so the logged output 
goes nowhere. However, if you have a hardware debugger attached to the 
system then it can trap those accesses and record the log.

> hardware logger" was occurring separately.  I guess I also thought NPK
> was a writing protocol and not a hardware address.
NPK is neither a protocol nor an address. It is a block of silicon 
called North Peak, also known as the Intel Trace Hub.

>
> It didn't occur to me that we'd need to directly write the logs to the
> hardware logger in cases of catastrophic failure because we already have
> methods of streaming the logs directly via the serial ports.  Though I
> suppose that we're talking about different "logs" at this point?
I don't know what logs you are talking about. This patch is quite 
clearly only talking about the GuC log. Which is generally accessible 
via debugfs snapshots or as part of a devcoredump capture. It is not 
ever 'streamed directly via the serial ports'.

John.

>
> The reviewed-by still stands.
> -Jonathan Cavitt
>
>>> I also take it this is modified on boot by, for example, writing
>>> "xe.guc_log_target=1" to CMDLINE_LINUX_DEFAULT as a part of the grub file.
>> That is generally how module parameters work. You can also set via
>> modprobe.conf files as long as the Xe driver is a module and not
>> compiled in.
>>
>> John.
>>
>>> Yeah, seems good.
>>> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
>>> -Jonathan Cavitt
>>>
>>>> ---
>>>>    drivers/gpu/drm/xe/xe_guc.c    | 4 ++++
>>>>    drivers/gpu/drm/xe/xe_module.c | 4 ++++
>>>>    drivers/gpu/drm/xe/xe_module.h | 1 +
>>>>    3 files changed, 9 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>>>> index e16d19b44bcc..9c0e3113f7d5 100644
>>>> --- a/drivers/gpu/drm/xe/xe_guc.c
>>>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>>>> @@ -35,6 +35,7 @@
>>>>    #include "xe_guc_submit.h"
>>>>    #include "xe_memirq.h"
>>>>    #include "xe_mmio.h"
>>>> +#include "xe_module.h"
>>>>    #include "xe_platform_types.h"
>>>>    #include "xe_sriov.h"
>>>>    #include "xe_uc.h"
>>>> @@ -74,6 +75,9 @@ static u32 guc_ctl_debug_flags(struct xe_guc *guc)
>>>>    	else
>>>>    		flags |= FIELD_PREP(GUC_LOG_VERBOSITY, GUC_LOG_LEVEL_TO_VERBOSITY(level));
>>>>    
>>>> +	if (xe_modparam.guc_log_target)
>>>> +		flags |= FIELD_PREP(GUC_LOG_DESTINATION, xe_modparam.guc_log_target);
>>>> +
>>>>    	return flags;
>>>>    }
>>>>    
>>>> diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
>>>> index 1c4dfafbcd0b..fc8c681819b9 100644
>>>> --- a/drivers/gpu/drm/xe/xe_module.c
>>>> +++ b/drivers/gpu/drm/xe/xe_module.c
>>>> @@ -21,6 +21,7 @@
>>>>    struct xe_modparam xe_modparam = {
>>>>    	.probe_display = true,
>>>>    	.guc_log_level = 3,
>>>> +	.guc_log_target = 0,
>>>>    	.force_probe = CONFIG_DRM_XE_FORCE_PROBE,
>>>>    #ifdef CONFIG_PCI_IOV
>>>>    	.max_vfs = IS_ENABLED(CONFIG_DRM_XE_DEBUG) ? ~0 : 0,
>>>> @@ -45,6 +46,9 @@ MODULE_PARM_DESC(vram_bar_size, "Set the vram bar size (in MiB) - <0=disable-res
>>>>    module_param_named(guc_log_level, xe_modparam.guc_log_level, int, 0600);
>>>>    MODULE_PARM_DESC(guc_log_level, "GuC firmware logging level (0=disable, 1..5=enable with verbosity min..max)");
>>>>    
>>>> +module_param_named(guc_log_target, xe_modparam.guc_log_target, int, 0600);
>>>> +MODULE_PARM_DESC(guc_log_target, "GuC firmware logging target (0=memory [default], 1 = NPK, 2 = memory + NPK)");
>>>> +
>>>>    module_param_named_unsafe(guc_firmware_path, xe_modparam.guc_firmware_path, charp, 0400);
>>>>    MODULE_PARM_DESC(guc_firmware_path,
>>>>    		 "GuC firmware path to use instead of the default one");
>>>> diff --git a/drivers/gpu/drm/xe/xe_module.h b/drivers/gpu/drm/xe/xe_module.h
>>>> index 5a3bfea8b7b4..4d978f6f26b6 100644
>>>> --- a/drivers/gpu/drm/xe/xe_module.h
>>>> +++ b/drivers/gpu/drm/xe/xe_module.h
>>>> @@ -14,6 +14,7 @@ struct xe_modparam {
>>>>    	bool probe_display;
>>>>    	u32 force_vram_bar_size;
>>>>    	int guc_log_level;
>>>> +	int guc_log_target;
>>>>    	char *guc_firmware_path;
>>>>    	char *huc_firmware_path;
>>>>    	char *gsc_firmware_path;
>>>> -- 
>>>> 2.49.0
>>>>
>>>>
>>

RE: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target

[Cavitt, Jonathan]

----Original Message-----
From: Harrison, John C <john.c.harrison@intel.com> 
Sent: Thursday, June 12, 2025 10:50 AM
To: Cavitt, Jonathan <jonathan.cavitt@intel.com>; Intel-Xe@Lists.FreeDesktop.Org
Subject: Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target
> 
> On 6/12/2025 7:32 AM, Cavitt, Jonathan wrote:
> > -----Original Message-----
> > From: Harrison, John C <john.c.harrison@intel.com>
> > Sent: Wednesday, June 11, 2025 4:57 PM
> > To: Cavitt, Jonathan <jonathan.cavitt@intel.com>; Intel-Xe@Lists.FreeDesktop.Org
> > Subject: Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target
> >> On 6/11/2025 3:04 PM, Cavitt, Jonathan wrote:
> >>> -----Original Message-----
> >>> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of John.C.Harrison@Intel.com
> >>> Sent: Wednesday, June 11, 2025 2:06 PM
> >>> To: Intel-Xe@Lists.FreeDesktop.Org
> >>> Cc: Harrison, John C <john.c.harrison@intel.com>
> >>> Subject: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target
> >>>> From: John Harrison <John.C.Harrison@Intel.com>
> >>>>
> >>>> The GuC has an option to write log data via NPK. This is basically a
> >>>> magic IO address that GuC writes arbitrary data to and which can be
> >>>> logged by a suitable hardware logger. This can allow retrieval of the
> >>>> GuC log in hardware debug environments even when the system as a whole
> >>>> dies horribly.
> >>>>
> >>>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> >>> So, this is basically a new modparam value that redirects GuC logs to
> >>> a specific IO address?  I take it guc_log_target = 2 is the default value, and
> >>> guc_log_target = 1 would print the logs to stdout, then?  I'd ask why we
> >>> use 0 as a default value and not just default to 2 all the time, but I think I
> >>> already know why (we need to guard against guc_log_target = 0 anyways
> >>> to prevent printing to stdin).
> >> Um, read the patch - "(0=memory [default], 1 = NPK, 2 = memory + NPK)".
> >> The default is zero. And no, nothing prints to stdout. This is about
> >> hardware level debugging. It has nothing to do with stdin/stdout/stderr.
> >> Those concepts do not exist in hardware nor in the KMD. If you send the
> >> GuC log to the NPK target then you need a hardware debugger (JTAG, etc.)
> >> to read it, as described in the commit message.
> > Ah, okay.  When I read "This is basically a magic IO address that GuC writes
> > arbitrary data to", I thought that was indicating that we're writing to the
> > in/out/err IO addresses, and that the data being logged "by a suitable
> You say "the in/out/err IO addresses" like there is such a thing. 
> In/out/err generally refers to stdin/stdout/stderr, being the default 
> first three file handles of a unix process. File handles are not IO 
> addresses. Such file handles also do not exist in the kernel. And they 
> absolutely do not exist inside the GT hardware. My comment was referring 

Okay, right.  The last time the distinction between I/O as a device concept
and I/O as an interface concept was relevant to me was about 8 years ago,
so I can understand how I got confused there.

> to memory mapped IO addresses, i.e. hardware registers. On a normal 
> system, there is nothing connected to said hardware so the logged output 
> goes nowhere. However, if you have a hardware debugger attached to the 
> system then it can trap those accesses and record the log.

You know, sometimes I forget that the intended customers for these
products are major companies that end up shoving these cards into
giant server racks and not PC users with screens and keyboards.

> 
> > hardware logger" was occurring separately.  I guess I also thought NPK
> > was a writing protocol and not a hardware address.
> NPK is neither a protocol nor an address. It is a block of silicon 
> called North Peak, also known as the Intel Trace Hub.

"The GuC has an option to write log data via NPK. This is basically a magic IO address..."

If NPK is "a block of silicon" and not an IO address, then perhaps this would be better
worded as:

"The GuC has the option to write log data to NPK, which is basically a block of silicon..."

> 
> >
> > It didn't occur to me that we'd need to directly write the logs to the
> > hardware logger in cases of catastrophic failure because we already have
> > methods of streaming the logs directly via the serial ports.  Though I
> > suppose that we're talking about different "logs" at this point?
> I don't know what logs you are talking about. This patch is quite 
> clearly only talking about the GuC log. Which is generally accessible 
> via debugfs snapshots or as part of a devcoredump capture.
> It is not ever 'streamed directly via the serial ports'.

I was referring to the dmesg logs at the time, though I will admit that I forgot
there were classes of logs that never get printed to dmesg.  I don't
personally agree with the practice and think that all relevant logs should
be printed to dmesg if possible, even if only at certain debug levels or
upon direct request.  However, I can at least see why we'd want to store those
separately in the NPK silicon block in case of catastrophic failure given the files
they normally get saved to are wiped on system reset.

> 
> John.
> 
> >
> > The reviewed-by still stands.
> > -Jonathan Cavitt
> >
> >>> I also take it this is modified on boot by, for example, writing
> >>> "xe.guc_log_target=1" to CMDLINE_LINUX_DEFAULT as a part of the grub file.
> >> That is generally how module parameters work. You can also set via
> >> modprobe.conf files as long as the Xe driver is a module and not
> >> compiled in.
> >>
> >> John.
> >>
> >>> Yeah, seems good.
> >>> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> >>> -Jonathan Cavitt
> >>>
> >>>> ---
> >>>>    drivers/gpu/drm/xe/xe_guc.c    | 4 ++++
> >>>>    drivers/gpu/drm/xe/xe_module.c | 4 ++++
> >>>>    drivers/gpu/drm/xe/xe_module.h | 1 +
> >>>>    3 files changed, 9 insertions(+)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> >>>> index e16d19b44bcc..9c0e3113f7d5 100644
> >>>> --- a/drivers/gpu/drm/xe/xe_guc.c
> >>>> +++ b/drivers/gpu/drm/xe/xe_guc.c
> >>>> @@ -35,6 +35,7 @@
> >>>>    #include "xe_guc_submit.h"
> >>>>    #include "xe_memirq.h"
> >>>>    #include "xe_mmio.h"
> >>>> +#include "xe_module.h"
> >>>>    #include "xe_platform_types.h"
> >>>>    #include "xe_sriov.h"
> >>>>    #include "xe_uc.h"
> >>>> @@ -74,6 +75,9 @@ static u32 guc_ctl_debug_flags(struct xe_guc *guc)
> >>>>    	else
> >>>>    		flags |= FIELD_PREP(GUC_LOG_VERBOSITY, GUC_LOG_LEVEL_TO_VERBOSITY(level));
> >>>>    
> >>>> +	if (xe_modparam.guc_log_target)
> >>>> +		flags |= FIELD_PREP(GUC_LOG_DESTINATION, xe_modparam.guc_log_target);
> >>>> +
> >>>>    	return flags;
> >>>>    }
> >>>>    
> >>>> diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
> >>>> index 1c4dfafbcd0b..fc8c681819b9 100644
> >>>> --- a/drivers/gpu/drm/xe/xe_module.c
> >>>> +++ b/drivers/gpu/drm/xe/xe_module.c
> >>>> @@ -21,6 +21,7 @@
> >>>>    struct xe_modparam xe_modparam = {
> >>>>    	.probe_display = true,
> >>>>    	.guc_log_level = 3,
> >>>> +	.guc_log_target = 0,
> >>>>    	.force_probe = CONFIG_DRM_XE_FORCE_PROBE,
> >>>>    #ifdef CONFIG_PCI_IOV
> >>>>    	.max_vfs = IS_ENABLED(CONFIG_DRM_XE_DEBUG) ? ~0 : 0,
> >>>> @@ -45,6 +46,9 @@ MODULE_PARM_DESC(vram_bar_size, "Set the vram bar size (in MiB) - <0=disable-res
> >>>>    module_param_named(guc_log_level, xe_modparam.guc_log_level, int, 0600);
> >>>>    MODULE_PARM_DESC(guc_log_level, "GuC firmware logging level (0=disable, 1..5=enable with verbosity min..max)");
> >>>>    
> >>>> +module_param_named(guc_log_target, xe_modparam.guc_log_target, int, 0600);
> >>>> +MODULE_PARM_DESC(guc_log_target, "GuC firmware logging target (0=memory [default], 1 = NPK, 2 = memory + NPK)");
> >>>> +
> >>>>    module_param_named_unsafe(guc_firmware_path, xe_modparam.guc_firmware_path, charp, 0400);
> >>>>    MODULE_PARM_DESC(guc_firmware_path,
> >>>>    		 "GuC firmware path to use instead of the default one");
> >>>> diff --git a/drivers/gpu/drm/xe/xe_module.h b/drivers/gpu/drm/xe/xe_module.h
> >>>> index 5a3bfea8b7b4..4d978f6f26b6 100644
> >>>> --- a/drivers/gpu/drm/xe/xe_module.h
> >>>> +++ b/drivers/gpu/drm/xe/xe_module.h
> >>>> @@ -14,6 +14,7 @@ struct xe_modparam {
> >>>>    	bool probe_display;
> >>>>    	u32 force_vram_bar_size;
> >>>>    	int guc_log_level;
> >>>> +	int guc_log_target;
> >>>>    	char *guc_firmware_path;
> >>>>    	char *huc_firmware_path;
> >>>>    	char *gsc_firmware_path;
> >>>> -- 
> >>>> 2.49.0
> >>>>
> >>>>
> >>
> 
> 

Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target

[John Harrison]

On 6/12/2025 11:27 AM, Cavitt, Jonathan wrote:
> ----Original Message-----
> From: Harrison, John C <john.c.harrison@intel.com>
> Sent: Thursday, June 12, 2025 10:50 AM
> To: Cavitt, Jonathan <jonathan.cavitt@intel.com>; Intel-Xe@Lists.FreeDesktop.Org
> Subject: Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target
>> On 6/12/2025 7:32 AM, Cavitt, Jonathan wrote:
>>> -----Original Message-----
>>> From: Harrison, John C <john.c.harrison@intel.com>
>>> Sent: Wednesday, June 11, 2025 4:57 PM
>>> To: Cavitt, Jonathan <jonathan.cavitt@intel.com>; Intel-Xe@Lists.FreeDesktop.Org
>>> Subject: Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target
>>>> On 6/11/2025 3:04 PM, Cavitt, Jonathan wrote:
>>>>> -----Original Message-----
>>>>> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of John.C.Harrison@Intel.com
>>>>> Sent: Wednesday, June 11, 2025 2:06 PM
>>>>> To: Intel-Xe@Lists.FreeDesktop.Org
>>>>> Cc: Harrison, John C <john.c.harrison@intel.com>
>>>>> Subject: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target
>>>>>> From: John Harrison <John.C.Harrison@Intel.com>
>>>>>>
>>>>>> The GuC has an option to write log data via NPK. This is basically a
>>>>>> magic IO address that GuC writes arbitrary data to and which can be
>>>>>> logged by a suitable hardware logger. This can allow retrieval of the
>>>>>> GuC log in hardware debug environments even when the system as a whole
>>>>>> dies horribly.
>>>>>>
>>>>>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>>>> So, this is basically a new modparam value that redirects GuC logs to
>>>>> a specific IO address?  I take it guc_log_target = 2 is the default value, and
>>>>> guc_log_target = 1 would print the logs to stdout, then?  I'd ask why we
>>>>> use 0 as a default value and not just default to 2 all the time, but I think I
>>>>> already know why (we need to guard against guc_log_target = 0 anyways
>>>>> to prevent printing to stdin).
>>>> Um, read the patch - "(0=memory [default], 1 = NPK, 2 = memory + NPK)".
>>>> The default is zero. And no, nothing prints to stdout. This is about
>>>> hardware level debugging. It has nothing to do with stdin/stdout/stderr.
>>>> Those concepts do not exist in hardware nor in the KMD. If you send the
>>>> GuC log to the NPK target then you need a hardware debugger (JTAG, etc.)
>>>> to read it, as described in the commit message.
>>> Ah, okay.  When I read "This is basically a magic IO address that GuC writes
>>> arbitrary data to", I thought that was indicating that we're writing to the
>>> in/out/err IO addresses, and that the data being logged "by a suitable
>> You say "the in/out/err IO addresses" like there is such a thing.
>> In/out/err generally refers to stdin/stdout/stderr, being the default
>> first three file handles of a unix process. File handles are not IO
>> addresses. Such file handles also do not exist in the kernel. And they
>> absolutely do not exist inside the GT hardware. My comment was referring
> Okay, right.  The last time the distinction between I/O as a device concept
> and I/O as an interface concept was relevant to me was about 8 years ago,
> so I can understand how I got confused there.
>
>> to memory mapped IO addresses, i.e. hardware registers. On a normal
>> system, there is nothing connected to said hardware so the logged output
>> goes nowhere. However, if you have a hardware debugger attached to the
>> system then it can trap those accesses and record the log.
> You know, sometimes I forget that the intended customers for these
> products are major companies that end up shoving these cards into
> giant server racks and not PC users with screens and keyboards.
>
>>> hardware logger" was occurring separately.  I guess I also thought NPK
>>> was a writing protocol and not a hardware address.
>> NPK is neither a protocol nor an address. It is a block of silicon
>> called North Peak, also known as the Intel Trace Hub.
> "The GuC has an option to write log data via NPK. This is basically a magic IO address..."
>
> If NPK is "a block of silicon" and not an IO address, then perhaps this would be better
> worded as:
>
> "The GuC has the option to write log data to NPK, which is basically a block of silicon..."
NPK is a block which implements a register which is written to by GuC as 
an MMIO access. The point of saying 'basically' is because this is very 
simple view - GuC writes to a register. All else is irrelevant. If you 
want the full details then there is a white paper about it. But 
generally speaking, if you don't know already then it isn't relevant to 
you because you don't have the hundreds of thousands of dollars of 
hardware required to make use of it. So complicated descriptions are 
pointless.

>>> It didn't occur to me that we'd need to directly write the logs to the
>>> hardware logger in cases of catastrophic failure because we already have
>>> methods of streaming the logs directly via the serial ports.  Though I
>>> suppose that we're talking about different "logs" at this point?
>> I don't know what logs you are talking about. This patch is quite
>> clearly only talking about the GuC log. Which is generally accessible
>> via debugfs snapshots or as part of a devcoredump capture.
>> It is not ever 'streamed directly via the serial ports'.
> I was referring to the dmesg logs at the time, though I will admit that I forgot
> there were classes of logs that never get printed to dmesg.  I don't
> personally agree with the practice and think that all relevant logs should
> be printed to dmesg if possible, even if only at certain debug levels or
Sure, lets write to dmesg from inside the GT hardware. I'm sure we can 
add that in to the next product...

DMesg is for super important kernel messages. Sometimes, it is the only 
way to debug kernel related problems because the system dies and 
userland is no longer functional. But it is absolutely not meant to be 
the default output method for all possible logging systems. For example, 
the ftrace mechanism exists precisely because dmesg is not the right way 
to log many things.

> upon direct request.  However, I can at least see why we'd want to store those
> separately in the NPK silicon block in case of catastrophic failure given the files
> they normally get saved to are wiped on system reset.
Nothing is stored. NPK is simply a transport mechanism here. If there is 
nothing connected to it then it goes nowhere. /dev/null if you prefer. 
And there is no file to get wiped. The normal target for GuC logging is 
a memory buffer. Any access via a debugfs or sysfs 'file' is just code 
being run inside the kernel to read that memory buffer and return it to 
the user.

John.

>
>> John.
>>
>>> The reviewed-by still stands.
>>> -Jonathan Cavitt
>>>
>>>>> I also take it this is modified on boot by, for example, writing
>>>>> "xe.guc_log_target=1" to CMDLINE_LINUX_DEFAULT as a part of the grub file.
>>>> That is generally how module parameters work. You can also set via
>>>> modprobe.conf files as long as the Xe driver is a module and not
>>>> compiled in.
>>>>
>>>> John.
>>>>
>>>>> Yeah, seems good.
>>>>> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
>>>>> -Jonathan Cavitt
>>>>>
>>>>>> ---
>>>>>>     drivers/gpu/drm/xe/xe_guc.c    | 4 ++++
>>>>>>     drivers/gpu/drm/xe/xe_module.c | 4 ++++
>>>>>>     drivers/gpu/drm/xe/xe_module.h | 1 +
>>>>>>     3 files changed, 9 insertions(+)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>>>>>> index e16d19b44bcc..9c0e3113f7d5 100644
>>>>>> --- a/drivers/gpu/drm/xe/xe_guc.c
>>>>>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>>>>>> @@ -35,6 +35,7 @@
>>>>>>     #include "xe_guc_submit.h"
>>>>>>     #include "xe_memirq.h"
>>>>>>     #include "xe_mmio.h"
>>>>>> +#include "xe_module.h"
>>>>>>     #include "xe_platform_types.h"
>>>>>>     #include "xe_sriov.h"
>>>>>>     #include "xe_uc.h"
>>>>>> @@ -74,6 +75,9 @@ static u32 guc_ctl_debug_flags(struct xe_guc *guc)
>>>>>>     	else
>>>>>>     		flags |= FIELD_PREP(GUC_LOG_VERBOSITY, GUC_LOG_LEVEL_TO_VERBOSITY(level));
>>>>>>     
>>>>>> +	if (xe_modparam.guc_log_target)
>>>>>> +		flags |= FIELD_PREP(GUC_LOG_DESTINATION, xe_modparam.guc_log_target);
>>>>>> +
>>>>>>     	return flags;
>>>>>>     }
>>>>>>     
>>>>>> diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
>>>>>> index 1c4dfafbcd0b..fc8c681819b9 100644
>>>>>> --- a/drivers/gpu/drm/xe/xe_module.c
>>>>>> +++ b/drivers/gpu/drm/xe/xe_module.c
>>>>>> @@ -21,6 +21,7 @@
>>>>>>     struct xe_modparam xe_modparam = {
>>>>>>     	.probe_display = true,
>>>>>>     	.guc_log_level = 3,
>>>>>> +	.guc_log_target = 0,
>>>>>>     	.force_probe = CONFIG_DRM_XE_FORCE_PROBE,
>>>>>>     #ifdef CONFIG_PCI_IOV
>>>>>>     	.max_vfs = IS_ENABLED(CONFIG_DRM_XE_DEBUG) ? ~0 : 0,
>>>>>> @@ -45,6 +46,9 @@ MODULE_PARM_DESC(vram_bar_size, "Set the vram bar size (in MiB) - <0=disable-res
>>>>>>     module_param_named(guc_log_level, xe_modparam.guc_log_level, int, 0600);
>>>>>>     MODULE_PARM_DESC(guc_log_level, "GuC firmware logging level (0=disable, 1..5=enable with verbosity min..max)");
>>>>>>     
>>>>>> +module_param_named(guc_log_target, xe_modparam.guc_log_target, int, 0600);
>>>>>> +MODULE_PARM_DESC(guc_log_target, "GuC firmware logging target (0=memory [default], 1 = NPK, 2 = memory + NPK)");
>>>>>> +
>>>>>>     module_param_named_unsafe(guc_firmware_path, xe_modparam.guc_firmware_path, charp, 0400);
>>>>>>     MODULE_PARM_DESC(guc_firmware_path,
>>>>>>     		 "GuC firmware path to use instead of the default one");
>>>>>> diff --git a/drivers/gpu/drm/xe/xe_module.h b/drivers/gpu/drm/xe/xe_module.h
>>>>>> index 5a3bfea8b7b4..4d978f6f26b6 100644
>>>>>> --- a/drivers/gpu/drm/xe/xe_module.h
>>>>>> +++ b/drivers/gpu/drm/xe/xe_module.h
>>>>>> @@ -14,6 +14,7 @@ struct xe_modparam {
>>>>>>     	bool probe_display;
>>>>>>     	u32 force_vram_bar_size;
>>>>>>     	int guc_log_level;
>>>>>> +	int guc_log_target;
>>>>>>     	char *guc_firmware_path;
>>>>>>     	char *huc_firmware_path;
>>>>>>     	char *gsc_firmware_path;
>>>>>> -- 
>>>>>> 2.49.0
>>>>>>
>>>>>>
>>

Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target

[Summers, Stuart]

On Wed, 2025-06-11 at 14:05 -0700, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
> 
> The GuC has an option to write log data via NPK. This is basically a
> magic IO address that GuC writes arbitrary data to and which can be
> logged by a suitable hardware logger. This can allow retrieval of the
> GuC log in hardware debug environments even when the system as a
> whole
> dies horribly.
> 
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
>  drivers/gpu/drm/xe/xe_guc.c    | 4 ++++
>  drivers/gpu/drm/xe/xe_module.c | 4 ++++
>  drivers/gpu/drm/xe/xe_module.h | 1 +
>  3 files changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc.c
> b/drivers/gpu/drm/xe/xe_guc.c
> index e16d19b44bcc..9c0e3113f7d5 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -35,6 +35,7 @@
>  #include "xe_guc_submit.h"
>  #include "xe_memirq.h"
>  #include "xe_mmio.h"
> +#include "xe_module.h"
>  #include "xe_platform_types.h"
>  #include "xe_sriov.h"
>  #include "xe_uc.h"
> @@ -74,6 +75,9 @@ static u32 guc_ctl_debug_flags(struct xe_guc *guc)
>         else
>                 flags |= FIELD_PREP(GUC_LOG_VERBOSITY,
> GUC_LOG_LEVEL_TO_VERBOSITY(level));
>  
> +       if (xe_modparam.guc_log_target)
> +               flags |= FIELD_PREP(GUC_LOG_DESTINATION,
> xe_modparam.guc_log_target);

We do have the new configfs entries. Is there a reason to keep this in
the modparams instead of moving to configfs?

-Stuart

> +
>         return flags;
>  }
>  
> diff --git a/drivers/gpu/drm/xe/xe_module.c
> b/drivers/gpu/drm/xe/xe_module.c
> index 1c4dfafbcd0b..fc8c681819b9 100644
> --- a/drivers/gpu/drm/xe/xe_module.c
> +++ b/drivers/gpu/drm/xe/xe_module.c
> @@ -21,6 +21,7 @@
>  struct xe_modparam xe_modparam = {
>         .probe_display = true,
>         .guc_log_level = 3,
> +       .guc_log_target = 0,
>         .force_probe = CONFIG_DRM_XE_FORCE_PROBE,
>  #ifdef CONFIG_PCI_IOV
>         .max_vfs = IS_ENABLED(CONFIG_DRM_XE_DEBUG) ? ~0 : 0,
> @@ -45,6 +46,9 @@ MODULE_PARM_DESC(vram_bar_size, "Set the vram bar
> size (in MiB) - <0=disable-res
>  module_param_named(guc_log_level, xe_modparam.guc_log_level, int,
> 0600);
>  MODULE_PARM_DESC(guc_log_level, "GuC firmware logging level
> (0=disable, 1..5=enable with verbosity min..max)");
>  
> +module_param_named(guc_log_target, xe_modparam.guc_log_target, int,
> 0600);
> +MODULE_PARM_DESC(guc_log_target, "GuC firmware logging target
> (0=memory [default], 1 = NPK, 2 = memory + NPK)");
> +
>  module_param_named_unsafe(guc_firmware_path,
> xe_modparam.guc_firmware_path, charp, 0400);
>  MODULE_PARM_DESC(guc_firmware_path,
>                  "GuC firmware path to use instead of the default
> one");
> diff --git a/drivers/gpu/drm/xe/xe_module.h
> b/drivers/gpu/drm/xe/xe_module.h
> index 5a3bfea8b7b4..4d978f6f26b6 100644
> --- a/drivers/gpu/drm/xe/xe_module.h
> +++ b/drivers/gpu/drm/xe/xe_module.h
> @@ -14,6 +14,7 @@ struct xe_modparam {
>         bool probe_display;
>         u32 force_vram_bar_size;
>         int guc_log_level;
> +       int guc_log_target;
>         char *guc_firmware_path;
>         char *huc_firmware_path;
>         char *gsc_firmware_path;

RE: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target

[Cavitt, Jonathan]

-----Original Message-----
From: Harrison, John C <john.c.harrison@intel.com> 
Sent: Thursday, June 12, 2025 11:47 AM
To: Cavitt, Jonathan <jonathan.cavitt@intel.com>; Intel-Xe@Lists.FreeDesktop.Org
Subject: Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target
> 
> On 6/12/2025 11:27 AM, Cavitt, Jonathan wrote:
> > ----Original Message-----
> > From: Harrison, John C <john.c.harrison@intel.com>
> > Sent: Thursday, June 12, 2025 10:50 AM
> > To: Cavitt, Jonathan <jonathan.cavitt@intel.com>; Intel-Xe@Lists.FreeDesktop.Org
> > Subject: Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target
> >> On 6/12/2025 7:32 AM, Cavitt, Jonathan wrote:
> >>> -----Original Message-----
> >>> From: Harrison, John C <john.c.harrison@intel.com>
> >>> Sent: Wednesday, June 11, 2025 4:57 PM
> >>> To: Cavitt, Jonathan <jonathan.cavitt@intel.com>; Intel-Xe@Lists.FreeDesktop.Org
> >>> Subject: Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target
> >>>> On 6/11/2025 3:04 PM, Cavitt, Jonathan wrote:
> >>>>> -----Original Message-----
> >>>>> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of John.C.Harrison@Intel.com
> >>>>> Sent: Wednesday, June 11, 2025 2:06 PM
> >>>>> To: Intel-Xe@Lists.FreeDesktop.Org
> >>>>> Cc: Harrison, John C <john.c.harrison@intel.com>
> >>>>> Subject: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target
> >>>>>> From: John Harrison <John.C.Harrison@Intel.com>
> >>>>>>
> >>>>>> The GuC has an option to write log data via NPK. This is basically a
> >>>>>> magic IO address that GuC writes arbitrary data to and which can be
> >>>>>> logged by a suitable hardware logger. This can allow retrieval of the
> >>>>>> GuC log in hardware debug environments even when the system as a whole
> >>>>>> dies horribly.
> >>>>>>
> >>>>>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> >>>>> So, this is basically a new modparam value that redirects GuC logs to
> >>>>> a specific IO address?  I take it guc_log_target = 2 is the default value, and
> >>>>> guc_log_target = 1 would print the logs to stdout, then?  I'd ask why we
> >>>>> use 0 as a default value and not just default to 2 all the time, but I think I
> >>>>> already know why (we need to guard against guc_log_target = 0 anyways
> >>>>> to prevent printing to stdin).
> >>>> Um, read the patch - "(0=memory [default], 1 = NPK, 2 = memory + NPK)".
> >>>> The default is zero. And no, nothing prints to stdout. This is about
> >>>> hardware level debugging. It has nothing to do with stdin/stdout/stderr.
> >>>> Those concepts do not exist in hardware nor in the KMD. If you send the
> >>>> GuC log to the NPK target then you need a hardware debugger (JTAG, etc.)
> >>>> to read it, as described in the commit message.
> >>> Ah, okay.  When I read "This is basically a magic IO address that GuC writes
> >>> arbitrary data to", I thought that was indicating that we're writing to the
> >>> in/out/err IO addresses, and that the data being logged "by a suitable
> >> You say "the in/out/err IO addresses" like there is such a thing.
> >> In/out/err generally refers to stdin/stdout/stderr, being the default
> >> first three file handles of a unix process. File handles are not IO
> >> addresses. Such file handles also do not exist in the kernel. And they
> >> absolutely do not exist inside the GT hardware. My comment was referring
> > Okay, right.  The last time the distinction between I/O as a device concept
> > and I/O as an interface concept was relevant to me was about 8 years ago,
> > so I can understand how I got confused there.
> >
> >> to memory mapped IO addresses, i.e. hardware registers. On a normal
> >> system, there is nothing connected to said hardware so the logged output
> >> goes nowhere. However, if you have a hardware debugger attached to the
> >> system then it can trap those accesses and record the log.
> > You know, sometimes I forget that the intended customers for these
> > products are major companies that end up shoving these cards into
> > giant server racks and not PC users with screens and keyboards.
> >
> >>> hardware logger" was occurring separately.  I guess I also thought NPK
> >>> was a writing protocol and not a hardware address.
> >> NPK is neither a protocol nor an address. It is a block of silicon
> >> called North Peak, also known as the Intel Trace Hub.
> > "The GuC has an option to write log data via NPK. This is basically a magic IO address..."
> >
> > If NPK is "a block of silicon" and not an IO address, then perhaps this would be better
> > worded as:
> >
> > "The GuC has the option to write log data to NPK, which is basically a block of silicon..."
> NPK is a block which implements a register which is written to by GuC as 
> an MMIO access. The point of saying 'basically' is because this is very 
> simple view - GuC writes to a register. All else is irrelevant. If you 
> want the full details then there is a white paper about it. But 
> generally speaking, if you don't know already then it isn't relevant to 
> you because you don't have the hundreds of thousands of dollars of 
> hardware required to make use of it. So complicated descriptions are 
> pointless.

We can still keep the description precise without overloading it with "pointless"
details:

"""
The GuC has the option to write log data through NPK.  NPK acts as a
transport layer that can send arbitrary data to a dedicated hardware
logger if one is connected.  This allows for the retrieval of the GuC log
even in the event of catastrophic hardware failure.
"""

> 
> >>> It didn't occur to me that we'd need to directly write the logs to the
> >>> hardware logger in cases of catastrophic failure because we already have
> >>> methods of streaming the logs directly via the serial ports.  Though I
> >>> suppose that we're talking about different "logs" at this point?
> >> I don't know what logs you are talking about. This patch is quite
> >> clearly only talking about the GuC log. Which is generally accessible
> >> via debugfs snapshots or as part of a devcoredump capture.
> >> It is not ever 'streamed directly via the serial ports'.
> > I was referring to the dmesg logs at the time, though I will admit that I forgot
> > there were classes of logs that never get printed to dmesg.  I don't
> > personally agree with the practice and think that all relevant logs should
> > be printed to dmesg if possible, even if only at certain debug levels or
> Sure, lets write to dmesg from inside the GT hardware. I'm sure we can 
> add that in to the next product...

Your sarcasm is noted...

> 
> DMesg is for super important kernel messages. Sometimes, it is the only 
> way to debug kernel related problems because the system dies and 
> userland is no longer functional. But it is absolutely not meant to be 
> the default output method for all possible logging systems. For example, 
> the ftrace mechanism exists precisely because dmesg is not the right way 
> to log many things.

We can agree to disagree, I guess.

> 
> > upon direct request.  However, I can at least see why we'd want to store those
> > separately in the NPK silicon block in case of catastrophic failure given the files
> > they normally get saved to are wiped on system reset.
> Nothing is stored. NPK is simply a transport mechanism here. If there is 
> nothing connected to it then it goes nowhere. /dev/null if you prefer. 
> And there is no file to get wiped. The normal target for GuC logging is 
> a memory buffer. Any access via a debugfs or sysfs 'file' is just code 
> being run inside the kernel to read that memory buffer and return it to 
> the user.

Regardless, information is being wiped, and that's preventing us from
accessing the log after system reset because the log (or I guess "the data
used to construct the log" if we're being pedantic) doesn't exist anymore.

> 
> John.
> 
> >
> >> John.
> >>
> >>> The reviewed-by still stands.
> >>> -Jonathan Cavitt
> >>>
> >>>>> I also take it this is modified on boot by, for example, writing
> >>>>> "xe.guc_log_target=1" to CMDLINE_LINUX_DEFAULT as a part of the grub file.
> >>>> That is generally how module parameters work. You can also set via
> >>>> modprobe.conf files as long as the Xe driver is a module and not
> >>>> compiled in.
> >>>>
> >>>> John.
> >>>>
> >>>>> Yeah, seems good.
> >>>>> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
> >>>>> -Jonathan Cavitt
> >>>>>
> >>>>>> ---
> >>>>>>     drivers/gpu/drm/xe/xe_guc.c    | 4 ++++
> >>>>>>     drivers/gpu/drm/xe/xe_module.c | 4 ++++
> >>>>>>     drivers/gpu/drm/xe/xe_module.h | 1 +
> >>>>>>     3 files changed, 9 insertions(+)
> >>>>>>
> >>>>>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> >>>>>> index e16d19b44bcc..9c0e3113f7d5 100644
> >>>>>> --- a/drivers/gpu/drm/xe/xe_guc.c
> >>>>>> +++ b/drivers/gpu/drm/xe/xe_guc.c
> >>>>>> @@ -35,6 +35,7 @@
> >>>>>>     #include "xe_guc_submit.h"
> >>>>>>     #include "xe_memirq.h"
> >>>>>>     #include "xe_mmio.h"
> >>>>>> +#include "xe_module.h"
> >>>>>>     #include "xe_platform_types.h"
> >>>>>>     #include "xe_sriov.h"
> >>>>>>     #include "xe_uc.h"
> >>>>>> @@ -74,6 +75,9 @@ static u32 guc_ctl_debug_flags(struct xe_guc *guc)
> >>>>>>     	else
> >>>>>>     		flags |= FIELD_PREP(GUC_LOG_VERBOSITY, GUC_LOG_LEVEL_TO_VERBOSITY(level));
> >>>>>>     
> >>>>>> +	if (xe_modparam.guc_log_target)
> >>>>>> +		flags |= FIELD_PREP(GUC_LOG_DESTINATION, xe_modparam.guc_log_target);
> >>>>>> +
> >>>>>>     	return flags;
> >>>>>>     }
> >>>>>>     
> >>>>>> diff --git a/drivers/gpu/drm/xe/xe_module.c b/drivers/gpu/drm/xe/xe_module.c
> >>>>>> index 1c4dfafbcd0b..fc8c681819b9 100644
> >>>>>> --- a/drivers/gpu/drm/xe/xe_module.c
> >>>>>> +++ b/drivers/gpu/drm/xe/xe_module.c
> >>>>>> @@ -21,6 +21,7 @@
> >>>>>>     struct xe_modparam xe_modparam = {
> >>>>>>     	.probe_display = true,
> >>>>>>     	.guc_log_level = 3,
> >>>>>> +	.guc_log_target = 0,
> >>>>>>     	.force_probe = CONFIG_DRM_XE_FORCE_PROBE,
> >>>>>>     #ifdef CONFIG_PCI_IOV
> >>>>>>     	.max_vfs = IS_ENABLED(CONFIG_DRM_XE_DEBUG) ? ~0 : 0,
> >>>>>> @@ -45,6 +46,9 @@ MODULE_PARM_DESC(vram_bar_size, "Set the vram bar size (in MiB) - <0=disable-res
> >>>>>>     module_param_named(guc_log_level, xe_modparam.guc_log_level, int, 0600);
> >>>>>>     MODULE_PARM_DESC(guc_log_level, "GuC firmware logging level (0=disable, 1..5=enable with verbosity min..max)");
> >>>>>>     
> >>>>>> +module_param_named(guc_log_target, xe_modparam.guc_log_target, int, 0600);
> >>>>>> +MODULE_PARM_DESC(guc_log_target, "GuC firmware logging target (0=memory [default], 1 = NPK, 2 = memory + NPK)");
> >>>>>> +
> >>>>>>     module_param_named_unsafe(guc_firmware_path, xe_modparam.guc_firmware_path, charp, 0400);
> >>>>>>     MODULE_PARM_DESC(guc_firmware_path,
> >>>>>>     		 "GuC firmware path to use instead of the default one");
> >>>>>> diff --git a/drivers/gpu/drm/xe/xe_module.h b/drivers/gpu/drm/xe/xe_module.h
> >>>>>> index 5a3bfea8b7b4..4d978f6f26b6 100644
> >>>>>> --- a/drivers/gpu/drm/xe/xe_module.h
> >>>>>> +++ b/drivers/gpu/drm/xe/xe_module.h
> >>>>>> @@ -14,6 +14,7 @@ struct xe_modparam {
> >>>>>>     	bool probe_display;
> >>>>>>     	u32 force_vram_bar_size;
> >>>>>>     	int guc_log_level;
> >>>>>> +	int guc_log_target;
> >>>>>>     	char *guc_firmware_path;
> >>>>>>     	char *huc_firmware_path;
> >>>>>>     	char *gsc_firmware_path;
> >>>>>> -- 
> >>>>>> 2.49.0
> >>>>>>
> >>>>>>
> >>
> 
> 

Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target

[Lucas De Marchi]

On Wed, Jun 11, 2025 at 04:51:24PM -0700, John Harrison wrote:
>On 6/11/2025 2:49 PM, Lucas De Marchi wrote:
>>On Wed, Jun 11, 2025 at 02:05:53PM -0700, John.C.Harrison@Intel.com 
>>wrote:
>>>From: John Harrison <John.C.Harrison@Intel.com>
>>>
>>>The GuC has an option to write log data via NPK. This is basically a
>>>magic IO address that GuC writes arbitrary data to and which can be
>>>logged by a suitable hardware logger. This can allow retrieval of the
>>>GuC log in hardware debug environments even when the system as a whole
>>>dies horribly.
>>>
>>>Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>>---
>>>drivers/gpu/drm/xe/xe_guc.c    | 4 ++++
>>>drivers/gpu/drm/xe/xe_module.c | 4 ++++
>>>drivers/gpu/drm/xe/xe_module.h | 1 +
>>>3 files changed, 9 insertions(+)
>>>
>>>diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>>>index e16d19b44bcc..9c0e3113f7d5 100644
>>>--- a/drivers/gpu/drm/xe/xe_guc.c
>>>+++ b/drivers/gpu/drm/xe/xe_guc.c
>>>@@ -35,6 +35,7 @@
>>>#include "xe_guc_submit.h"
>>>#include "xe_memirq.h"
>>>#include "xe_mmio.h"
>>>+#include "xe_module.h"
>>>#include "xe_platform_types.h"
>>>#include "xe_sriov.h"
>>>#include "xe_uc.h"
>>>@@ -74,6 +75,9 @@ static u32 guc_ctl_debug_flags(struct xe_guc *guc)
>>>    else
>>>        flags |= FIELD_PREP(GUC_LOG_VERBOSITY, 
>>>GUC_LOG_LEVEL_TO_VERBOSITY(level));
>>>
>>>+    if (xe_modparam.guc_log_target)
>>>+        flags |= FIELD_PREP(GUC_LOG_DESTINATION, 
>>>xe_modparam.guc_log_target);
>>
>>is this supported across the board for all platforms and firmware
>>versions? Otherwise, what'd happen if you have and old igfx and you are
>>debugging a new dgfx? or vice-versa.
>All platforms that have a GuC and all firmware builds that have been 
>supported under Linux. North PeaK is part of the host chipset not the 
>GuC or GT.

so I imagine this only works in igfx? I'm mostly concerned about this
being a module param and then you try to debug one card and get the
other to do what you don't want (or crash, or refuse to load). For
similar reason we've been adding these debug aids via configfs rather
than module param.  If it's harmless, then.... well guc_log_level is
already there, doesn't hurt much to have the other.

Lucas De Marchi

Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target

[John Harrison]

On 6/12/2025 3:05 PM, Lucas De Marchi wrote:
> On Wed, Jun 11, 2025 at 04:51:24PM -0700, John Harrison wrote:
>> On 6/11/2025 2:49 PM, Lucas De Marchi wrote:
>>> On Wed, Jun 11, 2025 at 02:05:53PM -0700, John.C.Harrison@Intel.com 
>>> wrote:
>>>> From: John Harrison <John.C.Harrison@Intel.com>
>>>>
>>>> The GuC has an option to write log data via NPK. This is basically a
>>>> magic IO address that GuC writes arbitrary data to and which can be
>>>> logged by a suitable hardware logger. This can allow retrieval of the
>>>> GuC log in hardware debug environments even when the system as a whole
>>>> dies horribly.
>>>>
>>>> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>>>> ---
>>>> drivers/gpu/drm/xe/xe_guc.c    | 4 ++++
>>>> drivers/gpu/drm/xe/xe_module.c | 4 ++++
>>>> drivers/gpu/drm/xe/xe_module.h | 1 +
>>>> 3 files changed, 9 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>>>> index e16d19b44bcc..9c0e3113f7d5 100644
>>>> --- a/drivers/gpu/drm/xe/xe_guc.c
>>>> +++ b/drivers/gpu/drm/xe/xe_guc.c
>>>> @@ -35,6 +35,7 @@
>>>> #include "xe_guc_submit.h"
>>>> #include "xe_memirq.h"
>>>> #include "xe_mmio.h"
>>>> +#include "xe_module.h"
>>>> #include "xe_platform_types.h"
>>>> #include "xe_sriov.h"
>>>> #include "xe_uc.h"
>>>> @@ -74,6 +75,9 @@ static u32 guc_ctl_debug_flags(struct xe_guc *guc)
>>>>     else
>>>>         flags |= FIELD_PREP(GUC_LOG_VERBOSITY, 
>>>> GUC_LOG_LEVEL_TO_VERBOSITY(level));
>>>>
>>>> +    if (xe_modparam.guc_log_target)
>>>> +        flags |= FIELD_PREP(GUC_LOG_DESTINATION, 
>>>> xe_modparam.guc_log_target);
>>>
>>> is this supported across the board for all platforms and firmware
>>> versions? Otherwise, what'd happen if you have and old igfx and you are
>>> debugging a new dgfx? or vice-versa.
>> All platforms that have a GuC and all firmware builds that have been 
>> supported under Linux. North PeaK is part of the host chipset not the 
>> GuC or GT.
>
> so I imagine this only works in igfx? I'm mostly concerned about this
AFAIK, all platforms means all platforms. TGL, DG2, PVC, LNL, BMG, PTL, 
everything.

> being a module param and then you try to debug one card and get the
> other to do what you don't want (or crash, or refuse to load). For
> similar reason we've been adding these debug aids via configfs rather
> than module param.  If it's harmless, then.... well guc_log_level is
> already there, doesn't hurt much to have the other.
Yeah, Stuart mentioned the configfs thing. I'm going to take a look at 
doing it that way. My only concern with that is the learning curve to 
use configfs seems quite high. We can't just add a comment to an end 
user bug report saying "please set the module parameter". It would take 
quite a bit of explaining to get someone to set an option via configfs.

For this particular setting, it's not so much of a concern. As 
mentioned, this is not something any random end user can actually make 
use of. It requires some serious hardware to be attached to get the logs 
out. So someone using this is going to be more hack savvy than an 
average user.

John.

>
> Lucas De Marchi

[PATCH 0/2] Clean up of GuC init data macros & add extra log option

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

Code cleanups and add support for a debug feature.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>


John Harrison (2):
  drm/xe/guc: Clean up of GuC 'CTL' defines
  drm/xe/guc: Add support for NPK as a GuC log target

 drivers/gpu/drm/xe/xe_configfs.c | 61 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_configfs.h |  3 ++
 drivers/gpu/drm/xe/xe_guc.c      | 26 ++++++--------
 drivers/gpu/drm/xe/xe_guc_fwif.h | 28 +++++----------
 4 files changed, 84 insertions(+), 34 deletions(-)

-- 
2.49.0

[PATCH 1/2] drm/xe/guc: Clean up of GuC 'CTL' defines

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

All the field generation for the CTL defines (used for GuC init data)
were hand-rolled rather than using FIELD_PREP/REG_GENMASK/BIT macros.

Also, there were a bunch of macros defined for verbosity settings that
were never used.

So fix that all up.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_guc.c      | 21 ++++++---------------
 drivers/gpu/drm/xe/xe_guc_fwif.h | 28 +++++++++-------------------
 2 files changed, 15 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 1ca7f4f27e26..8fac3c518975 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -73,8 +73,7 @@ static u32 guc_ctl_debug_flags(struct xe_guc *guc)
 	if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
 		flags |= GUC_LOG_DISABLED;
 	else
-		flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) <<
-			 GUC_LOG_VERBOSITY_SHIFT;
+		flags |= FIELD_PREP(GUC_LOG_VERBOSITY, GUC_LOG_LEVEL_TO_VERBOSITY(level));
 
 	return flags;
 }
@@ -117,22 +116,14 @@ static u32 guc_ctl_log_params_flags(struct xe_guc *guc)
 	BUILD_BUG_ON(!CAPTURE_BUFFER_SIZE);
 	BUILD_BUG_ON(!IS_ALIGNED(CAPTURE_BUFFER_SIZE, CAPTURE_UNIT));
 
-	BUILD_BUG_ON((CRASH_BUFFER_SIZE / LOG_UNIT - 1) >
-			(GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT));
-	BUILD_BUG_ON((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) >
-			(GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT));
-	BUILD_BUG_ON((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) >
-			(GUC_LOG_CAPTURE_MASK >> GUC_LOG_CAPTURE_SHIFT));
-
 	flags = GUC_LOG_VALID |
 		GUC_LOG_NOTIFY_ON_HALF_FULL |
 		CAPTURE_FLAG |
 		LOG_FLAG |
-		((CRASH_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_CRASH_SHIFT) |
-		((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_DEBUG_SHIFT) |
-		((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) <<
-		 GUC_LOG_CAPTURE_SHIFT) |
-		(offset << GUC_LOG_BUF_ADDR_SHIFT);
+		FIELD_PREP(GUC_LOG_CRASH, CRASH_BUFFER_SIZE / LOG_UNIT - 1) |
+		FIELD_PREP(GUC_LOG_DEBUG, DEBUG_BUFFER_SIZE / LOG_UNIT - 1) |
+		FIELD_PREP(GUC_LOG_CAPTURE, CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) |
+		FIELD_PREP(GUC_LOG_BUF_ADDR, offset);
 
 	#undef LOG_UNIT
 	#undef LOG_FLAG
@@ -145,7 +136,7 @@ static u32 guc_ctl_log_params_flags(struct xe_guc *guc)
 static u32 guc_ctl_ads_flags(struct xe_guc *guc)
 {
 	u32 ads = guc_bo_ggtt_addr(guc, guc->ads.bo) >> PAGE_SHIFT;
-	u32 flags = ads << GUC_ADS_ADDR_SHIFT;
+	u32 flags = FIELD_PREP(GUC_ADS_ADDR, ads);
 
 	return flags;
 }
diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
index 6f57578b07cb..b05646cb4fb1 100644
--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
@@ -84,13 +84,10 @@ struct guc_update_exec_queue_policy {
 #define   GUC_LOG_NOTIFY_ON_HALF_FULL	BIT(1)
 #define   GUC_LOG_CAPTURE_ALLOC_UNITS	BIT(2)
 #define   GUC_LOG_LOG_ALLOC_UNITS	BIT(3)
-#define   GUC_LOG_CRASH_SHIFT		4
-#define   GUC_LOG_CRASH_MASK		(0x3 << GUC_LOG_CRASH_SHIFT)
-#define   GUC_LOG_DEBUG_SHIFT		6
-#define   GUC_LOG_DEBUG_MASK	        (0xF << GUC_LOG_DEBUG_SHIFT)
-#define   GUC_LOG_CAPTURE_SHIFT		10
-#define   GUC_LOG_CAPTURE_MASK	        (0x3 << GUC_LOG_CAPTURE_SHIFT)
-#define   GUC_LOG_BUF_ADDR_SHIFT	12
+#define   GUC_LOG_CRASH			REG_GENMASK(5, 4)
+#define   GUC_LOG_DEBUG			REG_GENMASK(9, 6)
+#define   GUC_LOG_CAPTURE		REG_GENMASK(11, 10)
+#define   GUC_LOG_BUF_ADDR		REG_GENMASK(31, 12)
 
 #define GUC_CTL_WA			1
 #define   GUC_WA_GAM_CREDITS		BIT(10)
@@ -110,21 +107,14 @@ struct guc_update_exec_queue_policy {
 #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
 
 #define GUC_CTL_DEBUG			3
-#define   GUC_LOG_VERBOSITY_SHIFT	0
-#define   GUC_LOG_VERBOSITY_LOW		(0 << GUC_LOG_VERBOSITY_SHIFT)
-#define   GUC_LOG_VERBOSITY_MED		(1 << GUC_LOG_VERBOSITY_SHIFT)
-#define   GUC_LOG_VERBOSITY_HIGH	(2 << GUC_LOG_VERBOSITY_SHIFT)
-#define   GUC_LOG_VERBOSITY_ULTRA	(3 << GUC_LOG_VERBOSITY_SHIFT)
-#define	  GUC_LOG_VERBOSITY_MIN		0
+#define   GUC_LOG_VERBOSITY		REG_GENMASK(1, 0)
 #define	  GUC_LOG_VERBOSITY_MAX		3
-#define	  GUC_LOG_VERBOSITY_MASK	0x0000000f
-#define	  GUC_LOG_DESTINATION_MASK	(3 << 4)
-#define   GUC_LOG_DISABLED		(1 << 6)
-#define   GUC_PROFILE_ENABLED		(1 << 7)
+#define	  GUC_LOG_DESTINATION		REG_GENMASK(5, 4)
+#define   GUC_LOG_DISABLED		BIT(6)
+#define   GUC_PROFILE_ENABLED		BIT(7)
 
 #define GUC_CTL_ADS			4
-#define   GUC_ADS_ADDR_SHIFT		1
-#define   GUC_ADS_ADDR_MASK		(0xFFFFF << GUC_ADS_ADDR_SHIFT)
+#define   GUC_ADS_ADDR			REG_GENMASK(21, 1)
 
 #define GUC_CTL_DEVID			5
 
-- 
2.49.0

[PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target

[John.C.Harrison]

From: John Harrison <John.C.Harrison@Intel.com>

The GuC has an option to write log data via NPK. This is basically a
magic IO address that GuC writes arbitrary data to and which can be
logged by a suitable hardware logger. This can allow retrieval of the
GuC log in hardware debug environments even when the system as a whole
dies horribly.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 drivers/gpu/drm/xe/xe_configfs.c | 61 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_configfs.h |  3 ++
 drivers/gpu/drm/xe/xe_guc.c      |  5 +++
 3 files changed, 69 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
index 8ec1ff1e4e80..9fbd7e2ab152 100644
--- a/drivers/gpu/drm/xe/xe_configfs.c
+++ b/drivers/gpu/drm/xe/xe_configfs.c
@@ -77,6 +77,17 @@
  * available for migrations, but it's disabled. This is intended for debugging
  * purposes only.
  *
+ * GuC log target:
+ * ---------------
+ *
+ * Specify the target for GuC firmware logging:
+ *   0 = memory
+ *   1 = NPK
+ *   2 = memory + NPK
+ *
+ * Note that logging via NPK (North Peak) is only useful if some kind of hardware
+ * debugger is attached that can save out the NPK stream externally.
+ *
  * Remove devices
  * ==============
  *
@@ -90,6 +101,7 @@ struct xe_config_device {
 
 	bool survivability_mode;
 	u64 engines_allowed;
+	u32 guc_log_target;
 
 	/* protects attributes */
 	struct mutex lock;
@@ -226,12 +238,38 @@ static ssize_t engines_allowed_store(struct config_item *item, const char *page,
 	return len;
 }
 
+static ssize_t guc_log_target_show(struct config_item *item, char *page)
+{
+	struct xe_config_device *dev = to_xe_config_device(item);
+
+	return sprintf(page, "%d\n", dev->guc_log_target);
+}
+
+static ssize_t guc_log_target_store(struct config_item *item, const char *page, size_t len)
+{
+	struct xe_config_device *dev = to_xe_config_device(item);
+	u32 guc_log_target;
+	int ret;
+
+	ret = kstrtou32(page, 0, &guc_log_target);
+	if (ret)
+		return ret;
+
+	mutex_lock(&dev->lock);
+	dev->guc_log_target = guc_log_target;
+	mutex_unlock(&dev->lock);
+
+	return len;
+}
+
 CONFIGFS_ATTR(, survivability_mode);
 CONFIGFS_ATTR(, engines_allowed);
+CONFIGFS_ATTR(, guc_log_target);
 
 static struct configfs_attribute *xe_config_device_attrs[] = {
 	&attr_survivability_mode,
 	&attr_engines_allowed,
+	&attr_guc_log_target,
 	NULL,
 };
 
@@ -386,6 +424,29 @@ u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev)
 	return engines_allowed;
 }
 
+/**
+ * xe_configfs_get_guc_log_target - get configfs GuC log target attribute
+ * @pdev: pci device
+ *
+ * find the configfs group that belongs to the pci device and return
+ * the GuC log target attribute
+ *
+ * Return: GuC log target if config group is found, false otherwise
+ */
+u32 xe_configfs_get_guc_log_target(struct pci_dev *pdev)
+{
+	struct xe_config_device *dev = configfs_find_group(pdev);
+	u32 guc_log_target;
+
+	if (!dev)
+		return false;
+
+	guc_log_target = dev->guc_log_target;
+	config_item_put(&dev->group.cg_item);
+
+	return guc_log_target;
+}
+
 int __init xe_configfs_init(void)
 {
 	struct config_group *root = &xe_configfs.su_group;
diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h
index fb8764008089..97f9ad0f9495 100644
--- a/drivers/gpu/drm/xe/xe_configfs.h
+++ b/drivers/gpu/drm/xe/xe_configfs.h
@@ -16,12 +16,15 @@ void xe_configfs_exit(void);
 bool xe_configfs_get_survivability_mode(struct pci_dev *pdev);
 void xe_configfs_clear_survivability_mode(struct pci_dev *pdev);
 u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev);
+u32 xe_configfs_get_guc_log_target(struct pci_dev *pdev);
 #else
 static inline int xe_configfs_init(void) { return 0; }
 static inline void xe_configfs_exit(void) { }
 static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pdev) { return false; }
 static inline void xe_configfs_clear_survivability_mode(struct pci_dev *pdev) { }
 static inline u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev) { return U64_MAX; }
+static inline u32 xe_configfs_get_guc_log_target(struct pci_dev *pdev) { return 0; }
+
 #endif
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index 8fac3c518975..53ef93e162d2 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -16,6 +16,7 @@
 #include "regs/xe_guc_regs.h"
 #include "regs/xe_irq_regs.h"
 #include "xe_bo.h"
+#include "xe_configfs.h"
 #include "xe_device.h"
 #include "xe_force_wake.h"
 #include "xe_gt.h"
@@ -67,6 +68,7 @@ static u32 guc_bo_ggtt_addr(struct xe_guc *guc,
 
 static u32 guc_ctl_debug_flags(struct xe_guc *guc)
 {
+	u32 target = xe_configfs_get_guc_log_target(to_pci_dev(guc_to_xe(guc)->drm.dev));
 	u32 level = xe_guc_log_get_level(&guc->log);
 	u32 flags = 0;
 
@@ -75,6 +77,9 @@ static u32 guc_ctl_debug_flags(struct xe_guc *guc)
 	else
 		flags |= FIELD_PREP(GUC_LOG_VERBOSITY, GUC_LOG_LEVEL_TO_VERBOSITY(level));
 
+	if (target)
+		flags |= FIELD_PREP(GUC_LOG_DESTINATION, target);
+
 	return flags;
 }
 
-- 
2.49.0

✓ CI.KUnit: success for Clean up of GuC init data macros & add extra log option

[Patchwork]

== Series Details ==

Series: Clean up of GuC init data macros & add extra log option
URL   : https://patchwork.freedesktop.org/series/152030/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[21:26:03] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:26:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:26:34] Starting KUnit Kernel (1/1)...
[21:26:34] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:26:34] ================== guc_buf (11 subtests) ===================
[21:26:34] [PASSED] test_smallest
[21:26:34] [PASSED] test_largest
[21:26:34] [PASSED] test_granular
[21:26:34] [PASSED] test_unique
[21:26:34] [PASSED] test_overlap
[21:26:34] [PASSED] test_reusable
[21:26:34] [PASSED] test_too_big
[21:26:34] [PASSED] test_flush
[21:26:34] [PASSED] test_lookup
[21:26:34] [PASSED] test_data
[21:26:34] [PASSED] test_class
[21:26:34] ===================== [PASSED] guc_buf =====================
[21:26:34] =================== guc_dbm (7 subtests) ===================
[21:26:34] [PASSED] test_empty
[21:26:34] [PASSED] test_default
[21:26:34] ======================== test_size  ========================
[21:26:34] [PASSED] 4
[21:26:34] [PASSED] 8
[21:26:34] [PASSED] 32
[21:26:34] [PASSED] 256
[21:26:34] ==================== [PASSED] test_size ====================
[21:26:34] ======================= test_reuse  ========================
[21:26:34] [PASSED] 4
[21:26:34] [PASSED] 8
[21:26:34] [PASSED] 32
[21:26:34] [PASSED] 256
[21:26:34] =================== [PASSED] test_reuse ====================
[21:26:34] =================== test_range_overlap  ====================
[21:26:34] [PASSED] 4
[21:26:34] [PASSED] 8
[21:26:34] [PASSED] 32
[21:26:34] [PASSED] 256
[21:26:34] =============== [PASSED] test_range_overlap ================
[21:26:34] =================== test_range_compact  ====================
[21:26:34] [PASSED] 4
[21:26:34] [PASSED] 8
[21:26:34] [PASSED] 32
[21:26:34] [PASSED] 256
[21:26:34] =============== [PASSED] test_range_compact ================
[21:26:34] ==================== test_range_spare  =====================
[21:26:34] [PASSED] 4
[21:26:34] [PASSED] 8
[21:26:34] [PASSED] 32
[21:26:34] [PASSED] 256
[21:26:34] ================ [PASSED] test_range_spare =================
[21:26:34] ===================== [PASSED] guc_dbm =====================
[21:26:34] =================== guc_idm (6 subtests) ===================
[21:26:34] [PASSED] bad_init
[21:26:34] [PASSED] no_init
[21:26:34] [PASSED] init_fini
[21:26:34] [PASSED] check_used
[21:26:34] [PASSED] check_quota
[21:26:34] [PASSED] check_all
[21:26:34] ===================== [PASSED] guc_idm =====================
[21:26:34] ================== no_relay (3 subtests) ===================
[21:26:34] [PASSED] xe_drops_guc2pf_if_not_ready
[21:26:34] [PASSED] xe_drops_guc2vf_if_not_ready
[21:26:34] [PASSED] xe_rejects_send_if_not_ready
[21:26:34] ==================== [PASSED] no_relay =====================
[21:26:34] ================== pf_relay (14 subtests) ==================
[21:26:34] [PASSED] pf_rejects_guc2pf_too_short
[21:26:34] [PASSED] pf_rejects_guc2pf_too_long
[21:26:34] [PASSED] pf_rejects_guc2pf_no_payload
[21:26:34] [PASSED] pf_fails_no_payload
[21:26:34] [PASSED] pf_fails_bad_origin
[21:26:34] [PASSED] pf_fails_bad_type
[21:26:34] [PASSED] pf_txn_reports_error
[21:26:34] [PASSED] pf_txn_sends_pf2guc
[21:26:34] [PASSED] pf_sends_pf2guc
[21:26:34] [SKIPPED] pf_loopback_nop
[21:26:34] [SKIPPED] pf_loopback_echo
[21:26:34] [SKIPPED] pf_loopback_fail
[21:26:34] [SKIPPED] pf_loopback_busy
[21:26:34] [SKIPPED] pf_loopback_retry
[21:26:34] ==================== [PASSED] pf_relay =====================
[21:26:34] ================== vf_relay (3 subtests) ===================
[21:26:34] [PASSED] vf_rejects_guc2vf_too_short
[21:26:34] [PASSED] vf_rejects_guc2vf_too_long
[21:26:34] [PASSED] vf_rejects_guc2vf_no_payload
[21:26:34] ==================== [PASSED] vf_relay =====================
[21:26:34] ===================== lmtt (1 subtest) =====================
[21:26:34] ======================== test_ops  =========================
[21:26:34] [PASSED] 2-level
[21:26:34] [PASSED] multi-level
[21:26:34] ==================== [PASSED] test_ops =====================
[21:26:34] ====================== [PASSED] lmtt =======================
[21:26:34] ================= pf_service (11 subtests) =================
[21:26:34] [PASSED] pf_negotiate_any
[21:26:34] [PASSED] pf_negotiate_base_match
[21:26:34] [PASSED] pf_negotiate_base_newer
[21:26:34] [PASSED] pf_negotiate_base_next
[21:26:34] [SKIPPED] pf_negotiate_base_older
[21:26:34] [PASSED] pf_negotiate_base_prev
[21:26:34] [PASSED] pf_negotiate_latest_match
[21:26:34] [PASSED] pf_negotiate_latest_newer
[21:26:34] [PASSED] pf_negotiate_latest_next
[21:26:34] [SKIPPED] pf_negotiate_latest_older
[21:26:34] [SKIPPED] pf_negotiate_latest_prev
[21:26:34] =================== [PASSED] pf_service ====================
[21:26:34] =================== xe_mocs (2 subtests) ===================
[21:26:34] ================ xe_live_mocs_kernel_kunit  ================
[21:26:34] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[21:26:34] ================ xe_live_mocs_reset_kunit  =================
[21:26:34] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[21:26:34] ==================== [SKIPPED] xe_mocs =====================
[21:26:34] ================= xe_migrate (2 subtests) ==================
[21:26:34] ================= xe_migrate_sanity_kunit  =================
[21:26:34] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[21:26:34] ================== xe_validate_ccs_kunit  ==================
[21:26:34] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[21:26:34] =================== [SKIPPED] xe_migrate ===================
[21:26:34] ================== xe_dma_buf (1 subtest) ==================
[21:26:34] ==================== xe_dma_buf_kunit  =====================
[21:26:34] ================ [SKIPPED] xe_dma_buf_kunit ================
[21:26:34] =================== [SKIPPED] xe_dma_buf ===================
[21:26:34] ================= xe_bo_shrink (1 subtest) =================
[21:26:34] =================== xe_bo_shrink_kunit  ====================
[21:26:34] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[21:26:34] ================== [SKIPPED] xe_bo_shrink ==================
[21:26:34] ==================== xe_bo (2 subtests) ====================
[21:26:34] ================== xe_ccs_migrate_kunit  ===================
[21:26:34] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[21:26:34] ==================== xe_bo_evict_kunit  ====================
[21:26:34] =============== [SKIPPED] xe_bo_evict_kunit ================
[21:26:34] ===================== [SKIPPED] xe_bo ======================
[21:26:34] ==================== args (11 subtests) ====================
[21:26:34] [PASSED] count_args_test
[21:26:34] [PASSED] call_args_example
[21:26:34] [PASSED] call_args_test
[21:26:34] [PASSED] drop_first_arg_example
[21:26:34] [PASSED] drop_first_arg_test
[21:26:34] [PASSED] first_arg_example
[21:26:34] [PASSED] first_arg_test
[21:26:34] [PASSED] last_arg_example
[21:26:34] [PASSED] last_arg_test
[21:26:34] [PASSED] pick_arg_example
[21:26:34] [PASSED] sep_comma_example
[21:26:34] ====================== [PASSED] args =======================
[21:26:34] =================== xe_pci (3 subtests) ====================
[21:26:34] ==================== check_graphics_ip  ====================
[21:26:34] [PASSED] 12.70 Xe_LPG
[21:26:34] [PASSED] 12.71 Xe_LPG
[21:26:34] [PASSED] 12.74 Xe_LPG+
[21:26:34] [PASSED] 20.01 Xe2_HPG
[21:26:34] [PASSED] 20.02 Xe2_HPG
[21:26:34] [PASSED] 20.04 Xe2_LPG
[21:26:34] [PASSED] 30.00 Xe3_LPG
[21:26:34] [PASSED] 30.01 Xe3_LPG
[21:26:34] [PASSED] 30.03 Xe3_LPG
[21:26:34] ================ [PASSED] check_graphics_ip ================
[21:26:34] ===================== check_media_ip  ======================
[21:26:34] [PASSED] 13.00 Xe_LPM+
[21:26:34] [PASSED] 13.01 Xe2_HPM
[21:26:34] [PASSED] 20.00 Xe2_LPM
[21:26:34] [PASSED] 30.00 Xe3_LPM
[21:26:34] [PASSED] 30.02 Xe3_LPM
[21:26:34] ================= [PASSED] check_media_ip ==================
[21:26:34] ================= check_platform_gt_count  =================
[21:26:34] [PASSED] 0x9A60 (TIGERLAKE)
[21:26:34] [PASSED] 0x9A68 (TIGERLAKE)
[21:26:34] [PASSED] 0x9A70 (TIGERLAKE)
[21:26:34] [PASSED] 0x9A40 (TIGERLAKE)
[21:26:34] [PASSED] 0x9A49 (TIGERLAKE)
[21:26:34] [PASSED] 0x9A59 (TIGERLAKE)
[21:26:34] [PASSED] 0x9A78 (TIGERLAKE)
[21:26:34] [PASSED] 0x9AC0 (TIGERLAKE)
[21:26:34] [PASSED] 0x9AC9 (TIGERLAKE)
[21:26:34] [PASSED] 0x9AD9 (TIGERLAKE)
[21:26:34] [PASSED] 0x9AF8 (TIGERLAKE)
[21:26:34] [PASSED] 0x4C80 (ROCKETLAKE)
[21:26:34] [PASSED] 0x4C8A (ROCKETLAKE)
[21:26:34] [PASSED] 0x4C8B (ROCKETLAKE)
[21:26:34] [PASSED] 0x4C8C (ROCKETLAKE)
[21:26:34] [PASSED] 0x4C90 (ROCKETLAKE)
[21:26:34] [PASSED] 0x4C9A (ROCKETLAKE)
[21:26:34] [PASSED] 0x4680 (ALDERLAKE_S)
[21:26:34] [PASSED] 0x4682 (ALDERLAKE_S)
[21:26:34] [PASSED] 0x4688 (ALDERLAKE_S)
[21:26:34] [PASSED] 0x468A (ALDERLAKE_S)
[21:26:34] [PASSED] 0x468B (ALDERLAKE_S)
[21:26:34] [PASSED] 0x4690 (ALDERLAKE_S)
[21:26:34] [PASSED] 0x4692 (ALDERLAKE_S)
[21:26:34] [PASSED] 0x4693 (ALDERLAKE_S)
[21:26:34] [PASSED] 0x46A0 (ALDERLAKE_P)
[21:26:34] [PASSED] 0x46A1 (ALDERLAKE_P)
[21:26:34] [PASSED] 0x46A2 (ALDERLAKE_P)
[21:26:34] [PASSED] 0x46A3 (ALDERLAKE_P)
[21:26:34] [PASSED] 0x46A6 (ALDERLAKE_P)
[21:26:34] [PASSED] 0x46A8 (ALDERLAKE_P)
[21:26:34] [PASSED] 0x46AA (ALDERLAKE_P)
[21:26:34] [PASSED] 0x462A (ALDERLAKE_P)
[21:26:34] [PASSED] 0x4626 (ALDERLAKE_P)
[21:26:34] [PASSED] 0x4628 (ALDERLAKE_P)
[21:26:34] [PASSED] 0x46B0 (ALDERLAKE_P)
[21:26:34] [PASSED] 0x46B1 (ALDERLAKE_P)
[21:26:34] [PASSED] 0x46B2 (ALDERLAKE_P)
[21:26:34] [PASSED] 0x46B3 (ALDERLAKE_P)
[21:26:34] [PASSED] 0x46C0 (ALDERLAKE_P)
[21:26:34] [PASSED] 0x46C1 (ALDERLAKE_P)
[21:26:34] [PASSED] 0x46C2 (ALDERLAKE_P)
[21:26:34] [PASSED] 0x46C3 (ALDERLAKE_P)
[21:26:34] [PASSED] 0x46D0 (ALDERLAKE_N)
[21:26:34] [PASSED] 0x46D1 (ALDERLAKE_N)
[21:26:34] [PASSED] 0x46D2 (ALDERLAKE_N)
[21:26:34] [PASSED] 0x46D3 (ALDERLAKE_N)
[21:26:34] [PASSED] 0x46D4 (ALDERLAKE_N)
[21:26:34] [PASSED] 0xA721 (ALDERLAKE_P)
[21:26:34] [PASSED] 0xA7A1 (ALDERLAKE_P)
[21:26:34] [PASSED] 0xA7A9 (ALDERLAKE_P)
[21:26:34] [PASSED] 0xA7AC (ALDERLAKE_P)
[21:26:34] [PASSED] 0xA7AD (ALDERLAKE_P)
[21:26:34] [PASSED] 0xA720 (ALDERLAKE_P)
[21:26:34] [PASSED] 0xA7A0 (ALDERLAKE_P)
[21:26:34] [PASSED] 0xA7A8 (ALDERLAKE_P)
[21:26:34] [PASSED] 0xA7AA (ALDERLAKE_P)
[21:26:34] [PASSED] 0xA7AB (ALDERLAKE_P)
[21:26:34] [PASSED] 0xA780 (ALDERLAKE_S)
[21:26:34] [PASSED] 0xA781 (ALDERLAKE_S)
[21:26:34] [PASSED] 0xA782 (ALDERLAKE_S)
[21:26:34] [PASSED] 0xA783 (ALDERLAKE_S)
[21:26:34] [PASSED] 0xA788 (ALDERLAKE_S)
[21:26:34] [PASSED] 0xA789 (ALDERLAKE_S)
[21:26:34] [PASSED] 0xA78A (ALDERLAKE_S)
[21:26:34] [PASSED] 0xA78B (ALDERLAKE_S)
[21:26:34] [PASSED] 0x4905 (DG1)
[21:26:34] [PASSED] 0x4906 (DG1)
[21:26:34] [PASSED] 0x4907 (DG1)
[21:26:34] [PASSED] 0x4908 (DG1)
[21:26:34] [PASSED] 0x4909 (DG1)
[21:26:34] [PASSED] 0x56C0 (DG2)
[21:26:34] [PASSED] 0x56C2 (DG2)
[21:26:34] [PASSED] 0x56C1 (DG2)
[21:26:34] [PASSED] 0x7D51 (METEORLAKE)
[21:26:34] [PASSED] 0x7DD1 (METEORLAKE)
[21:26:34] [PASSED] 0x7D41 (METEORLAKE)
[21:26:34] [PASSED] 0x7D67 (METEORLAKE)
[21:26:34] [PASSED] 0xB640 (METEORLAKE)
[21:26:34] [PASSED] 0x56A0 (DG2)
[21:26:34] [PASSED] 0x56A1 (DG2)
[21:26:34] [PASSED] 0x56A2 (DG2)
[21:26:34] [PASSED] 0x56BE (DG2)
[21:26:34] [PASSED] 0x56BF (DG2)
[21:26:34] [PASSED] 0x5690 (DG2)
[21:26:34] [PASSED] 0x5691 (DG2)
[21:26:34] [PASSED] 0x5692 (DG2)
[21:26:34] [PASSED] 0x56A5 (DG2)
[21:26:34] [PASSED] 0x56A6 (DG2)
[21:26:34] [PASSED] 0x56B0 (DG2)
[21:26:34] [PASSED] 0x56B1 (DG2)
[21:26:34] [PASSED] 0x56BA (DG2)
[21:26:34] [PASSED] 0x56BB (DG2)
[21:26:34] [PASSED] 0x56BC (DG2)
[21:26:34] [PASSED] 0x56BD (DG2)
[21:26:34] [PASSED] 0x5693 (DG2)
[21:26:34] [PASSED] 0x5694 (DG2)
[21:26:34] [PASSED] 0x5695 (DG2)
[21:26:34] [PASSED] 0x56A3 (DG2)
[21:26:34] [PASSED] 0x56A4 (DG2)
[21:26:34] [PASSED] 0x56B2 (DG2)
[21:26:34] [PASSED] 0x56B3 (DG2)
[21:26:34] [PASSED] 0x5696 (DG2)
[21:26:34] [PASSED] 0x5697 (DG2)
[21:26:34] [PASSED] 0xB69 (PVC)
[21:26:34] [PASSED] 0xB6E (PVC)
[21:26:34] [PASSED] 0xBD4 (PVC)
[21:26:34] [PASSED] 0xBD5 (PVC)
[21:26:34] [PASSED] 0xBD6 (PVC)
[21:26:34] [PASSED] 0xBD7 (PVC)
[21:26:34] [PASSED] 0xBD8 (PVC)
[21:26:34] [PASSED] 0xBD9 (PVC)
[21:26:34] [PASSED] 0xBDA (PVC)
[21:26:34] [PASSED] 0xBDB (PVC)
[21:26:34] [PASSED] 0xBE0 (PVC)
[21:26:34] [PASSED] 0xBE1 (PVC)
[21:26:34] [PASSED] 0xBE5 (PVC)
[21:26:34] [PASSED] 0x7D40 (METEORLAKE)
[21:26:34] [PASSED] 0x7D45 (METEORLAKE)
[21:26:34] [PASSED] 0x7D55 (METEORLAKE)
[21:26:34] [PASSED] 0x7D60 (METEORLAKE)
[21:26:34] [PASSED] 0x7DD5 (METEORLAKE)
[21:26:34] [PASSED] 0x6420 (LUNARLAKE)
[21:26:34] [PASSED] 0x64A0 (LUNARLAKE)
[21:26:34] [PASSED] 0x64B0 (LUNARLAKE)
[21:26:34] [PASSED] 0xE202 (BATTLEMAGE)
[21:26:34] [PASSED] 0xE209 (BATTLEMAGE)
[21:26:34] [PASSED] 0xE20B (BATTLEMAGE)
[21:26:34] [PASSED] 0xE20C (BATTLEMAGE)
[21:26:34] [PASSED] 0xE20D (BATTLEMAGE)
[21:26:34] [PASSED] 0xE210 (BATTLEMAGE)
[21:26:34] [PASSED] 0xE211 (BATTLEMAGE)
[21:26:34] [PASSED] 0xE212 (BATTLEMAGE)
[21:26:34] [PASSED] 0xE216 (BATTLEMAGE)
[21:26:34] [PASSED] 0xE220 (BATTLEMAGE)
[21:26:34] [PASSED] 0xE221 (BATTLEMAGE)
[21:26:34] [PASSED] 0xE222 (BATTLEMAGE)
[21:26:34] [PASSED] 0xE223 (BATTLEMAGE)
[21:26:34] [PASSED] 0xB080 (PANTHERLAKE)
[21:26:34] [PASSED] 0xB081 (PANTHERLAKE)
[21:26:34] [PASSED] 0xB082 (PANTHERLAKE)
[21:26:34] [PASSED] 0xB083 (PANTHERLAKE)
[21:26:34] [PASSED] 0xB084 (PANTHERLAKE)
[21:26:34] [PASSED] 0xB085 (PANTHERLAKE)
[21:26:34] [PASSED] 0xB086 (PANTHERLAKE)
[21:26:34] [PASSED] 0xB087 (PANTHERLAKE)
[21:26:34] [PASSED] 0xB08F (PANTHERLAKE)
[21:26:34] [PASSED] 0xB090 (PANTHERLAKE)
[21:26:34] [PASSED] 0xB0A0 (PANTHERLAKE)
[21:26:34] [PASSED] 0xB0B0 (PANTHERLAKE)
[21:26:34] [PASSED] 0xFD80 (PANTHERLAKE)
[21:26:34] [PASSED] 0xFD81 (PANTHERLAKE)
[21:26:34] ============= [PASSED] check_platform_gt_count =============
[21:26:34] ===================== [PASSED] xe_pci ======================
[21:26:34] =================== xe_rtp (2 subtests) ====================
[21:26:34] =============== xe_rtp_process_to_sr_tests  ================
[21:26:34] [PASSED] coalesce-same-reg
[21:26:34] [PASSED] no-match-no-add
[21:26:34] [PASSED] match-or
[21:26:34] [PASSED] match-or-xfail
[21:26:34] [PASSED] no-match-no-add-multiple-rules
[21:26:34] [PASSED] two-regs-two-entries
[21:26:34] [PASSED] clr-one-set-other
[21:26:34] [PASSED] set-field
[21:26:34] [PASSED] conflict-duplicate
[21:26:34] [PASSED] conflict-not-disjoint
[21:26:34] [PASSED] conflict-reg-type
[21:26:34] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[21:26:34] ================== xe_rtp_process_tests  ===================
[21:26:34] [PASSED] active1
[21:26:34] [PASSED] active2
[21:26:34] [PASSED] active-inactive
[21:26:34] [PASSED] inactive-active
[21:26:34] [PASSED] inactive-1st_or_active-inactive
[21:26:34] [PASSED] inactive-2nd_or_active-inactive
[21:26:34] [PASSED] inactive-last_or_active-inactive
[21:26:34] [PASSED] inactive-no_or_active-inactive
[21:26:34] ============== [PASSED] xe_rtp_process_tests ===============
[21:26:34] ===================== [PASSED] xe_rtp ======================
[21:26:34] ==================== xe_wa (1 subtest) =====================
[21:26:34] ======================== xe_wa_gt  =========================
[21:26:34] [PASSED] TIGERLAKE (B0)
[21:26:34] [PASSED] DG1 (A0)
[21:26:34] [PASSED] DG1 (B0)
[21:26:34] [PASSED] ALDERLAKE_S (A0)
[21:26:34] [PASSED] ALDERLAKE_S (B0)
[21:26:34] [PASSED] ALDERLAKE_S (C0)
[21:26:34] [PASSED] ALDERLAKE_S (D0)
[21:26:34] [PASSED] ALDERLAKE_P (A0)
[21:26:34] [PASSED] ALDERLAKE_P (B0)
[21:26:34] [PASSED] ALDERLAKE_P (C0)
[21:26:34] [PASSED] ALDERLAKE_S_RPLS (D0)
[21:26:34] [PASSED] ALDERLAKE_P_RPLU (E0)
[21:26:34] [PASSED] DG2_G10 (C0)
[21:26:34] [PASSED] DG2_G11 (B1)
[21:26:34] [PASSED] DG2_G12 (A1)
[21:26:34] [PASSED] METEORLAKE (g:A0, m:A0)
[21:26:34] [PASSED] METEORLAKE (g:A0, m:A0)
[21:26:34] [PASSED] METEORLAKE (g:A0, m:A0)
[21:26:34] [PASSED] LUNARLAKE (g:A0, m:A0)
[21:26:34] [PASSED] LUNARLAKE (g:B0, m:A0)
stty: 'standard input': Inappropriate ioctl for device
[21:26:34] [PASSED] BATTLEMAGE (g:A0, m:A1)
[21:26:34] ==================== [PASSED] xe_wa_gt =====================
[21:26:34] ====================== [PASSED] xe_wa ======================
[21:26:34] ============================================================
[21:26:34] Testing complete. Ran 297 tests: passed: 281, skipped: 16
[21:26:34] Elapsed time: 31.508s total, 4.188s configuring, 26.953s building, 0.313s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[21:26:34] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:26:36] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:26:57] Starting KUnit Kernel (1/1)...
[21:26:57] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:26:57] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[21:26:57] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[21:26:57] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[21:26:57] =========== drm_validate_clone_mode (2 subtests) ===========
[21:26:57] ============== drm_test_check_in_clone_mode  ===============
[21:26:57] [PASSED] in_clone_mode
[21:26:57] [PASSED] not_in_clone_mode
[21:26:57] ========== [PASSED] drm_test_check_in_clone_mode ===========
[21:26:57] =============== drm_test_check_valid_clones  ===============
[21:26:57] [PASSED] not_in_clone_mode
[21:26:57] [PASSED] valid_clone
[21:26:57] [PASSED] invalid_clone
[21:26:57] =========== [PASSED] drm_test_check_valid_clones ===========
[21:26:57] ============= [PASSED] drm_validate_clone_mode =============
[21:26:57] ============= drm_validate_modeset (1 subtest) =============
[21:26:57] [PASSED] drm_test_check_connector_changed_modeset
[21:26:57] ============== [PASSED] drm_validate_modeset ===============
[21:26:57] ====== drm_test_bridge_get_current_state (2 subtests) ======
[21:26:57] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[21:26:57] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[21:26:57] ======== [PASSED] drm_test_bridge_get_current_state ========
[21:26:57] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[21:26:57] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[21:26:57] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[21:26:57] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[21:26:57] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[21:26:57] ============== drm_bridge_alloc (2 subtests) ===============
[21:26:57] [PASSED] drm_test_drm_bridge_alloc_basic
[21:26:57] [PASSED] drm_test_drm_bridge_alloc_get_put
[21:26:57] ================ [PASSED] drm_bridge_alloc =================
[21:26:57] ================== drm_buddy (7 subtests) ==================
[21:26:57] [PASSED] drm_test_buddy_alloc_limit
[21:26:57] [PASSED] drm_test_buddy_alloc_optimistic
[21:26:57] [PASSED] drm_test_buddy_alloc_pessimistic
[21:26:57] [PASSED] drm_test_buddy_alloc_pathological
[21:26:57] [PASSED] drm_test_buddy_alloc_contiguous
[21:26:57] [PASSED] drm_test_buddy_alloc_clear
[21:26:57] [PASSED] drm_test_buddy_alloc_range_bias
[21:26:57] ==================== [PASSED] drm_buddy ====================
[21:26:57] ============= drm_cmdline_parser (40 subtests) =============
[21:26:57] [PASSED] drm_test_cmdline_force_d_only
[21:26:57] [PASSED] drm_test_cmdline_force_D_only_dvi
[21:26:57] [PASSED] drm_test_cmdline_force_D_only_hdmi
[21:26:57] [PASSED] drm_test_cmdline_force_D_only_not_digital
[21:26:57] [PASSED] drm_test_cmdline_force_e_only
[21:26:57] [PASSED] drm_test_cmdline_res
[21:26:57] [PASSED] drm_test_cmdline_res_vesa
[21:26:57] [PASSED] drm_test_cmdline_res_vesa_rblank
[21:26:57] [PASSED] drm_test_cmdline_res_rblank
[21:26:57] [PASSED] drm_test_cmdline_res_bpp
[21:26:57] [PASSED] drm_test_cmdline_res_refresh
[21:26:57] [PASSED] drm_test_cmdline_res_bpp_refresh
[21:26:57] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[21:26:57] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[21:26:57] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[21:26:57] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[21:26:57] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[21:26:57] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[21:26:57] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[21:26:57] [PASSED] drm_test_cmdline_res_margins_force_on
[21:26:57] [PASSED] drm_test_cmdline_res_vesa_margins
[21:26:57] [PASSED] drm_test_cmdline_name
[21:26:57] [PASSED] drm_test_cmdline_name_bpp
[21:26:57] [PASSED] drm_test_cmdline_name_option
[21:26:57] [PASSED] drm_test_cmdline_name_bpp_option
[21:26:57] [PASSED] drm_test_cmdline_rotate_0
[21:26:57] [PASSED] drm_test_cmdline_rotate_90
[21:26:57] [PASSED] drm_test_cmdline_rotate_180
[21:26:57] [PASSED] drm_test_cmdline_rotate_270
[21:26:57] [PASSED] drm_test_cmdline_hmirror
[21:26:57] [PASSED] drm_test_cmdline_vmirror
[21:26:57] [PASSED] drm_test_cmdline_margin_options
[21:26:57] [PASSED] drm_test_cmdline_multiple_options
[21:26:57] [PASSED] drm_test_cmdline_bpp_extra_and_option
[21:26:57] [PASSED] drm_test_cmdline_extra_and_option
[21:26:57] [PASSED] drm_test_cmdline_freestanding_options
[21:26:57] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[21:26:57] [PASSED] drm_test_cmdline_panel_orientation
[21:26:57] ================ drm_test_cmdline_invalid  =================
[21:26:57] [PASSED] margin_only
[21:26:57] [PASSED] interlace_only
[21:26:57] [PASSED] res_missing_x
[21:26:57] [PASSED] res_missing_y
[21:26:57] [PASSED] res_bad_y
[21:26:57] [PASSED] res_missing_y_bpp
[21:26:57] [PASSED] res_bad_bpp
[21:26:57] [PASSED] res_bad_refresh
[21:26:57] [PASSED] res_bpp_refresh_force_on_off
[21:26:57] [PASSED] res_invalid_mode
[21:26:57] [PASSED] res_bpp_wrong_place_mode
[21:26:57] [PASSED] name_bpp_refresh
[21:26:57] [PASSED] name_refresh
[21:26:57] [PASSED] name_refresh_wrong_mode
[21:26:57] [PASSED] name_refresh_invalid_mode
[21:26:57] [PASSED] rotate_multiple
[21:26:57] [PASSED] rotate_invalid_val
[21:26:57] [PASSED] rotate_truncated
[21:26:57] [PASSED] invalid_option
[21:26:57] [PASSED] invalid_tv_option
[21:26:57] [PASSED] truncated_tv_option
[21:26:57] ============ [PASSED] drm_test_cmdline_invalid =============
[21:26:57] =============== drm_test_cmdline_tv_options  ===============
[21:26:57] [PASSED] NTSC
[21:26:57] [PASSED] NTSC_443
[21:26:57] [PASSED] NTSC_J
[21:26:57] [PASSED] PAL
[21:26:57] [PASSED] PAL_M
[21:26:57] [PASSED] PAL_N
[21:26:57] [PASSED] SECAM
[21:26:57] [PASSED] MONO_525
[21:26:57] [PASSED] MONO_625
[21:26:57] =========== [PASSED] drm_test_cmdline_tv_options ===========
[21:26:57] =============== [PASSED] drm_cmdline_parser ================
[21:26:57] ========== drmm_connector_hdmi_init (20 subtests) ==========
[21:26:57] [PASSED] drm_test_connector_hdmi_init_valid
[21:26:57] [PASSED] drm_test_connector_hdmi_init_bpc_8
[21:26:57] [PASSED] drm_test_connector_hdmi_init_bpc_10
[21:26:57] [PASSED] drm_test_connector_hdmi_init_bpc_12
[21:26:57] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[21:26:57] [PASSED] drm_test_connector_hdmi_init_bpc_null
[21:26:57] [PASSED] drm_test_connector_hdmi_init_formats_empty
[21:26:57] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[21:26:57] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[21:26:57] [PASSED] supported_formats=0x9 yuv420_allowed=1
[21:26:57] [PASSED] supported_formats=0x9 yuv420_allowed=0
[21:26:57] [PASSED] supported_formats=0x3 yuv420_allowed=1
[21:26:57] [PASSED] supported_formats=0x3 yuv420_allowed=0
[21:26:57] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:26:57] [PASSED] drm_test_connector_hdmi_init_null_ddc
[21:26:57] [PASSED] drm_test_connector_hdmi_init_null_product
[21:26:57] [PASSED] drm_test_connector_hdmi_init_null_vendor
[21:26:57] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[21:26:57] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[21:26:57] [PASSED] drm_test_connector_hdmi_init_product_valid
[21:26:57] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[21:26:57] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[21:26:57] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[21:26:57] ========= drm_test_connector_hdmi_init_type_valid  =========
[21:26:57] [PASSED] HDMI-A
[21:26:57] [PASSED] HDMI-B
[21:26:57] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[21:26:57] ======== drm_test_connector_hdmi_init_type_invalid  ========
[21:26:57] [PASSED] Unknown
[21:26:57] [PASSED] VGA
[21:26:57] [PASSED] DVI-I
[21:26:57] [PASSED] DVI-D
[21:26:57] [PASSED] DVI-A
[21:26:57] [PASSED] Composite
[21:26:57] [PASSED] SVIDEO
[21:26:57] [PASSED] LVDS
[21:26:57] [PASSED] Component
[21:26:57] [PASSED] DIN
[21:26:57] [PASSED] DP
[21:26:57] [PASSED] TV
[21:26:57] [PASSED] eDP
[21:26:57] [PASSED] Virtual
[21:26:57] [PASSED] DSI
[21:26:57] [PASSED] DPI
[21:26:57] [PASSED] Writeback
[21:26:57] [PASSED] SPI
[21:26:57] [PASSED] USB
[21:26:57] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[21:26:57] ============ [PASSED] drmm_connector_hdmi_init =============
[21:26:57] ============= drmm_connector_init (3 subtests) =============
[21:26:57] [PASSED] drm_test_drmm_connector_init
[21:26:57] [PASSED] drm_test_drmm_connector_init_null_ddc
[21:26:57] ========= drm_test_drmm_connector_init_type_valid  =========
[21:26:57] [PASSED] Unknown
[21:26:57] [PASSED] VGA
[21:26:57] [PASSED] DVI-I
[21:26:57] [PASSED] DVI-D
[21:26:57] [PASSED] DVI-A
[21:26:57] [PASSED] Composite
[21:26:57] [PASSED] SVIDEO
[21:26:57] [PASSED] LVDS
[21:26:57] [PASSED] Component
[21:26:57] [PASSED] DIN
[21:26:57] [PASSED] DP
[21:26:57] [PASSED] HDMI-A
[21:26:57] [PASSED] HDMI-B
[21:26:57] [PASSED] TV
[21:26:57] [PASSED] eDP
[21:26:57] [PASSED] Virtual
[21:26:57] [PASSED] DSI
[21:26:57] [PASSED] DPI
[21:26:57] [PASSED] Writeback
[21:26:57] [PASSED] SPI
[21:26:57] [PASSED] USB
[21:26:57] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[21:26:57] =============== [PASSED] drmm_connector_init ===============
[21:26:57] ========= drm_connector_dynamic_init (6 subtests) ==========
[21:26:57] [PASSED] drm_test_drm_connector_dynamic_init
[21:26:57] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[21:26:57] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[21:26:57] [PASSED] drm_test_drm_connector_dynamic_init_properties
[21:26:57] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[21:26:57] [PASSED] Unknown
[21:26:57] [PASSED] VGA
[21:26:57] [PASSED] DVI-I
[21:26:57] [PASSED] DVI-D
[21:26:57] [PASSED] DVI-A
[21:26:57] [PASSED] Composite
[21:26:57] [PASSED] SVIDEO
[21:26:57] [PASSED] LVDS
[21:26:57] [PASSED] Component
[21:26:57] [PASSED] DIN
[21:26:57] [PASSED] DP
[21:26:57] [PASSED] HDMI-A
[21:26:57] [PASSED] HDMI-B
[21:26:57] [PASSED] TV
[21:26:57] [PASSED] eDP
[21:26:57] [PASSED] Virtual
[21:26:57] [PASSED] DSI
[21:26:57] [PASSED] DPI
[21:26:57] [PASSED] Writeback
[21:26:57] [PASSED] SPI
[21:26:57] [PASSED] USB
[21:26:57] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[21:26:57] ======== drm_test_drm_connector_dynamic_init_name  =========
[21:26:57] [PASSED] Unknown
[21:26:57] [PASSED] VGA
[21:26:57] [PASSED] DVI-I
[21:26:57] [PASSED] DVI-D
[21:26:57] [PASSED] DVI-A
[21:26:57] [PASSED] Composite
[21:26:57] [PASSED] SVIDEO
[21:26:57] [PASSED] LVDS
[21:26:57] [PASSED] Component
[21:26:57] [PASSED] DIN
[21:26:57] [PASSED] DP
[21:26:57] [PASSED] HDMI-A
[21:26:57] [PASSED] HDMI-B
[21:26:57] [PASSED] TV
[21:26:57] [PASSED] eDP
[21:26:57] [PASSED] Virtual
[21:26:57] [PASSED] DSI
[21:26:57] [PASSED] DPI
[21:26:57] [PASSED] Writeback
[21:26:57] [PASSED] SPI
[21:26:57] [PASSED] USB
[21:26:57] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[21:26:57] =========== [PASSED] drm_connector_dynamic_init ============
[21:26:57] ==== drm_connector_dynamic_register_early (4 subtests) =====
[21:26:57] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[21:26:57] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[21:26:57] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[21:26:57] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[21:26:57] ====== [PASSED] drm_connector_dynamic_register_early =======
[21:26:57] ======= drm_connector_dynamic_register (7 subtests) ========
[21:26:57] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[21:26:57] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[21:26:57] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[21:26:57] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[21:26:57] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[21:26:57] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[21:26:57] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[21:26:57] ========= [PASSED] drm_connector_dynamic_register ==========
[21:26:57] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[21:26:57] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[21:26:57] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[21:26:57] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[21:26:57] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[21:26:57] ========== drm_test_get_tv_mode_from_name_valid  ===========
[21:26:57] [PASSED] NTSC
[21:26:57] [PASSED] NTSC-443
[21:26:57] [PASSED] NTSC-J
[21:26:57] [PASSED] PAL
[21:26:57] [PASSED] PAL-M
[21:26:57] [PASSED] PAL-N
[21:26:57] [PASSED] SECAM
[21:26:57] [PASSED] Mono
[21:26:57] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[21:26:57] [PASSED] drm_test_get_tv_mode_from_name_truncated
[21:26:57] ============ [PASSED] drm_get_tv_mode_from_name ============
[21:26:57] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[21:26:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[21:26:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[21:26:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[21:26:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[21:26:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[21:26:57] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[21:26:57] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[21:26:57] [PASSED] VIC 96
[21:26:57] [PASSED] VIC 97
[21:26:57] [PASSED] VIC 101
[21:26:57] [PASSED] VIC 102
[21:26:57] [PASSED] VIC 106
[21:26:57] [PASSED] VIC 107
[21:26:57] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[21:26:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[21:26:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[21:26:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[21:26:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[21:26:57] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[21:26:57] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[21:26:57] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[21:26:57] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[21:26:57] [PASSED] Automatic
[21:26:57] [PASSED] Full
[21:26:57] [PASSED] Limited 16:235
[21:26:57] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[21:26:57] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[21:26:57] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[21:26:57] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[21:26:57] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[21:26:57] [PASSED] RGB
[21:26:57] [PASSED] YUV 4:2:0
[21:26:57] [PASSED] YUV 4:2:2
[21:26:57] [PASSED] YUV 4:4:4
[21:26:57] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[21:26:57] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[21:26:57] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[21:26:57] ============= drm_damage_helper (21 subtests) ==============
[21:26:57] [PASSED] drm_test_damage_iter_no_damage
[21:26:57] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[21:26:57] [PASSED] drm_test_damage_iter_no_damage_src_moved
[21:26:57] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[21:26:57] [PASSED] drm_test_damage_iter_no_damage_not_visible
[21:26:57] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[21:26:57] [PASSED] drm_test_damage_iter_no_damage_no_fb
[21:26:57] [PASSED] drm_test_damage_iter_simple_damage
[21:26:57] [PASSED] drm_test_damage_iter_single_damage
[21:26:57] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[21:26:57] [PASSED] drm_test_damage_iter_single_damage_outside_src
[21:26:57] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[21:26:57] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[21:26:57] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[21:26:57] [PASSED] drm_test_damage_iter_single_damage_src_moved
[21:26:57] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[21:26:57] [PASSED] drm_test_damage_iter_damage
[21:26:57] [PASSED] drm_test_damage_iter_damage_one_intersect
[21:26:57] [PASSED] drm_test_damage_iter_damage_one_outside
[21:26:57] [PASSED] drm_test_damage_iter_damage_src_moved
[21:26:57] [PASSED] drm_test_damage_iter_damage_not_visible
[21:26:57] ================ [PASSED] drm_damage_helper ================
[21:26:57] ============== drm_dp_mst_helper (3 subtests) ==============
[21:26:57] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[21:26:57] [PASSED] Clock 154000 BPP 30 DSC disabled
[21:26:57] [PASSED] Clock 234000 BPP 30 DSC disabled
[21:26:57] [PASSED] Clock 297000 BPP 24 DSC disabled
[21:26:57] [PASSED] Clock 332880 BPP 24 DSC enabled
[21:26:57] [PASSED] Clock 324540 BPP 24 DSC enabled
[21:26:57] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[21:26:57] ============== drm_test_dp_mst_calc_pbn_div  ===============
[21:26:57] [PASSED] Link rate 2000000 lane count 4
[21:26:57] [PASSED] Link rate 2000000 lane count 2
[21:26:57] [PASSED] Link rate 2000000 lane count 1
[21:26:57] [PASSED] Link rate 1350000 lane count 4
[21:26:57] [PASSED] Link rate 1350000 lane count 2
[21:26:57] [PASSED] Link rate 1350000 lane count 1
[21:26:57] [PASSED] Link rate 1000000 lane count 4
[21:26:57] [PASSED] Link rate 1000000 lane count 2
[21:26:57] [PASSED] Link rate 1000000 lane count 1
[21:26:57] [PASSED] Link rate 810000 lane count 4
[21:26:57] [PASSED] Link rate 810000 lane count 2
[21:26:57] [PASSED] Link rate 810000 lane count 1
[21:26:57] [PASSED] Link rate 540000 lane count 4
[21:26:57] [PASSED] Link rate 540000 lane count 2
[21:26:57] [PASSED] Link rate 540000 lane count 1
[21:26:57] [PASSED] Link rate 270000 lane count 4
[21:26:57] [PASSED] Link rate 270000 lane count 2
[21:26:57] [PASSED] Link rate 270000 lane count 1
[21:26:57] [PASSED] Link rate 162000 lane count 4
[21:26:57] [PASSED] Link rate 162000 lane count 2
[21:26:57] [PASSED] Link rate 162000 lane count 1
[21:26:57] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[21:26:57] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[21:26:57] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[21:26:57] [PASSED] DP_POWER_UP_PHY with port number
[21:26:57] [PASSED] DP_POWER_DOWN_PHY with port number
[21:26:57] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[21:26:57] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[21:26:57] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[21:26:57] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[21:26:57] [PASSED] DP_QUERY_PAYLOAD with port number
[21:26:57] [PASSED] DP_QUERY_PAYLOAD with VCPI
[21:26:57] [PASSED] DP_REMOTE_DPCD_READ with port number
[21:26:57] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[21:26:57] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[21:26:57] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[21:26:57] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[21:26:57] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[21:26:57] [PASSED] DP_REMOTE_I2C_READ with port number
[21:26:57] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[21:26:57] [PASSED] DP_REMOTE_I2C_READ with transactions array
[21:26:57] [PASSED] DP_REMOTE_I2C_WRITE with port number
[21:26:57] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[21:26:57] [PASSED] DP_REMOTE_I2C_WRITE with data array
[21:26:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[21:26:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[21:26:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[21:26:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[21:26:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[21:26:57] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[21:26:57] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[21:26:57] ================ [PASSED] drm_dp_mst_helper ================
[21:26:57] ================== drm_exec (7 subtests) ===================
[21:26:57] [PASSED] sanitycheck
[21:26:57] [PASSED] test_lock
[21:26:57] [PASSED] test_lock_unlock
[21:26:57] [PASSED] test_duplicates
[21:26:57] [PASSED] test_prepare
[21:26:57] [PASSED] test_prepare_array
[21:26:57] [PASSED] test_multiple_loops
[21:26:57] ==================== [PASSED] drm_exec =====================
[21:26:57] =========== drm_format_helper_test (17 subtests) ===========
[21:26:57] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[21:26:57] [PASSED] single_pixel_source_buffer
[21:26:57] [PASSED] single_pixel_clip_rectangle
[21:26:57] [PASSED] well_known_colors
[21:26:57] [PASSED] destination_pitch
[21:26:57] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[21:26:57] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[21:26:57] [PASSED] single_pixel_source_buffer
[21:26:57] [PASSED] single_pixel_clip_rectangle
[21:26:57] [PASSED] well_known_colors
[21:26:57] [PASSED] destination_pitch
[21:26:57] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[21:26:57] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[21:26:57] [PASSED] single_pixel_source_buffer
[21:26:57] [PASSED] single_pixel_clip_rectangle
[21:26:57] [PASSED] well_known_colors
[21:26:57] [PASSED] destination_pitch
[21:26:57] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[21:26:57] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[21:26:57] [PASSED] single_pixel_source_buffer
[21:26:57] [PASSED] single_pixel_clip_rectangle
[21:26:57] [PASSED] well_known_colors
[21:26:57] [PASSED] destination_pitch
[21:26:57] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[21:26:57] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[21:26:57] [PASSED] single_pixel_source_buffer
[21:26:57] [PASSED] single_pixel_clip_rectangle
[21:26:57] [PASSED] well_known_colors
[21:26:57] [PASSED] destination_pitch
[21:26:57] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[21:26:57] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[21:26:57] [PASSED] single_pixel_source_buffer
[21:26:57] [PASSED] single_pixel_clip_rectangle
[21:26:57] [PASSED] well_known_colors
[21:26:57] [PASSED] destination_pitch
[21:26:57] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[21:26:57] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[21:26:57] [PASSED] single_pixel_source_buffer
[21:26:57] [PASSED] single_pixel_clip_rectangle
[21:26:57] [PASSED] well_known_colors
[21:26:57] [PASSED] destination_pitch
[21:26:57] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[21:26:57] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[21:26:57] [PASSED] single_pixel_source_buffer
[21:26:57] [PASSED] single_pixel_clip_rectangle
[21:26:57] [PASSED] well_known_colors
[21:26:57] [PASSED] destination_pitch
[21:26:57] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[21:26:57] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[21:26:57] [PASSED] single_pixel_source_buffer
[21:26:57] [PASSED] single_pixel_clip_rectangle
[21:26:57] [PASSED] well_known_colors
[21:26:57] [PASSED] destination_pitch
[21:26:57] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[21:26:57] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[21:26:57] [PASSED] single_pixel_source_buffer
[21:26:57] [PASSED] single_pixel_clip_rectangle
[21:26:57] [PASSED] well_known_colors
[21:26:57] [PASSED] destination_pitch
[21:26:57] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[21:26:57] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[21:26:57] [PASSED] single_pixel_source_buffer
[21:26:57] [PASSED] single_pixel_clip_rectangle
[21:26:57] [PASSED] well_known_colors
[21:26:57] [PASSED] destination_pitch
[21:26:57] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[21:26:57] ============== drm_test_fb_xrgb8888_to_mono  ===============
[21:26:57] [PASSED] single_pixel_source_buffer
[21:26:57] [PASSED] single_pixel_clip_rectangle
[21:26:57] [PASSED] well_known_colors
[21:26:57] [PASSED] destination_pitch
[21:26:57] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[21:26:57] ==================== drm_test_fb_swab  =====================
[21:26:57] [PASSED] single_pixel_source_buffer
[21:26:57] [PASSED] single_pixel_clip_rectangle
[21:26:57] [PASSED] well_known_colors
[21:26:57] [PASSED] destination_pitch
[21:26:57] ================ [PASSED] drm_test_fb_swab =================
[21:26:57] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[21:26:57] [PASSED] single_pixel_source_buffer
[21:26:57] [PASSED] single_pixel_clip_rectangle
[21:26:57] [PASSED] well_known_colors
[21:26:57] [PASSED] destination_pitch
[21:26:57] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[21:26:57] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[21:26:57] [PASSED] single_pixel_source_buffer
[21:26:57] [PASSED] single_pixel_clip_rectangle
[21:26:57] [PASSED] well_known_colors
[21:26:57] [PASSED] destination_pitch
[21:26:57] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[21:26:57] ================= drm_test_fb_clip_offset  =================
[21:26:57] [PASSED] pass through
[21:26:57] [PASSED] horizontal offset
[21:26:57] [PASSED] vertical offset
[21:26:57] [PASSED] horizontal and vertical offset
[21:26:57] [PASSED] horizontal offset (custom pitch)
[21:26:57] [PASSED] vertical offset (custom pitch)
[21:26:57] [PASSED] horizontal and vertical offset (custom pitch)
[21:26:57] ============= [PASSED] drm_test_fb_clip_offset =============
[21:26:57] =================== drm_test_fb_memcpy  ====================
[21:26:57] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[21:26:57] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[21:26:57] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[21:26:57] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[21:26:57] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[21:26:57] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[21:26:57] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[21:26:57] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[21:26:57] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[21:26:57] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[21:26:57] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[21:26:57] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[21:26:57] =============== [PASSED] drm_test_fb_memcpy ================
[21:26:57] ============= [PASSED] drm_format_helper_test ==============
[21:26:57] ================= drm_format (18 subtests) =================
[21:26:57] [PASSED] drm_test_format_block_width_invalid
[21:26:57] [PASSED] drm_test_format_block_width_one_plane
[21:26:57] [PASSED] drm_test_format_block_width_two_plane
[21:26:57] [PASSED] drm_test_format_block_width_three_plane
[21:26:57] [PASSED] drm_test_format_block_width_tiled
[21:26:57] [PASSED] drm_test_format_block_height_invalid
[21:26:57] [PASSED] drm_test_format_block_height_one_plane
[21:26:57] [PASSED] drm_test_format_block_height_two_plane
[21:26:57] [PASSED] drm_test_format_block_height_three_plane
[21:26:57] [PASSED] drm_test_format_block_height_tiled
[21:26:57] [PASSED] drm_test_format_min_pitch_invalid
[21:26:57] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[21:26:57] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[21:26:57] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[21:26:57] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[21:26:57] [PASSED] drm_test_format_min_pitch_two_plane
[21:26:57] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[21:26:57] [PASSED] drm_test_format_min_pitch_tiled
[21:26:57] =================== [PASSED] drm_format ====================
[21:26:57] ============== drm_framebuffer (10 subtests) ===============
[21:26:57] ========== drm_test_framebuffer_check_src_coords  ==========
[21:26:57] [PASSED] Success: source fits into fb
[21:26:57] [PASSED] Fail: overflowing fb with x-axis coordinate
[21:26:57] [PASSED] Fail: overflowing fb with y-axis coordinate
[21:26:57] [PASSED] Fail: overflowing fb with source width
[21:26:57] [PASSED] Fail: overflowing fb with source height
[21:26:57] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[21:26:57] [PASSED] drm_test_framebuffer_cleanup
[21:26:57] =============== drm_test_framebuffer_create  ===============
[21:26:57] [PASSED] ABGR8888 normal sizes
[21:26:57] [PASSED] ABGR8888 max sizes
[21:26:57] [PASSED] ABGR8888 pitch greater than min required
[21:26:57] [PASSED] ABGR8888 pitch less than min required
[21:26:57] [PASSED] ABGR8888 Invalid width
[21:26:57] [PASSED] ABGR8888 Invalid buffer handle
[21:26:57] [PASSED] No pixel format
[21:26:57] [PASSED] ABGR8888 Width 0
[21:26:57] [PASSED] ABGR8888 Height 0
[21:26:57] [PASSED] ABGR8888 Out of bound height * pitch combination
[21:26:57] [PASSED] ABGR8888 Large buffer offset
[21:26:57] [PASSED] ABGR8888 Buffer offset for inexistent plane
[21:26:57] [PASSED] ABGR8888 Invalid flag
[21:26:57] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[21:26:57] [PASSED] ABGR8888 Valid buffer modifier
[21:26:57] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[21:26:57] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[21:26:57] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[21:26:57] [PASSED] NV12 Normal sizes
[21:26:57] [PASSED] NV12 Max sizes
[21:26:57] [PASSED] NV12 Invalid pitch
[21:26:57] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[21:26:57] [PASSED] NV12 different  modifier per-plane
[21:26:57] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[21:26:57] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[21:26:57] [PASSED] NV12 Modifier for inexistent plane
[21:26:57] [PASSED] NV12 Handle for inexistent plane
[21:26:57] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[21:26:57] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[21:26:57] [PASSED] YVU420 Normal sizes
[21:26:57] [PASSED] YVU420 Max sizes
[21:26:57] [PASSED] YVU420 Invalid pitch
[21:26:57] [PASSED] YVU420 Different pitches
[21:26:57] [PASSED] YVU420 Different buffer offsets/pitches
[21:26:57] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[21:26:57] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[21:26:57] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[21:26:57] [PASSED] YVU420 Valid modifier
[21:26:57] [PASSED] YVU420 Different modifiers per plane
[21:26:57] [PASSED] YVU420 Modifier for inexistent plane
[21:26:57] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[21:26:57] [PASSED] X0L2 Normal sizes
[21:26:57] [PASSED] X0L2 Max sizes
[21:26:57] [PASSED] X0L2 Invalid pitch
[21:26:57] [PASSED] X0L2 Pitch greater than minimum required
[21:26:57] [PASSED] X0L2 Handle for inexistent plane
[21:26:57] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[21:26:57] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[21:26:57] [PASSED] X0L2 Valid modifier
[21:26:57] [PASSED] X0L2 Modifier for inexistent plane
[21:26:57] =========== [PASSED] drm_test_framebuffer_create ===========
[21:26:57] [PASSED] drm_test_framebuffer_free
[21:26:57] [PASSED] drm_test_framebuffer_init
[21:26:57] [PASSED] drm_test_framebuffer_init_bad_format
[21:26:57] [PASSED] drm_test_framebuffer_init_dev_mismatch
[21:26:57] [PASSED] drm_test_framebuffer_lookup
[21:26:57] [PASSED] drm_test_framebuffer_lookup_inexistent
[21:26:57] [PASSED] drm_test_framebuffer_modifiers_not_supported
[21:26:57] ================= [PASSED] drm_framebuffer =================
[21:26:57] ================ drm_gem_shmem (8 subtests) ================
[21:26:57] [PASSED] drm_gem_shmem_test_obj_create
[21:26:57] [PASSED] drm_gem_shmem_test_obj_create_private
[21:26:57] [PASSED] drm_gem_shmem_test_pin_pages
[21:26:57] [PASSED] drm_gem_shmem_test_vmap
[21:26:57] [PASSED] drm_gem_shmem_test_get_pages_sgt
[21:26:57] [PASSED] drm_gem_shmem_test_get_sg_table
[21:26:57] [PASSED] drm_gem_shmem_test_madvise
[21:26:57] [PASSED] drm_gem_shmem_test_purge
[21:26:57] ================== [PASSED] drm_gem_shmem ==================
[21:26:57] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[21:26:57] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[21:26:57] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[21:26:57] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[21:26:57] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[21:26:57] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[21:26:57] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[21:26:57] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[21:26:57] [PASSED] Automatic
[21:26:57] [PASSED] Full
[21:26:57] [PASSED] Limited 16:235
[21:26:57] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[21:26:57] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[21:26:57] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[21:26:57] [PASSED] drm_test_check_disable_connector
[21:26:57] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[21:26:57] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[21:26:57] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[21:26:57] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[21:26:57] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[21:26:57] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[21:26:57] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[21:26:57] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[21:26:57] [PASSED] drm_test_check_output_bpc_dvi
[21:26:57] [PASSED] drm_test_check_output_bpc_format_vic_1
[21:26:57] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[21:26:57] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[21:26:57] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[21:26:57] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[21:26:57] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[21:26:57] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[21:26:57] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[21:26:57] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[21:26:57] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[21:26:57] [PASSED] drm_test_check_broadcast_rgb_value
[21:26:57] [PASSED] drm_test_check_bpc_8_value
[21:26:57] [PASSED] drm_test_check_bpc_10_value
[21:26:57] [PASSED] drm_test_check_bpc_12_value
[21:26:57] [PASSED] drm_test_check_format_value
[21:26:57] [PASSED] drm_test_check_tmds_char_value
[21:26:57] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[21:26:57] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[21:26:57] [PASSED] drm_test_check_mode_valid
[21:26:57] [PASSED] drm_test_check_mode_valid_reject
[21:26:57] [PASSED] drm_test_check_mode_valid_reject_rate
[21:26:57] [PASSED] drm_test_check_mode_valid_reject_max_clock
[21:26:57] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[21:26:57] ================= drm_managed (2 subtests) =================
[21:26:57] [PASSED] drm_test_managed_release_action
[21:26:57] [PASSED] drm_test_managed_run_action
[21:26:57] =================== [PASSED] drm_managed ===================
[21:26:57] =================== drm_mm (6 subtests) ====================
[21:26:57] [PASSED] drm_test_mm_init
[21:26:57] [PASSED] drm_test_mm_debug
[21:26:57] [PASSED] drm_test_mm_align32
[21:26:57] [PASSED] drm_test_mm_align64
[21:26:57] [PASSED] drm_test_mm_lowest
[21:26:57] [PASSED] drm_test_mm_highest
[21:26:57] ===================== [PASSED] drm_mm ======================
[21:26:57] ============= drm_modes_analog_tv (5 subtests) =============
[21:26:57] [PASSED] drm_test_modes_analog_tv_mono_576i
[21:26:57] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[21:26:57] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[21:26:57] [PASSED] drm_test_modes_analog_tv_pal_576i
[21:26:57] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[21:26:57] =============== [PASSED] drm_modes_analog_tv ===============
[21:26:57] ============== drm_plane_helper (2 subtests) ===============
[21:26:57] =============== drm_test_check_plane_state  ================
[21:26:57] [PASSED] clipping_simple
[21:26:57] [PASSED] clipping_rotate_reflect
[21:26:57] [PASSED] positioning_simple
[21:26:57] [PASSED] upscaling
[21:26:57] [PASSED] downscaling
[21:26:57] [PASSED] rounding1
[21:26:57] [PASSED] rounding2
[21:26:57] [PASSED] rounding3
[21:26:57] [PASSED] rounding4
[21:26:57] =========== [PASSED] drm_test_check_plane_state ============
[21:26:57] =========== drm_test_check_invalid_plane_state  ============
[21:26:57] [PASSED] positioning_invalid
[21:26:57] [PASSED] upscaling_invalid
[21:26:57] [PASSED] downscaling_invalid
[21:26:57] ======= [PASSED] drm_test_check_invalid_plane_state ========
[21:26:57] ================ [PASSED] drm_plane_helper =================
[21:26:57] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[21:26:57] ====== drm_test_connector_helper_tv_get_modes_check  =======
[21:26:57] [PASSED] None
[21:26:57] [PASSED] PAL
[21:26:57] [PASSED] NTSC
[21:26:57] [PASSED] Both, NTSC Default
[21:26:57] [PASSED] Both, PAL Default
[21:26:57] [PASSED] Both, NTSC Default, with PAL on command-line
[21:26:57] [PASSED] Both, PAL Default, with NTSC on command-line
[21:26:57] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[21:26:57] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[21:26:57] ================== drm_rect (9 subtests) ===================
[21:26:57] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[21:26:57] [PASSED] drm_test_rect_clip_scaled_not_clipped
[21:26:57] [PASSED] drm_test_rect_clip_scaled_clipped
[21:26:57] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[21:26:57] ================= drm_test_rect_intersect  =================
[21:26:57] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[21:26:57] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[21:26:57] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[21:26:57] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[21:26:57] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[21:26:57] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[21:26:57] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[21:26:57] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[21:26:57] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[21:26:57] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[21:26:57] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[21:26:57] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[21:26:57] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[21:26:57] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[21:26:57] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[21:26:57] ============= [PASSED] drm_test_rect_intersect =============
[21:26:57] ================ drm_test_rect_calc_hscale  ================
[21:26:57] [PASSED] normal use
[21:26:57] [PASSED] out of max range
[21:26:57] [PASSED] out of min range
[21:26:57] [PASSED] zero dst
[21:26:57] [PASSED] negative src
[21:26:57] [PASSED] negative dst
[21:26:57] ============ [PASSED] drm_test_rect_calc_hscale ============
[21:26:57] ================ drm_test_rect_calc_vscale  ================
[21:26:57] [PASSED] normal use
[21:26:57] [PASSED] out of max range
[21:26:57] [PASSED] out of min range
[21:26:57] [PASSED] zero dst
[21:26:57] [PASSED] negative src
[21:26:57] [PASSED] negative dst
[21:26:57] ============ [PASSED] drm_test_rect_calc_vscale ============
[21:26:57] ================== drm_test_rect_rotate  ===================
[21:26:57] [PASSED] reflect-x
[21:26:57] [PASSED] reflect-y
[21:26:57] [PASSED] rotate-0
[21:26:57] [PASSED] rotate-90
[21:26:57] [PASSED] rotate-180
[21:26:57] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[21:26:57] ============== [PASSED] drm_test_rect_rotate ===============
[21:26:57] ================ drm_test_rect_rotate_inv  =================
[21:26:57] [PASSED] reflect-x
[21:26:57] [PASSED] reflect-y
[21:26:57] [PASSED] rotate-0
[21:26:57] [PASSED] rotate-90
[21:26:57] [PASSED] rotate-180
[21:26:57] [PASSED] rotate-270
[21:26:57] ============ [PASSED] drm_test_rect_rotate_inv =============
[21:26:57] ==================== [PASSED] drm_rect =====================
[21:26:57] ============ drm_sysfb_modeset_test (1 subtest) ============
[21:26:57] ============ drm_test_sysfb_build_fourcc_list  =============
[21:26:57] [PASSED] no native formats
[21:26:57] [PASSED] XRGB8888 as native format
[21:26:57] [PASSED] remove duplicates
[21:26:57] [PASSED] convert alpha formats
[21:26:57] [PASSED] random formats
[21:26:57] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[21:26:57] ============= [PASSED] drm_sysfb_modeset_test ==============
[21:26:57] ============================================================
[21:26:57] Testing complete. Ran 616 tests: passed: 616
[21:26:57] Elapsed time: 23.150s total, 1.690s configuring, 21.293s building, 0.150s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[21:26:58] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:26:59] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:27:07] Starting KUnit Kernel (1/1)...
[21:27:07] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:27:07] ================= ttm_device (5 subtests) ==================
[21:27:07] [PASSED] ttm_device_init_basic
[21:27:07] [PASSED] ttm_device_init_multiple
[21:27:07] [PASSED] ttm_device_fini_basic
[21:27:07] [PASSED] ttm_device_init_no_vma_man
[21:27:07] ================== ttm_device_init_pools  ==================
[21:27:07] [PASSED] No DMA allocations, no DMA32 required
[21:27:07] [PASSED] DMA allocations, DMA32 required
[21:27:07] [PASSED] No DMA allocations, DMA32 required
[21:27:07] [PASSED] DMA allocations, no DMA32 required
[21:27:07] ============== [PASSED] ttm_device_init_pools ==============
[21:27:07] =================== [PASSED] ttm_device ====================
[21:27:07] ================== ttm_pool (8 subtests) ===================
[21:27:07] ================== ttm_pool_alloc_basic  ===================
[21:27:07] [PASSED] One page
[21:27:07] [PASSED] More than one page
[21:27:07] [PASSED] Above the allocation limit
[21:27:07] [PASSED] One page, with coherent DMA mappings enabled
[21:27:07] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:27:07] ============== [PASSED] ttm_pool_alloc_basic ===============
[21:27:07] ============== ttm_pool_alloc_basic_dma_addr  ==============
[21:27:07] [PASSED] One page
[21:27:07] [PASSED] More than one page
[21:27:07] [PASSED] Above the allocation limit
[21:27:07] [PASSED] One page, with coherent DMA mappings enabled
[21:27:07] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:27:07] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[21:27:07] [PASSED] ttm_pool_alloc_order_caching_match
[21:27:07] [PASSED] ttm_pool_alloc_caching_mismatch
[21:27:07] [PASSED] ttm_pool_alloc_order_mismatch
[21:27:07] [PASSED] ttm_pool_free_dma_alloc
[21:27:07] [PASSED] ttm_pool_free_no_dma_alloc
[21:27:07] [PASSED] ttm_pool_fini_basic
[21:27:07] ==================== [PASSED] ttm_pool =====================
[21:27:07] ================ ttm_resource (8 subtests) =================
[21:27:07] ================= ttm_resource_init_basic  =================
[21:27:07] [PASSED] Init resource in TTM_PL_SYSTEM
[21:27:07] [PASSED] Init resource in TTM_PL_VRAM
[21:27:07] [PASSED] Init resource in a private placement
[21:27:07] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[21:27:07] ============= [PASSED] ttm_resource_init_basic =============
[21:27:07] [PASSED] ttm_resource_init_pinned
[21:27:07] [PASSED] ttm_resource_fini_basic
[21:27:07] [PASSED] ttm_resource_manager_init_basic
[21:27:07] [PASSED] ttm_resource_manager_usage_basic
[21:27:07] [PASSED] ttm_resource_manager_set_used_basic
[21:27:07] [PASSED] ttm_sys_man_alloc_basic
[21:27:07] [PASSED] ttm_sys_man_free_basic
[21:27:07] ================== [PASSED] ttm_resource ===================
[21:27:07] =================== ttm_tt (15 subtests) ===================
[21:27:07] ==================== ttm_tt_init_basic  ====================
[21:27:07] [PASSED] Page-aligned size
[21:27:07] [PASSED] Extra pages requested
[21:27:07] ================ [PASSED] ttm_tt_init_basic ================
[21:27:07] [PASSED] ttm_tt_init_misaligned
[21:27:07] [PASSED] ttm_tt_fini_basic
[21:27:07] [PASSED] ttm_tt_fini_sg
[21:27:07] [PASSED] ttm_tt_fini_shmem
[21:27:07] [PASSED] ttm_tt_create_basic
[21:27:07] [PASSED] ttm_tt_create_invalid_bo_type
[21:27:07] [PASSED] ttm_tt_create_ttm_exists
[21:27:07] [PASSED] ttm_tt_create_failed
[21:27:07] [PASSED] ttm_tt_destroy_basic
[21:27:07] [PASSED] ttm_tt_populate_null_ttm
[21:27:07] [PASSED] ttm_tt_populate_populated_ttm
[21:27:07] [PASSED] ttm_tt_unpopulate_basic
[21:27:07] [PASSED] ttm_tt_unpopulate_empty_ttm
[21:27:07] [PASSED] ttm_tt_swapin_basic
[21:27:07] ===================== [PASSED] ttm_tt ======================
[21:27:07] =================== ttm_bo (14 subtests) ===================
[21:27:07] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[21:27:07] [PASSED] Cannot be interrupted and sleeps
[21:27:07] [PASSED] Cannot be interrupted, locks straight away
[21:27:07] [PASSED] Can be interrupted, sleeps
[21:27:07] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[21:27:07] [PASSED] ttm_bo_reserve_locked_no_sleep
[21:27:07] [PASSED] ttm_bo_reserve_no_wait_ticket
[21:27:07] [PASSED] ttm_bo_reserve_double_resv
[21:27:07] [PASSED] ttm_bo_reserve_interrupted
[21:27:07] [PASSED] ttm_bo_reserve_deadlock
[21:27:07] [PASSED] ttm_bo_unreserve_basic
[21:27:07] [PASSED] ttm_bo_unreserve_pinned
[21:27:07] [PASSED] ttm_bo_unreserve_bulk
[21:27:07] [PASSED] ttm_bo_put_basic
[21:27:07] [PASSED] ttm_bo_put_shared_resv
[21:27:07] [PASSED] ttm_bo_pin_basic
[21:27:07] [PASSED] ttm_bo_pin_unpin_resource
[21:27:07] [PASSED] ttm_bo_multiple_pin_one_unpin
[21:27:07] ===================== [PASSED] ttm_bo ======================
[21:27:07] ============== ttm_bo_validate (21 subtests) ===============
[21:27:07] ============== ttm_bo_init_reserved_sys_man  ===============
[21:27:07] [PASSED] Buffer object for userspace
[21:27:07] [PASSED] Kernel buffer object
[21:27:07] [PASSED] Shared buffer object
[21:27:07] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[21:27:07] ============== ttm_bo_init_reserved_mock_man  ==============
[21:27:07] [PASSED] Buffer object for userspace
[21:27:07] [PASSED] Kernel buffer object
[21:27:07] [PASSED] Shared buffer object
[21:27:07] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[21:27:07] [PASSED] ttm_bo_init_reserved_resv
[21:27:07] ================== ttm_bo_validate_basic  ==================
[21:27:07] [PASSED] Buffer object for userspace
[21:27:07] [PASSED] Kernel buffer object
[21:27:07] [PASSED] Shared buffer object
[21:27:07] ============== [PASSED] ttm_bo_validate_basic ==============
[21:27:07] [PASSED] ttm_bo_validate_invalid_placement
[21:27:07] ============= ttm_bo_validate_same_placement  ==============
[21:27:07] [PASSED] System manager
[21:27:07] [PASSED] VRAM manager
[21:27:07] ========= [PASSED] ttm_bo_validate_same_placement ==========
[21:27:07] [PASSED] ttm_bo_validate_failed_alloc
[21:27:07] [PASSED] ttm_bo_validate_pinned
[21:27:07] [PASSED] ttm_bo_validate_busy_placement
[21:27:07] ================ ttm_bo_validate_multihop  =================
[21:27:07] [PASSED] Buffer object for userspace
[21:27:07] [PASSED] Kernel buffer object
[21:27:07] [PASSED] Shared buffer object
[21:27:07] ============ [PASSED] ttm_bo_validate_multihop =============
[21:27:07] ========== ttm_bo_validate_no_placement_signaled  ==========
[21:27:07] [PASSED] Buffer object in system domain, no page vector
[21:27:07] [PASSED] Buffer object in system domain with an existing page vector
[21:27:07] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[21:27:07] ======== ttm_bo_validate_no_placement_not_signaled  ========
[21:27:07] [PASSED] Buffer object for userspace
[21:27:07] [PASSED] Kernel buffer object
[21:27:07] [PASSED] Shared buffer object
[21:27:07] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[21:27:07] [PASSED] ttm_bo_validate_move_fence_signaled
[21:27:07] ========= ttm_bo_validate_move_fence_not_signaled  =========
[21:27:07] [PASSED] Waits for GPU
[21:27:07] [PASSED] Tries to lock straight away
[21:27:07] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[21:27:07] [PASSED] ttm_bo_validate_happy_evict
[21:27:07] [PASSED] ttm_bo_validate_all_pinned_evict
[21:27:07] [PASSED] ttm_bo_validate_allowed_only_evict
[21:27:07] [PASSED] ttm_bo_validate_deleted_evict
[21:27:07] [PASSED] ttm_bo_validate_busy_domain_evict
[21:27:07] [PASSED] ttm_bo_validate_evict_gutting
[21:27:07] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[21:27:07] ================= [PASSED] ttm_bo_validate =================
[21:27:07] ============================================================
[21:27:07] Testing complete. Ran 101 tests: passed: 101
[21:27:07] Elapsed time: 9.582s total, 1.646s configuring, 7.720s building, 0.179s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Clean up of GuC init data macros & add extra log option

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1564 bytes --]

== Series Details ==

Series: Clean up of GuC init data macros & add extra log option
URL   : https://patchwork.freedesktop.org/series/152030/
State : success

== Summary ==

CI Bug Log - changes from xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f_BAT -> xe-pw-152030v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 8)
------------------------------

  Missing    (1): bat-adlp-vm 

Known issues
------------

  Here are the changes found in xe-pw-152030v1_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - bat-adlp-7:         [DMESG-WARN][1] ([Intel XE#4543]) -> [PASS][2] +1 other test pass
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank.html

  
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543


Build changes
-------------

  * Linux: xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f -> xe-pw-152030v1

  IGT_8475: 1ddc997191d8aa008b49b5a4c47cf295c9a3c4f4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f: 10ed8e2e5529207fe710c22898b0c09ef7f16b0f
  xe-pw-152030v1: 152030v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/index.html

[-- Attachment #2: Type: text/html, Size: 2133 bytes --]

✗ Xe.CI.Full: failure for Clean up of GuC init data macros & add extra log option

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 49084 bytes --]

== Series Details ==

Series: Clean up of GuC init data macros & add extra log option
URL   : https://patchwork.freedesktop.org/series/152030/
State : failure

== Summary ==

CI Bug Log - changes from xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f_FULL -> xe-pw-152030v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-152030v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-152030v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-152030v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a2:
    - shard-dg2-set2:     NOTRUN -> [FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-432/igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a2.html

  * igt@kms_plane_lowres@tiling-x@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][2] -> [DMESG-WARN][3] +3 other tests dmesg-warn
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-dg2-464/igt@kms_plane_lowres@tiling-x@pipe-a-dp-4.html
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-466/igt@kms_plane_lowres@tiling-x@pipe-a-dp-4.html

  
Known issues
------------

  Here are the changes found in xe-pw-152030v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@linear-8bpp-rotate-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][4] ([Intel XE#316])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_big_fb@linear-8bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-addfb:
    - shard-adlp:         [PASS][5] -> [SKIP][6] ([Intel XE#2351] / [Intel XE#4947])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@kms_big_fb@x-tiled-addfb.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_big_fb@x-tiled-addfb.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-180:
    - shard-dg2-set2:     NOTRUN -> [SKIP][7] ([Intel XE#1124]) +2 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-433/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-dg2-set2:     NOTRUN -> [SKIP][8] ([Intel XE#607])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][9] ([Intel XE#2191])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-4-displays-1920x1080p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][10] ([Intel XE#367])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_bw@linear-tiling-4-displays-1920x1080p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2652] / [Intel XE#787]) +3 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-7/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][12] ([Intel XE#2907])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][13] ([Intel XE#455] / [Intel XE#787]) +14 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-434/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-dp-4.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#787]) +90 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-463/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [PASS][15] -> [INCOMPLETE][16] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124] / [Intel XE#4345])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     [PASS][17] -> [INCOMPLETE][18] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-6.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][19] -> [INCOMPLETE][20] ([Intel XE#2705] / [Intel XE#4212]) +1 other test incomplete
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html

  * igt@kms_chamelium_color@ctm-0-75:
    - shard-dg2-set2:     NOTRUN -> [SKIP][21] ([Intel XE#306]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_chamelium_color@ctm-0-75.html

  * igt@kms_chamelium_frames@hdmi-crc-fast:
    - shard-dg2-set2:     NOTRUN -> [SKIP][22] ([Intel XE#373]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_chamelium_frames@hdmi-crc-fast.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2-set2:     NOTRUN -> [FAIL][23] ([Intel XE#1178]) +2 other tests fail
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@atomic@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][24] ([Intel XE#1178])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-7/igt@kms_content_protection@atomic@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-size-hints:
    - shard-adlp:         [PASS][25] -> [SKIP][26] ([Intel XE#4950]) +5 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@kms_cursor_crc@cursor-size-hints.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_cursor_crc@cursor-size-hints.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
    - shard-bmg:          [PASS][27] -> [SKIP][28] ([Intel XE#2291]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-bmg-2/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-bmg:          [PASS][29] -> [SKIP][30] ([Intel XE#4302])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-bmg-8/igt@kms_display_modes@extended-mode-basic.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-6/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][31] ([Intel XE#4494])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-432/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-bmg:          [PASS][32] -> [SKIP][33] ([Intel XE#4354])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-bmg-3/igt@kms_dp_link_training@non-uhbr-sst.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-6/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_fbcon_fbt@psr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][34] ([Intel XE#776])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_fbcon_fbt@psr.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-lnl:          [PASS][35] -> [FAIL][36] ([Intel XE#4164])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-lnl-5/igt@kms_fbcon_fbt@psr-suspend.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-lnl-1/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@2x-nonexisting-fb:
    - shard-bmg:          [PASS][37] -> [SKIP][38] ([Intel XE#2316]) +3 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-bmg-3/igt@kms_flip@2x-nonexisting-fb.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-6/igt@kms_flip@2x-nonexisting-fb.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank:
    - shard-dg2-set2:     [PASS][39] -> [FAIL][40] ([Intel XE#3098])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-dg2-463/igt@kms_flip@flip-vs-absolute-wf_vblank.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-432/igt@kms_flip@flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a2:
    - shard-dg2-set2:     NOTRUN -> [FAIL][41] ([Intel XE#3098])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-432/igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a2.html

  * igt@kms_flip@flip-vs-rmfb@c-hdmi-a1:
    - shard-adlp:         [PASS][42] -> [DMESG-WARN][43] ([Intel XE#4543]) +1 other test dmesg-warn
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-6/igt@kms_flip@flip-vs-rmfb@c-hdmi-a1.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-6/igt@kms_flip@flip-vs-rmfb@c-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-dg2-set2:     NOTRUN -> [SKIP][44] ([Intel XE#455]) +14 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][45] ([Intel XE#651]) +12 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-stridechange:
    - shard-adlp:         [PASS][46] -> [SKIP][47] ([Intel XE#4947]) +1 other test skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@kms_frontbuffer_tracking@fbc-stridechange.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_frontbuffer_tracking@fbc-stridechange.html

  * igt@kms_frontbuffer_tracking@psr-slowdraw:
    - shard-dg2-set2:     NOTRUN -> [SKIP][48] ([Intel XE#653]) +11 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_frontbuffer_tracking@psr-slowdraw.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-dg2-set2:     NOTRUN -> [SKIP][49] ([Intel XE#2925])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256:
    - shard-dg2-set2:     NOTRUN -> [FAIL][50] ([Intel XE#616]) +3 other tests fail
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_plane_cursor@primary@pipe-a-hdmi-a-6-size-256.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][51] ([Intel XE#5020])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][52] ([Intel XE#908])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-433/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][53] ([Intel XE#1489]) +2 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr@psr2-primary-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][54] ([Intel XE#2850] / [Intel XE#929]) +5 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_psr@psr2-primary-render.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-dg2-set2:     NOTRUN -> [SKIP][55] ([Intel XE#3414])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-433/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [PASS][56] -> [FAIL][57] ([Intel XE#4459]) +1 other test fail
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-lnl-3/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-lnl-8/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind:
    - shard-dg2-set2:     [PASS][58] -> [SKIP][59] ([Intel XE#1392]) +4 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-dg2-463/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html

  * igt@xe_exec_fault_mode@twice-invalid-fault:
    - shard-dg2-set2:     NOTRUN -> [SKIP][60] ([Intel XE#288]) +8 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-433/igt@xe_exec_fault_mode@twice-invalid-fault.html

  * igt@xe_exec_reset@gt-reset-stress:
    - shard-adlp:         [PASS][61] -> [DMESG-WARN][62] ([Intel XE#4812])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@xe_exec_reset@gt-reset-stress.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@xe_exec_reset@gt-reset-stress.html

  * igt@xe_exec_reset@parallel-gt-reset:
    - shard-bmg:          [PASS][63] -> [DMESG-WARN][64] ([Intel XE#3876])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-bmg-4/igt@xe_exec_reset@parallel-gt-reset.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-8/igt@xe_exec_reset@parallel-gt-reset.html

  * igt@xe_exec_sip_eudebug@wait-writesip-nodebug:
    - shard-dg2-set2:     NOTRUN -> [SKIP][65] ([Intel XE#4837]) +5 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@xe_exec_sip_eudebug@wait-writesip-nodebug.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset:
    - shard-lnl:          [PASS][66] -> [FAIL][67] ([Intel XE#5018])
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-lnl-1/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-lnl-3/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html

  * igt@xe_exec_system_allocator@twice-malloc-fork-read:
    - shard-dg2-set2:     NOTRUN -> [SKIP][68] ([Intel XE#4915]) +103 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@xe_exec_system_allocator@twice-malloc-fork-read.html

  * igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit:
    - shard-dg2-set2:     NOTRUN -> [SKIP][69] ([Intel XE#2229])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html

  * igt@xe_oa@whitelisted-registers-userspace-config:
    - shard-dg2-set2:     NOTRUN -> [SKIP][70] ([Intel XE#3573]) +2 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@xe_oa@whitelisted-registers-userspace-config.html

  * igt@xe_pat@pat-index-xehpc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][71] ([Intel XE#2838] / [Intel XE#979])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pm_residency@gt-c6-freeze@gt0:
    - shard-adlp:         [PASS][72] -> [DMESG-WARN][73] ([Intel XE#2953] / [Intel XE#4173]) +2 other tests dmesg-warn
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-8/igt@xe_pm_residency@gt-c6-freeze@gt0.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-3/igt@xe_pm_residency@gt-c6-freeze@gt0.html

  * igt@xe_pmu@gt-frequency:
    - shard-dg2-set2:     [PASS][74] -> [FAIL][75] ([Intel XE#4819]) +1 other test fail
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-dg2-433/igt@xe_pmu@gt-frequency.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-434/igt@xe_pmu@gt-frequency.html

  * igt@xe_pxp@pxp-stale-bo-bind-post-suspend:
    - shard-dg2-set2:     NOTRUN -> [SKIP][76] ([Intel XE#4733]) +2 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-433/igt@xe_pxp@pxp-stale-bo-bind-post-suspend.html

  * igt@xe_query@multigpu-query-invalid-query:
    - shard-dg2-set2:     NOTRUN -> [SKIP][77] ([Intel XE#944])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-433/igt@xe_query@multigpu-query-invalid-query.html

  * igt@xe_spin_batch@spin-mem-copy:
    - shard-dg2-set2:     NOTRUN -> [SKIP][78] ([Intel XE#4821])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@xe_spin_batch@spin-mem-copy.html

  * igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling:
    - shard-adlp:         [PASS][79] -> [SKIP][80] ([Intel XE#4945]) +16 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html

  
#### Possible fixes ####

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-adlp:         [DMESG-FAIL][81] ([Intel XE#4543]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
    - shard-bmg:          [FAIL][83] ([Intel XE#5376]) -> [PASS][84] +1 other test pass
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-bmg-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [INCOMPLETE][85] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) -> [PASS][86] +1 other test pass
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-bmg:          [SKIP][87] ([Intel XE#2291]) -> [PASS][88] +2 other tests pass
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-bmg-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-7/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [FAIL][89] ([Intel XE#4633]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-bmg:          [SKIP][91] ([Intel XE#2316]) -> [PASS][92] +5 other tests pass
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-bmg-6/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-4/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][93] ([Intel XE#4543]) -> [PASS][94] +2 other tests pass
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-9/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-2/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [FAIL][95] ([Intel XE#301]) -> [PASS][96] +2 other tests pass
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][97] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][98] +2 other tests pass
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-2/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html

  * igt@kms_hdr@invalid-hdr:
    - shard-dg2-set2:     [SKIP][99] ([Intel XE#455]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-dg2-433/igt@kms_hdr@invalid-hdr.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-463/igt@kms_hdr@invalid-hdr.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-adlp:         [FAIL][101] ([Intel XE#718]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-4/igt@kms_pm_dc@dc6-dpms.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-8/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-bmg:          [SKIP][103] ([Intel XE#1435]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-bmg-6/igt@kms_setmode@clone-exclusive-crtc.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-7/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@xe_exec_basic@multigpu-no-exec-null-defer-bind:
    - shard-dg2-set2:     [SKIP][105] ([Intel XE#1392]) -> [PASS][106] +2 other tests pass
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-null-defer-bind.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-434/igt@xe_exec_basic@multigpu-no-exec-null-defer-bind.html

  * igt@xe_exec_capture@reset:
    - shard-dg2-set2:     [FAIL][107] ([Intel XE#5481]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-dg2-435/igt@xe_exec_capture@reset.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-436/igt@xe_exec_capture@reset.html

  
#### Warnings ####

  * igt@kms_big_fb@4-tiled-16bpp-rotate-0:
    - shard-adlp:         [SKIP][109] ([Intel XE#1124]) -> [SKIP][110] ([Intel XE#4947]) +2 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html

  * igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p:
    - shard-adlp:         [SKIP][111] ([Intel XE#2191]) -> [SKIP][112] ([Intel XE#4950])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-1-displays-2560x1440p:
    - shard-adlp:         [SKIP][113] ([Intel XE#367]) -> [SKIP][114] ([Intel XE#4950])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html

  * igt@kms_ccs@bad-pixel-format-y-tiled-gen12-rc-ccs:
    - shard-adlp:         [SKIP][115] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][116] ([Intel XE#2351] / [Intel XE#4947])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-rc-ccs.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc:
    - shard-adlp:         [SKIP][117] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][118] ([Intel XE#4947])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_chamelium_audio@dp-audio-edid:
    - shard-adlp:         [SKIP][119] ([Intel XE#373]) -> [SKIP][120] ([Intel XE#4950])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@kms_chamelium_audio@dp-audio-edid.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_chamelium_audio@dp-audio-edid.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          [SKIP][121] ([Intel XE#2341]) -> [FAIL][122] ([Intel XE#1178])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-bmg-6/igt@kms_content_protection@atomic.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-7/igt@kms_content_protection@atomic.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank:
    - shard-adlp:         [SKIP][123] ([Intel XE#310]) -> [SKIP][124] ([Intel XE#4950])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@kms_flip@2x-blocking-absolute-wf_vblank.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_flip@2x-blocking-absolute-wf_vblank.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][125] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][126] ([Intel XE#301])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-rmfb:
    - shard-adlp:         [DMESG-WARN][127] ([Intel XE#5208]) -> [DMESG-WARN][128] ([Intel XE#4543] / [Intel XE#5208])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-6/igt@kms_flip@flip-vs-rmfb.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-6/igt@kms_flip@flip-vs-rmfb.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-adlp:         [SKIP][129] ([Intel XE#651]) -> [SKIP][130] ([Intel XE#4947])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-mmap-wc.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw:
    - shard-bmg:          [SKIP][131] ([Intel XE#2312]) -> [SKIP][132] ([Intel XE#2311]) +12 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][133] ([Intel XE#2311]) -> [SKIP][134] ([Intel XE#2312]) +9 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][135] ([Intel XE#2312]) -> [SKIP][136] ([Intel XE#5390]) +5 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen:
    - shard-bmg:          [SKIP][137] ([Intel XE#5390]) -> [SKIP][138] ([Intel XE#2312]) +3 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
    - shard-adlp:         [SKIP][139] ([Intel XE#653]) -> [SKIP][140] ([Intel XE#4947]) +2 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
    - shard-adlp:         [SKIP][141] ([Intel XE#656]) -> [SKIP][142] ([Intel XE#4947]) +7 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff:
    - shard-bmg:          [SKIP][143] ([Intel XE#2312]) -> [SKIP][144] ([Intel XE#2313]) +11 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][145] ([Intel XE#2313]) -> [SKIP][146] ([Intel XE#2312]) +7 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-adlp:         [SKIP][147] ([Intel XE#734]) -> [FAIL][148] ([Intel XE#3325])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-4/igt@kms_pm_dc@dc9-dpms.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-8/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-adlp:         [SKIP][149] ([Intel XE#1489]) -> [SKIP][150] ([Intel XE#4947]) +1 other test skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@fbc-pr-basic:
    - shard-adlp:         [SKIP][151] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][152] ([Intel XE#4947])
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@kms_psr@fbc-pr-basic.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_psr@fbc-pr-basic.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-adlp:         [SKIP][153] ([Intel XE#3414]) -> [SKIP][154] ([Intel XE#4950])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-dg2-set2:     [SKIP][155] ([Intel XE#1500]) -> [SKIP][156] ([Intel XE#362])
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-dg2-433/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@flip-basic:
    - shard-adlp:         [SKIP][157] ([Intel XE#455]) -> [SKIP][158] ([Intel XE#4950]) +1 other test skip
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@kms_vrr@flip-basic.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@kms_vrr@flip-basic.html

  * igt@xe_eudebug@basic-vm-bind:
    - shard-adlp:         [SKIP][159] ([Intel XE#4837] / [Intel XE#5565]) -> [SKIP][160] ([Intel XE#4945])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@xe_eudebug@basic-vm-bind.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@xe_eudebug@basic-vm-bind.html

  * igt@xe_evict@evict-beng-large-cm:
    - shard-adlp:         [SKIP][161] ([Intel XE#261] / [Intel XE#5564]) -> [SKIP][162] ([Intel XE#4945])
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@xe_evict@evict-beng-large-cm.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@xe_evict@evict-beng-large-cm.html

  * igt@xe_evict@evict-small-external-cm:
    - shard-adlp:         [SKIP][163] ([Intel XE#261] / [Intel XE#5564] / [Intel XE#688]) -> [SKIP][164] ([Intel XE#4945])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@xe_evict@evict-small-external-cm.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@xe_evict@evict-small-external-cm.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr:
    - shard-adlp:         [SKIP][165] ([Intel XE#1392] / [Intel XE#5575]) -> [SKIP][166] ([Intel XE#4945]) +1 other test skip
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr.html

  * igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race-imm:
    - shard-adlp:         [SKIP][167] ([Intel XE#288] / [Intel XE#5561]) -> [SKIP][168] ([Intel XE#4945]) +5 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race-imm.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race-imm.html

  * igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence:
    - shard-adlp:         [SKIP][169] ([Intel XE#2360] / [Intel XE#5573]) -> [SKIP][170] ([Intel XE#4945])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@xe_exec_mix_modes@exec-spinner-interrupted-dma-fence.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-shared-remap:
    - shard-adlp:         [SKIP][171] ([Intel XE#4915] / [Intel XE#5560]) -> [SKIP][172] ([Intel XE#4945]) +35 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-shared-remap.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-shared-remap.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-lnl:          [INCOMPLETE][173] -> [ABORT][174] ([Intel XE#4917] / [Intel XE#5466])
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-lnl-7/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-lnl-2/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  * igt@xe_oa@blocking:
    - shard-adlp:         [SKIP][175] ([Intel XE#3573]) -> [SKIP][176] ([Intel XE#4945])
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f/shard-adlp-3/igt@xe_oa@blocking.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/shard-adlp-9/igt@xe_oa@blocking.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1500]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1500
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
  [Intel XE#2360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2360
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3325
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
  [Intel XE#4164]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4164
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
  [Intel XE#4494]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4494
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4812
  [Intel XE#4819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4819
  [Intel XE#4821]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4821
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
  [Intel XE#4945]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4945
  [Intel XE#4947]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4947
  [Intel XE#4950]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4950
  [Intel XE#5018]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5018
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5300]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5300
  [Intel XE#5376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5376
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#5481]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5481
  [Intel XE#5560]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5560
  [Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
  [Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
  [Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
  [Intel XE#5573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5573
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#734]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/734
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979


Build changes
-------------

  * Linux: xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f -> xe-pw-152030v1

  IGT_8475: 1ddc997191d8aa008b49b5a4c47cf295c9a3c4f4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3467-10ed8e2e5529207fe710c22898b0c09ef7f16b0f: 10ed8e2e5529207fe710c22898b0c09ef7f16b0f
  xe-pw-152030v1: 152030v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152030v1/index.html

[-- Attachment #2: Type: text/html, Size: 57296 bytes --]

Re: [PATCH 2/2] drm/xe/guc: Add support for NPK as a GuC log target

[Lucas De Marchi]

On Wed, Jul 23, 2025 at 02:20:20PM -0700, John.C.Harrison@Intel.com wrote:
>From: John Harrison <John.C.Harrison@Intel.com>
>
>The GuC has an option to write log data via NPK. This is basically a
>magic IO address that GuC writes arbitrary data to and which can be
>logged by a suitable hardware logger. This can allow retrieval of the
>GuC log in hardware debug environments even when the system as a whole
>dies horribly.
>
>Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
>---
> drivers/gpu/drm/xe/xe_configfs.c | 61 ++++++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_configfs.h |  3 ++
> drivers/gpu/drm/xe/xe_guc.c      |  5 +++
> 3 files changed, 69 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
>index 8ec1ff1e4e80..9fbd7e2ab152 100644
>--- a/drivers/gpu/drm/xe/xe_configfs.c
>+++ b/drivers/gpu/drm/xe/xe_configfs.c
>@@ -77,6 +77,17 @@
>  * available for migrations, but it's disabled. This is intended for debugging
>  * purposes only.
>  *
>+ * GuC log target:
>+ * ---------------
>+ *
>+ * Specify the target for GuC firmware logging:
>+ *   0 = memory
>+ *   1 = NPK
>+ *   2 = memory + NPK
>+ *
>+ * Note that logging via NPK (North Peak) is only useful if some kind of hardware
>+ * debugger is attached that can save out the NPK stream externally.
>+ *
>  * Remove devices
>  * ==============
>  *
>@@ -90,6 +101,7 @@ struct xe_config_device {
>
> 	bool survivability_mode;
> 	u64 engines_allowed;
>+	u32 guc_log_target;

could be u8, right?

>
> 	/* protects attributes */
> 	struct mutex lock;
>@@ -226,12 +238,38 @@ static ssize_t engines_allowed_store(struct config_item *item, const char *page,
> 	return len;
> }
>
>+static ssize_t guc_log_target_show(struct config_item *item, char *page)
>+{
>+	struct xe_config_device *dev = to_xe_config_device(item);
>+
>+	return sprintf(page, "%d\n", dev->guc_log_target);
>+}
>+
>+static ssize_t guc_log_target_store(struct config_item *item, const char *page, size_t len)
>+{
>+	struct xe_config_device *dev = to_xe_config_device(item);
>+	u32 guc_log_target;
>+	int ret;
>+
>+	ret = kstrtou32(page, 0, &guc_log_target);
>+	if (ret)
>+		return ret;
>+
>+	mutex_lock(&dev->lock);
>+	dev->guc_log_target = guc_log_target;

nit: we are copy and pasting this function for each attribute and adjusting
the type/var. In https://patchwork.freedesktop.org/patch/665377/?series=151729&rev=2
I decided to name it `var` so at least it's easier to copy and paste and
an eventual consolidation later more obvious.

>+	mutex_unlock(&dev->lock);
>+
>+	return len;
>+}
>+
> CONFIGFS_ATTR(, survivability_mode);
> CONFIGFS_ATTR(, engines_allowed);
>+CONFIGFS_ATTR(, guc_log_target);
>
> static struct configfs_attribute *xe_config_device_attrs[] = {
> 	&attr_survivability_mode,
> 	&attr_engines_allowed,
>+	&attr_guc_log_target,

There's also this patch that will conflict here,
https://patchwork.freedesktop.org/patch/665141/?series=151773&rev=4
particularly if the the suggestion for adding a defaults is done.

> 	NULL,
> };
>
>@@ -386,6 +424,29 @@ u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev)
> 	return engines_allowed;
> }
>
>+/**
>+ * xe_configfs_get_guc_log_target - get configfs GuC log target attribute
>+ * @pdev: pci device
>+ *
>+ * find the configfs group that belongs to the pci device and return
>+ * the GuC log target attribute

There's also this in my patch series:
https://patchwork.freedesktop.org/patch/665376/?series=151729&rev=2
Any opinion?

>+ *
>+ * Return: GuC log target if config group is found, false otherwise
>+ */
>+u32 xe_configfs_get_guc_log_target(struct pci_dev *pdev)
>+{
>+	struct xe_config_device *dev = configfs_find_group(pdev);
>+	u32 guc_log_target;
>+
>+	if (!dev)
>+		return false;
>+
>+	guc_log_target = dev->guc_log_target;
>+	config_item_put(&dev->group.cg_item);
>+
>+	return guc_log_target;
>+}
>+
> int __init xe_configfs_init(void)
> {
> 	struct config_group *root = &xe_configfs.su_group;
>diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h
>index fb8764008089..97f9ad0f9495 100644
>--- a/drivers/gpu/drm/xe/xe_configfs.h
>+++ b/drivers/gpu/drm/xe/xe_configfs.h
>@@ -16,12 +16,15 @@ void xe_configfs_exit(void);
> bool xe_configfs_get_survivability_mode(struct pci_dev *pdev);
> void xe_configfs_clear_survivability_mode(struct pci_dev *pdev);
> u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev);
>+u32 xe_configfs_get_guc_log_target(struct pci_dev *pdev);
> #else
> static inline int xe_configfs_init(void) { return 0; }
> static inline void xe_configfs_exit(void) { }
> static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pdev) { return false; }
> static inline void xe_configfs_clear_survivability_mode(struct pci_dev *pdev) { }
> static inline u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev) { return U64_MAX; }
>+static inline u32 xe_configfs_get_guc_log_target(struct pci_dev *pdev) { return 0; }
>+

trailing newline here that can be fixed while pushing.

I'm ok pushing this and I and Michal rebase on top after the reviews are
finished.

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

> #endif
>
> #endif
>diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>index 8fac3c518975..53ef93e162d2 100644
>--- a/drivers/gpu/drm/xe/xe_guc.c
>+++ b/drivers/gpu/drm/xe/xe_guc.c
>@@ -16,6 +16,7 @@
> #include "regs/xe_guc_regs.h"
> #include "regs/xe_irq_regs.h"
> #include "xe_bo.h"
>+#include "xe_configfs.h"
> #include "xe_device.h"
> #include "xe_force_wake.h"
> #include "xe_gt.h"
>@@ -67,6 +68,7 @@ static u32 guc_bo_ggtt_addr(struct xe_guc *guc,
>
> static u32 guc_ctl_debug_flags(struct xe_guc *guc)
> {
>+	u32 target = xe_configfs_get_guc_log_target(to_pci_dev(guc_to_xe(guc)->drm.dev));
> 	u32 level = xe_guc_log_get_level(&guc->log);
> 	u32 flags = 0;
>
>@@ -75,6 +77,9 @@ static u32 guc_ctl_debug_flags(struct xe_guc *guc)
> 	else
> 		flags |= FIELD_PREP(GUC_LOG_VERBOSITY, GUC_LOG_LEVEL_TO_VERBOSITY(level));
>
>+	if (target)
>+		flags |= FIELD_PREP(GUC_LOG_DESTINATION, target);
>+
> 	return flags;
> }
>
>-- 
>2.49.0
>