From: fei.yang@intel.com
To: intel-xe@lists.freedesktop.org
Cc: lucas.demarchi@intel.com, Fei Yang <fei.yang@intel.com>
Subject: [PATCH 0/1] drm/xe: TileAddrRange registers are being deprecated.
Date: Mon, 29 Sep 2025 13:12:20 -0700 [thread overview]
Message-ID: <20250929201222.337295-1-fei.yang@intel.com> (raw)
From: Fei Yang <fei.yang@intel.com>
The TILEx_ADDR_RANGE registers will eventually be replaced by equivalent
registers within SoC MMIO space. When that happens these registers will
be deprecated. During the transition, TileAddrRange registers might not
contain valid values, but the same registers in SG unit continues to be
maintained. Reading that instead to avoid potential breakage.
Fei Yang (1):
drm/xe: TileAddrRange registers are being deprecated.
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 ++
drivers/gpu/drm/xe/xe_vram.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
--
2.43.0
next reply other threads:[~2025-09-29 20:07 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-29 20:12 fei.yang [this message]
2025-09-29 20:12 ` [PATCH 1/1] drm/xe: TileAddrRange registers are being deprecated fei.yang
2025-09-30 14:36 ` Lucas De Marchi
2025-09-29 20:15 ` ✓ CI.KUnit: success for " Patchwork
2025-09-29 21:17 ` ✓ Xe.CI.BAT: " Patchwork
2025-09-29 23:23 ` ✗ Xe.CI.Full: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2025-09-30 23:26 [PATCH 0/1] " fei.yang
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