From: fei.yang@intel.com
To: intel-xe@lists.freedesktop.org
Cc: lucas.demarchi@intel.com, Fei Yang <fei.yang@intel.com>
Subject: [PATCH 0/1] drm/xe: TileAddrRange registers are being deprecated.
Date: Tue, 30 Sep 2025 16:26:44 -0700 [thread overview]
Message-ID: <20250930232645.600251-1-fei.yang@intel.com> (raw)
From: Fei Yang <fei.yang@intel.com>
Quoting BSpec: 59353, "The TILEx_ADDR_RANGE registers no longer have any
impact on HW behavior. They now function only as scratch registers for
communication between SoC FW and the GPU driver, and will eventually be
replaced by equivalent registers within SoC MMIO space. At that point,
these registers can be deprecated from XeTLB.".
While the transition is ongoing, the SGAddrRangeforTile continues to be
valid and works on all platforms supported by xe, reading that instead
to avoid potential breakage.
Fei Yang (1):
drm/xe: TileAddrRange registers are being deprecated.
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 ++-
drivers/gpu/drm/xe/xe_vram.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
--
2.43.0
next reply other threads:[~2025-09-30 23:22 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-30 23:26 fei.yang [this message]
2025-09-30 23:26 ` [PATCH 1/1] drm/xe: TileAddrRange registers are being deprecated fei.yang
2025-10-01 20:15 ` Lucas De Marchi
2025-10-01 22:31 ` Matt Roper
2025-10-01 0:13 ` ✓ CI.KUnit: success for " Patchwork
2025-10-01 0:54 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-01 3:12 ` ✓ Xe.CI.Full: " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2025-09-29 20:12 [PATCH 0/1] " fei.yang
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