[PATCH 00/16] Optimize vrr.guardband and fix LRR

[PATCH 00/16] Optimize vrr.guardband and fix LRR

[Ankit Nautiyal]

Instead of setting vrr.guardband to vblank, use optimal guardband that
works for most of the cases. This will help in avoiding need of change
in guardband and fix the LRR feature that needs seamless switching to
a lower refresh rate.

First few patches fix/refactor and extract common functions required for
dsc/scaler prefill time computation. Later patches use these helpers to
compute an optimized guardband.

Also, for seamless_mn where vtotal is same but mode clock is changed to
seamlessly switch to lower rate, re-compute the vrr timings.

Few things that still need work:
-The timestamps corresponding with next start of vactive still need to be
fixed with the new scheme.
-Re-enabling CMRR

Rev2:
-Address comments from Mitul.
-Extract helpers for dsc/scaler prefill latencies.
-Fix downscaling factor for chroma subsampling.
-Use missing pkg C max latency.
-Fix guardband computation for seamless mn, always use vblank for
higher resolution.

Rev3:
-Drop patches for computing and storing PSR/Panel Replay wake times
latencies and use existing helpers to compute these in intel_alpm.c.
-Drop patch to change the Vmin as it was not required.

Rev4:
-Rebase
-Drop patch for checking bounds for scaler array access.
-Use a new flag for setting vrr timings for seamless drrs.

Rev5:
-Address comments from Mitul, Jani:
-Refactor few helpers for computing latencies.
-Rename the helper to check the guardband to intel_crtc_guardband_atomic_check()
-Refactor the helper intel_panel_highest_mode().

Rev6:
-Rebase
-Address review comments from Mitul.
-Improve documentation for and other minor fixes in Patch#12

Rev7:
-Address comments from Jani.
-Move the latency helpers from intel_display.c to intel_vrr.c and rename
the helpers appropriately.
-Drop redundant check for HAS_VRR with intel_vrr_possible().

Rev8:
-Fix CI issues.
-For fixed RR wait for delayed vblank before dsb interrupt.

Rev9:
-Fix vrr.vsync_start/end timings for 3D modes (patch#1)
-Rewrite the patch to wait for delayed vblank before dsb interrupt
(patch #11)
-Fix the flipline and vmin timings with optimized guardband (patch#12)

Rev10:
-Address comments from Ville: Use min guardband computation for setting
the vblank delay and set the crtc_vblank_start to delayed vblank.
(Patch#13)
-Modify the TRANS_SET_CONTEXT_LATENCY as per new guardband and use
vrr.guardband to readback vblank_start. (Patch#11)

-From previous revision:
->Drop patch#11 "drm/i915/dsb: Align flipdone with delayed vblank using
guardband wait", as this is no longer required.
->Modify Patch#12 "drm/i915/vrr: Use static guardband to support seamless
LRR switching" to only introduce a helper to compute the fix guardband.
Modify the commit message and the subject.

Rev11:
-Drop patches that are no longer required:
 -Patch for clamping SCL.
 -Patch to use vrr.vsync to compute vtotal
-Use guardband check for all platforms supporting VRR. (Patch#8)
-Add new patch to determine when to use optimized guardband. (Patch#11)
 Use optimized guardband whenever the VRR TG is active.
-Separate out patch to recompute the vblank start for optimized
 guardband. (Patch#12)

Rev12:
-Address issue with VRR for platforms which do not have VRR TG always
 active. For such platforms when switching to VRR, the vblank start is
 shifted for optimizing/reducing the guardband. This causes mismatch
 between old and new CRTC states and triggering unnecessary full modesets.
-Rename allow_vblank_delay_fastset() to allow_vblank_delay_fastset_lrr() to
 clarify its role in handling vblank delay via LRR codepaths. (Patch#14)
-Introduce allow_vblank_delay_fastset() to extend the logic and allow
 vblank delay when optimized guardband is used. (Patch#15)

Rev13:
-Address review comments from Ville.
-Change vblank_start only for platforms that have
 intel_vrr_always_use_vrr_tg == true. For others add the adjustement.
-Separate the patches to enable optimized guardband:
 - Patch#15 enables the optimized guardband only for
   intel_vrr_always_use_vrr_tg == true.
 - Patch#16 enables it for all relavant platforms.

Ankit Nautiyal (16):
  drm/i915/vrr: Use crtc_vsync_start/end for computing
    vrr.vsync_start/end
  drm/i915/skl_watermark: Fix the scaling factor for chroma subsampling
  drm/i915/skl_watermark: Pass linetime as argument to latency helpers
  drm/i915/skl_scaler: Introduce helper for chroma downscale factor
  drm/i915/display: Extract helpers to set dsc/scaler prefill latencies
  drm/i915/dp: Add SDP latency computation helper
  drm/i915/alpm: Add function to compute max link-wake latency
  drm/i915/display: Add guardband check for feature latencies
  drm/i915/skl_watermark: Remove redundant latency checks from vblank
    validation
  drm/i915/vrr:
    s/intel_vrr_compute_config_late/intel_vrr_compute_guardband
  drm/i915/vblank: Add helper to get correct vblank length
  drm/i915/vrr: Recompute vblank_start for platforms with always-on VRR
    TG
  drm/i915/display: Add vblank_start adjustment logic for always-on VRR
    TG
  drm/i915/vrr: Introduce helper to compute min static guardband
  drm/i915/display: Use optimized guardband for always-on VRR TG
  drm/i915/vrr: Use optimized guardband when VRR TG is active

 drivers/gpu/drm/i915/display/intel_alpm.c    |  15 ++
 drivers/gpu/drm/i915/display/intel_alpm.h    |   2 +
 drivers/gpu/drm/i915/display/intel_display.c | 195 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.c      |  47 +++++
 drivers/gpu/drm/i915/display/intel_dp.h      |   2 +
 drivers/gpu/drm/i915/display/intel_pfit.c    |  11 +-
 drivers/gpu/drm/i915/display/intel_psr.c     |   3 +-
 drivers/gpu/drm/i915/display/intel_vblank.c  |  10 +
 drivers/gpu/drm/i915/display/intel_vblank.h  |   2 +
 drivers/gpu/drm/i915/display/intel_vdsc.c    |  17 ++
 drivers/gpu/drm/i915/display/intel_vdsc.h    |   4 +
 drivers/gpu/drm/i915/display/intel_vrr.c     | 154 ++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vrr.h     |   3 +-
 drivers/gpu/drm/i915/display/skl_scaler.c    |  21 ++
 drivers/gpu/drm/i915/display/skl_scaler.h    |  10 +
 drivers/gpu/drm/i915/display/skl_watermark.c |  92 +--------
 drivers/gpu/drm/i915/display/skl_watermark.h |   1 +
 17 files changed, 485 insertions(+), 104 deletions(-)

-- 
2.45.2

[PATCH 01/16] drm/i915/vrr: Use crtc_vsync_start/end for computing vrr.vsync_start/end

[Ankit Nautiyal]

Use adjusted_mode->crtc_vsync_start/end instead of
adjusted_mode->vsync_start while computing vrr.vsync_start/end.
For most modes, these are same but for 3D/stereo modes the
crtc_vsync_start is different than vsync_start.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 190c51be5cbc..4bc14b5e685f 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -394,10 +394,10 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	if (HAS_AS_SDP(display)) {
 		crtc_state->vrr.vsync_start =
 			(crtc_state->hw.adjusted_mode.crtc_vtotal -
-			 crtc_state->hw.adjusted_mode.vsync_start);
+			 crtc_state->hw.adjusted_mode.crtc_vsync_start);
 		crtc_state->vrr.vsync_end =
 			(crtc_state->hw.adjusted_mode.crtc_vtotal -
-			 crtc_state->hw.adjusted_mode.vsync_end);
+			 crtc_state->hw.adjusted_mode.crtc_vsync_end);
 	}
 }
 
-- 
2.45.2

[PATCH 02/16] drm/i915/skl_watermark: Fix the scaling factor for chroma subsampling

[Ankit Nautiyal]

The Bspec:70151, mentions Chroma subsampling is a 2x downscale
operation. This means that the downscale factor is 2 in each direction.
So correct the downscaling factor to 4.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 9eb28d935757..4b1ef4fa8ed2 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2188,7 +2188,7 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state)
 				    crtc_state->hw.adjusted_mode.clock);
 	int num_scaler_users = hweight32(scaler_state->scaler_users);
 	int chroma_downscaling_factor =
-		crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
+		crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 4 : 1;
 	u32 dsc_prefill_latency = 0;
 
 	if (!crtc_state->dsc.compression_enable ||
@@ -2231,7 +2231,7 @@ scaler_prefill_latency(const struct intel_crtc_state *crtc_state)
 		u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
 		u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
 		int chroma_downscaling_factor =
-			crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
+			crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 4 : 1;
 		int latency;
 
 		latency = DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k *
-- 
2.45.2

[PATCH 03/16] drm/i915/skl_watermark: Pass linetime as argument to latency helpers

[Ankit Nautiyal]

Refactor dsc_prefill_latency and scaler_prefill_latency to take
linetime as an explicit parameter instead of computing it internally.

This avoids redundant calculations and simplifies scanline conversion
logic in skl_is_vblank_too_short().

This change also facilitates future extraction of these helpers for use
cases where latencies are computed for an optimized guardband, based on the
highest resolution mode, rather than the current mode.

v2: Sum all latency numbers and use intel_usecs_to_scanlines() to
convert to scanlines. (Ville).

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 19 +++++++++----------
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 4b1ef4fa8ed2..be87a861eb70 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2179,13 +2179,11 @@ cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
 }
 
 static int
-dsc_prefill_latency(const struct intel_crtc_state *crtc_state)
+dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct intel_crtc_scaler_state *scaler_state =
 					&crtc_state->scaler_state;
-	int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,
-				    crtc_state->hw.adjusted_mode.clock);
 	int num_scaler_users = hweight32(scaler_state->scaler_users);
 	int chroma_downscaling_factor =
 		crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 4 : 1;
@@ -2209,18 +2207,16 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state)
 
 	dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
 
-	return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, dsc_prefill_latency);
+	return dsc_prefill_latency;
 }
 
 static int
-scaler_prefill_latency(const struct intel_crtc_state *crtc_state)
+scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
 {
 	const struct intel_crtc_scaler_state *scaler_state =
 					&crtc_state->scaler_state;
 	int num_scaler_users = hweight32(scaler_state->scaler_users);
 	int scaler_prefill_latency = 0;
-	int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,
-				    crtc_state->hw.adjusted_mode.clock);
 
 	if (!num_scaler_users)
 		return scaler_prefill_latency;
@@ -2241,7 +2237,7 @@ scaler_prefill_latency(const struct intel_crtc_state *crtc_state)
 
 	scaler_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
 
-	return intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, scaler_prefill_latency);
+	return scaler_prefill_latency;
 }
 
 static bool
@@ -2250,11 +2246,14 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
 {
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
+	int linetime = DIV_ROUND_UP(1000 * adjusted_mode->htotal,
+				    adjusted_mode->clock);
+
+	latency += scaler_prefill_latency(crtc_state, linetime) +
+		   dsc_prefill_latency(crtc_state, linetime);
 
 	return crtc_state->framestart_delay +
 		intel_usecs_to_scanlines(adjusted_mode, latency) +
-		scaler_prefill_latency(crtc_state) +
-		dsc_prefill_latency(crtc_state) +
 		wm0_lines >
 		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
 }
-- 
2.45.2

[PATCH 04/16] drm/i915/skl_scaler: Introduce helper for chroma downscale factor

[Ankit Nautiyal]

For 444 to 420 output format conversion, scaler uses 2x downscaling in
each direction. Introduce skl_scaler_chroma_downscale_factor() to
encapsulate the chroma subsampling adjustment used in scaler/dsc
pre-fill latency calculations.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/skl_scaler.c    | 5 +++++
 drivers/gpu/drm/i915/display/skl_scaler.h    | 3 +++
 drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++----
 3 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index c6cccf170ff1..af2cbd54c32e 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -968,3 +968,8 @@ void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state)
 			  1);
 	intel_de_write(display, XELPD_DISPLAY_ERR_FATAL_MASK, 0);
 }
+
+int skl_scaler_chroma_downscale_factor(const struct intel_crtc_state *crtc_state)
+{
+	return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 4 : 1;
+}
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h
index 12a19016c5f6..257330d4c329 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.h
+++ b/drivers/gpu/drm/i915/display/skl_scaler.h
@@ -45,4 +45,7 @@ skl_scaler_mode_valid(struct intel_display *display,
 void adl_scaler_ecc_mask(const struct intel_crtc_state *crtc_state);
 
 void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state);
+
+int skl_scaler_chroma_downscale_factor(const struct intel_crtc_state *crtc_state);
+
 #endif
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index be87a861eb70..2da54569f06a 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -30,6 +30,7 @@
 #include "intel_plane.h"
 #include "intel_wm.h"
 #include "skl_universal_plane_regs.h"
+#include "skl_scaler.h"
 #include "skl_watermark.h"
 #include "skl_watermark_regs.h"
 
@@ -2185,8 +2186,7 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
 	const struct intel_crtc_scaler_state *scaler_state =
 					&crtc_state->scaler_state;
 	int num_scaler_users = hweight32(scaler_state->scaler_users);
-	int chroma_downscaling_factor =
-		crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 4 : 1;
+	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
 	u32 dsc_prefill_latency = 0;
 
 	if (!crtc_state->dsc.compression_enable ||
@@ -2226,8 +2226,7 @@ scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
 	if (num_scaler_users > 1) {
 		u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
 		u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
-		int chroma_downscaling_factor =
-			crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 4 : 1;
+		int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
 		int latency;
 
 		latency = DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k *
-- 
2.45.2

[PATCH 05/16] drm/i915/display: Extract helpers to set dsc/scaler prefill latencies

[Ankit Nautiyal]

Currently dsc/scaler prefill latencies are handled during watermark
calculations. With the optimized guardband, we need to compute the
latencies to find the minimum guardband that works for most cases.
Extract the helpers to compute these latencies, so that they can be used
while computing vrr guardband.

While at it, put declarations in reverse xmas tree order for better
redability.

v2: Initialize {h,v}scale_k to 0, and simplify the check in
intel_display_scaler_prefill_latency(). (Mitul)

v3: Move helpers from intel_display.c to intel_vrr.c as they are specific
to account for latencies to program vrr guardband. (Jani)

v4: Move helpers to dsc/scaler files. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c    | 17 +++++++
 drivers/gpu/drm/i915/display/intel_vdsc.h    |  4 ++
 drivers/gpu/drm/i915/display/skl_scaler.c    | 16 +++++++
 drivers/gpu/drm/i915/display/skl_scaler.h    |  7 +++
 drivers/gpu/drm/i915/display/skl_watermark.c | 47 +++++++++-----------
 5 files changed, 66 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 8e799e225af1..e59d62994798 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -1077,3 +1077,20 @@ int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state)
 
 	return min_cdclk;
 }
+
+int intel_dsc_guardband_latency(int num_scaler_users, u64 *hscale, u64 *vscale,
+				int chroma_downscaling_factor,
+				int cdclk_prefill_adjustment,
+				int linetime)
+{
+	int dsc_prefill_latency;
+
+	dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10);
+
+	for (int i = 0; i < num_scaler_users; i++)
+		dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale[i] * vscale[i],
+						       1000000);
+	dsc_prefill_latency *= cdclk_prefill_adjustment;
+
+	return dsc_prefill_latency;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 9e2812f99dd7..60aecadf95bf 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -32,5 +32,9 @@ void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
 void intel_vdsc_state_dump(struct drm_printer *p, int indent,
 			   const struct intel_crtc_state *crtc_state);
 int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state);
+int intel_dsc_guardband_latency(int num_scaler_users, u64 *hscale, u64 *vscale,
+				int chroma_downscaling_factor,
+				int cdclk_prefill_adjustment,
+				int linetime);
 
 #endif /* __INTEL_VDSC_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index af2cbd54c32e..69130744c09e 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -973,3 +973,19 @@ int skl_scaler_chroma_downscale_factor(const struct intel_crtc_state *crtc_state
 {
 	return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 4 : 1;
 }
+
+int skl_scaler_guardband_latency(int num_scaler_users, u64 hscale, u64 vscale,
+				 int chroma_downscaling_factor,
+				 int cdclk_prefill_adjustment,
+				 int linetime)
+{
+	int scaler_prefill_latency;
+
+	scaler_prefill_latency = 4 * linetime +
+				 DIV_ROUND_UP_ULL((4 * linetime * hscale * vscale *
+						   chroma_downscaling_factor), 1000000);
+
+	scaler_prefill_latency *= cdclk_prefill_adjustment;
+
+	return scaler_prefill_latency;
+}
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.h b/drivers/gpu/drm/i915/display/skl_scaler.h
index 257330d4c329..5aa53d576aba 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.h
+++ b/drivers/gpu/drm/i915/display/skl_scaler.h
@@ -5,6 +5,8 @@
 #ifndef INTEL_SCALER_H
 #define INTEL_SCALER_H
 
+#include <linux/types.h>
+
 enum drm_mode_status;
 struct drm_display_mode;
 struct intel_atomic_state;
@@ -48,4 +50,9 @@ void adl_scaler_ecc_unmask(const struct intel_crtc_state *crtc_state);
 
 int skl_scaler_chroma_downscale_factor(const struct intel_crtc_state *crtc_state);
 
+int skl_scaler_guardband_latency(int num_scaler_users, u64 hscale, u64 vscale,
+				 int chroma_downscaling_factor,
+				 int cdclk_prefill_adjustment,
+				 int linetime);
+
 #endif
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 2da54569f06a..deb43f0c348a 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -28,6 +28,7 @@
 #include "intel_flipq.h"
 #include "intel_pcode.h"
 #include "intel_plane.h"
+#include "intel_vdsc.h"
 #include "intel_wm.h"
 #include "skl_universal_plane_regs.h"
 #include "skl_scaler.h"
@@ -2182,11 +2183,12 @@ cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
 static int
 dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
 {
+	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
+	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	const struct intel_crtc_scaler_state *scaler_state =
-					&crtc_state->scaler_state;
 	int num_scaler_users = hweight32(scaler_state->scaler_users);
-	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
+	u64 hscale_k[ARRAY_SIZE(scaler_state->scalers)];
+	u64 vscale_k[ARRAY_SIZE(scaler_state->scalers)];
 	u32 dsc_prefill_latency = 0;
 
 	if (!crtc_state->dsc.compression_enable ||
@@ -2194,18 +2196,16 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
 	    num_scaler_users > crtc->num_scalers)
 		return dsc_prefill_latency;
 
-	dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10);
-
 	for (int i = 0; i < num_scaler_users; i++) {
-		u64 hscale_k, vscale_k;
-
-		hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
-		vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
-		dsc_prefill_latency = DIV_ROUND_UP_ULL(dsc_prefill_latency * hscale_k * vscale_k,
-						       1000000);
+		hscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
+		vscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
 	}
 
-	dsc_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
+	dsc_prefill_latency =
+		intel_dsc_guardband_latency(num_scaler_users, hscale_k, vscale_k,
+					    chroma_downscaling_factor,
+					    cdclk_prefill_adjustment(crtc_state),
+					    linetime);
 
 	return dsc_prefill_latency;
 }
@@ -2213,28 +2213,25 @@ dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
 static int
 scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
 {
-	const struct intel_crtc_scaler_state *scaler_state =
-					&crtc_state->scaler_state;
+	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
+	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
 	int num_scaler_users = hweight32(scaler_state->scaler_users);
+	u64 hscale_k = 0, vscale_k = 0;
 	int scaler_prefill_latency = 0;
 
 	if (!num_scaler_users)
 		return scaler_prefill_latency;
 
-	scaler_prefill_latency = 4 * linetime;
-
 	if (num_scaler_users > 1) {
-		u64 hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
-		u64 vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
-		int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
-		int latency;
-
-		latency = DIV_ROUND_UP_ULL((4 * linetime * hscale_k * vscale_k *
-					    chroma_downscaling_factor), 1000000);
-		scaler_prefill_latency += latency;
+		hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
+		vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
 	}
 
-	scaler_prefill_latency *= cdclk_prefill_adjustment(crtc_state);
+	scaler_prefill_latency =
+		skl_scaler_guardband_latency(num_scaler_users, hscale_k, vscale_k,
+					     chroma_downscaling_factor,
+					     cdclk_prefill_adjustment(crtc_state),
+					     linetime);
 
 	return scaler_prefill_latency;
 }
-- 
2.45.2

[PATCH 06/16] drm/i915/dp: Add SDP latency computation helper

[Ankit Nautiyal]

Add a helper to compute vblank time needed for transmitting specific
DisplayPort SDPs like PPS, GAMUT_METADATA, and VSC_EXT. Latency is
based on line count per packet type and current line time.

Used to ensure adequate vblank when features like DSC/HDR are enabled.

Bspec: 70151
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 47 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h |  2 ++
 2 files changed, 49 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 2eab591a8ef5..83c46e4680b3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6857,3 +6857,50 @@ void intel_dp_mst_resume(struct intel_display *display)
 		}
 	}
 }
+
+static
+int intel_dp_get_sdp_latency(u32 type, int linetime_us)
+{
+	int lines;
+
+	switch (type) {
+	case DP_SDP_VSC_EXT_VESA:
+	case DP_SDP_VSC_EXT_CEA:
+		lines = 10;
+		break;
+	case HDMI_PACKET_TYPE_GAMUT_METADATA:
+		lines = 8;
+		break;
+	case DP_SDP_PPS:
+		lines = 6;
+		break;
+	default:
+		lines = 0;
+		break;
+	}
+
+	return lines * linetime_us;
+}
+
+int intel_dp_compute_sdp_latency(const struct intel_crtc_state *crtc_state,
+				 bool assume_all_enabled)
+{
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	int sdp_latency = 0;
+	int linetime_us;
+
+	linetime_us = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000,
+				   adjusted_mode->crtc_clock);
+	if (assume_all_enabled ||
+	    crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
+		sdp_latency = max(sdp_latency,
+				  intel_dp_get_sdp_latency(HDMI_PACKET_TYPE_GAMUT_METADATA,
+							   linetime_us));
+
+	if (assume_all_enabled || crtc_state->dsc.compression_enable)
+		sdp_latency = max(sdp_latency,
+				  intel_dp_get_sdp_latency(DP_SDP_PPS, linetime_us));
+
+	return sdp_latency;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index f90cfd1dbbd0..d222749b191c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -215,5 +215,7 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
 int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector);
 void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
 bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state);
+int intel_dp_compute_sdp_latency(const struct intel_crtc_state *crtc_state,
+				 bool assume_all_enabled);
 
 #endif /* __INTEL_DP_H__ */
-- 
2.45.2

[PATCH 07/16] drm/i915/alpm: Add function to compute max link-wake latency

[Ankit Nautiyal]

Introduce a helper to compute the max link wake latency when using
Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF features.

This will be used to compute the minimum guardband so that the link wake
latencies are accounted and these features work smoothly for higher
refresh rate panels.

Bspec: 70151, 71477
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/display/intel_alpm.h |  2 ++
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 749119cc0b28..df380ecf7d0f 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -598,3 +598,18 @@ bool intel_alpm_get_error(struct intel_dp *intel_dp)
 
 	return false;
 }
+
+int intel_alpm_compute_max_link_wake_latency(const struct intel_crtc_state *crtc_state,
+					     bool assume_all_enabled)
+{
+	int psr2_vblank_time = 0;
+	int auxless_wake_time = 0;
+
+	if (assume_all_enabled || crtc_state->has_sel_update)
+		psr2_vblank_time =  io_buffer_wake_time(crtc_state);
+
+	if (assume_all_enabled || crtc_state->has_panel_replay)
+		auxless_wake_time = _lnl_compute_aux_less_wake_time(crtc_state);
+
+	return max(psr2_vblank_time, auxless_wake_time);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index a861c20b5d79..b371827af356 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -38,4 +38,6 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
 				 const struct intel_crtc_state *crtc_state);
 void intel_alpm_disable(struct intel_dp *intel_dp);
 bool intel_alpm_get_error(struct intel_dp *intel_dp);
+int intel_alpm_compute_max_link_wake_latency(const struct intel_crtc_state *crtc_state,
+					     bool assume_all_enabled);
 #endif
-- 
2.45.2

[PATCH 08/16] drm/i915/display: Add guardband check for feature latencies

[Ankit Nautiyal]

Add a check during atomic crtc check phase to ensure the programmed VRR
guardband is sufficient to cover latencies introduced by enabled features
such as DSC, PSR/PR, scalers, and DP SDPs.

Currently, the guardband is programmed to match the vblank length, so
existing checks in skl_is_vblank_too_short() are valid. However, upcoming
changes will optimize the guardband independently of vblank, making those
checks incorrect.

Introduce an explicit guardband check to prepare for future updates
that will remove checking against the vblank length and later program an
optimized guardband.

Note: Need some work to account for package C state latency and the use
of PKG_C_Latency register. When PKG_C_LATENCY is configured hardware will
automatically wake from package C states before framestart so that
package C state latency can be considered to be 0.

v2: Use new helper for PSR2/Panel Replay latency.

v3:
- Align the name of helper with intel_crtc_atomic_check and rename it to
  intel_crtc_guardband_atomic_check(). (Jani)
- Simplify checks in the helper. (Mitul)
- Make a separate helper to compute wm0 prefill time. (Mitul)

v4: Drop redundant HAS_VRR() check. (Jani).

v5:
- Use intel_usecs_to_scanlines() instead of hand rolled stuff. (Ville)
- Allow guardband check on all VRR supporting platforms.
- Add a TODO note for accounting for pkgc latency.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> (#v3)
---
 drivers/gpu/drm/i915/display/intel_display.c | 147 +++++++++++++++++++
 drivers/gpu/drm/i915/display/skl_watermark.c |   2 +-
 drivers/gpu/drm/i915/display/skl_watermark.h |   1 +
 3 files changed, 149 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b57efd870774..ec415b939770 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4189,6 +4189,147 @@ static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
 	return 0;
 }
 
+static int
+cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_atomic_state *state =
+		to_intel_atomic_state(crtc_state->uapi.state);
+	const struct intel_cdclk_state *cdclk_state;
+
+	cdclk_state = intel_atomic_get_cdclk_state(state);
+	if (IS_ERR(cdclk_state)) {
+		drm_WARN_ON(display->drm, PTR_ERR(cdclk_state));
+		return 1;
+	}
+
+	return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,
+				   2 * intel_cdclk_logical(cdclk_state)));
+}
+
+static int
+dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
+{
+	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
+	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	int num_scaler_users = hweight32(scaler_state->scaler_users);
+	u64 hscale_k[ARRAY_SIZE(scaler_state->scalers)];
+	u64 vscale_k[ARRAY_SIZE(scaler_state->scalers)];
+	u32 dsc_prefill_latency = 0;
+
+	if (!crtc_state->dsc.compression_enable ||
+	    !num_scaler_users ||
+	    num_scaler_users > crtc->num_scalers)
+		return dsc_prefill_latency;
+
+	for (int i = 0; i < num_scaler_users; i++) {
+		hscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
+		vscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
+	}
+
+	dsc_prefill_latency =
+		intel_dsc_guardband_latency(num_scaler_users, hscale_k, vscale_k,
+					    chroma_downscaling_factor,
+					    cdclk_prefill_adjustment(crtc_state),
+					    linetime);
+
+	return dsc_prefill_latency;
+}
+
+static int
+scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
+{
+	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
+	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
+	int num_scaler_users = hweight32(scaler_state->scaler_users);
+	u64 hscale_k = 0, vscale_k = 0;
+	int scaler_prefill_latency = 0;
+
+	if (!num_scaler_users)
+		return scaler_prefill_latency;
+
+	if (num_scaler_users > 1) {
+		hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
+		vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
+	}
+
+	scaler_prefill_latency =
+		skl_scaler_guardband_latency(num_scaler_users, hscale_k, vscale_k,
+					     chroma_downscaling_factor,
+					     cdclk_prefill_adjustment(crtc_state),
+					     linetime);
+
+	return scaler_prefill_latency;
+}
+
+static int
+wm0_prefill_latency(int linetime_us, int max_wm0_lines)
+{
+	return 20 + linetime_us * max_wm0_lines;
+}
+
+static int intel_crtc_guardband_atomic_check(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	int dsc_prefill_time = 0;
+	int scaler_prefill_time;
+	int wm0_prefill_time;
+	int psr2_pr_latency;
+	int min_guardband;
+	int guardband_us;
+	int sagv_latency;
+	int linetime_us;
+	int sdp_latency;
+	int pm_delay;
+
+	if (!adjusted_mode->crtc_clock)
+		return 0;
+
+	linetime_us = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000,
+				   adjusted_mode->crtc_clock);
+
+	/*
+	 * #TODO
+	 * Account for package C state latency and setting of PKG_C_LATENCY
+	 * register.
+	 * When PKG_C_LATENCY is configured (not all 1s), hardware will
+	 * automatically wake from package C states before framestart so
+	 * that package C state latency can be considered to be 0.
+	 *
+	 * Use max of sagv and package C state latency.
+	 */
+	sagv_latency = display->sagv.block_time_us;
+
+	wm0_prefill_time = wm0_prefill_latency(linetime_us, skl_max_wm0_lines(crtc_state));
+
+	scaler_prefill_time = scaler_prefill_latency(crtc_state, linetime_us);
+
+	dsc_prefill_time = dsc_prefill_latency(crtc_state, linetime_us);
+
+	pm_delay = crtc_state->framestart_delay +
+		   sagv_latency +
+		   wm0_prefill_time +
+		   scaler_prefill_time +
+		   dsc_prefill_time;
+
+	psr2_pr_latency = intel_alpm_compute_max_link_wake_latency(crtc_state, false);
+	sdp_latency = intel_dp_compute_sdp_latency(crtc_state, false);
+
+	guardband_us = max(sdp_latency, psr2_pr_latency);
+	guardband_us = max(guardband_us, pm_delay);
+	min_guardband = intel_usecs_to_scanlines(adjusted_mode, guardband_us);
+
+	if (crtc_state->vrr.guardband < min_guardband) {
+		drm_dbg_kms(display->drm, "vrr.guardband %d < min guardband %d\n",
+			    crtc_state->vrr.guardband, min_guardband);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 				   struct intel_crtc *crtc)
 {
@@ -4251,6 +4392,12 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 	if (ret)
 		return ret;
 
+	if (intel_vrr_possible(crtc_state)) {
+		ret = intel_crtc_guardband_atomic_check(crtc_state);
+		if (ret)
+			return ret;
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index deb43f0c348a..9a368bb9e92a 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2254,7 +2254,7 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
 		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
 }
 
-static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
+int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum plane_id plane_id;
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index 62790816f030..8706c2010ebe 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -78,6 +78,7 @@ void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
 void intel_program_dpkgc_latency(struct intel_atomic_state *state);
 
 bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state);
+int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state);
 
 #endif /* __SKL_WATERMARK_H__ */
 
-- 
2.45.2

[PATCH 09/16] drm/i915/skl_watermark: Remove redundant latency checks from vblank validation

[Ankit Nautiyal]

Drop DSC and scaler prefill latency checks from skl_is_vblank_too_short().
These are now covered by the guardband validation added during the atomic
CRTC check phase.

This cleanup prepares for future changes where the guardband will be
optimized independently of vblank length, making vblank-based checks
obsolete.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 80 --------------------
 1 file changed, 80 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 9a368bb9e92a..73e5b2d8ae83 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -28,7 +28,6 @@
 #include "intel_flipq.h"
 #include "intel_pcode.h"
 #include "intel_plane.h"
-#include "intel_vdsc.h"
 #include "intel_wm.h"
 #include "skl_universal_plane_regs.h"
 #include "skl_scaler.h"
@@ -2162,91 +2161,12 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
 	return 0;
 }
 
-static int
-cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_display *display = to_intel_display(crtc_state);
-	struct intel_atomic_state *state =
-		to_intel_atomic_state(crtc_state->uapi.state);
-	const struct intel_cdclk_state *cdclk_state;
-
-	cdclk_state = intel_atomic_get_cdclk_state(state);
-	if (IS_ERR(cdclk_state)) {
-		drm_WARN_ON(display->drm, PTR_ERR(cdclk_state));
-		return 1;
-	}
-
-	return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,
-				   2 * intel_cdclk_logical(cdclk_state)));
-}
-
-static int
-dsc_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
-{
-	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
-	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	int num_scaler_users = hweight32(scaler_state->scaler_users);
-	u64 hscale_k[ARRAY_SIZE(scaler_state->scalers)];
-	u64 vscale_k[ARRAY_SIZE(scaler_state->scalers)];
-	u32 dsc_prefill_latency = 0;
-
-	if (!crtc_state->dsc.compression_enable ||
-	    !num_scaler_users ||
-	    num_scaler_users > crtc->num_scalers)
-		return dsc_prefill_latency;
-
-	for (int i = 0; i < num_scaler_users; i++) {
-		hscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].hscale, 1000) >> 16);
-		vscale_k[i] = max(1000, mul_u32_u32(scaler_state->scalers[i].vscale, 1000) >> 16);
-	}
-
-	dsc_prefill_latency =
-		intel_dsc_guardband_latency(num_scaler_users, hscale_k, vscale_k,
-					    chroma_downscaling_factor,
-					    cdclk_prefill_adjustment(crtc_state),
-					    linetime);
-
-	return dsc_prefill_latency;
-}
-
-static int
-scaler_prefill_latency(const struct intel_crtc_state *crtc_state, int linetime)
-{
-	const struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
-	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
-	int num_scaler_users = hweight32(scaler_state->scaler_users);
-	u64 hscale_k = 0, vscale_k = 0;
-	int scaler_prefill_latency = 0;
-
-	if (!num_scaler_users)
-		return scaler_prefill_latency;
-
-	if (num_scaler_users > 1) {
-		hscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].hscale, 1000) >> 16);
-		vscale_k = max(1000, mul_u32_u32(scaler_state->scalers[0].vscale, 1000) >> 16);
-	}
-
-	scaler_prefill_latency =
-		skl_scaler_guardband_latency(num_scaler_users, hscale_k, vscale_k,
-					     chroma_downscaling_factor,
-					     cdclk_prefill_adjustment(crtc_state),
-					     linetime);
-
-	return scaler_prefill_latency;
-}
-
 static bool
 skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
 			int wm0_lines, int latency)
 {
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
-	int linetime = DIV_ROUND_UP(1000 * adjusted_mode->htotal,
-				    adjusted_mode->clock);
-
-	latency += scaler_prefill_latency(crtc_state, linetime) +
-		   dsc_prefill_latency(crtc_state, linetime);
 
 	return crtc_state->framestart_delay +
 		intel_usecs_to_scanlines(adjusted_mode, latency) +
-- 
2.45.2

[PATCH 10/16] drm/i915/vrr: s/intel_vrr_compute_config_late/intel_vrr_compute_guardband

[Ankit Nautiyal]

The helper intel_vrr_compute_config_late() practically just computes the
guardband. Rename intel_vrr_compute_config_late() to
intel_vrr_compute_guardband().

Since we are going to compute the guardband and then move the
vblank_start for optmizing guardband, move the helper to
intel_crtc_compute_config() which handles such changes.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
 drivers/gpu/drm/i915/display/intel_vrr.c     | 2 +-
 drivers/gpu/drm/i915/display/intel_vrr.h     | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ec415b939770..b2d4e24fd7c6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2414,6 +2414,8 @@ static int intel_crtc_compute_config(struct intel_atomic_state *state,
 	if (ret)
 		return ret;
 
+	intel_vrr_compute_guardband(crtc_state);
+
 	ret = intel_dpll_crtc_compute_clock(state, crtc);
 	if (ret)
 		return ret;
@@ -4869,8 +4871,6 @@ intel_modeset_pipe_config_late(struct intel_atomic_state *state,
 	struct drm_connector *connector;
 	int i;
 
-	intel_vrr_compute_config_late(crtc_state);
-
 	for_each_new_connector_in_state(&state->base, connector,
 					conn_state, i) {
 		struct intel_encoder *encoder =
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 4bc14b5e685f..8d71d7dc9d12 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -433,7 +433,7 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
 		   intel_vrr_max_vblank_guardband(crtc_state));
 }
 
-void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
+void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 7317f8730089..bc9044621635 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -21,7 +21,7 @@ bool intel_vrr_possible(const struct intel_crtc_state *crtc_state);
 void intel_vrr_check_modeset(struct intel_atomic_state *state);
 void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			      struct drm_connector_state *conn_state);
-void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state);
+void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state);
 void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 void intel_vrr_enable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_send_push(struct intel_dsb *dsb,
-- 
2.45.2

[PATCH 11/16] drm/i915/vblank: Add helper to get correct vblank length

[Ankit Nautiyal]

Currently crtc_vblank_start is assumed to be the vblank_start for the fixed
refresh rate case. That value can be different from the variable refresh
rate case whenever always_use_vrr_tg()==false. On icl/tgl it's always
different due to the extra vblank delay, and also on adl+ it could be
different if we were to use an optimized guardband.

So places where crtc_vblank_start is used to compute vblank length needs
change so as to account for cases where vrr is enabled. Specifically
with vrr.enable the effective vblank length is actually guardband.

Add a helper to get the correct vblank length for both vrr and fixed
refresh rate cases. Use this helper where vblank_start is used to
compute the vblank length.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_pfit.c    | 11 +++++++----
 drivers/gpu/drm/i915/display/intel_psr.c     |  3 +--
 drivers/gpu/drm/i915/display/intel_vblank.c  | 10 ++++++++++
 drivers/gpu/drm/i915/display/intel_vblank.h  |  2 ++
 drivers/gpu/drm/i915/display/skl_watermark.c |  3 ++-
 5 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
index 68539e7c2a24..ebbaa1d419ba 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.c
+++ b/drivers/gpu/drm/i915/display/intel_pfit.c
@@ -14,6 +14,7 @@
 #include "intel_lvds_regs.h"
 #include "intel_pfit.h"
 #include "intel_pfit_regs.h"
+#include "intel_vblank.h"
 #include "skl_scaler.h"
 
 static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_state)
@@ -306,14 +307,15 @@ centre_horizontally(struct drm_display_mode *adjusted_mode,
 }
 
 static void
-centre_vertically(struct drm_display_mode *adjusted_mode,
+centre_vertically(struct intel_crtc_state *crtc_state,
+		  struct drm_display_mode *adjusted_mode,
 		  int height)
 {
 	u32 border, sync_pos, blank_width, sync_width;
 
 	/* keep the vsync and vblank widths constant */
 	sync_width = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
-	blank_width = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start;
+	blank_width = intel_crtc_vblank_length(crtc_state);
 	sync_pos = (blank_width - sync_width + 1) / 2;
 
 	border = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
@@ -392,7 +394,8 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
 					  PFIT_HORIZ_INTERP_BILINEAR);
 		}
 	} else if (scaled_width < scaled_height) { /* letter */
-		centre_vertically(adjusted_mode,
+		centre_vertically(crtc_state,
+				  adjusted_mode,
 				  scaled_width / pipe_src_w);
 
 		*border = LVDS_BORDER_ENABLE;
@@ -489,7 +492,7 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
 		 * heights and modify the values programmed into the CRTC.
 		 */
 		centre_horizontally(adjusted_mode, pipe_src_w);
-		centre_vertically(adjusted_mode, pipe_src_h);
+		centre_vertically(crtc_state, adjusted_mode, pipe_src_h);
 		border = LVDS_BORDER_ENABLE;
 		break;
 	case DRM_MODE_SCALE_ASPECT:
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index f7115969b4c5..ae6b94a5d450 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1365,8 +1365,7 @@ static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
 				       bool aux_less)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
-	int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -
-		crtc_state->hw.adjusted_mode.crtc_vblank_start;
+	int vblank = intel_crtc_vblank_length(crtc_state);
 	int wake_lines;
 
 	if (aux_less)
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 0b7fcc05e64c..2fc0c1c0bb87 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -767,3 +767,13 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 
 	return scanline;
 }
+
+int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state)
+{
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+	if (crtc_state->vrr.enable)
+		return crtc_state->vrr.guardband;
+	else
+		return adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h
index 21fbb08d61d5..98d04cacd65f 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.h
+++ b/drivers/gpu/drm/i915/display/intel_vblank.h
@@ -48,4 +48,6 @@ const struct intel_crtc_state *
 intel_pre_commit_crtc_state(struct intel_atomic_state *state,
 			    struct intel_crtc *crtc);
 
+int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_VBLANK_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 73e5b2d8ae83..6fb2c78fe29b 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -28,6 +28,7 @@
 #include "intel_flipq.h"
 #include "intel_pcode.h"
 #include "intel_plane.h"
+#include "intel_vblank.h"
 #include "intel_wm.h"
 #include "skl_universal_plane_regs.h"
 #include "skl_scaler.h"
@@ -2171,7 +2172,7 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
 	return crtc_state->framestart_delay +
 		intel_usecs_to_scanlines(adjusted_mode, latency) +
 		wm0_lines >
-		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
+		intel_crtc_vblank_length(crtc_state);
 }
 
 int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
-- 
2.45.2

[PATCH 12/16] drm/i915/vrr: Recompute vblank_start for platforms with always-on VRR TG

[Ankit Nautiyal]

Currently, crtc_vblank_start is read from either the VBLANK_START register
(on pre-ADL platforms) or computed as vdisplay + set_context_latency in
intel_get_transcoder_timings().

This works when the entire vblank region after vdisplay is treated as
guardband, i.e.:
delayed vblank start = vdisplay + SCL = vtotal - guardband.

However, with optimized guardband, the guardband becomes shorter, and the
delayed vblank_start moves further away from vdisplay.

For platforms where intel_vrr_always_use_vrr_tg == false, the delayed
vblank start is only relevant in VRR mode. We retain the original
crtc_vblank_start and apply adjustments in VRR-specific paths. Evasion
logic, push clear already use vtotal - guardband directly for VRR case.

On platforms where intel_vrr_always_use_vrr_tg == true, the delayed
vblank_start is used in both fixed and VRR modes. So we need to change the
crtc_vblank_start so that fixed rr case works properly.

Therefore for the readout, we need to overwrite crtc_vblank_start
with vtotal - guardband to ensure correct behavior across both modes.

This change prepares the pipeline for optimized guardband usage by ensuring
crtc_vblank_start reflects the correct timing on platforms with always-on
VRR TG.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 8d71d7dc9d12..221b25832e56 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -821,6 +821,20 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	 */
 	if (crtc_state->vrr.enable)
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+
+	/*
+	 * For platforms that always use the VRR timing generator, we overwrite
+	 * crtc_vblank_start with vtotal - guardband to reflect the delayed
+	 * vblank start. This works for both default and optimized guardband values.
+	 * On other platforms, we keep the original value from
+	 * intel_get_transcoder_timings() and apply adjustments only in VRR-specific
+	 * paths as needed.
+	 */
+	if (intel_vrr_always_use_vrr_tg(display))
+		crtc_state->hw.adjusted_mode.crtc_vblank_start =
+			crtc_state->hw.adjusted_mode.crtc_vtotal -
+			crtc_state->vrr.guardband;
+
 }
 
 int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state)
-- 
2.45.2

[PATCH 13/16] drm/i915/display: Add vblank_start adjustment logic for always-on VRR TG

[Ankit Nautiyal]

As we move towards using a shorter, optimized guardband, we need to adjust
how the delayed vblank start is computed.

Introduce intel_crtc_compute_vrr_guardband() to handle guardband
computation and apply vblank_start adjustment for platforms that always use
the VRR timing generator.

This function wraps the existing intel_vrr_compute_guardband() and adjusts
crtc_vblank_start using (vblank_length - guardband) only when
intel_vrr_always_use_vrr_tg() is true. Since the guardband is not yet
optimized, the adjustment currently evaluates to zero, preserving existing
behavior.

This paves way for guardband optimization, by handling the movement of
the crtc_vblank_start for platforms that have VRR TG always active.

Also update allow_vblank_delay_fastset() to permit vblank delay adjustments
during fastboot when VRR TG is always active, even without inherited state.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 33 ++++++++++++++++++--
 1 file changed, 30 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b2d4e24fd7c6..1964e41b5704 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2403,6 +2403,27 @@ static int intel_crtc_compute_set_context_latency(struct intel_atomic_state *sta
 	return 0;
 }
 
+static void intel_crtc_compute_vrr_guardband(struct intel_atomic_state *state,
+					     struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(state);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct drm_display_mode *adjusted_mode =
+		&crtc_state->hw.adjusted_mode;
+
+	intel_vrr_compute_guardband(crtc_state);
+
+	if (intel_vrr_always_use_vrr_tg(display)) {
+		int vblank_length = adjusted_mode->crtc_vtotal -
+				    (crtc_state->set_context_latency +
+				     adjusted_mode->crtc_vdisplay);
+
+		adjusted_mode->crtc_vblank_start +=
+			vblank_length - crtc_state->vrr.guardband;
+	}
+}
+
 static int intel_crtc_compute_config(struct intel_atomic_state *state,
 				     struct intel_crtc *crtc)
 {
@@ -2414,7 +2435,7 @@ static int intel_crtc_compute_config(struct intel_atomic_state *state,
 	if (ret)
 		return ret;
 
-	intel_vrr_compute_guardband(crtc_state);
+	intel_crtc_compute_vrr_guardband(state, crtc);
 
 	ret = intel_dpll_crtc_compute_clock(state, crtc);
 	if (ret)
@@ -5105,9 +5126,15 @@ static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_s
 	 * Allow fastboot to fix up vblank delay (handled via LRR
 	 * codepaths), a bit dodgy as the registers aren't
 	 * double buffered but seems to be working more or less...
+	 *
+	 * Also allow this when the VRR timing generator is always on,
+	 * which implies optimized guardband is used. In such cases,
+	 * vblank delay may vary even without inherited state, but it's
+	 * still safe as VRR guardband is still same.
 	 */
-	return HAS_LRR(display) && old_crtc_state->inherited &&
-		!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
+	return HAS_LRR(display) &&
+	       (old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) &&
+	       !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
 }
 
 bool
-- 
2.45.2

[PATCH 14/16] drm/i915/vrr: Introduce helper to compute min static guardband

[Ankit Nautiyal]

In the current VRR implementation, vrr.vmin and vrr.guardband are set such
that they do not need to change when switching from fixed refresh rate to
variable refresh rate. Specifically, vrr.guardband is always set to match
the vblank length. This approach works for most cases, but not for LRR,
where the guardband would need to change while the VRR timing generator is
still active.

With the VRR TG always active, live updates to guardband are unsafe and not
recommended. To ensure hardware safety, guardband was moved out of the
!fastset block, meaning any change now requires a full modeset.
This breaks seamless LRR switching, which was previously supported.

Since the problem arises from guardband being matched to the vblank length,
solution is to use a minimal, sufficient static value, instead. So we use a
static guardband defined during mode-set that fits within the smallest
expected vblank and remains unchanged in case of features like LRR where
vtotal changes. To compute this minimum guardband we take into account
latencies/delays due to different features as mentioned in the Bspec.

Introduce a helper to compute the minimal sufficient guardband.

v2: Use helpers for dsc/scaler prefill latencies. (Mitul)
Account for pkgc latency and take max of pkgc and sagv latencies.

v3: Use new helper for PSR2/Panel Replay latency.

v4: Avoid re-setting the Vmin/Flipline for optimized guardband.

v5:
- Refactor the function to make it as a helper which can be used to
  update crtc_vblank_start and guardband can then be derived from it.
  (Ville)
- Modify the subject and commit message for the same.

v6: Use intel_usecs_to_scanlines() instead of hand rolled stuff. (Ville)

v7: Rename helper to intel_vrr_compute_optimized_guardband.

Bspec: 70151
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com> (#v3)
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 117 +++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h |   2 +
 2 files changed, 119 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 221b25832e56..2dca4be28a9c 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -6,12 +6,18 @@
 
 #include <drm/drm_print.h>
 
+#include "intel_alpm.h"
+#include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
+#include "intel_dp.h"
+#include "intel_vdsc.h"
 #include "intel_vrr.h"
 #include "intel_vrr_regs.h"
+#include "skl_scaler.h"
+#include "skl_watermark.h"
 
 #define FIXED_POINT_PRECISION		100
 #define CMRR_PRECISION_TOLERANCE	10
@@ -433,6 +439,117 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
 		   intel_vrr_max_vblank_guardband(crtc_state));
 }
 
+static
+int scaler_prefill_latency(struct intel_crtc_state *crtc_state, int linetime_us)
+{
+	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
+	u64 hscale_k, vscale_k;
+	int cdclk_adjustment;
+	int num_scaler_users;
+
+	/*
+	 * Assuming:
+	 * Both scaler enabled.
+	 * scaler 1 downscaling factor as 2 x 2 (Horiz x Vert)
+	 * scaler 2 downscaling factor as 2 x 1 (Horiz x Vert)
+	 * Cdclk Adjustment : 1
+	 */
+	num_scaler_users = 2;
+	hscale_k = 2 * 1000;
+	vscale_k = 2 * 1000;
+	cdclk_adjustment = 1;
+
+	return skl_scaler_guardband_latency(num_scaler_users, hscale_k, vscale_k,
+					    chroma_downscaling_factor,
+					    cdclk_adjustment,
+					    linetime_us);
+}
+
+static
+int dsc_prefill_latency(struct intel_crtc_state *crtc_state, int linetime_us)
+{
+#define MAX_SCALERS 2
+	int chroma_downscaling_factor = skl_scaler_chroma_downscale_factor(crtc_state);
+	u64 hscale_k[MAX_SCALERS], vscale_k[MAX_SCALERS];
+	int cdclk_adjustment;
+	int num_scaler_users;
+
+	/*
+	 * Assuming:
+	 * Both scaler enabled.
+	 * scaler 1 downscaling factor as 2 x 2 (Horiz x Vert)
+	 * scaler 2 downscaling factor as 2 x 1 (Horiz x Vert)
+	 * Cdclk Adjustment : 1
+	 */
+	num_scaler_users = MAX_SCALERS;
+	hscale_k[0] = 2 * 1000;
+	vscale_k[0] = 2 * 1000;
+	hscale_k[1] = 2 * 1000;
+	vscale_k[1] = 1 * 1000;
+
+	cdclk_adjustment = 1;
+
+	return intel_dsc_guardband_latency(num_scaler_users, hscale_k, vscale_k,
+					   chroma_downscaling_factor,
+					   cdclk_adjustment,
+					   linetime_us);
+}
+
+int intel_vrr_compute_optimized_guardband(struct intel_crtc_state *crtc_state,
+					  struct intel_connector *connector)
+{
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	struct intel_display *display = to_intel_display(crtc_state);
+	int dsc_prefill_time = 0;
+	int psr2_pr_latency = 0;
+	int scaler_prefill_time;
+	int wm0_prefill_time;
+	int pkgc_max_latency;
+	int sagv_latency;
+	int sdp_latency = 0;
+	int guardband_us;
+	int linetime_us;
+	int guardband;
+	int pm_delay;
+
+	linetime_us = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000,
+				   adjusted_mode->crtc_clock);
+
+	pkgc_max_latency = skl_watermark_max_latency(display, 1);
+	sagv_latency = display->sagv.block_time_us;
+
+	/* Assuming max wm0 lines = 4 */
+	wm0_prefill_time = 4 * linetime_us + 20;
+
+	scaler_prefill_time = scaler_prefill_latency(crtc_state, linetime_us);
+
+	if (crtc_state->dsc.compression_enable)
+		dsc_prefill_time = dsc_prefill_latency(crtc_state, linetime_us);
+
+	pm_delay = crtc_state->framestart_delay +
+		   max(sagv_latency, pkgc_max_latency) +
+		   wm0_prefill_time +
+		   scaler_prefill_time +
+		   dsc_prefill_time;
+
+	switch (connector->base.connector_type) {
+	case DRM_MODE_CONNECTOR_eDP:
+	case DRM_MODE_CONNECTOR_DisplayPort:
+		psr2_pr_latency = intel_alpm_compute_max_link_wake_latency(crtc_state, true);
+		sdp_latency = intel_dp_compute_sdp_latency(crtc_state, true);
+		break;
+	default:
+		break;
+	}
+
+	guardband_us = max(sdp_latency, psr2_pr_latency);
+	guardband_us = max(guardband_us, pm_delay);
+
+	guardband = intel_usecs_to_scanlines(adjusted_mode, guardband_us);
+
+	return guardband;
+}
+
 void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index bc9044621635..8d1f31ae92df 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -42,5 +42,7 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
 bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
 int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);
+int intel_vrr_compute_optimized_guardband(struct intel_crtc_state *crtc_state,
+					  struct intel_connector *connector);
 
 #endif /* __INTEL_VRR_H__ */
-- 
2.45.2

[PATCH 15/16] drm/i915/display: Use optimized guardband for always-on VRR TG

[Ankit Nautiyal]

As we have all bits in place for using the optimized guardband,
enable it only for platforms that always use VRR TG for now.

For remaining platforms continue to use the guardband equal to the
vblank length.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 30 +++++++++++++++-----
 1 file changed, 23 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1964e41b5704..6f61278a36c2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2411,16 +2411,32 @@ static void intel_crtc_compute_vrr_guardband(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
+	struct drm_connector_state *conn_state;
+	struct drm_connector *drm_connector;
+	int i;
 
-	intel_vrr_compute_guardband(crtc_state);
+	for_each_new_connector_in_state(&state->base,
+					drm_connector,
+					conn_state, i) {
+		struct intel_connector *connector;
+		int vblank_length;
 
-	if (intel_vrr_always_use_vrr_tg(display)) {
-		int vblank_length = adjusted_mode->crtc_vtotal -
-				    (crtc_state->set_context_latency +
-				     adjusted_mode->crtc_vdisplay);
+		if (conn_state->crtc != &crtc->base)
+			continue;
 
-		adjusted_mode->crtc_vblank_start +=
-			vblank_length - crtc_state->vrr.guardband;
+		connector = to_intel_connector(drm_connector);
+		if (intel_vrr_always_use_vrr_tg(display)) {
+			intel_vrr_compute_optimized_guardband(crtc_state, connector);
+
+			vblank_length = adjusted_mode->crtc_vtotal -
+					(crtc_state->set_context_latency +
+					 adjusted_mode->crtc_vdisplay);
+
+			adjusted_mode->crtc_vblank_start +=
+				vblank_length - crtc_state->vrr.guardband;
+		} else {
+			intel_vrr_compute_guardband(crtc_state);
+		}
 	}
 }
 
-- 
2.45.2

[PATCH 16/16] drm/i915/vrr: Use optimized guardband when VRR TG is active

[Ankit Nautiyal]

Currently, optimized guardband is only used on platforms where the VRR
timing generator is always enabled. We want to use the optimized/reduced
guardband whenever we are using the VRR timing generator, as the legacy
timing generator doesn't need vrr guardband.

On platforms where the VRR timing generator is always ON, we optimize the
guardband regardless of whether the display is operating in fixed or
variable refresh rate mode.

On platforms where the VRR timing generator is not always ON, we optimize
the guardband only when VRR is enabled.

Add a helper intel_vrr_use_optimized_guardband() to determine if the
optimized/reduced guardband should be used.

The actual computation is now performed internally within
intel_vrr_compute_guardband() which calls
intel_vrr_compute_optimized_guardband() when appropriate.

This completes the transition to optimized guardband usage across all
supported platforms.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  5 +----
 drivers/gpu/drm/i915/display/intel_vrr.c     | 23 +++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_vrr.h     |  5 ++---
 3 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6f61278a36c2..84f830294007 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2425,17 +2425,14 @@ static void intel_crtc_compute_vrr_guardband(struct intel_atomic_state *state,
 			continue;
 
 		connector = to_intel_connector(drm_connector);
+		intel_vrr_compute_guardband(crtc_state, connector);
 		if (intel_vrr_always_use_vrr_tg(display)) {
-			intel_vrr_compute_optimized_guardband(crtc_state, connector);
-
 			vblank_length = adjusted_mode->crtc_vtotal -
 					(crtc_state->set_context_latency +
 					 adjusted_mode->crtc_vdisplay);
 
 			adjusted_mode->crtc_vblank_start +=
 				vblank_length - crtc_state->vrr.guardband;
-		} else {
-			intel_vrr_compute_guardband(crtc_state);
 		}
 	}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 2dca4be28a9c..24f608d4a28f 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -495,8 +495,15 @@ int dsc_prefill_latency(struct intel_crtc_state *crtc_state, int linetime_us)
 					   linetime_us);
 }
 
-int intel_vrr_compute_optimized_guardband(struct intel_crtc_state *crtc_state,
-					  struct intel_connector *connector)
+static bool intel_vrr_use_optimized_guardband(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	return intel_vrr_always_use_vrr_tg(display) || crtc_state->vrr.enable;
+}
+
+static int intel_vrr_compute_optimized_guardband(struct intel_crtc_state *crtc_state,
+						 struct intel_connector *connector)
 {
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -550,16 +557,22 @@ int intel_vrr_compute_optimized_guardband(struct intel_crtc_state *crtc_state,
 	return guardband;
 }
 
-void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
+void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state,
+				 struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	int guardband;
 
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
-	crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
-					intel_vrr_max_guardband(crtc_state));
+	if (intel_vrr_use_optimized_guardband(crtc_state))
+		guardband = intel_vrr_compute_optimized_guardband(crtc_state, connector);
+	else
+		guardband = crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay;
+
+	crtc_state->vrr.guardband = min(guardband, intel_vrr_max_guardband(crtc_state));
 
 	if (DISPLAY_VER(display) < 13)
 		crtc_state->vrr.pipeline_full =
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 8d1f31ae92df..6986e8f122dc 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -21,7 +21,8 @@ bool intel_vrr_possible(const struct intel_crtc_state *crtc_state);
 void intel_vrr_check_modeset(struct intel_atomic_state *state);
 void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			      struct drm_connector_state *conn_state);
-void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state);
+void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state,
+				 struct intel_connector *connector);
 void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 void intel_vrr_enable(const struct intel_crtc_state *crtc_state);
 void intel_vrr_send_push(struct intel_dsb *dsb,
@@ -42,7 +43,5 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state);
 bool intel_vrr_always_use_vrr_tg(struct intel_display *display);
 int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state);
 int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);
-int intel_vrr_compute_optimized_guardband(struct intel_crtc_state *crtc_state,
-					  struct intel_connector *connector);
 
 #endif /* __INTEL_VRR_H__ */
-- 
2.45.2

✓ CI.KUnit: success for Optimize vrr.guardband and fix LRR (rev14)

[Patchwork]

== Series Details ==

Series: Optimize vrr.guardband and fix LRR (rev14)
URL   : https://patchwork.freedesktop.org/series/151244/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[04:53:14] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:53:19] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:53:48] Starting KUnit Kernel (1/1)...
[04:53:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:53:48] ================== guc_buf (11 subtests) ===================
[04:53:48] [PASSED] test_smallest
[04:53:48] [PASSED] test_largest
[04:53:48] [PASSED] test_granular
[04:53:48] [PASSED] test_unique
[04:53:48] [PASSED] test_overlap
[04:53:48] [PASSED] test_reusable
[04:53:48] [PASSED] test_too_big
[04:53:48] [PASSED] test_flush
[04:53:48] [PASSED] test_lookup
[04:53:48] [PASSED] test_data
[04:53:48] [PASSED] test_class
[04:53:48] ===================== [PASSED] guc_buf =====================
[04:53:48] =================== guc_dbm (7 subtests) ===================
[04:53:48] [PASSED] test_empty
[04:53:48] [PASSED] test_default
[04:53:48] ======================== test_size  ========================
[04:53:48] [PASSED] 4
[04:53:48] [PASSED] 8
[04:53:48] [PASSED] 32
[04:53:48] [PASSED] 256
[04:53:48] ==================== [PASSED] test_size ====================
[04:53:48] ======================= test_reuse  ========================
[04:53:48] [PASSED] 4
[04:53:48] [PASSED] 8
[04:53:48] [PASSED] 32
[04:53:48] [PASSED] 256
[04:53:48] =================== [PASSED] test_reuse ====================
[04:53:48] =================== test_range_overlap  ====================
[04:53:48] [PASSED] 4
[04:53:48] [PASSED] 8
[04:53:48] [PASSED] 32
[04:53:48] [PASSED] 256
[04:53:48] =============== [PASSED] test_range_overlap ================
[04:53:48] =================== test_range_compact  ====================
[04:53:48] [PASSED] 4
[04:53:48] [PASSED] 8
[04:53:48] [PASSED] 32
[04:53:48] [PASSED] 256
[04:53:48] =============== [PASSED] test_range_compact ================
[04:53:48] ==================== test_range_spare  =====================
[04:53:48] [PASSED] 4
[04:53:48] [PASSED] 8
[04:53:48] [PASSED] 32
[04:53:48] [PASSED] 256
[04:53:48] ================ [PASSED] test_range_spare =================
[04:53:48] ===================== [PASSED] guc_dbm =====================
[04:53:48] =================== guc_idm (6 subtests) ===================
[04:53:48] [PASSED] bad_init
[04:53:48] [PASSED] no_init
[04:53:48] [PASSED] init_fini
[04:53:48] [PASSED] check_used
[04:53:48] [PASSED] check_quota
[04:53:48] [PASSED] check_all
[04:53:48] ===================== [PASSED] guc_idm =====================
[04:53:48] ================== no_relay (3 subtests) ===================
[04:53:48] [PASSED] xe_drops_guc2pf_if_not_ready
[04:53:48] [PASSED] xe_drops_guc2vf_if_not_ready
[04:53:48] [PASSED] xe_rejects_send_if_not_ready
[04:53:48] ==================== [PASSED] no_relay =====================
[04:53:48] ================== pf_relay (14 subtests) ==================
[04:53:48] [PASSED] pf_rejects_guc2pf_too_short
[04:53:48] [PASSED] pf_rejects_guc2pf_too_long
[04:53:48] [PASSED] pf_rejects_guc2pf_no_payload
[04:53:48] [PASSED] pf_fails_no_payload
[04:53:48] [PASSED] pf_fails_bad_origin
[04:53:48] [PASSED] pf_fails_bad_type
[04:53:48] [PASSED] pf_txn_reports_error
[04:53:48] [PASSED] pf_txn_sends_pf2guc
[04:53:48] [PASSED] pf_sends_pf2guc
[04:53:48] [SKIPPED] pf_loopback_nop
[04:53:48] [SKIPPED] pf_loopback_echo
[04:53:48] [SKIPPED] pf_loopback_fail
[04:53:48] [SKIPPED] pf_loopback_busy
[04:53:48] [SKIPPED] pf_loopback_retry
[04:53:48] ==================== [PASSED] pf_relay =====================
[04:53:48] ================== vf_relay (3 subtests) ===================
[04:53:48] [PASSED] vf_rejects_guc2vf_too_short
[04:53:48] [PASSED] vf_rejects_guc2vf_too_long
[04:53:48] [PASSED] vf_rejects_guc2vf_no_payload
[04:53:48] ==================== [PASSED] vf_relay =====================
[04:53:48] ===================== lmtt (1 subtest) =====================
[04:53:48] ======================== test_ops  =========================
[04:53:48] [PASSED] 2-level
[04:53:48] [PASSED] multi-level
[04:53:48] ==================== [PASSED] test_ops =====================
[04:53:48] ====================== [PASSED] lmtt =======================
[04:53:48] ================= pf_service (11 subtests) =================
[04:53:48] [PASSED] pf_negotiate_any
[04:53:48] [PASSED] pf_negotiate_base_match
[04:53:48] [PASSED] pf_negotiate_base_newer
[04:53:48] [PASSED] pf_negotiate_base_next
[04:53:48] [SKIPPED] pf_negotiate_base_older
[04:53:48] [PASSED] pf_negotiate_base_prev
[04:53:48] [PASSED] pf_negotiate_latest_match
[04:53:48] [PASSED] pf_negotiate_latest_newer
[04:53:48] [PASSED] pf_negotiate_latest_next
[04:53:48] [SKIPPED] pf_negotiate_latest_older
[04:53:48] [SKIPPED] pf_negotiate_latest_prev
[04:53:48] =================== [PASSED] pf_service ====================
[04:53:48] ================= xe_guc_g2g (2 subtests) ==================
[04:53:48] ============== xe_live_guc_g2g_kunit_default  ==============
[04:53:48] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[04:53:48] ============== xe_live_guc_g2g_kunit_allmem  ===============
[04:53:48] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[04:53:48] =================== [SKIPPED] xe_guc_g2g ===================
[04:53:48] =================== xe_mocs (2 subtests) ===================
[04:53:48] ================ xe_live_mocs_kernel_kunit  ================
[04:53:48] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[04:53:48] ================ xe_live_mocs_reset_kunit  =================
[04:53:48] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[04:53:48] ==================== [SKIPPED] xe_mocs =====================
[04:53:48] ================= xe_migrate (2 subtests) ==================
[04:53:48] ================= xe_migrate_sanity_kunit  =================
[04:53:48] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[04:53:48] ================== xe_validate_ccs_kunit  ==================
[04:53:48] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[04:53:48] =================== [SKIPPED] xe_migrate ===================
[04:53:48] ================== xe_dma_buf (1 subtest) ==================
[04:53:48] ==================== xe_dma_buf_kunit  =====================
[04:53:48] ================ [SKIPPED] xe_dma_buf_kunit ================
[04:53:48] =================== [SKIPPED] xe_dma_buf ===================
[04:53:48] ================= xe_bo_shrink (1 subtest) =================
[04:53:48] =================== xe_bo_shrink_kunit  ====================
[04:53:48] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[04:53:48] ================== [SKIPPED] xe_bo_shrink ==================
[04:53:48] ==================== xe_bo (2 subtests) ====================
[04:53:48] ================== xe_ccs_migrate_kunit  ===================
[04:53:48] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[04:53:48] ==================== xe_bo_evict_kunit  ====================
[04:53:48] =============== [SKIPPED] xe_bo_evict_kunit ================
[04:53:48] ===================== [SKIPPED] xe_bo ======================
[04:53:48] ==================== args (11 subtests) ====================
[04:53:48] [PASSED] count_args_test
[04:53:48] [PASSED] call_args_example
[04:53:48] [PASSED] call_args_test
[04:53:48] [PASSED] drop_first_arg_example
[04:53:48] [PASSED] drop_first_arg_test
[04:53:48] [PASSED] first_arg_example
[04:53:48] [PASSED] first_arg_test
[04:53:48] [PASSED] last_arg_example
[04:53:48] [PASSED] last_arg_test
[04:53:48] [PASSED] pick_arg_example
[04:53:48] [PASSED] sep_comma_example
[04:53:48] ====================== [PASSED] args =======================
[04:53:48] =================== xe_pci (3 subtests) ====================
[04:53:48] ==================== check_graphics_ip  ====================
[04:53:48] [PASSED] 12.00 Xe_LP
[04:53:48] [PASSED] 12.10 Xe_LP+
[04:53:48] [PASSED] 12.55 Xe_HPG
[04:53:48] [PASSED] 12.60 Xe_HPC
[04:53:48] [PASSED] 12.70 Xe_LPG
[04:53:48] [PASSED] 12.71 Xe_LPG
[04:53:48] [PASSED] 12.74 Xe_LPG+
[04:53:48] [PASSED] 20.01 Xe2_HPG
[04:53:48] [PASSED] 20.02 Xe2_HPG
[04:53:48] [PASSED] 20.04 Xe2_LPG
[04:53:48] [PASSED] 30.00 Xe3_LPG
[04:53:48] [PASSED] 30.01 Xe3_LPG
[04:53:48] [PASSED] 30.03 Xe3_LPG
[04:53:48] ================ [PASSED] check_graphics_ip ================
[04:53:48] ===================== check_media_ip  ======================
[04:53:48] [PASSED] 12.00 Xe_M
[04:53:48] [PASSED] 12.55 Xe_HPM
[04:53:48] [PASSED] 13.00 Xe_LPM+
[04:53:48] [PASSED] 13.01 Xe2_HPM
[04:53:48] [PASSED] 20.00 Xe2_LPM
[04:53:48] [PASSED] 30.00 Xe3_LPM
[04:53:48] [PASSED] 30.02 Xe3_LPM
[04:53:48] ================= [PASSED] check_media_ip ==================
[04:53:48] ================= check_platform_gt_count  =================
[04:53:48] [PASSED] 0x9A60 (TIGERLAKE)
[04:53:48] [PASSED] 0x9A68 (TIGERLAKE)
[04:53:48] [PASSED] 0x9A70 (TIGERLAKE)
[04:53:48] [PASSED] 0x9A40 (TIGERLAKE)
[04:53:48] [PASSED] 0x9A49 (TIGERLAKE)
[04:53:48] [PASSED] 0x9A59 (TIGERLAKE)
[04:53:48] [PASSED] 0x9A78 (TIGERLAKE)
[04:53:48] [PASSED] 0x9AC0 (TIGERLAKE)
[04:53:48] [PASSED] 0x9AC9 (TIGERLAKE)
[04:53:48] [PASSED] 0x9AD9 (TIGERLAKE)
[04:53:48] [PASSED] 0x9AF8 (TIGERLAKE)
[04:53:48] [PASSED] 0x4C80 (ROCKETLAKE)
[04:53:48] [PASSED] 0x4C8A (ROCKETLAKE)
[04:53:48] [PASSED] 0x4C8B (ROCKETLAKE)
[04:53:48] [PASSED] 0x4C8C (ROCKETLAKE)
[04:53:48] [PASSED] 0x4C90 (ROCKETLAKE)
[04:53:48] [PASSED] 0x4C9A (ROCKETLAKE)
[04:53:48] [PASSED] 0x4680 (ALDERLAKE_S)
[04:53:48] [PASSED] 0x4682 (ALDERLAKE_S)
[04:53:48] [PASSED] 0x4688 (ALDERLAKE_S)
[04:53:48] [PASSED] 0x468A (ALDERLAKE_S)
[04:53:48] [PASSED] 0x468B (ALDERLAKE_S)
[04:53:48] [PASSED] 0x4690 (ALDERLAKE_S)
[04:53:48] [PASSED] 0x4692 (ALDERLAKE_S)
[04:53:48] [PASSED] 0x4693 (ALDERLAKE_S)
[04:53:48] [PASSED] 0x46A0 (ALDERLAKE_P)
[04:53:48] [PASSED] 0x46A1 (ALDERLAKE_P)
[04:53:48] [PASSED] 0x46A2 (ALDERLAKE_P)
[04:53:48] [PASSED] 0x46A3 (ALDERLAKE_P)
[04:53:48] [PASSED] 0x46A6 (ALDERLAKE_P)
[04:53:48] [PASSED] 0x46A8 (ALDERLAKE_P)
[04:53:48] [PASSED] 0x46AA (ALDERLAKE_P)
[04:53:48] [PASSED] 0x462A (ALDERLAKE_P)
[04:53:48] [PASSED] 0x4626 (ALDERLAKE_P)
[04:53:48] [PASSED] 0x4628 (ALDERLAKE_P)
[04:53:48] [PASSED] 0x46B0 (ALDERLAKE_P)
[04:53:48] [PASSED] 0x46B1 (ALDERLAKE_P)
[04:53:48] [PASSED] 0x46B2 (ALDERLAKE_P)
[04:53:48] [PASSED] 0x46B3 (ALDERLAKE_P)
[04:53:48] [PASSED] 0x46C0 (ALDERLAKE_P)
[04:53:48] [PASSED] 0x46C1 (ALDERLAKE_P)
[04:53:48] [PASSED] 0x46C2 (ALDERLAKE_P)
[04:53:48] [PASSED] 0x46C3 (ALDERLAKE_P)
[04:53:48] [PASSED] 0x46D0 (ALDERLAKE_N)
[04:53:48] [PASSED] 0x46D1 (ALDERLAKE_N)
[04:53:48] [PASSED] 0x46D2 (ALDERLAKE_N)
[04:53:48] [PASSED] 0x46D3 (ALDERLAKE_N)
[04:53:48] [PASSED] 0x46D4 (ALDERLAKE_N)
[04:53:48] [PASSED] 0xA721 (ALDERLAKE_P)
[04:53:48] [PASSED] 0xA7A1 (ALDERLAKE_P)
[04:53:48] [PASSED] 0xA7A9 (ALDERLAKE_P)
[04:53:48] [PASSED] 0xA7AC (ALDERLAKE_P)
[04:53:48] [PASSED] 0xA7AD (ALDERLAKE_P)
[04:53:48] [PASSED] 0xA720 (ALDERLAKE_P)
[04:53:48] [PASSED] 0xA7A0 (ALDERLAKE_P)
[04:53:48] [PASSED] 0xA7A8 (ALDERLAKE_P)
[04:53:48] [PASSED] 0xA7AA (ALDERLAKE_P)
[04:53:48] [PASSED] 0xA7AB (ALDERLAKE_P)
[04:53:48] [PASSED] 0xA780 (ALDERLAKE_S)
[04:53:48] [PASSED] 0xA781 (ALDERLAKE_S)
[04:53:48] [PASSED] 0xA782 (ALDERLAKE_S)
[04:53:48] [PASSED] 0xA783 (ALDERLAKE_S)
[04:53:48] [PASSED] 0xA788 (ALDERLAKE_S)
[04:53:48] [PASSED] 0xA789 (ALDERLAKE_S)
[04:53:48] [PASSED] 0xA78A (ALDERLAKE_S)
[04:53:48] [PASSED] 0xA78B (ALDERLAKE_S)
[04:53:48] [PASSED] 0x4905 (DG1)
[04:53:48] [PASSED] 0x4906 (DG1)
[04:53:48] [PASSED] 0x4907 (DG1)
[04:53:48] [PASSED] 0x4908 (DG1)
[04:53:48] [PASSED] 0x4909 (DG1)
[04:53:48] [PASSED] 0x56C0 (DG2)
[04:53:48] [PASSED] 0x56C2 (DG2)
[04:53:48] [PASSED] 0x56C1 (DG2)
[04:53:48] [PASSED] 0x7D51 (METEORLAKE)
[04:53:48] [PASSED] 0x7DD1 (METEORLAKE)
[04:53:48] [PASSED] 0x7D41 (METEORLAKE)
[04:53:48] [PASSED] 0x7D67 (METEORLAKE)
[04:53:48] [PASSED] 0xB640 (METEORLAKE)
[04:53:48] [PASSED] 0x56A0 (DG2)
[04:53:48] [PASSED] 0x56A1 (DG2)
[04:53:48] [PASSED] 0x56A2 (DG2)
[04:53:48] [PASSED] 0x56BE (DG2)
[04:53:48] [PASSED] 0x56BF (DG2)
[04:53:48] [PASSED] 0x5690 (DG2)
[04:53:48] [PASSED] 0x5691 (DG2)
[04:53:48] [PASSED] 0x5692 (DG2)
[04:53:48] [PASSED] 0x56A5 (DG2)
[04:53:48] [PASSED] 0x56A6 (DG2)
[04:53:48] [PASSED] 0x56B0 (DG2)
[04:53:48] [PASSED] 0x56B1 (DG2)
[04:53:48] [PASSED] 0x56BA (DG2)
[04:53:48] [PASSED] 0x56BB (DG2)
[04:53:48] [PASSED] 0x56BC (DG2)
[04:53:48] [PASSED] 0x56BD (DG2)
[04:53:48] [PASSED] 0x5693 (DG2)
[04:53:48] [PASSED] 0x5694 (DG2)
[04:53:48] [PASSED] 0x5695 (DG2)
[04:53:48] [PASSED] 0x56A3 (DG2)
[04:53:48] [PASSED] 0x56A4 (DG2)
[04:53:48] [PASSED] 0x56B2 (DG2)
[04:53:48] [PASSED] 0x56B3 (DG2)
[04:53:48] [PASSED] 0x5696 (DG2)
[04:53:48] [PASSED] 0x5697 (DG2)
[04:53:48] [PASSED] 0xB69 (PVC)
[04:53:48] [PASSED] 0xB6E (PVC)
[04:53:48] [PASSED] 0xBD4 (PVC)
[04:53:48] [PASSED] 0xBD5 (PVC)
[04:53:48] [PASSED] 0xBD6 (PVC)
[04:53:48] [PASSED] 0xBD7 (PVC)
[04:53:48] [PASSED] 0xBD8 (PVC)
[04:53:48] [PASSED] 0xBD9 (PVC)
[04:53:48] [PASSED] 0xBDA (PVC)
[04:53:48] [PASSED] 0xBDB (PVC)
[04:53:48] [PASSED] 0xBE0 (PVC)
[04:53:48] [PASSED] 0xBE1 (PVC)
[04:53:48] [PASSED] 0xBE5 (PVC)
[04:53:48] [PASSED] 0x7D40 (METEORLAKE)
[04:53:48] [PASSED] 0x7D45 (METEORLAKE)
[04:53:48] [PASSED] 0x7D55 (METEORLAKE)
[04:53:48] [PASSED] 0x7D60 (METEORLAKE)
[04:53:48] [PASSED] 0x7DD5 (METEORLAKE)
[04:53:48] [PASSED] 0x6420 (LUNARLAKE)
[04:53:48] [PASSED] 0x64A0 (LUNARLAKE)
[04:53:48] [PASSED] 0x64B0 (LUNARLAKE)
[04:53:48] [PASSED] 0xE202 (BATTLEMAGE)
[04:53:48] [PASSED] 0xE209 (BATTLEMAGE)
[04:53:48] [PASSED] 0xE20B (BATTLEMAGE)
[04:53:48] [PASSED] 0xE20C (BATTLEMAGE)
[04:53:48] [PASSED] 0xE20D (BATTLEMAGE)
[04:53:48] [PASSED] 0xE210 (BATTLEMAGE)
[04:53:48] [PASSED] 0xE211 (BATTLEMAGE)
[04:53:48] [PASSED] 0xE212 (BATTLEMAGE)
[04:53:48] [PASSED] 0xE216 (BATTLEMAGE)
[04:53:48] [PASSED] 0xE220 (BATTLEMAGE)
[04:53:48] [PASSED] 0xE221 (BATTLEMAGE)
[04:53:48] [PASSED] 0xE222 (BATTLEMAGE)
[04:53:48] [PASSED] 0xE223 (BATTLEMAGE)
[04:53:48] [PASSED] 0xB080 (PANTHERLAKE)
[04:53:48] [PASSED] 0xB081 (PANTHERLAKE)
[04:53:48] [PASSED] 0xB082 (PANTHERLAKE)
[04:53:48] [PASSED] 0xB083 (PANTHERLAKE)
[04:53:48] [PASSED] 0xB084 (PANTHERLAKE)
[04:53:48] [PASSED] 0xB085 (PANTHERLAKE)
[04:53:48] [PASSED] 0xB086 (PANTHERLAKE)
[04:53:48] [PASSED] 0xB087 (PANTHERLAKE)
[04:53:48] [PASSED] 0xB08F (PANTHERLAKE)
[04:53:48] [PASSED] 0xB090 (PANTHERLAKE)
[04:53:48] [PASSED] 0xB0A0 (PANTHERLAKE)
[04:53:48] [PASSED] 0xB0B0 (PANTHERLAKE)
[04:53:48] [PASSED] 0xFD80 (PANTHERLAKE)
[04:53:48] [PASSED] 0xFD81 (PANTHERLAKE)
[04:53:48] ============= [PASSED] check_platform_gt_count =============
[04:53:48] ===================== [PASSED] xe_pci ======================
[04:53:48] =================== xe_rtp (2 subtests) ====================
[04:53:48] =============== xe_rtp_process_to_sr_tests  ================
[04:53:48] [PASSED] coalesce-same-reg
[04:53:48] [PASSED] no-match-no-add
[04:53:48] [PASSED] match-or
[04:53:48] [PASSED] match-or-xfail
[04:53:48] [PASSED] no-match-no-add-multiple-rules
[04:53:48] [PASSED] two-regs-two-entries
[04:53:48] [PASSED] clr-one-set-other
[04:53:48] [PASSED] set-field
[04:53:48] [PASSED] conflict-duplicate
[04:53:48] [PASSED] conflict-not-disjoint
[04:53:48] [PASSED] conflict-reg-type
[04:53:48] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[04:53:48] ================== xe_rtp_process_tests  ===================
[04:53:48] [PASSED] active1
[04:53:48] [PASSED] active2
[04:53:48] [PASSED] active-inactive
[04:53:48] [PASSED] inactive-active
[04:53:48] [PASSED] inactive-1st_or_active-inactive
[04:53:48] [PASSED] inactive-2nd_or_active-inactive
[04:53:48] [PASSED] inactive-last_or_active-inactive
[04:53:48] [PASSED] inactive-no_or_active-inactive
[04:53:48] ============== [PASSED] xe_rtp_process_tests ===============
[04:53:48] ===================== [PASSED] xe_rtp ======================
[04:53:48] ==================== xe_wa (1 subtest) =====================
[04:53:48] ======================== xe_wa_gt  =========================
[04:53:48] [PASSED] TIGERLAKE B0
[04:53:48] [PASSED] DG1 A0
[04:53:48] [PASSED] DG1 B0
[04:53:48] [PASSED] ALDERLAKE_S A0
[04:53:48] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[04:53:48] [PASSED] ALDERLAKE_S C0
[04:53:48] [PASSED] ALDERLAKE_S D0
[04:53:48] [PASSED] ALDERLAKE_P A0
[04:53:48] [PASSED] ALDERLAKE_P B0
[04:53:48] [PASSED] ALDERLAKE_P C0
[04:53:48] [PASSED] ALDERLAKE_S RPLS D0
[04:53:48] [PASSED] ALDERLAKE_P RPLU E0
[04:53:48] [PASSED] DG2 G10 C0
[04:53:48] [PASSED] DG2 G11 B1
[04:53:48] [PASSED] DG2 G12 A1
[04:53:48] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:53:48] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[04:53:48] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[04:53:48] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[04:53:48] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[04:53:48] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[04:53:48] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[04:53:48] ==================== [PASSED] xe_wa_gt =====================
[04:53:48] ====================== [PASSED] xe_wa ======================
[04:53:48] ============================================================
[04:53:48] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[04:53:48] Elapsed time: 33.889s total, 4.281s configuring, 29.241s building, 0.326s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[04:53:48] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:53:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:54:14] Starting KUnit Kernel (1/1)...
[04:54:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:54:14] ============ drm_test_pick_cmdline (2 subtests) ============
[04:54:14] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[04:54:14] =============== drm_test_pick_cmdline_named  ===============
[04:54:14] [PASSED] NTSC
[04:54:14] [PASSED] NTSC-J
[04:54:14] [PASSED] PAL
[04:54:14] [PASSED] PAL-M
[04:54:14] =========== [PASSED] drm_test_pick_cmdline_named ===========
[04:54:14] ============== [PASSED] drm_test_pick_cmdline ==============
[04:54:14] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[04:54:14] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[04:54:14] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[04:54:14] =========== drm_validate_clone_mode (2 subtests) ===========
[04:54:14] ============== drm_test_check_in_clone_mode  ===============
[04:54:14] [PASSED] in_clone_mode
[04:54:14] [PASSED] not_in_clone_mode
[04:54:14] ========== [PASSED] drm_test_check_in_clone_mode ===========
[04:54:14] =============== drm_test_check_valid_clones  ===============
[04:54:14] [PASSED] not_in_clone_mode
[04:54:14] [PASSED] valid_clone
[04:54:14] [PASSED] invalid_clone
[04:54:14] =========== [PASSED] drm_test_check_valid_clones ===========
[04:54:14] ============= [PASSED] drm_validate_clone_mode =============
[04:54:14] ============= drm_validate_modeset (1 subtest) =============
[04:54:14] [PASSED] drm_test_check_connector_changed_modeset
[04:54:14] ============== [PASSED] drm_validate_modeset ===============
[04:54:14] ====== drm_test_bridge_get_current_state (2 subtests) ======
[04:54:14] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[04:54:14] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[04:54:14] ======== [PASSED] drm_test_bridge_get_current_state ========
[04:54:14] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[04:54:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[04:54:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[04:54:14] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[04:54:14] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[04:54:14] ============== drm_bridge_alloc (2 subtests) ===============
[04:54:14] [PASSED] drm_test_drm_bridge_alloc_basic
[04:54:14] [PASSED] drm_test_drm_bridge_alloc_get_put
[04:54:14] ================ [PASSED] drm_bridge_alloc =================
[04:54:14] ================== drm_buddy (7 subtests) ==================
[04:54:14] [PASSED] drm_test_buddy_alloc_limit
[04:54:14] [PASSED] drm_test_buddy_alloc_optimistic
[04:54:14] [PASSED] drm_test_buddy_alloc_pessimistic
[04:54:14] [PASSED] drm_test_buddy_alloc_pathological
[04:54:14] [PASSED] drm_test_buddy_alloc_contiguous
[04:54:14] [PASSED] drm_test_buddy_alloc_clear
[04:54:14] [PASSED] drm_test_buddy_alloc_range_bias
[04:54:14] ==================== [PASSED] drm_buddy ====================
[04:54:14] ============= drm_cmdline_parser (40 subtests) =============
[04:54:14] [PASSED] drm_test_cmdline_force_d_only
[04:54:14] [PASSED] drm_test_cmdline_force_D_only_dvi
[04:54:14] [PASSED] drm_test_cmdline_force_D_only_hdmi
[04:54:14] [PASSED] drm_test_cmdline_force_D_only_not_digital
[04:54:14] [PASSED] drm_test_cmdline_force_e_only
[04:54:14] [PASSED] drm_test_cmdline_res
[04:54:14] [PASSED] drm_test_cmdline_res_vesa
[04:54:14] [PASSED] drm_test_cmdline_res_vesa_rblank
[04:54:14] [PASSED] drm_test_cmdline_res_rblank
[04:54:14] [PASSED] drm_test_cmdline_res_bpp
[04:54:14] [PASSED] drm_test_cmdline_res_refresh
[04:54:14] [PASSED] drm_test_cmdline_res_bpp_refresh
[04:54:14] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[04:54:14] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[04:54:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[04:54:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[04:54:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[04:54:14] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[04:54:14] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[04:54:14] [PASSED] drm_test_cmdline_res_margins_force_on
[04:54:14] [PASSED] drm_test_cmdline_res_vesa_margins
[04:54:14] [PASSED] drm_test_cmdline_name
[04:54:14] [PASSED] drm_test_cmdline_name_bpp
[04:54:14] [PASSED] drm_test_cmdline_name_option
[04:54:14] [PASSED] drm_test_cmdline_name_bpp_option
[04:54:14] [PASSED] drm_test_cmdline_rotate_0
[04:54:14] [PASSED] drm_test_cmdline_rotate_90
[04:54:14] [PASSED] drm_test_cmdline_rotate_180
[04:54:14] [PASSED] drm_test_cmdline_rotate_270
[04:54:14] [PASSED] drm_test_cmdline_hmirror
[04:54:14] [PASSED] drm_test_cmdline_vmirror
[04:54:14] [PASSED] drm_test_cmdline_margin_options
[04:54:14] [PASSED] drm_test_cmdline_multiple_options
[04:54:14] [PASSED] drm_test_cmdline_bpp_extra_and_option
[04:54:14] [PASSED] drm_test_cmdline_extra_and_option
[04:54:14] [PASSED] drm_test_cmdline_freestanding_options
[04:54:14] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[04:54:14] [PASSED] drm_test_cmdline_panel_orientation
[04:54:14] ================ drm_test_cmdline_invalid  =================
[04:54:14] [PASSED] margin_only
[04:54:14] [PASSED] interlace_only
[04:54:14] [PASSED] res_missing_x
[04:54:14] [PASSED] res_missing_y
[04:54:14] [PASSED] res_bad_y
[04:54:14] [PASSED] res_missing_y_bpp
[04:54:14] [PASSED] res_bad_bpp
[04:54:14] [PASSED] res_bad_refresh
[04:54:14] [PASSED] res_bpp_refresh_force_on_off
[04:54:14] [PASSED] res_invalid_mode
[04:54:14] [PASSED] res_bpp_wrong_place_mode
[04:54:14] [PASSED] name_bpp_refresh
[04:54:14] [PASSED] name_refresh
[04:54:14] [PASSED] name_refresh_wrong_mode
[04:54:14] [PASSED] name_refresh_invalid_mode
[04:54:14] [PASSED] rotate_multiple
[04:54:14] [PASSED] rotate_invalid_val
[04:54:14] [PASSED] rotate_truncated
[04:54:14] [PASSED] invalid_option
[04:54:14] [PASSED] invalid_tv_option
[04:54:14] [PASSED] truncated_tv_option
[04:54:14] ============ [PASSED] drm_test_cmdline_invalid =============
[04:54:14] =============== drm_test_cmdline_tv_options  ===============
[04:54:14] [PASSED] NTSC
[04:54:14] [PASSED] NTSC_443
[04:54:14] [PASSED] NTSC_J
[04:54:14] [PASSED] PAL
[04:54:14] [PASSED] PAL_M
[04:54:14] [PASSED] PAL_N
[04:54:14] [PASSED] SECAM
[04:54:14] [PASSED] MONO_525
[04:54:14] [PASSED] MONO_625
[04:54:14] =========== [PASSED] drm_test_cmdline_tv_options ===========
[04:54:14] =============== [PASSED] drm_cmdline_parser ================
[04:54:14] ========== drmm_connector_hdmi_init (20 subtests) ==========
[04:54:14] [PASSED] drm_test_connector_hdmi_init_valid
[04:54:14] [PASSED] drm_test_connector_hdmi_init_bpc_8
[04:54:14] [PASSED] drm_test_connector_hdmi_init_bpc_10
[04:54:14] [PASSED] drm_test_connector_hdmi_init_bpc_12
[04:54:14] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[04:54:14] [PASSED] drm_test_connector_hdmi_init_bpc_null
[04:54:14] [PASSED] drm_test_connector_hdmi_init_formats_empty
[04:54:14] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[04:54:14] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[04:54:14] [PASSED] supported_formats=0x9 yuv420_allowed=1
[04:54:14] [PASSED] supported_formats=0x9 yuv420_allowed=0
[04:54:14] [PASSED] supported_formats=0x3 yuv420_allowed=1
[04:54:14] [PASSED] supported_formats=0x3 yuv420_allowed=0
[04:54:14] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[04:54:14] [PASSED] drm_test_connector_hdmi_init_null_ddc
[04:54:14] [PASSED] drm_test_connector_hdmi_init_null_product
[04:54:14] [PASSED] drm_test_connector_hdmi_init_null_vendor
[04:54:14] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[04:54:14] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[04:54:14] [PASSED] drm_test_connector_hdmi_init_product_valid
[04:54:14] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[04:54:14] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[04:54:14] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[04:54:14] ========= drm_test_connector_hdmi_init_type_valid  =========
[04:54:14] [PASSED] HDMI-A
[04:54:14] [PASSED] HDMI-B
[04:54:14] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[04:54:14] ======== drm_test_connector_hdmi_init_type_invalid  ========
[04:54:14] [PASSED] Unknown
[04:54:14] [PASSED] VGA
[04:54:14] [PASSED] DVI-I
[04:54:14] [PASSED] DVI-D
[04:54:14] [PASSED] DVI-A
[04:54:14] [PASSED] Composite
[04:54:14] [PASSED] SVIDEO
[04:54:14] [PASSED] LVDS
[04:54:14] [PASSED] Component
[04:54:14] [PASSED] DIN
[04:54:14] [PASSED] DP
[04:54:14] [PASSED] TV
[04:54:14] [PASSED] eDP
[04:54:14] [PASSED] Virtual
[04:54:14] [PASSED] DSI
[04:54:14] [PASSED] DPI
[04:54:14] [PASSED] Writeback
[04:54:14] [PASSED] SPI
[04:54:14] [PASSED] USB
[04:54:14] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[04:54:14] ============ [PASSED] drmm_connector_hdmi_init =============
[04:54:14] ============= drmm_connector_init (3 subtests) =============
[04:54:14] [PASSED] drm_test_drmm_connector_init
[04:54:14] [PASSED] drm_test_drmm_connector_init_null_ddc
[04:54:14] ========= drm_test_drmm_connector_init_type_valid  =========
[04:54:14] [PASSED] Unknown
[04:54:14] [PASSED] VGA
[04:54:14] [PASSED] DVI-I
[04:54:14] [PASSED] DVI-D
[04:54:14] [PASSED] DVI-A
[04:54:14] [PASSED] Composite
[04:54:14] [PASSED] SVIDEO
[04:54:14] [PASSED] LVDS
[04:54:14] [PASSED] Component
[04:54:14] [PASSED] DIN
[04:54:14] [PASSED] DP
[04:54:14] [PASSED] HDMI-A
[04:54:14] [PASSED] HDMI-B
[04:54:14] [PASSED] TV
[04:54:14] [PASSED] eDP
[04:54:14] [PASSED] Virtual
[04:54:14] [PASSED] DSI
[04:54:14] [PASSED] DPI
[04:54:14] [PASSED] Writeback
[04:54:14] [PASSED] SPI
[04:54:14] [PASSED] USB
[04:54:14] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[04:54:14] =============== [PASSED] drmm_connector_init ===============
[04:54:14] ========= drm_connector_dynamic_init (6 subtests) ==========
[04:54:14] [PASSED] drm_test_drm_connector_dynamic_init
[04:54:14] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[04:54:14] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[04:54:14] [PASSED] drm_test_drm_connector_dynamic_init_properties
[04:54:14] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[04:54:14] [PASSED] Unknown
[04:54:14] [PASSED] VGA
[04:54:14] [PASSED] DVI-I
[04:54:14] [PASSED] DVI-D
[04:54:14] [PASSED] DVI-A
[04:54:14] [PASSED] Composite
[04:54:14] [PASSED] SVIDEO
[04:54:14] [PASSED] LVDS
[04:54:14] [PASSED] Component
[04:54:14] [PASSED] DIN
[04:54:14] [PASSED] DP
[04:54:14] [PASSED] HDMI-A
[04:54:14] [PASSED] HDMI-B
[04:54:14] [PASSED] TV
[04:54:14] [PASSED] eDP
[04:54:14] [PASSED] Virtual
[04:54:14] [PASSED] DSI
[04:54:14] [PASSED] DPI
[04:54:14] [PASSED] Writeback
[04:54:14] [PASSED] SPI
[04:54:14] [PASSED] USB
[04:54:14] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[04:54:14] ======== drm_test_drm_connector_dynamic_init_name  =========
[04:54:14] [PASSED] Unknown
[04:54:14] [PASSED] VGA
[04:54:14] [PASSED] DVI-I
[04:54:14] [PASSED] DVI-D
[04:54:14] [PASSED] DVI-A
[04:54:14] [PASSED] Composite
[04:54:14] [PASSED] SVIDEO
[04:54:14] [PASSED] LVDS
[04:54:14] [PASSED] Component
[04:54:14] [PASSED] DIN
[04:54:14] [PASSED] DP
[04:54:14] [PASSED] HDMI-A
[04:54:14] [PASSED] HDMI-B
[04:54:14] [PASSED] TV
[04:54:14] [PASSED] eDP
[04:54:14] [PASSED] Virtual
[04:54:14] [PASSED] DSI
[04:54:14] [PASSED] DPI
[04:54:14] [PASSED] Writeback
[04:54:14] [PASSED] SPI
[04:54:14] [PASSED] USB
[04:54:14] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[04:54:14] =========== [PASSED] drm_connector_dynamic_init ============
[04:54:14] ==== drm_connector_dynamic_register_early (4 subtests) =====
[04:54:14] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[04:54:14] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[04:54:14] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[04:54:14] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[04:54:14] ====== [PASSED] drm_connector_dynamic_register_early =======
[04:54:14] ======= drm_connector_dynamic_register (7 subtests) ========
[04:54:14] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[04:54:14] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[04:54:14] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[04:54:14] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[04:54:14] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[04:54:14] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[04:54:14] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[04:54:14] ========= [PASSED] drm_connector_dynamic_register ==========
[04:54:14] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[04:54:14] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[04:54:14] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[04:54:14] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[04:54:14] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[04:54:14] ========== drm_test_get_tv_mode_from_name_valid  ===========
[04:54:14] [PASSED] NTSC
[04:54:14] [PASSED] NTSC-443
[04:54:14] [PASSED] NTSC-J
[04:54:14] [PASSED] PAL
[04:54:14] [PASSED] PAL-M
[04:54:14] [PASSED] PAL-N
[04:54:14] [PASSED] SECAM
[04:54:14] [PASSED] Mono
[04:54:14] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[04:54:14] [PASSED] drm_test_get_tv_mode_from_name_truncated
[04:54:14] ============ [PASSED] drm_get_tv_mode_from_name ============
[04:54:14] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[04:54:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[04:54:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[04:54:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[04:54:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[04:54:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[04:54:14] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[04:54:14] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[04:54:14] [PASSED] VIC 96
[04:54:14] [PASSED] VIC 97
[04:54:14] [PASSED] VIC 101
[04:54:14] [PASSED] VIC 102
[04:54:14] [PASSED] VIC 106
[04:54:14] [PASSED] VIC 107
[04:54:14] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[04:54:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[04:54:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[04:54:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[04:54:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[04:54:14] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[04:54:14] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[04:54:14] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[04:54:14] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[04:54:14] [PASSED] Automatic
[04:54:14] [PASSED] Full
[04:54:14] [PASSED] Limited 16:235
[04:54:14] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[04:54:14] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[04:54:14] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[04:54:14] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[04:54:14] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[04:54:14] [PASSED] RGB
[04:54:14] [PASSED] YUV 4:2:0
[04:54:14] [PASSED] YUV 4:2:2
[04:54:14] [PASSED] YUV 4:4:4
[04:54:14] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[04:54:14] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[04:54:14] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[04:54:14] ============= drm_damage_helper (21 subtests) ==============
[04:54:14] [PASSED] drm_test_damage_iter_no_damage
[04:54:14] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[04:54:14] [PASSED] drm_test_damage_iter_no_damage_src_moved
[04:54:14] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[04:54:14] [PASSED] drm_test_damage_iter_no_damage_not_visible
[04:54:14] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[04:54:14] [PASSED] drm_test_damage_iter_no_damage_no_fb
[04:54:14] [PASSED] drm_test_damage_iter_simple_damage
[04:54:14] [PASSED] drm_test_damage_iter_single_damage
[04:54:14] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[04:54:14] [PASSED] drm_test_damage_iter_single_damage_outside_src
[04:54:14] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[04:54:14] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[04:54:14] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[04:54:14] [PASSED] drm_test_damage_iter_single_damage_src_moved
[04:54:14] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[04:54:14] [PASSED] drm_test_damage_iter_damage
[04:54:14] [PASSED] drm_test_damage_iter_damage_one_intersect
[04:54:14] [PASSED] drm_test_damage_iter_damage_one_outside
[04:54:14] [PASSED] drm_test_damage_iter_damage_src_moved
[04:54:14] [PASSED] drm_test_damage_iter_damage_not_visible
[04:54:14] ================ [PASSED] drm_damage_helper ================
[04:54:14] ============== drm_dp_mst_helper (3 subtests) ==============
[04:54:14] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[04:54:14] [PASSED] Clock 154000 BPP 30 DSC disabled
[04:54:14] [PASSED] Clock 234000 BPP 30 DSC disabled
[04:54:14] [PASSED] Clock 297000 BPP 24 DSC disabled
[04:54:14] [PASSED] Clock 332880 BPP 24 DSC enabled
[04:54:14] [PASSED] Clock 324540 BPP 24 DSC enabled
[04:54:14] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[04:54:14] ============== drm_test_dp_mst_calc_pbn_div  ===============
[04:54:14] [PASSED] Link rate 2000000 lane count 4
[04:54:14] [PASSED] Link rate 2000000 lane count 2
[04:54:14] [PASSED] Link rate 2000000 lane count 1
[04:54:14] [PASSED] Link rate 1350000 lane count 4
[04:54:14] [PASSED] Link rate 1350000 lane count 2
[04:54:14] [PASSED] Link rate 1350000 lane count 1
[04:54:14] [PASSED] Link rate 1000000 lane count 4
[04:54:14] [PASSED] Link rate 1000000 lane count 2
[04:54:14] [PASSED] Link rate 1000000 lane count 1
[04:54:14] [PASSED] Link rate 810000 lane count 4
[04:54:14] [PASSED] Link rate 810000 lane count 2
[04:54:14] [PASSED] Link rate 810000 lane count 1
[04:54:14] [PASSED] Link rate 540000 lane count 4
[04:54:14] [PASSED] Link rate 540000 lane count 2
[04:54:14] [PASSED] Link rate 540000 lane count 1
[04:54:14] [PASSED] Link rate 270000 lane count 4
[04:54:14] [PASSED] Link rate 270000 lane count 2
[04:54:14] [PASSED] Link rate 270000 lane count 1
[04:54:14] [PASSED] Link rate 162000 lane count 4
[04:54:14] [PASSED] Link rate 162000 lane count 2
[04:54:14] [PASSED] Link rate 162000 lane count 1
[04:54:14] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[04:54:14] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[04:54:14] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[04:54:14] [PASSED] DP_POWER_UP_PHY with port number
[04:54:14] [PASSED] DP_POWER_DOWN_PHY with port number
[04:54:14] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[04:54:14] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[04:54:14] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[04:54:14] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[04:54:14] [PASSED] DP_QUERY_PAYLOAD with port number
[04:54:14] [PASSED] DP_QUERY_PAYLOAD with VCPI
[04:54:14] [PASSED] DP_REMOTE_DPCD_READ with port number
[04:54:14] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[04:54:14] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[04:54:14] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[04:54:14] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[04:54:14] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[04:54:14] [PASSED] DP_REMOTE_I2C_READ with port number
[04:54:14] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[04:54:14] [PASSED] DP_REMOTE_I2C_READ with transactions array
[04:54:14] [PASSED] DP_REMOTE_I2C_WRITE with port number
[04:54:14] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[04:54:14] [PASSED] DP_REMOTE_I2C_WRITE with data array
[04:54:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[04:54:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[04:54:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[04:54:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[04:54:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[04:54:14] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[04:54:14] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[04:54:14] ================ [PASSED] drm_dp_mst_helper ================
[04:54:14] ================== drm_exec (7 subtests) ===================
[04:54:14] [PASSED] sanitycheck
[04:54:14] [PASSED] test_lock
[04:54:14] [PASSED] test_lock_unlock
[04:54:14] [PASSED] test_duplicates
[04:54:14] [PASSED] test_prepare
[04:54:14] [PASSED] test_prepare_array
[04:54:14] [PASSED] test_multiple_loops
[04:54:14] ==================== [PASSED] drm_exec =====================
[04:54:14] =========== drm_format_helper_test (17 subtests) ===========
[04:54:14] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[04:54:14] [PASSED] single_pixel_source_buffer
[04:54:14] [PASSED] single_pixel_clip_rectangle
[04:54:14] [PASSED] well_known_colors
[04:54:14] [PASSED] destination_pitch
[04:54:14] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[04:54:14] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[04:54:14] [PASSED] single_pixel_source_buffer
[04:54:14] [PASSED] single_pixel_clip_rectangle
[04:54:14] [PASSED] well_known_colors
[04:54:14] [PASSED] destination_pitch
[04:54:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[04:54:14] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[04:54:14] [PASSED] single_pixel_source_buffer
[04:54:14] [PASSED] single_pixel_clip_rectangle
[04:54:14] [PASSED] well_known_colors
[04:54:14] [PASSED] destination_pitch
[04:54:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[04:54:14] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[04:54:14] [PASSED] single_pixel_source_buffer
[04:54:14] [PASSED] single_pixel_clip_rectangle
[04:54:14] [PASSED] well_known_colors
[04:54:14] [PASSED] destination_pitch
[04:54:14] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[04:54:14] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[04:54:14] [PASSED] single_pixel_source_buffer
[04:54:14] [PASSED] single_pixel_clip_rectangle
[04:54:14] [PASSED] well_known_colors
[04:54:14] [PASSED] destination_pitch
[04:54:14] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[04:54:14] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[04:54:14] [PASSED] single_pixel_source_buffer
[04:54:14] [PASSED] single_pixel_clip_rectangle
[04:54:14] [PASSED] well_known_colors
[04:54:14] [PASSED] destination_pitch
[04:54:14] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[04:54:14] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[04:54:14] [PASSED] single_pixel_source_buffer
[04:54:14] [PASSED] single_pixel_clip_rectangle
[04:54:14] [PASSED] well_known_colors
[04:54:14] [PASSED] destination_pitch
[04:54:14] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[04:54:14] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[04:54:14] [PASSED] single_pixel_source_buffer
[04:54:14] [PASSED] single_pixel_clip_rectangle
[04:54:14] [PASSED] well_known_colors
[04:54:14] [PASSED] destination_pitch
[04:54:14] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[04:54:14] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[04:54:14] [PASSED] single_pixel_source_buffer
[04:54:14] [PASSED] single_pixel_clip_rectangle
[04:54:14] [PASSED] well_known_colors
[04:54:14] [PASSED] destination_pitch
[04:54:14] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[04:54:14] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[04:54:14] [PASSED] single_pixel_source_buffer
[04:54:14] [PASSED] single_pixel_clip_rectangle
[04:54:14] [PASSED] well_known_colors
[04:54:14] [PASSED] destination_pitch
[04:54:14] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[04:54:14] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[04:54:14] [PASSED] single_pixel_source_buffer
[04:54:14] [PASSED] single_pixel_clip_rectangle
[04:54:14] [PASSED] well_known_colors
[04:54:14] [PASSED] destination_pitch
[04:54:14] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[04:54:14] ============== drm_test_fb_xrgb8888_to_mono  ===============
[04:54:14] [PASSED] single_pixel_source_buffer
[04:54:14] [PASSED] single_pixel_clip_rectangle
[04:54:14] [PASSED] well_known_colors
[04:54:14] [PASSED] destination_pitch
[04:54:14] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[04:54:14] ==================== drm_test_fb_swab  =====================
[04:54:14] [PASSED] single_pixel_source_buffer
[04:54:14] [PASSED] single_pixel_clip_rectangle
[04:54:14] [PASSED] well_known_colors
[04:54:14] [PASSED] destination_pitch
[04:54:14] ================ [PASSED] drm_test_fb_swab =================
[04:54:14] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[04:54:14] [PASSED] single_pixel_source_buffer
[04:54:14] [PASSED] single_pixel_clip_rectangle
[04:54:14] [PASSED] well_known_colors
[04:54:14] [PASSED] destination_pitch
[04:54:14] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[04:54:14] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[04:54:14] [PASSED] single_pixel_source_buffer
[04:54:14] [PASSED] single_pixel_clip_rectangle
[04:54:14] [PASSED] well_known_colors
[04:54:14] [PASSED] destination_pitch
[04:54:14] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[04:54:14] ================= drm_test_fb_clip_offset  =================
[04:54:14] [PASSED] pass through
[04:54:14] [PASSED] horizontal offset
[04:54:14] [PASSED] vertical offset
[04:54:14] [PASSED] horizontal and vertical offset
[04:54:14] [PASSED] horizontal offset (custom pitch)
[04:54:14] [PASSED] vertical offset (custom pitch)
[04:54:14] [PASSED] horizontal and vertical offset (custom pitch)
[04:54:14] ============= [PASSED] drm_test_fb_clip_offset =============
[04:54:14] =================== drm_test_fb_memcpy  ====================
[04:54:14] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[04:54:14] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[04:54:14] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[04:54:14] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[04:54:14] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[04:54:14] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[04:54:14] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[04:54:14] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[04:54:14] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[04:54:14] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[04:54:14] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[04:54:14] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[04:54:14] =============== [PASSED] drm_test_fb_memcpy ================
[04:54:14] ============= [PASSED] drm_format_helper_test ==============
[04:54:14] ================= drm_format (18 subtests) =================
[04:54:14] [PASSED] drm_test_format_block_width_invalid
[04:54:14] [PASSED] drm_test_format_block_width_one_plane
[04:54:14] [PASSED] drm_test_format_block_width_two_plane
[04:54:14] [PASSED] drm_test_format_block_width_three_plane
[04:54:14] [PASSED] drm_test_format_block_width_tiled
[04:54:14] [PASSED] drm_test_format_block_height_invalid
[04:54:14] [PASSED] drm_test_format_block_height_one_plane
[04:54:14] [PASSED] drm_test_format_block_height_two_plane
[04:54:14] [PASSED] drm_test_format_block_height_three_plane
[04:54:14] [PASSED] drm_test_format_block_height_tiled
[04:54:14] [PASSED] drm_test_format_min_pitch_invalid
[04:54:14] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[04:54:14] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[04:54:14] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[04:54:14] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[04:54:14] [PASSED] drm_test_format_min_pitch_two_plane
[04:54:14] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[04:54:14] [PASSED] drm_test_format_min_pitch_tiled
[04:54:14] =================== [PASSED] drm_format ====================
[04:54:14] ============== drm_framebuffer (10 subtests) ===============
[04:54:14] ========== drm_test_framebuffer_check_src_coords  ==========
[04:54:14] [PASSED] Success: source fits into fb
[04:54:14] [PASSED] Fail: overflowing fb with x-axis coordinate
[04:54:14] [PASSED] Fail: overflowing fb with y-axis coordinate
[04:54:14] [PASSED] Fail: overflowing fb with source width
[04:54:14] [PASSED] Fail: overflowing fb with source height
[04:54:14] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[04:54:14] [PASSED] drm_test_framebuffer_cleanup
[04:54:14] =============== drm_test_framebuffer_create  ===============
[04:54:14] [PASSED] ABGR8888 normal sizes
[04:54:14] [PASSED] ABGR8888 max sizes
[04:54:14] [PASSED] ABGR8888 pitch greater than min required
[04:54:14] [PASSED] ABGR8888 pitch less than min required
[04:54:14] [PASSED] ABGR8888 Invalid width
[04:54:14] [PASSED] ABGR8888 Invalid buffer handle
[04:54:14] [PASSED] No pixel format
[04:54:14] [PASSED] ABGR8888 Width 0
[04:54:14] [PASSED] ABGR8888 Height 0
[04:54:14] [PASSED] ABGR8888 Out of bound height * pitch combination
[04:54:14] [PASSED] ABGR8888 Large buffer offset
[04:54:14] [PASSED] ABGR8888 Buffer offset for inexistent plane
[04:54:14] [PASSED] ABGR8888 Invalid flag
[04:54:14] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[04:54:14] [PASSED] ABGR8888 Valid buffer modifier
[04:54:14] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[04:54:14] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[04:54:14] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[04:54:14] [PASSED] NV12 Normal sizes
[04:54:14] [PASSED] NV12 Max sizes
[04:54:14] [PASSED] NV12 Invalid pitch
[04:54:14] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[04:54:14] [PASSED] NV12 different  modifier per-plane
[04:54:14] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[04:54:14] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[04:54:14] [PASSED] NV12 Modifier for inexistent plane
[04:54:14] [PASSED] NV12 Handle for inexistent plane
[04:54:14] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[04:54:14] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[04:54:14] [PASSED] YVU420 Normal sizes
[04:54:14] [PASSED] YVU420 Max sizes
[04:54:14] [PASSED] YVU420 Invalid pitch
[04:54:14] [PASSED] YVU420 Different pitches
[04:54:14] [PASSED] YVU420 Different buffer offsets/pitches
[04:54:14] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[04:54:14] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[04:54:14] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[04:54:14] [PASSED] YVU420 Valid modifier
[04:54:14] [PASSED] YVU420 Different modifiers per plane
[04:54:14] [PASSED] YVU420 Modifier for inexistent plane
[04:54:14] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[04:54:14] [PASSED] X0L2 Normal sizes
[04:54:14] [PASSED] X0L2 Max sizes
[04:54:14] [PASSED] X0L2 Invalid pitch
[04:54:14] [PASSED] X0L2 Pitch greater than minimum required
[04:54:14] [PASSED] X0L2 Handle for inexistent plane
[04:54:14] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[04:54:14] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[04:54:14] [PASSED] X0L2 Valid modifier
[04:54:14] [PASSED] X0L2 Modifier for inexistent plane
[04:54:14] =========== [PASSED] drm_test_framebuffer_create ===========
[04:54:14] [PASSED] drm_test_framebuffer_free
[04:54:14] [PASSED] drm_test_framebuffer_init
[04:54:14] [PASSED] drm_test_framebuffer_init_bad_format
[04:54:14] [PASSED] drm_test_framebuffer_init_dev_mismatch
[04:54:14] [PASSED] drm_test_framebuffer_lookup
[04:54:14] [PASSED] drm_test_framebuffer_lookup_inexistent
[04:54:14] [PASSED] drm_test_framebuffer_modifiers_not_supported
[04:54:14] ================= [PASSED] drm_framebuffer =================
[04:54:14] ================ drm_gem_shmem (8 subtests) ================
[04:54:14] [PASSED] drm_gem_shmem_test_obj_create
[04:54:14] [PASSED] drm_gem_shmem_test_obj_create_private
[04:54:14] [PASSED] drm_gem_shmem_test_pin_pages
[04:54:14] [PASSED] drm_gem_shmem_test_vmap
[04:54:14] [PASSED] drm_gem_shmem_test_get_pages_sgt
[04:54:14] [PASSED] drm_gem_shmem_test_get_sg_table
[04:54:14] [PASSED] drm_gem_shmem_test_madvise
[04:54:14] [PASSED] drm_gem_shmem_test_purge
[04:54:14] ================== [PASSED] drm_gem_shmem ==================
[04:54:14] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[04:54:14] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[04:54:14] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[04:54:14] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[04:54:14] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[04:54:14] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[04:54:14] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[04:54:14] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[04:54:14] [PASSED] Automatic
[04:54:14] [PASSED] Full
[04:54:14] [PASSED] Limited 16:235
[04:54:14] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[04:54:14] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[04:54:14] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[04:54:14] [PASSED] drm_test_check_disable_connector
[04:54:14] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[04:54:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[04:54:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[04:54:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[04:54:14] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[04:54:14] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[04:54:14] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[04:54:14] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[04:54:14] [PASSED] drm_test_check_output_bpc_dvi
[04:54:14] [PASSED] drm_test_check_output_bpc_format_vic_1
[04:54:14] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[04:54:14] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[04:54:14] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[04:54:14] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[04:54:14] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[04:54:14] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[04:54:14] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[04:54:14] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[04:54:14] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[04:54:14] [PASSED] drm_test_check_broadcast_rgb_value
[04:54:14] [PASSED] drm_test_check_bpc_8_value
[04:54:14] [PASSED] drm_test_check_bpc_10_value
[04:54:14] [PASSED] drm_test_check_bpc_12_value
[04:54:14] [PASSED] drm_test_check_format_value
[04:54:14] [PASSED] drm_test_check_tmds_char_value
[04:54:14] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[04:54:14] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[04:54:14] [PASSED] drm_test_check_mode_valid
[04:54:14] [PASSED] drm_test_check_mode_valid_reject
[04:54:14] [PASSED] drm_test_check_mode_valid_reject_rate
[04:54:14] [PASSED] drm_test_check_mode_valid_reject_max_clock
[04:54:14] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[04:54:14] ================= drm_managed (2 subtests) =================
[04:54:14] [PASSED] drm_test_managed_release_action
[04:54:14] [PASSED] drm_test_managed_run_action
[04:54:14] =================== [PASSED] drm_managed ===================
[04:54:14] =================== drm_mm (6 subtests) ====================
[04:54:14] [PASSED] drm_test_mm_init
[04:54:14] [PASSED] drm_test_mm_debug
[04:54:14] [PASSED] drm_test_mm_align32
[04:54:14] [PASSED] drm_test_mm_align64
[04:54:14] [PASSED] drm_test_mm_lowest
[04:54:14] [PASSED] drm_test_mm_highest
[04:54:14] ===================== [PASSED] drm_mm ======================
[04:54:14] ============= drm_modes_analog_tv (5 subtests) =============
[04:54:14] [PASSED] drm_test_modes_analog_tv_mono_576i
[04:54:14] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[04:54:14] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[04:54:14] [PASSED] drm_test_modes_analog_tv_pal_576i
[04:54:14] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[04:54:14] =============== [PASSED] drm_modes_analog_tv ===============
[04:54:14] ============== drm_plane_helper (2 subtests) ===============
[04:54:14] =============== drm_test_check_plane_state  ================
[04:54:14] [PASSED] clipping_simple
[04:54:14] [PASSED] clipping_rotate_reflect
[04:54:14] [PASSED] positioning_simple
[04:54:14] [PASSED] upscaling
[04:54:14] [PASSED] downscaling
[04:54:14] [PASSED] rounding1
[04:54:14] [PASSED] rounding2
[04:54:14] [PASSED] rounding3
[04:54:14] [PASSED] rounding4
[04:54:14] =========== [PASSED] drm_test_check_plane_state ============
[04:54:14] =========== drm_test_check_invalid_plane_state  ============
[04:54:14] [PASSED] positioning_invalid
[04:54:14] [PASSED] upscaling_invalid
[04:54:14] [PASSED] downscaling_invalid
[04:54:14] ======= [PASSED] drm_test_check_invalid_plane_state ========
[04:54:14] ================ [PASSED] drm_plane_helper =================
[04:54:14] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[04:54:14] ====== drm_test_connector_helper_tv_get_modes_check  =======
[04:54:14] [PASSED] None
[04:54:14] [PASSED] PAL
[04:54:14] [PASSED] NTSC
[04:54:14] [PASSED] Both, NTSC Default
[04:54:14] [PASSED] Both, PAL Default
[04:54:14] [PASSED] Both, NTSC Default, with PAL on command-line
[04:54:14] [PASSED] Both, PAL Default, with NTSC on command-line
[04:54:14] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[04:54:14] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[04:54:14] ================== drm_rect (9 subtests) ===================
[04:54:14] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[04:54:14] [PASSED] drm_test_rect_clip_scaled_not_clipped
[04:54:14] [PASSED] drm_test_rect_clip_scaled_clipped
[04:54:14] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[04:54:14] ================= drm_test_rect_intersect  =================
[04:54:14] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[04:54:14] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[04:54:14] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[04:54:14] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[04:54:14] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[04:54:14] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[04:54:14] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[04:54:14] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[04:54:14] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[04:54:14] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[04:54:14] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[04:54:14] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[04:54:14] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[04:54:14] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[04:54:14] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[04:54:14] ============= [PASSED] drm_test_rect_intersect =============
[04:54:14] ================ drm_test_rect_calc_hscale  ================
[04:54:14] [PASSED] normal use
[04:54:14] [PASSED] out of max range
[04:54:14] [PASSED] out of min range
[04:54:14] [PASSED] zero dst
[04:54:14] [PASSED] negative src
[04:54:14] [PASSED] negative dst
[04:54:14] ============ [PASSED] drm_test_rect_calc_hscale ============
[04:54:14] ================ drm_test_rect_calc_vscale  ================
[04:54:14] [PASSED] normal use
[04:54:14] [PASSED] out of max range
[04:54:14] [PASSED] out of min range
[04:54:14] [PASSED] zero dst
[04:54:14] [PASSED] negative src
stty: 'standard input': Inappropriate ioctl for device
[04:54:14] [PASSED] negative dst
[04:54:14] ============ [PASSED] drm_test_rect_calc_vscale ============
[04:54:14] ================== drm_test_rect_rotate  ===================
[04:54:14] [PASSED] reflect-x
[04:54:14] [PASSED] reflect-y
[04:54:14] [PASSED] rotate-0
[04:54:14] [PASSED] rotate-90
[04:54:14] [PASSED] rotate-180
[04:54:14] [PASSED] rotate-270
[04:54:14] ============== [PASSED] drm_test_rect_rotate ===============
[04:54:14] ================ drm_test_rect_rotate_inv  =================
[04:54:14] [PASSED] reflect-x
[04:54:14] [PASSED] reflect-y
[04:54:14] [PASSED] rotate-0
[04:54:14] [PASSED] rotate-90
[04:54:14] [PASSED] rotate-180
[04:54:14] [PASSED] rotate-270
[04:54:14] ============ [PASSED] drm_test_rect_rotate_inv =============
[04:54:14] ==================== [PASSED] drm_rect =====================
[04:54:14] ============ drm_sysfb_modeset_test (1 subtest) ============
[04:54:14] ============ drm_test_sysfb_build_fourcc_list  =============
[04:54:14] [PASSED] no native formats
[04:54:14] [PASSED] XRGB8888 as native format
[04:54:14] [PASSED] remove duplicates
[04:54:14] [PASSED] convert alpha formats
[04:54:14] [PASSED] random formats
[04:54:14] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[04:54:14] ============= [PASSED] drm_sysfb_modeset_test ==============
[04:54:14] ============================================================
[04:54:14] Testing complete. Ran 621 tests: passed: 621
[04:54:14] Elapsed time: 25.672s total, 1.790s configuring, 23.665s building, 0.174s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[04:54:14] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:54:16] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[04:54:25] Starting KUnit Kernel (1/1)...
[04:54:25] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[04:54:25] ================= ttm_device (5 subtests) ==================
[04:54:25] [PASSED] ttm_device_init_basic
[04:54:25] [PASSED] ttm_device_init_multiple
[04:54:25] [PASSED] ttm_device_fini_basic
[04:54:25] [PASSED] ttm_device_init_no_vma_man
[04:54:25] ================== ttm_device_init_pools  ==================
[04:54:25] [PASSED] No DMA allocations, no DMA32 required
[04:54:25] [PASSED] DMA allocations, DMA32 required
[04:54:25] [PASSED] No DMA allocations, DMA32 required
[04:54:25] [PASSED] DMA allocations, no DMA32 required
[04:54:25] ============== [PASSED] ttm_device_init_pools ==============
[04:54:25] =================== [PASSED] ttm_device ====================
[04:54:25] ================== ttm_pool (8 subtests) ===================
[04:54:25] ================== ttm_pool_alloc_basic  ===================
[04:54:25] [PASSED] One page
[04:54:25] [PASSED] More than one page
[04:54:25] [PASSED] Above the allocation limit
[04:54:25] [PASSED] One page, with coherent DMA mappings enabled
[04:54:25] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:54:25] ============== [PASSED] ttm_pool_alloc_basic ===============
[04:54:25] ============== ttm_pool_alloc_basic_dma_addr  ==============
[04:54:25] [PASSED] One page
[04:54:25] [PASSED] More than one page
[04:54:25] [PASSED] Above the allocation limit
[04:54:25] [PASSED] One page, with coherent DMA mappings enabled
[04:54:25] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[04:54:25] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[04:54:25] [PASSED] ttm_pool_alloc_order_caching_match
[04:54:25] [PASSED] ttm_pool_alloc_caching_mismatch
[04:54:25] [PASSED] ttm_pool_alloc_order_mismatch
[04:54:25] [PASSED] ttm_pool_free_dma_alloc
[04:54:25] [PASSED] ttm_pool_free_no_dma_alloc
[04:54:25] [PASSED] ttm_pool_fini_basic
[04:54:25] ==================== [PASSED] ttm_pool =====================
[04:54:25] ================ ttm_resource (8 subtests) =================
[04:54:25] ================= ttm_resource_init_basic  =================
[04:54:25] [PASSED] Init resource in TTM_PL_SYSTEM
[04:54:25] [PASSED] Init resource in TTM_PL_VRAM
[04:54:25] [PASSED] Init resource in a private placement
[04:54:25] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[04:54:25] ============= [PASSED] ttm_resource_init_basic =============
[04:54:25] [PASSED] ttm_resource_init_pinned
[04:54:25] [PASSED] ttm_resource_fini_basic
[04:54:25] [PASSED] ttm_resource_manager_init_basic
[04:54:25] [PASSED] ttm_resource_manager_usage_basic
[04:54:25] [PASSED] ttm_resource_manager_set_used_basic
[04:54:25] [PASSED] ttm_sys_man_alloc_basic
[04:54:25] [PASSED] ttm_sys_man_free_basic
[04:54:25] ================== [PASSED] ttm_resource ===================
[04:54:25] =================== ttm_tt (15 subtests) ===================
[04:54:25] ==================== ttm_tt_init_basic  ====================
[04:54:25] [PASSED] Page-aligned size
[04:54:25] [PASSED] Extra pages requested
[04:54:25] ================ [PASSED] ttm_tt_init_basic ================
[04:54:25] [PASSED] ttm_tt_init_misaligned
[04:54:25] [PASSED] ttm_tt_fini_basic
[04:54:25] [PASSED] ttm_tt_fini_sg
[04:54:25] [PASSED] ttm_tt_fini_shmem
[04:54:25] [PASSED] ttm_tt_create_basic
[04:54:25] [PASSED] ttm_tt_create_invalid_bo_type
[04:54:25] [PASSED] ttm_tt_create_ttm_exists
[04:54:25] [PASSED] ttm_tt_create_failed
[04:54:25] [PASSED] ttm_tt_destroy_basic
[04:54:25] [PASSED] ttm_tt_populate_null_ttm
[04:54:25] [PASSED] ttm_tt_populate_populated_ttm
[04:54:25] [PASSED] ttm_tt_unpopulate_basic
[04:54:25] [PASSED] ttm_tt_unpopulate_empty_ttm
[04:54:25] [PASSED] ttm_tt_swapin_basic
[04:54:25] ===================== [PASSED] ttm_tt ======================
[04:54:25] =================== ttm_bo (14 subtests) ===================
[04:54:25] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[04:54:25] [PASSED] Cannot be interrupted and sleeps
[04:54:25] [PASSED] Cannot be interrupted, locks straight away
[04:54:25] [PASSED] Can be interrupted, sleeps
[04:54:25] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[04:54:25] [PASSED] ttm_bo_reserve_locked_no_sleep
[04:54:25] [PASSED] ttm_bo_reserve_no_wait_ticket
[04:54:25] [PASSED] ttm_bo_reserve_double_resv
[04:54:25] [PASSED] ttm_bo_reserve_interrupted
[04:54:25] [PASSED] ttm_bo_reserve_deadlock
[04:54:25] [PASSED] ttm_bo_unreserve_basic
[04:54:25] [PASSED] ttm_bo_unreserve_pinned
[04:54:25] [PASSED] ttm_bo_unreserve_bulk
[04:54:25] [PASSED] ttm_bo_fini_basic
[04:54:25] [PASSED] ttm_bo_fini_shared_resv
[04:54:25] [PASSED] ttm_bo_pin_basic
[04:54:25] [PASSED] ttm_bo_pin_unpin_resource
[04:54:25] [PASSED] ttm_bo_multiple_pin_one_unpin
[04:54:25] ===================== [PASSED] ttm_bo ======================
[04:54:25] ============== ttm_bo_validate (21 subtests) ===============
[04:54:25] ============== ttm_bo_init_reserved_sys_man  ===============
[04:54:25] [PASSED] Buffer object for userspace
[04:54:25] [PASSED] Kernel buffer object
[04:54:25] [PASSED] Shared buffer object
[04:54:25] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[04:54:25] ============== ttm_bo_init_reserved_mock_man  ==============
[04:54:25] [PASSED] Buffer object for userspace
[04:54:25] [PASSED] Kernel buffer object
[04:54:25] [PASSED] Shared buffer object
[04:54:25] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[04:54:25] [PASSED] ttm_bo_init_reserved_resv
[04:54:25] ================== ttm_bo_validate_basic  ==================
[04:54:25] [PASSED] Buffer object for userspace
[04:54:25] [PASSED] Kernel buffer object
[04:54:25] [PASSED] Shared buffer object
[04:54:25] ============== [PASSED] ttm_bo_validate_basic ==============
[04:54:25] [PASSED] ttm_bo_validate_invalid_placement
[04:54:25] ============= ttm_bo_validate_same_placement  ==============
[04:54:25] [PASSED] System manager
[04:54:25] [PASSED] VRAM manager
[04:54:25] ========= [PASSED] ttm_bo_validate_same_placement ==========
[04:54:25] [PASSED] ttm_bo_validate_failed_alloc
[04:54:25] [PASSED] ttm_bo_validate_pinned
[04:54:25] [PASSED] ttm_bo_validate_busy_placement
[04:54:25] ================ ttm_bo_validate_multihop  =================
[04:54:25] [PASSED] Buffer object for userspace
[04:54:25] [PASSED] Kernel buffer object
[04:54:25] [PASSED] Shared buffer object
[04:54:25] ============ [PASSED] ttm_bo_validate_multihop =============
[04:54:25] ========== ttm_bo_validate_no_placement_signaled  ==========
[04:54:25] [PASSED] Buffer object in system domain, no page vector
[04:54:25] [PASSED] Buffer object in system domain with an existing page vector
[04:54:25] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[04:54:25] ======== ttm_bo_validate_no_placement_not_signaled  ========
[04:54:25] [PASSED] Buffer object for userspace
[04:54:25] [PASSED] Kernel buffer object
[04:54:25] [PASSED] Shared buffer object
[04:54:25] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[04:54:25] [PASSED] ttm_bo_validate_move_fence_signaled
[04:54:25] ========= ttm_bo_validate_move_fence_not_signaled  =========
[04:54:25] [PASSED] Waits for GPU
[04:54:25] [PASSED] Tries to lock straight away
[04:54:25] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[04:54:25] [PASSED] ttm_bo_validate_happy_evict
[04:54:25] [PASSED] ttm_bo_validate_all_pinned_evict
[04:54:25] [PASSED] ttm_bo_validate_allowed_only_evict
[04:54:25] [PASSED] ttm_bo_validate_deleted_evict
[04:54:25] [PASSED] ttm_bo_validate_busy_domain_evict
[04:54:25] [PASSED] ttm_bo_validate_evict_gutting
[04:54:25] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[04:54:25] ================= [PASSED] ttm_bo_validate =================
[04:54:25] ============================================================
[04:54:25] Testing complete. Ran 101 tests: passed: 101
[04:54:25] Elapsed time: 11.220s total, 1.681s configuring, 9.323s building, 0.188s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for Optimize vrr.guardband and fix LRR (rev14)

[Patchwork]

== Series Details ==

Series: Optimize vrr.guardband and fix LRR (rev14)
URL   : https://patchwork.freedesktop.org/series/151244/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast af95880a54d743a43dd2d575764e0807a89da01f
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2035:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2035:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2035:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2035:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2035:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2035:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2035:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2035:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2035:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Optimize vrr.guardband and fix LRR (rev14)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6610 bytes --]

== Series Details ==

Series: Optimize vrr.guardband and fix LRR (rev14)
URL   : https://patchwork.freedesktop.org/series/151244/
State : success

== Summary ==

CI Bug Log - changes from xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47_BAT -> xe-pw-151244v14_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 11)
------------------------------

  Additional (1): bat-lnl-2 

Known issues
------------

  Here are the changes found in xe-pw-151244v14_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@nullptr:
    - bat-lnl-2:          NOTRUN -> [SKIP][1] ([Intel XE#2134]) +4 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/bat-lnl-2/igt@fbdev@nullptr.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-lnl-2:          NOTRUN -> [SKIP][2] ([Intel XE#1466] / [Intel XE#2235])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/bat-lnl-2/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_flip@basic-flip-vs-dpms:
    - bat-lnl-2:          NOTRUN -> [SKIP][3] ([Intel XE#2235] / [Intel XE#2482]) +3 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/bat-lnl-2/igt@kms_flip@basic-flip-vs-dpms.html

  * igt@kms_force_connector_basic@force-connector-state:
    - bat-lnl-2:          NOTRUN -> [SKIP][4] ([Intel XE#2235] / [Intel XE#352]) +2 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/bat-lnl-2/igt@kms_force_connector_basic@force-connector-state.html

  * igt@kms_frontbuffer_tracking@basic:
    - bat-lnl-2:          NOTRUN -> [SKIP][5] ([Intel XE#2235] / [Intel XE#2548])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/bat-lnl-2/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_hdmi_inject@inject-audio:
    - bat-lnl-2:          NOTRUN -> [SKIP][6] ([Intel XE#1470] / [Intel XE#2235] / [Intel XE#2853])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/bat-lnl-2/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24:
    - bat-lnl-2:          NOTRUN -> [SKIP][7] ([Intel XE#2235]) +13 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/bat-lnl-2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24.html

  * igt@kms_psr@psr-cursor-plane-move:
    - bat-lnl-2:          NOTRUN -> [SKIP][8] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +2 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/bat-lnl-2/igt@kms_psr@psr-cursor-plane-move.html

  * igt@sriov_basic@enable-vfs-autoprobe-off:
    - bat-lnl-2:          NOTRUN -> [SKIP][9] ([Intel XE#1091] / [Intel XE#2849]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/bat-lnl-2/igt@sriov_basic@enable-vfs-autoprobe-off.html

  * igt@xe_evict@evict-beng-small:
    - bat-lnl-2:          NOTRUN -> [SKIP][10] ([Intel XE#688]) +11 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/bat-lnl-2/igt@xe_evict@evict-beng-small.html

  * igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit:
    - bat-lnl-2:          NOTRUN -> [SKIP][11] ([Intel XE#2229]) +2 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/bat-lnl-2/igt@xe_live_ktest@xe_bo@xe_bo_evict_kunit.html

  * igt@xe_mmap@vram:
    - bat-lnl-2:          NOTRUN -> [SKIP][12] ([Intel XE#1416])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/bat-lnl-2/igt@xe_mmap@vram.html

  * igt@xe_pat@pat-index-xehpc:
    - bat-lnl-2:          NOTRUN -> [SKIP][13] ([Intel XE#1420] / [Intel XE#2838])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/bat-lnl-2/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pat@pat-index-xelp:
    - bat-lnl-2:          NOTRUN -> [SKIP][14] ([Intel XE#977])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/bat-lnl-2/igt@xe_pat@pat-index-xelp.html

  * igt@xe_pat@pat-index-xelpg:
    - bat-lnl-2:          NOTRUN -> [SKIP][15] ([Intel XE#2236] / [Intel XE#979])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/bat-lnl-2/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_sriov_flr@flr-vf1-clear:
    - bat-lnl-2:          NOTRUN -> [SKIP][16] ([Intel XE#3342])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/bat-lnl-2/igt@xe_sriov_flr@flr-vf1-clear.html

  
  [Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1416
  [Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
  [Intel XE#1466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1466
  [Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470
  [Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2235]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2235
  [Intel XE#2236]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2236
  [Intel XE#2482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2482
  [Intel XE#2548]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2548
  [Intel XE#2838]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2838
  [Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2853]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2853
  [Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
  [Intel XE#352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/352
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#977]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/977
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979


Build changes
-------------

  * Linux: xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47 -> xe-pw-151244v14

  IGT_8574: 44a15713124663a622c6eddf7c6ee5ba732e0d41 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47: 0ce21448d1c984adf76d9dbfb3ad626ef8f33e47
  xe-pw-151244v14: 151244v14

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/index.html

[-- Attachment #2: Type: text/html, Size: 7838 bytes --]

✗ Xe.CI.Full: failure for Optimize vrr.guardband and fix LRR (rev14)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 38650 bytes --]

== Series Details ==

Series: Optimize vrr.guardband and fix LRR (rev14)
URL   : https://patchwork.freedesktop.org/series/151244/
State : failure

== Summary ==

CI Bug Log - changes from xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47_FULL -> xe-pw-151244v14_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-151244v14_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-151244v14_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-151244v14_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_cursor_legacy@single-move@pipe-c:
    - shard-dg2-set2:     [PASS][1] -> [DMESG-WARN][2] +1 other test dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-dg2-464/igt@kms_cursor_legacy@single-move@pipe-c.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@kms_cursor_legacy@single-move@pipe-c.html

  
New tests
---------

  New tests have been introduced between xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47_FULL and xe-pw-151244v14_FULL:

### New IGT tests (4) ###

  * igt@kms_plane_alpha_blend@alpha-basic@pipe-d-hdmi-a-1:
    - Statuses : 1 pass(s)
    - Exec time: [2.50] s

  * igt@kms_plane_alpha_blend@constant-alpha-mid@pipe-d-hdmi-a-1:
    - Statuses : 1 pass(s)
    - Exec time: [0.64] s

  * igt@kms_rmfb@close-fd@pipe-b-hdmi-a-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.25] s

  * igt@kms_rmfb@rmfb-ioctl@pipe-b-hdmi-a-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.24] s

  

Known issues
------------

  Here are the changes found in xe-pw-151244v14_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][3] ([Intel XE#316])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][4] ([Intel XE#1124]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@kms_big_fb@y-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-dg2-set2:     NOTRUN -> [SKIP][5] ([Intel XE#619])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-432/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_bw@linear-tiling-2-displays-2560x1440p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][6] ([Intel XE#367])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-432/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][7] ([Intel XE#455] / [Intel XE#787]) +19 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2652] / [Intel XE#787]) +3 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-bmg:          [PASS][9] -> [INCOMPLETE][10] ([Intel XE#3862]) +1 other test incomplete
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-1/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#787]) +118 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-432/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [PASS][12] -> [INCOMPLETE][13] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4:
    - shard-dg2-set2:     [PASS][14] -> [INCOMPLETE][15] ([Intel XE#6168])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [PASS][16] -> [DMESG-WARN][17] ([Intel XE#1727] / [Intel XE#3113])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][18] ([Intel XE#6168])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][19] ([Intel XE#1727] / [Intel XE#3113])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_chamelium_hpd@hdmi-hpd:
    - shard-dg2-set2:     NOTRUN -> [SKIP][20] ([Intel XE#373]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@kms_chamelium_hpd@hdmi-hpd.html

  * igt@kms_content_protection@atomic-dpms@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][21] ([Intel XE#1178])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-435/igt@kms_content_protection@atomic-dpms@pipe-a-dp-4.html

  * igt@kms_content_protection@atomic@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][22] ([Intel XE#1178])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-3/igt@kms_content_protection@atomic@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1:
    - shard-adlp:         [PASS][23] -> [DMESG-WARN][24] ([Intel XE#2953] / [Intel XE#4173]) +1 other test dmesg-warn
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-adlp-8/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-adlp-3/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
    - shard-bmg:          [PASS][25] -> [SKIP][26] ([Intel XE#2291])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-lnl:          [PASS][27] -> [FAIL][28] ([Intel XE#4164])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-lnl-1/igt@kms_fbcon_fbt@psr-suspend.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-lnl-4/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@display-2x:
    - shard-bmg:          [PASS][29] -> [SKIP][30] ([Intel XE#2373])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-1/igt@kms_feature_discovery@display-2x.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-6/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-bmg:          [PASS][31] -> [SKIP][32] ([Intel XE#2316]) +4 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-1/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-lnl:          [PASS][33] -> [FAIL][34] ([Intel XE#301])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@flip-vs-rmfb-interruptible:
    - shard-adlp:         [PASS][35] -> [DMESG-WARN][36] ([Intel XE#4543] / [Intel XE#5208])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-adlp-6/igt@kms_flip@flip-vs-rmfb-interruptible.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-adlp-1/igt@kms_flip@flip-vs-rmfb-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-adlp:         [PASS][37] -> [DMESG-WARN][38] ([Intel XE#4543]) +10 other tests dmesg-warn
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-adlp-6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-adlp-1/igt@kms_flip@flip-vs-suspend-interruptible.html
    - shard-dg2-set2:     [PASS][39] -> [INCOMPLETE][40] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-dg2-466/igt@kms_flip@flip-vs-suspend-interruptible.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-436/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip_tiling@flip-change-tiling:
    - shard-adlp:         [PASS][41] -> [DMESG-FAIL][42] ([Intel XE#4543]) +1 other test dmesg-fail
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-adlp-1/igt@kms_flip_tiling@flip-change-tiling.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-adlp-1/igt@kms_flip_tiling@flip-change-tiling.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-y:
    - shard-adlp:         [PASS][43] -> [FAIL][44] ([Intel XE#1874]) +1 other test fail
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-adlp-1/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-y.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-adlp-1/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-y.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-slowdraw:
    - shard-dg2-set2:     NOTRUN -> [SKIP][45] ([Intel XE#651]) +4 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcdrrs-slowdraw.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][46] ([Intel XE#653]) +9 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_hdr@invalid-hdr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][47] ([Intel XE#455]) +3 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-dg2-set2:     NOTRUN -> [SKIP][48] ([Intel XE#2927])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-432/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-bmg:          [PASS][49] -> [SKIP][50] ([Intel XE#3012]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-3/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-bmg:          [PASS][51] -> [SKIP][52] ([Intel XE#4596])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-8/igt@kms_plane_multiple@2x-tiling-x.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-dg2-set2:     NOTRUN -> [SKIP][53] ([Intel XE#870])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> [SKIP][54] ([Intel XE#1406] / [Intel XE#1489]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move:
    - shard-dg2-set2:     NOTRUN -> [SKIP][55] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@kms_psr@fbc-psr2-cursor-plane-move.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][56] ([Intel XE#3414])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_setmode@basic@pipe-b-edp-1:
    - shard-lnl:          [PASS][57] -> [FAIL][58] ([Intel XE#2883]) +2 other tests fail
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-lnl-7/igt@kms_setmode@basic@pipe-b-edp-1.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-lnl-7/igt@kms_setmode@basic@pipe-b-edp-1.html

  * igt@xe_compute_preempt@compute-preempt-many:
    - shard-dg2-set2:     NOTRUN -> [FAIL][59] ([Intel XE#5890]) +1 other test fail
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@xe_compute_preempt@compute-preempt-many.html

  * igt@xe_copy_basic@mem-set-linear-0x3fff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][60] ([Intel XE#1126])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@xe_copy_basic@mem-set-linear-0x3fff.html

  * igt@xe_eu_stall@blocking-re-enable:
    - shard-dg2-set2:     NOTRUN -> [SKIP][61] ([Intel XE#5626])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@xe_eu_stall@blocking-re-enable.html

  * igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-sram:
    - shard-dg2-set2:     NOTRUN -> [SKIP][62] ([Intel XE#4837]) +1 other test skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-432/igt@xe_eudebug_online@writes-caching-sram-bb-sram-target-sram.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-bind:
    - shard-dg2-set2:     NOTRUN -> [SKIP][63] ([Intel XE#1392])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic-defer-bind.html

  * igt@xe_exec_basic@multigpu-no-exec-bindexecqueue:
    - shard-dg2-set2:     [PASS][64] -> [SKIP][65] ([Intel XE#1392]) +4 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-dg2-434/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue.html

  * igt@xe_exec_fault_mode@twice-userptr-prefetch:
    - shard-dg2-set2:     NOTRUN -> [SKIP][66] ([Intel XE#288]) +6 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@xe_exec_fault_mode@twice-userptr-prefetch.html

  * igt@xe_exec_reset@parallel-gt-reset:
    - shard-adlp:         [PASS][67] -> [DMESG-WARN][68] ([Intel XE#3876])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-adlp-8/igt@xe_exec_reset@parallel-gt-reset.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-adlp-8/igt@xe_exec_reset@parallel-gt-reset.html

  * igt@xe_exec_system_allocator@process-many-execqueues-mmap-huge-nomemset:
    - shard-dg2-set2:     NOTRUN -> [SKIP][69] ([Intel XE#4915]) +61 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@xe_exec_system_allocator@process-many-execqueues-mmap-huge-nomemset.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv:
    - shard-dg2-set2:     [PASS][70] -> [DMESG-WARN][71] ([Intel XE#5893])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-dg2-433/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-463/igt@xe_fault_injection@probe-fail-guc-xe_guc_mmio_send_recv.html

  * igt@xe_oa@oa-unit-exclusive-stream-sample-oa:
    - shard-dg2-set2:     NOTRUN -> [SKIP][72] ([Intel XE#3573])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@xe_oa@oa-unit-exclusive-stream-sample-oa.html

  * igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p:
    - shard-dg2-set2:     NOTRUN -> [FAIL][73] ([Intel XE#1173]) +1 other test fail
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@xe_peer2peer@read@read-gpua-vram01-gpub-system-p2p.html

  * igt@xe_pmu@gt-frequency:
    - shard-dg2-set2:     [PASS][74] -> [FAIL][75] ([Intel XE#4819]) +1 other test fail
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-dg2-464/igt@xe_pmu@gt-frequency.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@xe_pmu@gt-frequency.html

  * igt@xe_query@multigpu-query-invalid-size:
    - shard-dg2-set2:     NOTRUN -> [SKIP][76] ([Intel XE#944])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@xe_query@multigpu-query-invalid-size.html

  * igt@xe_render_copy@render-stress-0-copies:
    - shard-dg2-set2:     NOTRUN -> [SKIP][77] ([Intel XE#4814])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-432/igt@xe_render_copy@render-stress-0-copies.html

  * igt@xe_sriov_flr@flr-each-isolation:
    - shard-dg2-set2:     NOTRUN -> [SKIP][78] ([Intel XE#3342])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@xe_sriov_flr@flr-each-isolation.html

  
#### Possible fixes ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     [INCOMPLETE][79] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168]) -> [PASS][80] +1 other test pass
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][81] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-bmg:          [SKIP][83] ([Intel XE#2291]) -> [PASS][84] +5 other tests pass
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-3/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-bmg:          [SKIP][85] ([Intel XE#1340]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-3/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-bmg:          [SKIP][87] ([Intel XE#2316]) -> [PASS][88] +5 other tests pass
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-6/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-7/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][89] ([Intel XE#4543]) -> [PASS][90] +9 other tests pass
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-adlp-9/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-adlp-4/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-lnl:          [FAIL][91] ([Intel XE#301]) -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-adlp:         [DMESG-WARN][93] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][94] +1 other test pass
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-adlp-2/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-adlp-9/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_plane_scaling@2x-scaler-multi-pipe:
    - shard-bmg:          [SKIP][95] ([Intel XE#2571]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-6/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-5/igt@kms_plane_scaling@2x-scaler-multi-pipe.html

  * igt@xe_exec_basic@multigpu-once-basic-defer-mmap:
    - shard-dg2-set2:     [SKIP][97] ([Intel XE#1392]) -> [PASS][98] +3 other tests pass
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-dg2-432/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-435/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html

  * igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate-race-imm:
    - shard-bmg:          [FAIL][99] ([Intel XE#6050]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-4/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate-race-imm.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-4/igt@xe_exec_fault_mode@twice-bindexecqueue-userptr-invalidate-race-imm.html

  * igt@xe_exec_system_allocator@twice-malloc-nomemset:
    - shard-bmg:          [DMESG-FAIL][101] ([Intel XE#5213]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-4/igt@xe_exec_system_allocator@twice-malloc-nomemset.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-4/igt@xe_exec_system_allocator@twice-malloc-nomemset.html

  * igt@xe_pm@s2idle-basic:
    - shard-adlp:         [DMESG-WARN][103] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4504]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-adlp-9/igt@xe_pm@s2idle-basic.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-adlp-4/igt@xe_pm@s2idle-basic.html

  
#### Warnings ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][105] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522]) -> [INCOMPLETE][106] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          [SKIP][107] ([Intel XE#2341]) -> [FAIL][108] ([Intel XE#1178])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-6/igt@kms_content_protection@atomic.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-3/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-bmg:          [FAIL][109] ([Intel XE#1178]) -> [SKIP][110] ([Intel XE#2341])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-1/igt@kms_content_protection@atomic-dpms.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-6/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [FAIL][111] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][112] ([Intel XE#301])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt:
    - shard-bmg:          [SKIP][113] ([Intel XE#2312]) -> [SKIP][114] ([Intel XE#5390]) +4 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][115] ([Intel XE#5390]) -> [SKIP][116] ([Intel XE#2312]) +7 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][117] ([Intel XE#2311]) -> [SKIP][118] ([Intel XE#2312]) +13 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][119] ([Intel XE#2312]) -> [SKIP][120] ([Intel XE#2311]) +9 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-msflip-blt.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw:
    - shard-bmg:          [SKIP][121] ([Intel XE#2312]) -> [SKIP][122] ([Intel XE#2313]) +10 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][123] ([Intel XE#2313]) -> [SKIP][124] ([Intel XE#2312]) +10 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-adlp:         [SKIP][125] ([Intel XE#734]) -> [FAIL][126] ([Intel XE#3325])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-adlp-6/igt@kms_pm_dc@dc9-dpms.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-adlp-8/igt@kms_pm_dc@dc9-dpms.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-dg2-set2:     [ABORT][127] ([Intel XE#5466]) -> [ABORT][128] ([Intel XE#4917] / [Intel XE#5466])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-dg2-434/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-dg2-432/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
    - shard-bmg:          [ABORT][129] ([Intel XE#5466] / [Intel XE#5530]) -> [ABORT][130] ([Intel XE#4917] / [Intel XE#5466] / [Intel XE#5530])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47/shard-bmg-2/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/shard-bmg-8/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
  [Intel XE#1173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1173
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
  [Intel XE#2571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2571
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
  [Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3325
  [Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
  [Intel XE#4164]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4164
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4504
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4814
  [Intel XE#4819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4819
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5213]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5213
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5624]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5624
  [Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
  [Intel XE#5890]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5890
  [Intel XE#5893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5893
  [Intel XE#6050]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6050
  [Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
  [Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#734]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/734
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47 -> xe-pw-151244v14

  IGT_8574: 44a15713124663a622c6eddf7c6ee5ba732e0d41 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3867-0ce21448d1c984adf76d9dbfb3ad626ef8f33e47: 0ce21448d1c984adf76d9dbfb3ad626ef8f33e47
  xe-pw-151244v14: 151244v14

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151244v14/index.html

[-- Attachment #2: Type: text/html, Size: 45424 bytes --]

Re: [PATCH 13/16] drm/i915/display: Add vblank_start adjustment logic for always-on VRR TG

[Ville Syrjälä]

On Mon, Oct 06, 2025 at 09:58:49AM +0530, Ankit Nautiyal wrote:
> As we move towards using a shorter, optimized guardband, we need to adjust
> how the delayed vblank start is computed.
> 
> Introduce intel_crtc_compute_vrr_guardband() to handle guardband
> computation and apply vblank_start adjustment for platforms that always use
> the VRR timing generator.
> 
> This function wraps the existing intel_vrr_compute_guardband() and adjusts
> crtc_vblank_start using (vblank_length - guardband) only when
> intel_vrr_always_use_vrr_tg() is true. Since the guardband is not yet
> optimized, the adjustment currently evaluates to zero, preserving existing
> behavior.
> 
> This paves way for guardband optimization, by handling the movement of
> the crtc_vblank_start for platforms that have VRR TG always active.
> 
> Also update allow_vblank_delay_fastset() to permit vblank delay adjustments
> during fastboot when VRR TG is always active, even without inherited state.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 33 ++++++++++++++++++--
>  1 file changed, 30 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b2d4e24fd7c6..1964e41b5704 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2403,6 +2403,27 @@ static int intel_crtc_compute_set_context_latency(struct intel_atomic_state *sta
>  	return 0;
>  }
>  
> +static void intel_crtc_compute_vrr_guardband(struct intel_atomic_state *state,
> +					     struct intel_crtc *crtc)

Why this wrapper? You could just stick the adjustemnt into
intel_vrr_compute_guardband().

> +{
> +	struct intel_display *display = to_intel_display(state);
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	struct drm_display_mode *adjusted_mode =
> +		&crtc_state->hw.adjusted_mode;
> +
> +	intel_vrr_compute_guardband(crtc_state);
> +
> +	if (intel_vrr_always_use_vrr_tg(display)) {
> +		int vblank_length = adjusted_mode->crtc_vtotal -
> +				    (crtc_state->set_context_latency +
> +				     adjusted_mode->crtc_vdisplay);
> +
> +		adjusted_mode->crtc_vblank_start +=
> +			vblank_length - crtc_state->vrr.guardband;

Why aren't you using the same 'vblank_start = vtotal-guardband' here as
during readout?

> +	}
> +}
> +
>  static int intel_crtc_compute_config(struct intel_atomic_state *state,
>  				     struct intel_crtc *crtc)
>  {
> @@ -2414,7 +2435,7 @@ static int intel_crtc_compute_config(struct intel_atomic_state *state,
>  	if (ret)
>  		return ret;
>  
> -	intel_vrr_compute_guardband(crtc_state);
> +	intel_crtc_compute_vrr_guardband(state, crtc);
>  
>  	ret = intel_dpll_crtc_compute_clock(state, crtc);
>  	if (ret)
> @@ -5105,9 +5126,15 @@ static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_s
>  	 * Allow fastboot to fix up vblank delay (handled via LRR
>  	 * codepaths), a bit dodgy as the registers aren't
>  	 * double buffered but seems to be working more or less...
> +	 *
> +	 * Also allow this when the VRR timing generator is always on,
> +	 * which implies optimized guardband is used. In such cases,
> +	 * vblank delay may vary even without inherited state, but it's
> +	 * still safe as VRR guardband is still same.
>  	 */
> -	return HAS_LRR(display) && old_crtc_state->inherited &&
> -		!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
> +	return HAS_LRR(display) &&
> +	       (old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) &&
> +	       !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);

This part doesn't seem directly related to the making crtc_vblank_start
correct. We still use the non-optimzied guardband so crtc_vblank_start
should not be changing during normal runtime operation.

>  }
>  
>  bool
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 11/16] drm/i915/vblank: Add helper to get correct vblank length

[Ville Syrjälä]

On Mon, Oct 06, 2025 at 09:58:47AM +0530, Ankit Nautiyal wrote:
> Currently crtc_vblank_start is assumed to be the vblank_start for the fixed
> refresh rate case. That value can be different from the variable refresh
> rate case whenever always_use_vrr_tg()==false. On icl/tgl it's always
> different due to the extra vblank delay, and also on adl+ it could be
> different if we were to use an optimized guardband.
> 
> So places where crtc_vblank_start is used to compute vblank length needs
> change so as to account for cases where vrr is enabled. Specifically
> with vrr.enable the effective vblank length is actually guardband.
> 
> Add a helper to get the correct vblank length for both vrr and fixed
> refresh rate cases. Use this helper where vblank_start is used to
> compute the vblank length.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_pfit.c    | 11 +++++++----
>  drivers/gpu/drm/i915/display/intel_psr.c     |  3 +--
>  drivers/gpu/drm/i915/display/intel_vblank.c  | 10 ++++++++++
>  drivers/gpu/drm/i915/display/intel_vblank.h  |  2 ++
>  drivers/gpu/drm/i915/display/skl_watermark.c |  3 ++-
>  5 files changed, 22 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
> index 68539e7c2a24..ebbaa1d419ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_pfit.c
> +++ b/drivers/gpu/drm/i915/display/intel_pfit.c
> @@ -14,6 +14,7 @@
>  #include "intel_lvds_regs.h"
>  #include "intel_pfit.h"
>  #include "intel_pfit_regs.h"
> +#include "intel_vblank.h"
>  #include "skl_scaler.h"
>  
>  static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_state)
> @@ -306,14 +307,15 @@ centre_horizontally(struct drm_display_mode *adjusted_mode,
>  }
>  
>  static void
> -centre_vertically(struct drm_display_mode *adjusted_mode,
> +centre_vertically(struct intel_crtc_state *crtc_state,
> +		  struct drm_display_mode *adjusted_mode,
>  		  int height)
>  {
>  	u32 border, sync_pos, blank_width, sync_width;
>  
>  	/* keep the vsync and vblank widths constant */
>  	sync_width = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
> -	blank_width = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start;
> +	blank_width = intel_crtc_vblank_length(crtc_state);

This pfit stuff is computed way before the guardband, and also only
relevant for ancient gen2-4 hardware. So no point in touching this
stuff IMO.

>  	sync_pos = (blank_width - sync_width + 1) / 2;
>  
>  	border = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
> @@ -392,7 +394,8 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
>  					  PFIT_HORIZ_INTERP_BILINEAR);
>  		}
>  	} else if (scaled_width < scaled_height) { /* letter */
> -		centre_vertically(adjusted_mode,
> +		centre_vertically(crtc_state,
> +				  adjusted_mode,
>  				  scaled_width / pipe_src_w);
>  
>  		*border = LVDS_BORDER_ENABLE;
> @@ -489,7 +492,7 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
>  		 * heights and modify the values programmed into the CRTC.
>  		 */
>  		centre_horizontally(adjusted_mode, pipe_src_w);
> -		centre_vertically(adjusted_mode, pipe_src_h);
> +		centre_vertically(crtc_state, adjusted_mode, pipe_src_h);
>  		border = LVDS_BORDER_ENABLE;
>  		break;
>  	case DRM_MODE_SCALE_ASPECT:
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index f7115969b4c5..ae6b94a5d450 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1365,8 +1365,7 @@ static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
>  				       bool aux_less)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> -	int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -
> -		crtc_state->hw.adjusted_mode.crtc_vblank_start;
> +	int vblank = intel_crtc_vblank_length(crtc_state);

I *think* this also gets computed during .compute_config() which is
before the guardband calculation. So if this stuff actually depends on
the guardband then we have a real problem here. And if it doesn't (as
in it really interested in the undelayed vblank length) them maybe it
should just compute it as crtc_vtotal-crtc_vactive.

>  	int wake_lines;
>  
>  	if (aux_less)
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> index 0b7fcc05e64c..2fc0c1c0bb87 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -767,3 +767,13 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
>  
>  	return scanline;
>  }
> +
> +int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state)
> +{
> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +
> +	if (crtc_state->vrr.enable)
> +		return crtc_state->vrr.guardband;
> +	else
> +		return adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;

Maybe that should be crtc_vblank_end instead of crtc_vtotal? I guess it
doesn't actually matter given where this gets used.

I think the only case where vblank_end!=vtotal is exactly than ancient
gen2-4 pfit centering stuff. But I've never actually investigated
whether the exact value of vblank_end there even matters. I should do
that one day...

> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h
> index 21fbb08d61d5..98d04cacd65f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.h
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.h
> @@ -48,4 +48,6 @@ const struct intel_crtc_state *
>  intel_pre_commit_crtc_state(struct intel_atomic_state *state,
>  			    struct intel_crtc *crtc);
>  
> +int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state);
> +
>  #endif /* __INTEL_VBLANK_H__ */
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 73e5b2d8ae83..6fb2c78fe29b 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -28,6 +28,7 @@
>  #include "intel_flipq.h"
>  #include "intel_pcode.h"
>  #include "intel_plane.h"
> +#include "intel_vblank.h"
>  #include "intel_wm.h"
>  #include "skl_universal_plane_regs.h"
>  #include "skl_scaler.h"
> @@ -2171,7 +2172,7 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
>  	return crtc_state->framestart_delay +
>  		intel_usecs_to_scanlines(adjusted_mode, latency) +
>  		wm0_lines >
> -		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
> +		intel_crtc_vblank_length(crtc_state);
>  }
>  
>  int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 00/16] Optimize vrr.guardband and fix LRR

[Ville Syrjälä]

On Mon, Oct 06, 2025 at 09:58:36AM +0530, Ankit Nautiyal wrote:

I'd like to see a separate series with just the patches to fix
the crtc_vblank_start stuff, which I think is roughly these:

>   drm/i915/vrr: Use crtc_vsync_start/end for computing  vrr.vsync_start/end
>   drm/i915/vrr: s/intel_vrr_compute_config_late/intel_vrr_compute_guardband
>   drm/i915/vblank: Add helper to get correct vblank length
>   drm/i915/vrr: Recompute vblank_start for platforms with always-on VRR TG
>   drm/i915/display: Add vblank_start adjustment logic for always-on VRR TG

(+ whatever is needed to sort out the issues I outlined in the
 indiviual replies)

That is really just fixing existing things, and has nothing to
do with any of the prefill stuff/etc. in the rest of the series.

The prefill stuff btw seems to be completely borked in current
upstream code even; it computes things based on a completely stale
cdclk frequency (the new frequency will be computed much later).

I *think* I can reorder things sufficiently to fix that, but I really
must get https://patchwork.freedesktop.org/series/154921/ landed
first...

-- 
Ville Syrjälä
Intel

Re: [PATCH 11/16] drm/i915/vblank: Add helper to get correct vblank length

[Nautiyal, Ankit K]

On 10/7/2025 1:26 AM, Ville Syrjälä wrote:
> On Mon, Oct 06, 2025 at 09:58:47AM +0530, Ankit Nautiyal wrote:
>> Currently crtc_vblank_start is assumed to be the vblank_start for the fixed
>> refresh rate case. That value can be different from the variable refresh
>> rate case whenever always_use_vrr_tg()==false. On icl/tgl it's always
>> different due to the extra vblank delay, and also on adl+ it could be
>> different if we were to use an optimized guardband.
>>
>> So places where crtc_vblank_start is used to compute vblank length needs
>> change so as to account for cases where vrr is enabled. Specifically
>> with vrr.enable the effective vblank length is actually guardband.
>>
>> Add a helper to get the correct vblank length for both vrr and fixed
>> refresh rate cases. Use this helper where vblank_start is used to
>> compute the vblank length.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_pfit.c    | 11 +++++++----
>>   drivers/gpu/drm/i915/display/intel_psr.c     |  3 +--
>>   drivers/gpu/drm/i915/display/intel_vblank.c  | 10 ++++++++++
>>   drivers/gpu/drm/i915/display/intel_vblank.h  |  2 ++
>>   drivers/gpu/drm/i915/display/skl_watermark.c |  3 ++-
>>   5 files changed, 22 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
>> index 68539e7c2a24..ebbaa1d419ba 100644
>> --- a/drivers/gpu/drm/i915/display/intel_pfit.c
>> +++ b/drivers/gpu/drm/i915/display/intel_pfit.c
>> @@ -14,6 +14,7 @@
>>   #include "intel_lvds_regs.h"
>>   #include "intel_pfit.h"
>>   #include "intel_pfit_regs.h"
>> +#include "intel_vblank.h"
>>   #include "skl_scaler.h"
>>   
>>   static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_state)
>> @@ -306,14 +307,15 @@ centre_horizontally(struct drm_display_mode *adjusted_mode,
>>   }
>>   
>>   static void
>> -centre_vertically(struct drm_display_mode *adjusted_mode,
>> +centre_vertically(struct intel_crtc_state *crtc_state,
>> +		  struct drm_display_mode *adjusted_mode,
>>   		  int height)
>>   {
>>   	u32 border, sync_pos, blank_width, sync_width;
>>   
>>   	/* keep the vsync and vblank widths constant */
>>   	sync_width = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
>> -	blank_width = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start;
>> +	blank_width = intel_crtc_vblank_length(crtc_state);
> This pfit stuff is computed way before the guardband, and also only
> relevant for ancient gen2-4 hardware. So no point in touching this
> stuff IMO.

Alright can skip this stuff.


>
>>   	sync_pos = (blank_width - sync_width + 1) / 2;
>>   
>>   	border = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
>> @@ -392,7 +394,8 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
>>   					  PFIT_HORIZ_INTERP_BILINEAR);
>>   		}
>>   	} else if (scaled_width < scaled_height) { /* letter */
>> -		centre_vertically(adjusted_mode,
>> +		centre_vertically(crtc_state,
>> +				  adjusted_mode,
>>   				  scaled_width / pipe_src_w);
>>   
>>   		*border = LVDS_BORDER_ENABLE;
>> @@ -489,7 +492,7 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
>>   		 * heights and modify the values programmed into the CRTC.
>>   		 */
>>   		centre_horizontally(adjusted_mode, pipe_src_w);
>> -		centre_vertically(adjusted_mode, pipe_src_h);
>> +		centre_vertically(crtc_state, adjusted_mode, pipe_src_h);
>>   		border = LVDS_BORDER_ENABLE;
>>   		break;
>>   	case DRM_MODE_SCALE_ASPECT:
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index f7115969b4c5..ae6b94a5d450 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -1365,8 +1365,7 @@ static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
>>   				       bool aux_less)
>>   {
>>   	struct intel_display *display = to_intel_display(intel_dp);
>> -	int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -
>> -		crtc_state->hw.adjusted_mode.crtc_vblank_start;
>> +	int vblank = intel_crtc_vblank_length(crtc_state);
> I *think* this also gets computed during .compute_config() which is
> before the guardband calculation. So if this stuff actually depends on
> the guardband then we have a real problem here. And if it doesn't (as
> in it really interested in the undelayed vblank length) them maybe it
> should just compute it as crtc_vtotal-crtc_vactive.

As far as I understand it depends on guardband for VRR case.
For non vrr case : crtc_vtotal - crtc_vactive - scl lines
For vrr case: guardband length.

Currently since guardband is equal to vblank length this can be 
crtc_vtotal - crtc_vactive - scl lines.

Perhaps with the optimized guardband, we need to set the guardband 
during intel_vrr_compute_config().

Later intel_psr_compute_config gets called and then we can check the 
guardband.


>
>>   	int wake_lines;
>>   
>>   	if (aux_less)
>> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
>> index 0b7fcc05e64c..2fc0c1c0bb87 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
>> @@ -767,3 +767,13 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
>>   
>>   	return scanline;
>>   }
>> +
>> +int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state)
>> +{
>> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>> +
>> +	if (crtc_state->vrr.enable)
>> +		return crtc_state->vrr.guardband;
>> +	else
>> +		return adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
> Maybe that should be crtc_vblank_end instead of crtc_vtotal? I guess it
> doesn't actually matter given where this gets used.

We can use Vblank end.

Apart from these places, do you think there are more places where 
vblank_start adjustement is required?
For evasion logic and wait for push in case of VRR, we are already using 
vmin_vtotal - guardband to get the delayed vblank start so we are covered.

Regards,

Ankit

>
> I think the only case where vblank_end!=vtotal is exactly than ancient
> gen2-4 pfit centering stuff. But I've never actually investigated
> whether the exact value of vblank_end there even matters. I should do
> that one day...
>
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h
>> index 21fbb08d61d5..98d04cacd65f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vblank.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vblank.h
>> @@ -48,4 +48,6 @@ const struct intel_crtc_state *
>>   intel_pre_commit_crtc_state(struct intel_atomic_state *state,
>>   			    struct intel_crtc *crtc);
>>   
>> +int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state);
>> +
>>   #endif /* __INTEL_VBLANK_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
>> index 73e5b2d8ae83..6fb2c78fe29b 100644
>> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
>> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>> @@ -28,6 +28,7 @@
>>   #include "intel_flipq.h"
>>   #include "intel_pcode.h"
>>   #include "intel_plane.h"
>> +#include "intel_vblank.h"
>>   #include "intel_wm.h"
>>   #include "skl_universal_plane_regs.h"
>>   #include "skl_scaler.h"
>> @@ -2171,7 +2172,7 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
>>   	return crtc_state->framestart_delay +
>>   		intel_usecs_to_scanlines(adjusted_mode, latency) +
>>   		wm0_lines >
>> -		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
>> +		intel_crtc_vblank_length(crtc_state);
>>   }
>>   
>>   int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
>> -- 
>> 2.45.2

Re: [PATCH 13/16] drm/i915/display: Add vblank_start adjustment logic for always-on VRR TG

[Nautiyal, Ankit K]

On 10/7/2025 1:26 AM, Ville Syrjälä wrote:
> On Mon, Oct 06, 2025 at 09:58:49AM +0530, Ankit Nautiyal wrote:
>> As we move towards using a shorter, optimized guardband, we need to adjust
>> how the delayed vblank start is computed.
>>
>> Introduce intel_crtc_compute_vrr_guardband() to handle guardband
>> computation and apply vblank_start adjustment for platforms that always use
>> the VRR timing generator.
>>
>> This function wraps the existing intel_vrr_compute_guardband() and adjusts
>> crtc_vblank_start using (vblank_length - guardband) only when
>> intel_vrr_always_use_vrr_tg() is true. Since the guardband is not yet
>> optimized, the adjustment currently evaluates to zero, preserving existing
>> behavior.
>>
>> This paves way for guardband optimization, by handling the movement of
>> the crtc_vblank_start for platforms that have VRR TG always active.
>>
>> Also update allow_vblank_delay_fastset() to permit vblank delay adjustments
>> during fastboot when VRR TG is always active, even without inherited state.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c | 33 ++++++++++++++++++--
>>   1 file changed, 30 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index b2d4e24fd7c6..1964e41b5704 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -2403,6 +2403,27 @@ static int intel_crtc_compute_set_context_latency(struct intel_atomic_state *sta
>>   	return 0;
>>   }
>>   
>> +static void intel_crtc_compute_vrr_guardband(struct intel_atomic_state *state,
>> +					     struct intel_crtc *crtc)
> Why this wrapper? You could just stick the adjustemnt into
> intel_vrr_compute_guardband().


The idea was to prepare for the optimized guardband which needs 
connector also.

In subsequent patch I am getting the connector here to use the optimized 
guardband only for platforms with always_use_vrr_tg=true.
And at last I am making changes in intel_vrr_compute_guardband() itself.

As for this patch I can just avoid the wrapper and just use the adjustment.

>
>> +{
>> +	struct intel_display *display = to_intel_display(state);
>> +	struct intel_crtc_state *crtc_state =
>> +		intel_atomic_get_new_crtc_state(state, crtc);
>> +	struct drm_display_mode *adjusted_mode =
>> +		&crtc_state->hw.adjusted_mode;
>> +
>> +	intel_vrr_compute_guardband(crtc_state);
>> +
>> +	if (intel_vrr_always_use_vrr_tg(display)) {
>> +		int vblank_length = adjusted_mode->crtc_vtotal -
>> +				    (crtc_state->set_context_latency +
>> +				     adjusted_mode->crtc_vdisplay);
>> +
>> +		adjusted_mode->crtc_vblank_start +=
>> +			vblank_length - crtc_state->vrr.guardband;
> Why aren't you using the same 'vblank_start = vtotal-guardband' here as
> during readout?

Hmm I was thinking this more as change in the vblank_start. In 
compute_set_context_latency we move the vblank_start by SCL lines. Here 
we move further as much amount as the change in guardband.


But I guess that is not very intuitive, so I will just set 
crtc_vblank_start as vtotal - guardband here.


>
>> +	}
>> +}
>> +
>>   static int intel_crtc_compute_config(struct intel_atomic_state *state,
>>   				     struct intel_crtc *crtc)
>>   {
>> @@ -2414,7 +2435,7 @@ static int intel_crtc_compute_config(struct intel_atomic_state *state,
>>   	if (ret)
>>   		return ret;
>>   
>> -	intel_vrr_compute_guardband(crtc_state);
>> +	intel_crtc_compute_vrr_guardband(state, crtc);
>>   
>>   	ret = intel_dpll_crtc_compute_clock(state, crtc);
>>   	if (ret)
>> @@ -5105,9 +5126,15 @@ static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_s
>>   	 * Allow fastboot to fix up vblank delay (handled via LRR
>>   	 * codepaths), a bit dodgy as the registers aren't
>>   	 * double buffered but seems to be working more or less...
>> +	 *
>> +	 * Also allow this when the VRR timing generator is always on,
>> +	 * which implies optimized guardband is used. In such cases,
>> +	 * vblank delay may vary even without inherited state, but it's
>> +	 * still safe as VRR guardband is still same.
>>   	 */
>> -	return HAS_LRR(display) && old_crtc_state->inherited &&
>> -		!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
>> +	return HAS_LRR(display) &&
>> +	       (old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) &&
>> +	       !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
> This part doesn't seem directly related to the making crtc_vblank_start
> correct. We still use the non-optimzied guardband so crtc_vblank_start
> should not be changing during normal runtime operation.


Yes we do not need this at this time, but only when we really start 
using optimized guardband.
I can make it as a separate function.

Regards,

Ankit


>>   }
>>   
>>   bool
>> -- 
>> 2.45.2

Re: [PATCH 00/16] Optimize vrr.guardband and fix LRR

[Nautiyal, Ankit K]

On 10/7/2025 4:20 AM, Ville Syrjälä wrote:
> On Mon, Oct 06, 2025 at 09:58:36AM +0530, Ankit Nautiyal wrote:
>
> I'd like to see a separate series with just the patches to fix
> the crtc_vblank_start stuff, which I think is roughly these:
>
>>    drm/i915/vrr: Use crtc_vsync_start/end for computing  vrr.vsync_start/end
>>    drm/i915/vrr: s/intel_vrr_compute_config_late/intel_vrr_compute_guardband
>>    drm/i915/vblank: Add helper to get correct vblank length
>>    drm/i915/vrr: Recompute vblank_start for platforms with always-on VRR TG
>>    drm/i915/display: Add vblank_start adjustment logic for always-on VRR TG
> (+ whatever is needed to sort out the issues I outlined in the
>   indiviual replies)
>
> That is really just fixing existing things, and has nothing to
> do with any of the prefill stuff/etc. in the rest of the series.


Alright I can send a separate series for this.


Then optimized guardband and pipeline fill thing can wait.


For fixing LRR on PTL, is there any other stop gap?

Currently guardband depends on vmin vtotal and for LRR vtotal gets 
changed. Is it possible to get a constant value?


Regards,

Ankit

>
> The prefill stuff btw seems to be completely borked in current
> upstream code even; it computes things based on a completely stale
> cdclk frequency (the new frequency will be computed much later).
>
> I *think* I can reorder things sufficiently to fix that, but I really
> must get https://patchwork.freedesktop.org/series/154921/ landed
> first...
>

Re: [PATCH 11/16] drm/i915/vblank: Add helper to get correct vblank length

[Ville Syrjälä]

On Tue, Oct 07, 2025 at 11:22:44AM +0530, Nautiyal, Ankit K wrote:
> 
> On 10/7/2025 1:26 AM, Ville Syrjälä wrote:
> > On Mon, Oct 06, 2025 at 09:58:47AM +0530, Ankit Nautiyal wrote:
> >> Currently crtc_vblank_start is assumed to be the vblank_start for the fixed
> >> refresh rate case. That value can be different from the variable refresh
> >> rate case whenever always_use_vrr_tg()==false. On icl/tgl it's always
> >> different due to the extra vblank delay, and also on adl+ it could be
> >> different if we were to use an optimized guardband.
> >>
> >> So places where crtc_vblank_start is used to compute vblank length needs
> >> change so as to account for cases where vrr is enabled. Specifically
> >> with vrr.enable the effective vblank length is actually guardband.
> >>
> >> Add a helper to get the correct vblank length for both vrr and fixed
> >> refresh rate cases. Use this helper where vblank_start is used to
> >> compute the vblank length.
> >>
> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/display/intel_pfit.c    | 11 +++++++----
> >>   drivers/gpu/drm/i915/display/intel_psr.c     |  3 +--
> >>   drivers/gpu/drm/i915/display/intel_vblank.c  | 10 ++++++++++
> >>   drivers/gpu/drm/i915/display/intel_vblank.h  |  2 ++
> >>   drivers/gpu/drm/i915/display/skl_watermark.c |  3 ++-
> >>   5 files changed, 22 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
> >> index 68539e7c2a24..ebbaa1d419ba 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_pfit.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_pfit.c
> >> @@ -14,6 +14,7 @@
> >>   #include "intel_lvds_regs.h"
> >>   #include "intel_pfit.h"
> >>   #include "intel_pfit_regs.h"
> >> +#include "intel_vblank.h"
> >>   #include "skl_scaler.h"
> >>   
> >>   static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_state)
> >> @@ -306,14 +307,15 @@ centre_horizontally(struct drm_display_mode *adjusted_mode,
> >>   }
> >>   
> >>   static void
> >> -centre_vertically(struct drm_display_mode *adjusted_mode,
> >> +centre_vertically(struct intel_crtc_state *crtc_state,
> >> +		  struct drm_display_mode *adjusted_mode,
> >>   		  int height)
> >>   {
> >>   	u32 border, sync_pos, blank_width, sync_width;
> >>   
> >>   	/* keep the vsync and vblank widths constant */
> >>   	sync_width = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
> >> -	blank_width = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start;
> >> +	blank_width = intel_crtc_vblank_length(crtc_state);
> > This pfit stuff is computed way before the guardband, and also only
> > relevant for ancient gen2-4 hardware. So no point in touching this
> > stuff IMO.
> 
> Alright can skip this stuff.
> 
> 
> >
> >>   	sync_pos = (blank_width - sync_width + 1) / 2;
> >>   
> >>   	border = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
> >> @@ -392,7 +394,8 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
> >>   					  PFIT_HORIZ_INTERP_BILINEAR);
> >>   		}
> >>   	} else if (scaled_width < scaled_height) { /* letter */
> >> -		centre_vertically(adjusted_mode,
> >> +		centre_vertically(crtc_state,
> >> +				  adjusted_mode,
> >>   				  scaled_width / pipe_src_w);
> >>   
> >>   		*border = LVDS_BORDER_ENABLE;
> >> @@ -489,7 +492,7 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
> >>   		 * heights and modify the values programmed into the CRTC.
> >>   		 */
> >>   		centre_horizontally(adjusted_mode, pipe_src_w);
> >> -		centre_vertically(adjusted_mode, pipe_src_h);
> >> +		centre_vertically(crtc_state, adjusted_mode, pipe_src_h);
> >>   		border = LVDS_BORDER_ENABLE;
> >>   		break;
> >>   	case DRM_MODE_SCALE_ASPECT:
> >> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> >> index f7115969b4c5..ae6b94a5d450 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> >> @@ -1365,8 +1365,7 @@ static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
> >>   				       bool aux_less)
> >>   {
> >>   	struct intel_display *display = to_intel_display(intel_dp);
> >> -	int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -
> >> -		crtc_state->hw.adjusted_mode.crtc_vblank_start;
> >> +	int vblank = intel_crtc_vblank_length(crtc_state);
> > I *think* this also gets computed during .compute_config() which is
> > before the guardband calculation. So if this stuff actually depends on
> > the guardband then we have a real problem here. And if it doesn't (as
> > in it really interested in the undelayed vblank length) them maybe it
> > should just compute it as crtc_vtotal-crtc_vactive.
> 
> As far as I understand it depends on guardband for VRR case.
> For non vrr case : crtc_vtotal - crtc_vactive - scl lines
> For vrr case: guardband length.
> 
> Currently since guardband is equal to vblank length this can be 
> crtc_vtotal - crtc_vactive - scl lines.
> 
> Perhaps with the optimized guardband, we need to set the guardband 
> during intel_vrr_compute_config().
> 
> Later intel_psr_compute_config gets called and then we can check the 
> guardband.

Originally we moved the vblank delay calculation to happen later
because we needed to know about PSR for it to be done correctly.
I think someone will need to try to actually write down all the 
requirements from both PSR and VRR side and sides and come up
with a way to get it all done in the right order, without any
more chicken vs. egg problems.

> 
> 
> >
> >>   	int wake_lines;
> >>   
> >>   	if (aux_less)
> >> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> >> index 0b7fcc05e64c..2fc0c1c0bb87 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> >> @@ -767,3 +767,13 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
> >>   
> >>   	return scanline;
> >>   }
> >> +
> >> +int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state)
> >> +{
> >> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> >> +
> >> +	if (crtc_state->vrr.enable)
> >> +		return crtc_state->vrr.guardband;
> >> +	else
> >> +		return adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
> > Maybe that should be crtc_vblank_end instead of crtc_vtotal? I guess it
> > doesn't actually matter given where this gets used.
> 
> We can use Vblank end.
> 
> Apart from these places, do you think there are more places where 
> vblank_start adjustement is required?
> For evasion logic and wait for push in case of VRR, we are already using 
> vmin_vtotal - guardband to get the delayed vblank start so we are covered.
> 
> Regards,
> 
> Ankit
> 
> >
> > I think the only case where vblank_end!=vtotal is exactly than ancient
> > gen2-4 pfit centering stuff. But I've never actually investigated
> > whether the exact value of vblank_end there even matters. I should do
> > that one day...
> >
> >> +}
> >> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h
> >> index 21fbb08d61d5..98d04cacd65f 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_vblank.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_vblank.h
> >> @@ -48,4 +48,6 @@ const struct intel_crtc_state *
> >>   intel_pre_commit_crtc_state(struct intel_atomic_state *state,
> >>   			    struct intel_crtc *crtc);
> >>   
> >> +int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state);
> >> +
> >>   #endif /* __INTEL_VBLANK_H__ */
> >> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> >> index 73e5b2d8ae83..6fb2c78fe29b 100644
> >> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> >> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> >> @@ -28,6 +28,7 @@
> >>   #include "intel_flipq.h"
> >>   #include "intel_pcode.h"
> >>   #include "intel_plane.h"
> >> +#include "intel_vblank.h"
> >>   #include "intel_wm.h"
> >>   #include "skl_universal_plane_regs.h"
> >>   #include "skl_scaler.h"
> >> @@ -2171,7 +2172,7 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
> >>   	return crtc_state->framestart_delay +
> >>   		intel_usecs_to_scanlines(adjusted_mode, latency) +
> >>   		wm0_lines >
> >> -		adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
> >> +		intel_crtc_vblank_length(crtc_state);
> >>   }
> >>   
> >>   int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
> >> -- 
> >> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 13/16] drm/i915/display: Add vblank_start adjustment logic for always-on VRR TG

[Ville Syrjälä]

On Tue, Oct 07, 2025 at 12:00:34PM +0530, Nautiyal, Ankit K wrote:
> 
> On 10/7/2025 1:26 AM, Ville Syrjälä wrote:
> > On Mon, Oct 06, 2025 at 09:58:49AM +0530, Ankit Nautiyal wrote:
> >> As we move towards using a shorter, optimized guardband, we need to adjust
> >> how the delayed vblank start is computed.
> >>
> >> Introduce intel_crtc_compute_vrr_guardband() to handle guardband
> >> computation and apply vblank_start adjustment for platforms that always use
> >> the VRR timing generator.
> >>
> >> This function wraps the existing intel_vrr_compute_guardband() and adjusts
> >> crtc_vblank_start using (vblank_length - guardband) only when
> >> intel_vrr_always_use_vrr_tg() is true. Since the guardband is not yet
> >> optimized, the adjustment currently evaluates to zero, preserving existing
> >> behavior.
> >>
> >> This paves way for guardband optimization, by handling the movement of
> >> the crtc_vblank_start for platforms that have VRR TG always active.
> >>
> >> Also update allow_vblank_delay_fastset() to permit vblank delay adjustments
> >> during fastboot when VRR TG is always active, even without inherited state.
> >>
> >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/display/intel_display.c | 33 ++++++++++++++++++--
> >>   1 file changed, 30 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> >> index b2d4e24fd7c6..1964e41b5704 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >> @@ -2403,6 +2403,27 @@ static int intel_crtc_compute_set_context_latency(struct intel_atomic_state *sta
> >>   	return 0;
> >>   }
> >>   
> >> +static void intel_crtc_compute_vrr_guardband(struct intel_atomic_state *state,
> >> +					     struct intel_crtc *crtc)
> > Why this wrapper? You could just stick the adjustemnt into
> > intel_vrr_compute_guardband().
> 
> 
> The idea was to prepare for the optimized guardband which needs 
> connector also.

You shouldn't need the connector there. Looks like you were just using
it to figure out the output type when you could have just grabbed that
from the crtc state.

> 
> In subsequent patch I am getting the connector here to use the optimized 
> guardband only for platforms with always_use_vrr_tg=true.
> And at last I am making changes in intel_vrr_compute_guardband() itself.
> 
> As for this patch I can just avoid the wrapper and just use the adjustment.
> 
> >
> >> +{
> >> +	struct intel_display *display = to_intel_display(state);
> >> +	struct intel_crtc_state *crtc_state =
> >> +		intel_atomic_get_new_crtc_state(state, crtc);
> >> +	struct drm_display_mode *adjusted_mode =
> >> +		&crtc_state->hw.adjusted_mode;
> >> +
> >> +	intel_vrr_compute_guardband(crtc_state);
> >> +
> >> +	if (intel_vrr_always_use_vrr_tg(display)) {
> >> +		int vblank_length = adjusted_mode->crtc_vtotal -
> >> +				    (crtc_state->set_context_latency +
> >> +				     adjusted_mode->crtc_vdisplay);
> >> +
> >> +		adjusted_mode->crtc_vblank_start +=
> >> +			vblank_length - crtc_state->vrr.guardband;
> > Why aren't you using the same 'vblank_start = vtotal-guardband' here as
> > during readout?
> 
> Hmm I was thinking this more as change in the vblank_start. In 
> compute_set_context_latency we move the vblank_start by SCL lines. Here 
> we move further as much amount as the change in guardband.

The SCL adjustment is for the legacy timing generator timings.
This should just overwrite the whole thing with what the VRR
timing generator will actually do.

> 
> 
> But I guess that is not very intuitive, so I will just set 
> crtc_vblank_start as vtotal - guardband here.
> 
> 
> >
> >> +	}
> >> +}
> >> +
> >>   static int intel_crtc_compute_config(struct intel_atomic_state *state,
> >>   				     struct intel_crtc *crtc)
> >>   {
> >> @@ -2414,7 +2435,7 @@ static int intel_crtc_compute_config(struct intel_atomic_state *state,
> >>   	if (ret)
> >>   		return ret;
> >>   
> >> -	intel_vrr_compute_guardband(crtc_state);
> >> +	intel_crtc_compute_vrr_guardband(state, crtc);
> >>   
> >>   	ret = intel_dpll_crtc_compute_clock(state, crtc);
> >>   	if (ret)
> >> @@ -5105,9 +5126,15 @@ static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_s
> >>   	 * Allow fastboot to fix up vblank delay (handled via LRR
> >>   	 * codepaths), a bit dodgy as the registers aren't
> >>   	 * double buffered but seems to be working more or less...
> >> +	 *
> >> +	 * Also allow this when the VRR timing generator is always on,
> >> +	 * which implies optimized guardband is used. In such cases,
> >> +	 * vblank delay may vary even without inherited state, but it's
> >> +	 * still safe as VRR guardband is still same.
> >>   	 */
> >> -	return HAS_LRR(display) && old_crtc_state->inherited &&
> >> -		!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
> >> +	return HAS_LRR(display) &&
> >> +	       (old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) &&
> >> +	       !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
> > This part doesn't seem directly related to the making crtc_vblank_start
> > correct. We still use the non-optimzied guardband so crtc_vblank_start
> > should not be changing during normal runtime operation.
> 
> 
> Yes we do not need this at this time, but only when we really start 
> using optimized guardband.
> I can make it as a separate function.
> 
> Regards,
> 
> Ankit
> 
> 
> >>   }
> >>   
> >>   bool
> >> -- 
> >> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 00/16] Optimize vrr.guardband and fix LRR

[Ville Syrjälä]

On Tue, Oct 07, 2025 at 12:03:47PM +0530, Nautiyal, Ankit K wrote:
> 
> On 10/7/2025 4:20 AM, Ville Syrjälä wrote:
> > On Mon, Oct 06, 2025 at 09:58:36AM +0530, Ankit Nautiyal wrote:
> >
> > I'd like to see a separate series with just the patches to fix
> > the crtc_vblank_start stuff, which I think is roughly these:
> >
> >>    drm/i915/vrr: Use crtc_vsync_start/end for computing  vrr.vsync_start/end
> >>    drm/i915/vrr: s/intel_vrr_compute_config_late/intel_vrr_compute_guardband
> >>    drm/i915/vblank: Add helper to get correct vblank length
> >>    drm/i915/vrr: Recompute vblank_start for platforms with always-on VRR TG
> >>    drm/i915/display: Add vblank_start adjustment logic for always-on VRR TG
> > (+ whatever is needed to sort out the issues I outlined in the
> >   indiviual replies)
> >
> > That is really just fixing existing things, and has nothing to
> > do with any of the prefill stuff/etc. in the rest of the series.
> 
> 
> Alright I can send a separate series for this.
> 
> 
> Then optimized guardband and pipeline fill thing can wait.
> 
> 
> For fixing LRR on PTL, is there any other stop gap?
> 
> Currently guardband depends on vmin vtotal and for LRR vtotal gets 
> changed. Is it possible to get a constant value?

If we aren't convinced that changing the guardband is ok then using
the optimized guardband is the only choice that I can see.

> 
> 
> Regards,
> 
> Ankit
> 
> >
> > The prefill stuff btw seems to be completely borked in current
> > upstream code even; it computes things based on a completely stale
> > cdclk frequency (the new frequency will be computed much later).

Also the scaler stuff is borked in the same way. Fixing that is probably
going to require some actual work :/

> >
> > I *think* I can reorder things sufficiently to fix that, but I really
> > must get https://patchwork.freedesktop.org/series/154921/ landed
> > first...
> >

-- 
Ville Syrjälä
Intel

Re: [PATCH 11/16] drm/i915/vblank: Add helper to get correct vblank length

[Ville Syrjälä]

On Tue, Oct 07, 2025 at 06:16:57PM +0300, Ville Syrjälä wrote:
> On Tue, Oct 07, 2025 at 11:22:44AM +0530, Nautiyal, Ankit K wrote:
> > 
> > On 10/7/2025 1:26 AM, Ville Syrjälä wrote:
> > > On Mon, Oct 06, 2025 at 09:58:47AM +0530, Ankit Nautiyal wrote:
> > >> Currently crtc_vblank_start is assumed to be the vblank_start for the fixed
> > >> refresh rate case. That value can be different from the variable refresh
> > >> rate case whenever always_use_vrr_tg()==false. On icl/tgl it's always
> > >> different due to the extra vblank delay, and also on adl+ it could be
> > >> different if we were to use an optimized guardband.
> > >>
> > >> So places where crtc_vblank_start is used to compute vblank length needs
> > >> change so as to account for cases where vrr is enabled. Specifically
> > >> with vrr.enable the effective vblank length is actually guardband.
> > >>
> > >> Add a helper to get the correct vblank length for both vrr and fixed
> > >> refresh rate cases. Use this helper where vblank_start is used to
> > >> compute the vblank length.
> > >>
> > >> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > >> ---
> > >>   drivers/gpu/drm/i915/display/intel_pfit.c    | 11 +++++++----
> > >>   drivers/gpu/drm/i915/display/intel_psr.c     |  3 +--
> > >>   drivers/gpu/drm/i915/display/intel_vblank.c  | 10 ++++++++++
> > >>   drivers/gpu/drm/i915/display/intel_vblank.h  |  2 ++
> > >>   drivers/gpu/drm/i915/display/skl_watermark.c |  3 ++-
> > >>   5 files changed, 22 insertions(+), 7 deletions(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
> > >> index 68539e7c2a24..ebbaa1d419ba 100644
> > >> --- a/drivers/gpu/drm/i915/display/intel_pfit.c
> > >> +++ b/drivers/gpu/drm/i915/display/intel_pfit.c
> > >> @@ -14,6 +14,7 @@
> > >>   #include "intel_lvds_regs.h"
> > >>   #include "intel_pfit.h"
> > >>   #include "intel_pfit_regs.h"
> > >> +#include "intel_vblank.h"
> > >>   #include "skl_scaler.h"
> > >>   
> > >>   static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_state)
> > >> @@ -306,14 +307,15 @@ centre_horizontally(struct drm_display_mode *adjusted_mode,
> > >>   }
> > >>   
> > >>   static void
> > >> -centre_vertically(struct drm_display_mode *adjusted_mode,
> > >> +centre_vertically(struct intel_crtc_state *crtc_state,
> > >> +		  struct drm_display_mode *adjusted_mode,
> > >>   		  int height)
> > >>   {
> > >>   	u32 border, sync_pos, blank_width, sync_width;
> > >>   
> > >>   	/* keep the vsync and vblank widths constant */
> > >>   	sync_width = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
> > >> -	blank_width = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start;
> > >> +	blank_width = intel_crtc_vblank_length(crtc_state);
> > > This pfit stuff is computed way before the guardband, and also only
> > > relevant for ancient gen2-4 hardware. So no point in touching this
> > > stuff IMO.
> > 
> > Alright can skip this stuff.
> > 
> > 
> > >
> > >>   	sync_pos = (blank_width - sync_width + 1) / 2;
> > >>   
> > >>   	border = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
> > >> @@ -392,7 +394,8 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
> > >>   					  PFIT_HORIZ_INTERP_BILINEAR);
> > >>   		}
> > >>   	} else if (scaled_width < scaled_height) { /* letter */
> > >> -		centre_vertically(adjusted_mode,
> > >> +		centre_vertically(crtc_state,
> > >> +				  adjusted_mode,
> > >>   				  scaled_width / pipe_src_w);
> > >>   
> > >>   		*border = LVDS_BORDER_ENABLE;
> > >> @@ -489,7 +492,7 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
> > >>   		 * heights and modify the values programmed into the CRTC.
> > >>   		 */
> > >>   		centre_horizontally(adjusted_mode, pipe_src_w);
> > >> -		centre_vertically(adjusted_mode, pipe_src_h);
> > >> +		centre_vertically(crtc_state, adjusted_mode, pipe_src_h);
> > >>   		border = LVDS_BORDER_ENABLE;
> > >>   		break;
> > >>   	case DRM_MODE_SCALE_ASPECT:
> > >> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> > >> index f7115969b4c5..ae6b94a5d450 100644
> > >> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > >> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > >> @@ -1365,8 +1365,7 @@ static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
> > >>   				       bool aux_less)
> > >>   {
> > >>   	struct intel_display *display = to_intel_display(intel_dp);
> > >> -	int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -
> > >> -		crtc_state->hw.adjusted_mode.crtc_vblank_start;
> > >> +	int vblank = intel_crtc_vblank_length(crtc_state);
> > > I *think* this also gets computed during .compute_config() which is
> > > before the guardband calculation. So if this stuff actually depends on
> > > the guardband then we have a real problem here. And if it doesn't (as
> > > in it really interested in the undelayed vblank length) them maybe it
> > > should just compute it as crtc_vtotal-crtc_vactive.
> > 
> > As far as I understand it depends on guardband for VRR case.
> > For non vrr case : crtc_vtotal - crtc_vactive - scl lines
> > For vrr case: guardband length.
> > 
> > Currently since guardband is equal to vblank length this can be 
> > crtc_vtotal - crtc_vactive - scl lines.
> > 
> > Perhaps with the optimized guardband, we need to set the guardband 
> > during intel_vrr_compute_config().
> > 
> > Later intel_psr_compute_config gets called and then we can check the 
> > guardband.
> 
> Originally we moved the vblank delay calculation to happen later
> because we needed to know about PSR for it to be done correctly.
> I think someone will need to try to actually write down all the 
> requirements from both PSR and VRR side and sides and come up
> with a way to get it all done in the right order, without any
> more chicken vs. egg problems.

I haven't actually checked any of PSR details here, but I'm thinking
if my assumptions hold that there is a dependency both ways, we migth
need soemthing like this:

1. .compute_config()
   Check if PSR is generallty possible/desired, and verify that a maximum
   guardband would suffice for PSR (this check could also take PSR specific
   SCL requirements into consideration)

2. compute_scl()
   Bump SCL if PSR (or anything else) needs it

3. vrr_compute_guardband()
   Try to accomodate PSR requirements, but don't worry if we can't satisy
   that

.compute_config_late()
   Check whether the actual guardband is sufficient for PSR, and
   calculate any other state that depends on the guardband. If not,
   disable PSR (hopefully we can still do that at this point...)

I think that might generally work (if the assumption about being
able to revert the early PSR decision in .compute_config_late()
is valid).

The only corner case I see is if something else requires
bumping SCL and that reduces the guardband below what PSR needs.
But perhaps we should not worry about such issues, unless perhaps
that other SCL bumping requirement can be trivially accomodated
in the PSR .compute_config() as well.

Or I suppose we might try to see if we could compute SCL (considering
only the non-PSR requirements) even earlier (as in before PSR
.compute_config()), and then have the PSR code itself bump SCL if
required during .compute_config(). But this sort of approach we could
look into later, doesn't have to be done now IMO.

-- 
Ville Syrjälä
Intel

Re: [PATCH 11/16] drm/i915/vblank: Add helper to get correct vblank length

[Nautiyal, Ankit K]

On 10/7/2025 11:00 PM, Ville Syrjälä wrote:
> On Tue, Oct 07, 2025 at 06:16:57PM +0300, Ville Syrjälä wrote:
>> On Tue, Oct 07, 2025 at 11:22:44AM +0530, Nautiyal, Ankit K wrote:
>>> On 10/7/2025 1:26 AM, Ville Syrjälä wrote:
>>>> On Mon, Oct 06, 2025 at 09:58:47AM +0530, Ankit Nautiyal wrote:
>>>>> Currently crtc_vblank_start is assumed to be the vblank_start for the fixed
>>>>> refresh rate case. That value can be different from the variable refresh
>>>>> rate case whenever always_use_vrr_tg()==false. On icl/tgl it's always
>>>>> different due to the extra vblank delay, and also on adl+ it could be
>>>>> different if we were to use an optimized guardband.
>>>>>
>>>>> So places where crtc_vblank_start is used to compute vblank length needs
>>>>> change so as to account for cases where vrr is enabled. Specifically
>>>>> with vrr.enable the effective vblank length is actually guardband.
>>>>>
>>>>> Add a helper to get the correct vblank length for both vrr and fixed
>>>>> refresh rate cases. Use this helper where vblank_start is used to
>>>>> compute the vblank length.
>>>>>
>>>>> Signed-off-by: Ankit Nautiyal<ankit.k.nautiyal@intel.com>
>>>>> ---
>>>>>    drivers/gpu/drm/i915/display/intel_pfit.c    | 11 +++++++----
>>>>>    drivers/gpu/drm/i915/display/intel_psr.c     |  3 +--
>>>>>    drivers/gpu/drm/i915/display/intel_vblank.c  | 10 ++++++++++
>>>>>    drivers/gpu/drm/i915/display/intel_vblank.h  |  2 ++
>>>>>    drivers/gpu/drm/i915/display/skl_watermark.c |  3 ++-
>>>>>    5 files changed, 22 insertions(+), 7 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
>>>>> index 68539e7c2a24..ebbaa1d419ba 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_pfit.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_pfit.c
>>>>> @@ -14,6 +14,7 @@
>>>>>    #include "intel_lvds_regs.h"
>>>>>    #include "intel_pfit.h"
>>>>>    #include "intel_pfit_regs.h"
>>>>> +#include "intel_vblank.h"
>>>>>    #include "skl_scaler.h"
>>>>>    
>>>>>    static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_state)
>>>>> @@ -306,14 +307,15 @@ centre_horizontally(struct drm_display_mode *adjusted_mode,
>>>>>    }
>>>>>    
>>>>>    static void
>>>>> -centre_vertically(struct drm_display_mode *adjusted_mode,
>>>>> +centre_vertically(struct intel_crtc_state *crtc_state,
>>>>> +		  struct drm_display_mode *adjusted_mode,
>>>>>    		  int height)
>>>>>    {
>>>>>    	u32 border, sync_pos, blank_width, sync_width;
>>>>>    
>>>>>    	/* keep the vsync and vblank widths constant */
>>>>>    	sync_width = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
>>>>> -	blank_width = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start;
>>>>> +	blank_width = intel_crtc_vblank_length(crtc_state);
>>>> This pfit stuff is computed way before the guardband, and also only
>>>> relevant for ancient gen2-4 hardware. So no point in touching this
>>>> stuff IMO.
>>> Alright can skip this stuff.
>>>
>>>
>>>>>    	sync_pos = (blank_width - sync_width + 1) / 2;
>>>>>    
>>>>>    	border = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
>>>>> @@ -392,7 +394,8 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
>>>>>    					  PFIT_HORIZ_INTERP_BILINEAR);
>>>>>    		}
>>>>>    	} else if (scaled_width < scaled_height) { /* letter */
>>>>> -		centre_vertically(adjusted_mode,
>>>>> +		centre_vertically(crtc_state,
>>>>> +				  adjusted_mode,
>>>>>    				  scaled_width / pipe_src_w);
>>>>>    
>>>>>    		*border = LVDS_BORDER_ENABLE;
>>>>> @@ -489,7 +492,7 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
>>>>>    		 * heights and modify the values programmed into the CRTC.
>>>>>    		 */
>>>>>    		centre_horizontally(adjusted_mode, pipe_src_w);
>>>>> -		centre_vertically(adjusted_mode, pipe_src_h);
>>>>> +		centre_vertically(crtc_state, adjusted_mode, pipe_src_h);
>>>>>    		border = LVDS_BORDER_ENABLE;
>>>>>    		break;
>>>>>    	case DRM_MODE_SCALE_ASPECT:
>>>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>>>>> index f7115969b4c5..ae6b94a5d450 100644
>>>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>>>> @@ -1365,8 +1365,7 @@ static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
>>>>>    				       bool aux_less)
>>>>>    {
>>>>>    	struct intel_display *display = to_intel_display(intel_dp);
>>>>> -	int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -
>>>>> -		crtc_state->hw.adjusted_mode.crtc_vblank_start;
>>>>> +	int vblank = intel_crtc_vblank_length(crtc_state);
>>>> I *think* this also gets computed during .compute_config() which is
>>>> before the guardband calculation. So if this stuff actually depends on
>>>> the guardband then we have a real problem here. And if it doesn't (as
>>>> in it really interested in the undelayed vblank length) them maybe it
>>>> should just compute it as crtc_vtotal-crtc_vactive.
>>> As far as I understand it depends on guardband for VRR case.
>>> For non vrr case : crtc_vtotal - crtc_vactive - scl lines
>>> For vrr case: guardband length.
>>>
>>> Currently since guardband is equal to vblank length this can be
>>> crtc_vtotal - crtc_vactive - scl lines.
>>>
>>> Perhaps with the optimized guardband, we need to set the guardband
>>> during intel_vrr_compute_config().
>>>
>>> Later intel_psr_compute_config gets called and then we can check the
>>> guardband.
>> Originally we moved the vblank delay calculation to happen later
>> because we needed to know about PSR for it to be done correctly.
>> I think someone will need to try to actually write down all the
>> requirements from both PSR and VRR side and sides and come up
>> with a way to get it all done in the right order, without any
>> more chicken vs. egg problems.
> I haven't actually checked any of PSR details here, but I'm thinking
> if my assumptions hold that there is a dependency both ways, we migth
> need soemthing like this:
>
> 1. .compute_config()
>     Check if PSR is generallty possible/desired, and verify that a maximum
>     guardband would suffice for PSR (this check could also take PSR specific
>     SCL requirements into consideration)


psr_compute_config currently checks for wake_lines_fit_into_vblank().

So here we continue to check against maximum guardband (vblank_length)

So only thing to add here is the SCL considerations.

> 2. compute_scl()
>     Bump SCL if PSR (or anything else) needs it

This is already there, so we are good.


> 3. vrr_compute_guardband()
>     Try to accomodate PSR requirements, but don't worry if we can't satisy
>     that

Hmm here currently we are not checking anything.

With optimized guardband we must check with max psr requirements and not 
the current psr requirements.

(With VRR psr will be off so we don't want to change guardband here)


> .compute_config_late()
>     Check whether the actual guardband is sufficient for PSR, and
>     calculate any other state that depends on the guardband. If not,
>     disable PSR (hopefully we can still do that at this point...)


Can try disabling psr here if the guardband is not sufficient with 
actual psr requirements.

We can check here for other latencies also e.g. SDP.

But scaler related latencies we cannot check here.


Coming back to this patch to use the vblank_start adjustment, I guess we 
need to re-evaluate.


Regards,

Ankit

> I think that might generally work (if the assumption about being
> able to revert the early PSR decision in .compute_config_late()
> is valid).
>
> The only corner case I see is if something else requires
> bumping SCL and that reduces the guardband below what PSR needs.
> But perhaps we should not worry about such issues, unless perhaps
> that other SCL bumping requirement can be trivially accomodated
> in the PSR .compute_config() as well.
>
> Or I suppose we might try to see if we could compute SCL (considering
> only the non-PSR requirements) even earlier (as in before PSR
> .compute_config()), and then have the PSR code itself bump SCL if
> required during .compute_config(). But this sort of approach we could
> look into later, doesn't have to be done now IMO.
>